1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/pci-aspm.h> 22 #include <linux/ath9k_platform.h> 23 #include <linux/module.h> 24 #include "ath9k.h" 25 26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 37 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 41 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ 42 { 0 } 43 }; 44 45 46 /* return bus cachesize in 4B word units */ 47 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 48 { 49 struct ath_softc *sc = (struct ath_softc *) common->priv; 50 u8 u8tmp; 51 52 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 53 *csz = (int)u8tmp; 54 55 /* 56 * This check was put in to avoid "unpleasant" consequences if 57 * the bootrom has not fully initialized all PCI devices. 58 * Sometimes the cache line size register is not set 59 */ 60 61 if (*csz == 0) 62 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 63 } 64 65 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 66 { 67 struct ath_softc *sc = (struct ath_softc *) common->priv; 68 struct ath9k_platform_data *pdata = sc->dev->platform_data; 69 70 if (pdata) { 71 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 72 ath_err(common, 73 "%s: eeprom read failed, offset %08x is out of range\n", 74 __func__, off); 75 } 76 77 *data = pdata->eeprom_data[off]; 78 } else { 79 struct ath_hw *ah = (struct ath_hw *) common->ah; 80 81 common->ops->read(ah, AR5416_EEPROM_OFFSET + 82 (off << AR5416_EEPROM_S)); 83 84 if (!ath9k_hw_wait(ah, 85 AR_EEPROM_STATUS_DATA, 86 AR_EEPROM_STATUS_DATA_BUSY | 87 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 88 AH_WAIT_TIMEOUT)) { 89 return false; 90 } 91 92 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 93 AR_EEPROM_STATUS_DATA_VAL); 94 } 95 96 return true; 97 } 98 99 /* Need to be called after we discover btcoex capabilities */ 100 static void ath_pci_aspm_init(struct ath_common *common) 101 { 102 struct ath_softc *sc = (struct ath_softc *) common->priv; 103 struct ath_hw *ah = sc->sc_ah; 104 struct pci_dev *pdev = to_pci_dev(sc->dev); 105 struct pci_dev *parent; 106 u16 aspm; 107 108 if (!ah->is_pciexpress) 109 return; 110 111 parent = pdev->bus->self; 112 if (!parent) 113 return; 114 115 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 116 (AR_SREV_9285(ah))) { 117 /* Bluetooth coexistence requires disabling ASPM. */ 118 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 119 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 120 121 /* 122 * Both upstream and downstream PCIe components should 123 * have the same ASPM settings. 124 */ 125 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 126 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 127 128 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 129 return; 130 } 131 132 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 133 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { 134 ah->aspm_enabled = true; 135 /* Initialize PCIe PM and SERDES registers. */ 136 ath9k_hw_configpcipowersave(ah, false); 137 ath_info(common, "ASPM enabled: 0x%x\n", aspm); 138 } 139 } 140 141 static const struct ath_bus_ops ath_pci_bus_ops = { 142 .ath_bus_type = ATH_PCI, 143 .read_cachesize = ath_pci_read_cachesize, 144 .eeprom_read = ath_pci_eeprom_read, 145 .aspm_init = ath_pci_aspm_init, 146 }; 147 148 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 149 { 150 struct ath_softc *sc; 151 struct ieee80211_hw *hw; 152 u8 csz; 153 u32 val; 154 int ret = 0; 155 char hw_name[64]; 156 157 if (pcim_enable_device(pdev)) 158 return -EIO; 159 160 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 161 if (ret) { 162 pr_err("32-bit DMA not available\n"); 163 return ret; 164 } 165 166 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 167 if (ret) { 168 pr_err("32-bit DMA consistent DMA enable failed\n"); 169 return ret; 170 } 171 172 /* 173 * Cache line size is used to size and align various 174 * structures used to communicate with the hardware. 175 */ 176 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 177 if (csz == 0) { 178 /* 179 * Linux 2.4.18 (at least) writes the cache line size 180 * register as a 16-bit wide register which is wrong. 181 * We must have this setup properly for rx buffer 182 * DMA to work so force a reasonable value here if it 183 * comes up zero. 184 */ 185 csz = L1_CACHE_BYTES / sizeof(u32); 186 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 187 } 188 /* 189 * The default setting of latency timer yields poor results, 190 * set it to the value used by other systems. It may be worth 191 * tweaking this setting more. 192 */ 193 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 194 195 pci_set_master(pdev); 196 197 /* 198 * Disable the RETRY_TIMEOUT register (0x41) to keep 199 * PCI Tx retries from interfering with C3 CPU state. 200 */ 201 pci_read_config_dword(pdev, 0x40, &val); 202 if ((val & 0x0000ff00) != 0) 203 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 204 205 ret = pcim_iomap_regions(pdev, BIT(0), "ath9k"); 206 if (ret) { 207 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 208 return -ENODEV; 209 } 210 211 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 212 if (!hw) { 213 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 214 return -ENOMEM; 215 } 216 217 SET_IEEE80211_DEV(hw, &pdev->dev); 218 pci_set_drvdata(pdev, hw); 219 220 sc = hw->priv; 221 sc->hw = hw; 222 sc->dev = &pdev->dev; 223 sc->mem = pcim_iomap_table(pdev)[0]; 224 225 /* Will be cleared in ath9k_start() */ 226 set_bit(SC_OP_INVALID, &sc->sc_flags); 227 228 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 229 if (ret) { 230 dev_err(&pdev->dev, "request_irq failed\n"); 231 goto err_irq; 232 } 233 234 sc->irq = pdev->irq; 235 236 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 237 if (ret) { 238 dev_err(&pdev->dev, "Failed to initialize device\n"); 239 goto err_init; 240 } 241 242 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 243 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 244 hw_name, (unsigned long)sc->mem, pdev->irq); 245 246 return 0; 247 248 err_init: 249 free_irq(sc->irq, sc); 250 err_irq: 251 ieee80211_free_hw(hw); 252 return ret; 253 } 254 255 static void ath_pci_remove(struct pci_dev *pdev) 256 { 257 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 258 struct ath_softc *sc = hw->priv; 259 260 if (!is_ath9k_unloaded) 261 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 262 ath9k_deinit_device(sc); 263 free_irq(sc->irq, sc); 264 ieee80211_free_hw(sc->hw); 265 } 266 267 #ifdef CONFIG_PM_SLEEP 268 269 static int ath_pci_suspend(struct device *device) 270 { 271 struct pci_dev *pdev = to_pci_dev(device); 272 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 273 struct ath_softc *sc = hw->priv; 274 275 if (sc->wow_enabled) 276 return 0; 277 278 /* The device has to be moved to FULLSLEEP forcibly. 279 * Otherwise the chip never moved to full sleep, 280 * when no interface is up. 281 */ 282 ath9k_stop_btcoex(sc); 283 ath9k_hw_disable(sc->sc_ah); 284 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 285 286 return 0; 287 } 288 289 static int ath_pci_resume(struct device *device) 290 { 291 struct pci_dev *pdev = to_pci_dev(device); 292 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 293 struct ath_softc *sc = hw->priv; 294 struct ath_hw *ah = sc->sc_ah; 295 struct ath_common *common = ath9k_hw_common(ah); 296 u32 val; 297 298 /* 299 * Suspend/Resume resets the PCI configuration space, so we have to 300 * re-disable the RETRY_TIMEOUT register (0x41) to keep 301 * PCI Tx retries from interfering with C3 CPU state 302 */ 303 pci_read_config_dword(pdev, 0x40, &val); 304 if ((val & 0x0000ff00) != 0) 305 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 306 307 ath_pci_aspm_init(common); 308 ah->reset_power_on = false; 309 310 return 0; 311 } 312 313 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume); 314 315 #define ATH9K_PM_OPS (&ath9k_pm_ops) 316 317 #else /* !CONFIG_PM_SLEEP */ 318 319 #define ATH9K_PM_OPS NULL 320 321 #endif /* !CONFIG_PM_SLEEP */ 322 323 324 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 325 326 static struct pci_driver ath_pci_driver = { 327 .name = "ath9k", 328 .id_table = ath_pci_id_table, 329 .probe = ath_pci_probe, 330 .remove = ath_pci_remove, 331 .driver.pm = ATH9K_PM_OPS, 332 }; 333 334 int ath_pci_init(void) 335 { 336 return pci_register_driver(&ath_pci_driver); 337 } 338 339 void ath_pci_exit(void) 340 { 341 pci_unregister_driver(&ath_pci_driver); 342 } 343