1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/pci-aspm.h> 22 #include <linux/ath9k_platform.h> 23 #include <linux/module.h> 24 #include "ath9k.h" 25 26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 37 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 41 { 0 } 42 }; 43 44 45 /* return bus cachesize in 4B word units */ 46 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 47 { 48 struct ath_softc *sc = (struct ath_softc *) common->priv; 49 u8 u8tmp; 50 51 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 52 *csz = (int)u8tmp; 53 54 /* 55 * This check was put in to avoid "unpleasant" consequences if 56 * the bootrom has not fully initialized all PCI devices. 57 * Sometimes the cache line size register is not set 58 */ 59 60 if (*csz == 0) 61 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 62 } 63 64 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 65 { 66 struct ath_softc *sc = (struct ath_softc *) common->priv; 67 struct ath9k_platform_data *pdata = sc->dev->platform_data; 68 69 if (pdata) { 70 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 71 ath_err(common, 72 "%s: eeprom read failed, offset %08x is out of range\n", 73 __func__, off); 74 } 75 76 *data = pdata->eeprom_data[off]; 77 } else { 78 struct ath_hw *ah = (struct ath_hw *) common->ah; 79 80 common->ops->read(ah, AR5416_EEPROM_OFFSET + 81 (off << AR5416_EEPROM_S)); 82 83 if (!ath9k_hw_wait(ah, 84 AR_EEPROM_STATUS_DATA, 85 AR_EEPROM_STATUS_DATA_BUSY | 86 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 87 AH_WAIT_TIMEOUT)) { 88 return false; 89 } 90 91 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 92 AR_EEPROM_STATUS_DATA_VAL); 93 } 94 95 return true; 96 } 97 98 static void ath_pci_extn_synch_enable(struct ath_common *common) 99 { 100 struct ath_softc *sc = (struct ath_softc *) common->priv; 101 struct pci_dev *pdev = to_pci_dev(sc->dev); 102 u8 lnkctl; 103 104 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl); 105 lnkctl |= PCI_EXP_LNKCTL_ES; 106 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); 107 } 108 109 /* Need to be called after we discover btcoex capabilities */ 110 static void ath_pci_aspm_init(struct ath_common *common) 111 { 112 struct ath_softc *sc = (struct ath_softc *) common->priv; 113 struct ath_hw *ah = sc->sc_ah; 114 struct pci_dev *pdev = to_pci_dev(sc->dev); 115 struct pci_dev *parent; 116 int pos; 117 u8 aspm; 118 119 if (!ah->is_pciexpress) 120 return; 121 122 pos = pci_pcie_cap(pdev); 123 if (!pos) 124 return; 125 126 parent = pdev->bus->self; 127 if (!parent) 128 return; 129 130 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 131 /* Bluetooth coexistance requires disabling ASPM. */ 132 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); 133 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 134 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm); 135 136 /* 137 * Both upstream and downstream PCIe components should 138 * have the same ASPM settings. 139 */ 140 pos = pci_pcie_cap(parent); 141 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 142 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 143 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); 144 145 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 146 return; 147 } 148 149 pos = pci_pcie_cap(parent); 150 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 151 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 152 ah->aspm_enabled = true; 153 /* Initialize PCIe PM and SERDES registers. */ 154 ath9k_hw_configpcipowersave(ah, false); 155 ath_info(common, "ASPM enabled: 0x%x\n", aspm); 156 } 157 } 158 159 static const struct ath_bus_ops ath_pci_bus_ops = { 160 .ath_bus_type = ATH_PCI, 161 .read_cachesize = ath_pci_read_cachesize, 162 .eeprom_read = ath_pci_eeprom_read, 163 .extn_synch_en = ath_pci_extn_synch_enable, 164 .aspm_init = ath_pci_aspm_init, 165 }; 166 167 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 168 { 169 void __iomem *mem; 170 struct ath_softc *sc; 171 struct ieee80211_hw *hw; 172 u8 csz; 173 u32 val; 174 int ret = 0; 175 char hw_name[64]; 176 177 if (pci_enable_device(pdev)) 178 return -EIO; 179 180 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 181 if (ret) { 182 pr_err("32-bit DMA not available\n"); 183 goto err_dma; 184 } 185 186 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 187 if (ret) { 188 pr_err("32-bit DMA consistent DMA enable failed\n"); 189 goto err_dma; 190 } 191 192 /* 193 * Cache line size is used to size and align various 194 * structures used to communicate with the hardware. 195 */ 196 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 197 if (csz == 0) { 198 /* 199 * Linux 2.4.18 (at least) writes the cache line size 200 * register as a 16-bit wide register which is wrong. 201 * We must have this setup properly for rx buffer 202 * DMA to work so force a reasonable value here if it 203 * comes up zero. 204 */ 205 csz = L1_CACHE_BYTES / sizeof(u32); 206 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 207 } 208 /* 209 * The default setting of latency timer yields poor results, 210 * set it to the value used by other systems. It may be worth 211 * tweaking this setting more. 212 */ 213 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 214 215 pci_set_master(pdev); 216 217 /* 218 * Disable the RETRY_TIMEOUT register (0x41) to keep 219 * PCI Tx retries from interfering with C3 CPU state. 220 */ 221 pci_read_config_dword(pdev, 0x40, &val); 222 if ((val & 0x0000ff00) != 0) 223 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 224 225 ret = pci_request_region(pdev, 0, "ath9k"); 226 if (ret) { 227 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 228 ret = -ENODEV; 229 goto err_region; 230 } 231 232 mem = pci_iomap(pdev, 0, 0); 233 if (!mem) { 234 pr_err("PCI memory map error\n") ; 235 ret = -EIO; 236 goto err_iomap; 237 } 238 239 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 240 if (!hw) { 241 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 242 ret = -ENOMEM; 243 goto err_alloc_hw; 244 } 245 246 SET_IEEE80211_DEV(hw, &pdev->dev); 247 pci_set_drvdata(pdev, hw); 248 249 sc = hw->priv; 250 sc->hw = hw; 251 sc->dev = &pdev->dev; 252 sc->mem = mem; 253 254 /* Will be cleared in ath9k_start() */ 255 set_bit(SC_OP_INVALID, &sc->sc_flags); 256 257 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 258 if (ret) { 259 dev_err(&pdev->dev, "request_irq failed\n"); 260 goto err_irq; 261 } 262 263 sc->irq = pdev->irq; 264 265 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 266 if (ret) { 267 dev_err(&pdev->dev, "Failed to initialize device\n"); 268 goto err_init; 269 } 270 271 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 272 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 273 hw_name, (unsigned long)mem, pdev->irq); 274 275 return 0; 276 277 err_init: 278 free_irq(sc->irq, sc); 279 err_irq: 280 ieee80211_free_hw(hw); 281 err_alloc_hw: 282 pci_iounmap(pdev, mem); 283 err_iomap: 284 pci_release_region(pdev, 0); 285 err_region: 286 /* Nothing */ 287 err_dma: 288 pci_disable_device(pdev); 289 return ret; 290 } 291 292 static void ath_pci_remove(struct pci_dev *pdev) 293 { 294 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 295 struct ath_softc *sc = hw->priv; 296 void __iomem *mem = sc->mem; 297 298 if (!is_ath9k_unloaded) 299 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 300 ath9k_deinit_device(sc); 301 free_irq(sc->irq, sc); 302 ieee80211_free_hw(sc->hw); 303 304 pci_iounmap(pdev, mem); 305 pci_disable_device(pdev); 306 pci_release_region(pdev, 0); 307 } 308 309 #ifdef CONFIG_PM 310 311 static int ath_pci_suspend(struct device *device) 312 { 313 struct pci_dev *pdev = to_pci_dev(device); 314 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 315 struct ath_softc *sc = hw->priv; 316 317 if (sc->wow_enabled) 318 return 0; 319 320 /* The device has to be moved to FULLSLEEP forcibly. 321 * Otherwise the chip never moved to full sleep, 322 * when no interface is up. 323 */ 324 ath9k_stop_btcoex(sc); 325 ath9k_hw_disable(sc->sc_ah); 326 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 327 328 return 0; 329 } 330 331 static int ath_pci_resume(struct device *device) 332 { 333 struct pci_dev *pdev = to_pci_dev(device); 334 u32 val; 335 336 /* 337 * Suspend/Resume resets the PCI configuration space, so we have to 338 * re-disable the RETRY_TIMEOUT register (0x41) to keep 339 * PCI Tx retries from interfering with C3 CPU state 340 */ 341 pci_read_config_dword(pdev, 0x40, &val); 342 if ((val & 0x0000ff00) != 0) 343 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 344 345 return 0; 346 } 347 348 static const struct dev_pm_ops ath9k_pm_ops = { 349 .suspend = ath_pci_suspend, 350 .resume = ath_pci_resume, 351 .freeze = ath_pci_suspend, 352 .thaw = ath_pci_resume, 353 .poweroff = ath_pci_suspend, 354 .restore = ath_pci_resume, 355 }; 356 357 #define ATH9K_PM_OPS (&ath9k_pm_ops) 358 359 #else /* !CONFIG_PM */ 360 361 #define ATH9K_PM_OPS NULL 362 363 #endif /* !CONFIG_PM */ 364 365 366 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 367 368 static struct pci_driver ath_pci_driver = { 369 .name = "ath9k", 370 .id_table = ath_pci_id_table, 371 .probe = ath_pci_probe, 372 .remove = ath_pci_remove, 373 .driver.pm = ATH9K_PM_OPS, 374 }; 375 376 int ath_pci_init(void) 377 { 378 return pci_register_driver(&ath_pci_driver); 379 } 380 381 void ath_pci_exit(void) 382 { 383 pci_unregister_driver(&ath_pci_driver); 384 } 385