1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/ath9k_platform.h> 21 #include "ath9k.h" 22 23 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 24 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 25 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 26 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 27 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 30 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 31 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 32 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 35 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 36 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 37 { 0 } 38 }; 39 40 41 /* return bus cachesize in 4B word units */ 42 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 43 { 44 struct ath_softc *sc = (struct ath_softc *) common->priv; 45 u8 u8tmp; 46 47 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 48 *csz = (int)u8tmp; 49 50 /* 51 * This check was put in to avoid "unpleasant" consequences if 52 * the bootrom has not fully initialized all PCI devices. 53 * Sometimes the cache line size register is not set 54 */ 55 56 if (*csz == 0) 57 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 58 } 59 60 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 61 { 62 struct ath_softc *sc = (struct ath_softc *) common->priv; 63 struct ath9k_platform_data *pdata = sc->dev->platform_data; 64 65 if (pdata) { 66 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 67 ath_err(common, 68 "%s: eeprom read failed, offset %08x is out of range\n", 69 __func__, off); 70 } 71 72 *data = pdata->eeprom_data[off]; 73 } else { 74 struct ath_hw *ah = (struct ath_hw *) common->ah; 75 76 common->ops->read(ah, AR5416_EEPROM_OFFSET + 77 (off << AR5416_EEPROM_S)); 78 79 if (!ath9k_hw_wait(ah, 80 AR_EEPROM_STATUS_DATA, 81 AR_EEPROM_STATUS_DATA_BUSY | 82 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 83 AH_WAIT_TIMEOUT)) { 84 return false; 85 } 86 87 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 88 AR_EEPROM_STATUS_DATA_VAL); 89 } 90 91 return true; 92 } 93 94 static void ath_pci_extn_synch_enable(struct ath_common *common) 95 { 96 struct ath_softc *sc = (struct ath_softc *) common->priv; 97 struct pci_dev *pdev = to_pci_dev(sc->dev); 98 u8 lnkctl; 99 100 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl); 101 lnkctl |= PCI_EXP_LNKCTL_ES; 102 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); 103 } 104 105 /* Need to be called after we discover btcoex capabilities */ 106 static void ath_pci_aspm_init(struct ath_common *common) 107 { 108 struct ath_softc *sc = (struct ath_softc *) common->priv; 109 struct ath_hw *ah = sc->sc_ah; 110 struct pci_dev *pdev = to_pci_dev(sc->dev); 111 struct pci_dev *parent; 112 int pos; 113 u8 aspm; 114 115 pos = pci_pcie_cap(pdev); 116 if (!pos) 117 return; 118 119 parent = pdev->bus->self; 120 if (!parent) 121 return; 122 123 if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) { 124 /* Bluetooth coexistance requires disabling ASPM. */ 125 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); 126 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 127 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm); 128 129 /* 130 * Both upstream and downstream PCIe components should 131 * have the same ASPM settings. 132 */ 133 pos = pci_pcie_cap(parent); 134 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 135 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 136 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); 137 138 return; 139 } 140 141 pos = pci_pcie_cap(parent); 142 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 143 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 144 ah->aspm_enabled = true; 145 /* Initialize PCIe PM and SERDES registers. */ 146 ath9k_hw_configpcipowersave(ah, false); 147 } 148 } 149 150 static const struct ath_bus_ops ath_pci_bus_ops = { 151 .ath_bus_type = ATH_PCI, 152 .read_cachesize = ath_pci_read_cachesize, 153 .eeprom_read = ath_pci_eeprom_read, 154 .extn_synch_en = ath_pci_extn_synch_enable, 155 .aspm_init = ath_pci_aspm_init, 156 }; 157 158 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 159 { 160 void __iomem *mem; 161 struct ath_softc *sc; 162 struct ieee80211_hw *hw; 163 u8 csz; 164 u32 val; 165 int ret = 0; 166 char hw_name[64]; 167 168 if (pci_enable_device(pdev)) 169 return -EIO; 170 171 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 172 if (ret) { 173 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 174 goto err_dma; 175 } 176 177 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 178 if (ret) { 179 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 180 "DMA enable failed\n"); 181 goto err_dma; 182 } 183 184 /* 185 * Cache line size is used to size and align various 186 * structures used to communicate with the hardware. 187 */ 188 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 189 if (csz == 0) { 190 /* 191 * Linux 2.4.18 (at least) writes the cache line size 192 * register as a 16-bit wide register which is wrong. 193 * We must have this setup properly for rx buffer 194 * DMA to work so force a reasonable value here if it 195 * comes up zero. 196 */ 197 csz = L1_CACHE_BYTES / sizeof(u32); 198 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 199 } 200 /* 201 * The default setting of latency timer yields poor results, 202 * set it to the value used by other systems. It may be worth 203 * tweaking this setting more. 204 */ 205 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 206 207 pci_set_master(pdev); 208 209 /* 210 * Disable the RETRY_TIMEOUT register (0x41) to keep 211 * PCI Tx retries from interfering with C3 CPU state. 212 */ 213 pci_read_config_dword(pdev, 0x40, &val); 214 if ((val & 0x0000ff00) != 0) 215 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 216 217 ret = pci_request_region(pdev, 0, "ath9k"); 218 if (ret) { 219 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 220 ret = -ENODEV; 221 goto err_region; 222 } 223 224 mem = pci_iomap(pdev, 0, 0); 225 if (!mem) { 226 printk(KERN_ERR "PCI memory map error\n") ; 227 ret = -EIO; 228 goto err_iomap; 229 } 230 231 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 232 if (!hw) { 233 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 234 ret = -ENOMEM; 235 goto err_alloc_hw; 236 } 237 238 SET_IEEE80211_DEV(hw, &pdev->dev); 239 pci_set_drvdata(pdev, hw); 240 241 sc = hw->priv; 242 sc->hw = hw; 243 sc->dev = &pdev->dev; 244 sc->mem = mem; 245 246 /* Will be cleared in ath9k_start() */ 247 sc->sc_flags |= SC_OP_INVALID; 248 249 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 250 if (ret) { 251 dev_err(&pdev->dev, "request_irq failed\n"); 252 goto err_irq; 253 } 254 255 sc->irq = pdev->irq; 256 257 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 258 if (ret) { 259 dev_err(&pdev->dev, "Failed to initialize device\n"); 260 goto err_init; 261 } 262 263 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 264 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 265 hw_name, (unsigned long)mem, pdev->irq); 266 267 return 0; 268 269 err_init: 270 free_irq(sc->irq, sc); 271 err_irq: 272 ieee80211_free_hw(hw); 273 err_alloc_hw: 274 pci_iounmap(pdev, mem); 275 err_iomap: 276 pci_release_region(pdev, 0); 277 err_region: 278 /* Nothing */ 279 err_dma: 280 pci_disable_device(pdev); 281 return ret; 282 } 283 284 static void ath_pci_remove(struct pci_dev *pdev) 285 { 286 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 287 struct ath_softc *sc = hw->priv; 288 void __iomem *mem = sc->mem; 289 290 if (!is_ath9k_unloaded) 291 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 292 ath9k_deinit_device(sc); 293 free_irq(sc->irq, sc); 294 ieee80211_free_hw(sc->hw); 295 296 pci_iounmap(pdev, mem); 297 pci_disable_device(pdev); 298 pci_release_region(pdev, 0); 299 } 300 301 #ifdef CONFIG_PM 302 303 static int ath_pci_suspend(struct device *device) 304 { 305 struct pci_dev *pdev = to_pci_dev(device); 306 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 307 struct ath_softc *sc = hw->priv; 308 309 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 310 311 /* The device has to be moved to FULLSLEEP forcibly. 312 * Otherwise the chip never moved to full sleep, 313 * when no interface is up. 314 */ 315 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 316 317 return 0; 318 } 319 320 static int ath_pci_resume(struct device *device) 321 { 322 struct pci_dev *pdev = to_pci_dev(device); 323 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 324 struct ath_softc *sc = hw->priv; 325 u32 val; 326 327 /* 328 * Suspend/Resume resets the PCI configuration space, so we have to 329 * re-disable the RETRY_TIMEOUT register (0x41) to keep 330 * PCI Tx retries from interfering with C3 CPU state 331 */ 332 pci_read_config_dword(pdev, 0x40, &val); 333 if ((val & 0x0000ff00) != 0) 334 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 335 336 ath9k_ps_wakeup(sc); 337 /* Enable LED */ 338 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, 339 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 340 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0); 341 342 /* 343 * Reset key cache to sane defaults (all entries cleared) instead of 344 * semi-random values after suspend/resume. 345 */ 346 ath9k_cmn_init_crypto(sc->sc_ah); 347 ath9k_ps_restore(sc); 348 349 sc->ps_idle = true; 350 ath_radio_disable(sc, hw); 351 352 return 0; 353 } 354 355 static const struct dev_pm_ops ath9k_pm_ops = { 356 .suspend = ath_pci_suspend, 357 .resume = ath_pci_resume, 358 .freeze = ath_pci_suspend, 359 .thaw = ath_pci_resume, 360 .poweroff = ath_pci_suspend, 361 .restore = ath_pci_resume, 362 }; 363 364 #define ATH9K_PM_OPS (&ath9k_pm_ops) 365 366 #else /* !CONFIG_PM */ 367 368 #define ATH9K_PM_OPS NULL 369 370 #endif /* !CONFIG_PM */ 371 372 373 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 374 375 static struct pci_driver ath_pci_driver = { 376 .name = "ath9k", 377 .id_table = ath_pci_id_table, 378 .probe = ath_pci_probe, 379 .remove = ath_pci_remove, 380 .driver.pm = ATH9K_PM_OPS, 381 }; 382 383 int ath_pci_init(void) 384 { 385 return pci_register_driver(&ath_pci_driver); 386 } 387 388 void ath_pci_exit(void) 389 { 390 pci_unregister_driver(&ath_pci_driver); 391 } 392