xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/main.c (revision da2ef666)
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21 
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 	/*
25 	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 	 *   0 for no restriction
27 	 *   1 for 1/4 us
28 	 *   2 for 1/2 us
29 	 *   3 for 1 us
30 	 *   4 for 2 us
31 	 *   5 for 4 us
32 	 *   6 for 8 us
33 	 *   7 for 16 us
34 	 */
35 	switch (mpdudensity) {
36 	case 0:
37 		return 0;
38 	case 1:
39 	case 2:
40 	case 3:
41 		/* Our lower layer calculations limit our precision to
42 		   1 microsecond */
43 		return 1;
44 	case 4:
45 		return 2;
46 	case 5:
47 		return 4;
48 	case 6:
49 		return 8;
50 	case 7:
51 		return 16;
52 	default:
53 		return 0;
54 	}
55 }
56 
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 				     bool sw_pending)
59 {
60 	bool pending = false;
61 
62 	spin_lock_bh(&txq->axq_lock);
63 
64 	if (txq->axq_depth) {
65 		pending = true;
66 		goto out;
67 	}
68 
69 	if (!sw_pending)
70 		goto out;
71 
72 	if (txq->mac80211_qnum >= 0) {
73 		struct ath_acq *acq;
74 
75 		acq = &sc->cur_chan->acq[txq->mac80211_qnum];
76 		if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
77 			pending = true;
78 	}
79 out:
80 	spin_unlock_bh(&txq->axq_lock);
81 	return pending;
82 }
83 
84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 	unsigned long flags;
87 	bool ret;
88 
89 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 	ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92 
93 	return ret;
94 }
95 
96 void ath_ps_full_sleep(struct timer_list *t)
97 {
98 	struct ath_softc *sc = from_timer(sc, t, sleep_timer);
99 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 	unsigned long flags;
101 	bool reset;
102 
103 	spin_lock_irqsave(&common->cc_lock, flags);
104 	ath_hw_cycle_counters_update(common);
105 	spin_unlock_irqrestore(&common->cc_lock, flags);
106 
107 	ath9k_hw_setrxabort(sc->sc_ah, 1);
108 	ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
109 
110 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
111 }
112 
113 void ath9k_ps_wakeup(struct ath_softc *sc)
114 {
115 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
116 	unsigned long flags;
117 	enum ath9k_power_mode power_mode;
118 
119 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
120 	if (++sc->ps_usecount != 1)
121 		goto unlock;
122 
123 	del_timer_sync(&sc->sleep_timer);
124 	power_mode = sc->sc_ah->power_mode;
125 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
126 
127 	/*
128 	 * While the hardware is asleep, the cycle counters contain no
129 	 * useful data. Better clear them now so that they don't mess up
130 	 * survey data results.
131 	 */
132 	if (power_mode != ATH9K_PM_AWAKE) {
133 		spin_lock(&common->cc_lock);
134 		ath_hw_cycle_counters_update(common);
135 		memset(&common->cc_survey, 0, sizeof(common->cc_survey));
136 		memset(&common->cc_ani, 0, sizeof(common->cc_ani));
137 		spin_unlock(&common->cc_lock);
138 	}
139 
140  unlock:
141 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
142 }
143 
144 void ath9k_ps_restore(struct ath_softc *sc)
145 {
146 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
147 	enum ath9k_power_mode mode;
148 	unsigned long flags;
149 
150 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
151 	if (--sc->ps_usecount != 0)
152 		goto unlock;
153 
154 	if (sc->ps_idle) {
155 		mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
156 		goto unlock;
157 	}
158 
159 	if (sc->ps_enabled &&
160 		   !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
161 				     PS_WAIT_FOR_CAB |
162 				     PS_WAIT_FOR_PSPOLL_DATA |
163 				     PS_WAIT_FOR_TX_ACK |
164 				     PS_WAIT_FOR_ANI))) {
165 		mode = ATH9K_PM_NETWORK_SLEEP;
166 		if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
167 			ath9k_btcoex_stop_gen_timer(sc);
168 	} else {
169 		goto unlock;
170 	}
171 
172 	spin_lock(&common->cc_lock);
173 	ath_hw_cycle_counters_update(common);
174 	spin_unlock(&common->cc_lock);
175 
176 	ath9k_hw_setpower(sc->sc_ah, mode);
177 
178  unlock:
179 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
180 }
181 
182 static void __ath_cancel_work(struct ath_softc *sc)
183 {
184 	cancel_work_sync(&sc->paprd_work);
185 	cancel_delayed_work_sync(&sc->hw_check_work);
186 	cancel_delayed_work_sync(&sc->hw_pll_work);
187 
188 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
189 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
190 		cancel_work_sync(&sc->mci_work);
191 #endif
192 }
193 
194 void ath_cancel_work(struct ath_softc *sc)
195 {
196 	__ath_cancel_work(sc);
197 	cancel_work_sync(&sc->hw_reset_work);
198 }
199 
200 void ath_restart_work(struct ath_softc *sc)
201 {
202 	ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
203 				     ATH_HW_CHECK_POLL_INT);
204 
205 	if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
206 		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
207 				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
208 
209 	ath_start_ani(sc);
210 }
211 
212 static bool ath_prepare_reset(struct ath_softc *sc)
213 {
214 	struct ath_hw *ah = sc->sc_ah;
215 	bool ret = true;
216 
217 	ieee80211_stop_queues(sc->hw);
218 	ath_stop_ani(sc);
219 	ath9k_hw_disable_interrupts(ah);
220 
221 	if (AR_SREV_9300_20_OR_LATER(ah)) {
222 		ret &= ath_stoprecv(sc);
223 		ret &= ath_drain_all_txq(sc);
224 	} else {
225 		ret &= ath_drain_all_txq(sc);
226 		ret &= ath_stoprecv(sc);
227 	}
228 
229 	return ret;
230 }
231 
232 static bool ath_complete_reset(struct ath_softc *sc, bool start)
233 {
234 	struct ath_hw *ah = sc->sc_ah;
235 	struct ath_common *common = ath9k_hw_common(ah);
236 	unsigned long flags;
237 
238 	ath9k_calculate_summary_state(sc, sc->cur_chan);
239 	ath_startrecv(sc);
240 	ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
241 			       sc->cur_chan->txpower,
242 			       &sc->cur_chan->cur_txpower);
243 	clear_bit(ATH_OP_HW_RESET, &common->op_flags);
244 
245 	if (!sc->cur_chan->offchannel && start) {
246 		/* restore per chanctx TSF timer */
247 		if (sc->cur_chan->tsf_val) {
248 			u32 offset;
249 
250 			offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
251 							 NULL);
252 			ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
253 		}
254 
255 
256 		if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
257 			goto work;
258 
259 		if (ah->opmode == NL80211_IFTYPE_STATION &&
260 		    test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
261 			spin_lock_irqsave(&sc->sc_pm_lock, flags);
262 			sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
263 			spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
264 		} else {
265 			ath9k_set_beacon(sc);
266 		}
267 	work:
268 		ath_restart_work(sc);
269 		ath_txq_schedule_all(sc);
270 	}
271 
272 	sc->gtt_cnt = 0;
273 
274 	ath9k_hw_set_interrupts(ah);
275 	ath9k_hw_enable_interrupts(ah);
276 	ieee80211_wake_queues(sc->hw);
277 	ath9k_p2p_ps_timer(sc);
278 
279 	return true;
280 }
281 
282 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
283 {
284 	struct ath_hw *ah = sc->sc_ah;
285 	struct ath_common *common = ath9k_hw_common(ah);
286 	struct ath9k_hw_cal_data *caldata = NULL;
287 	bool fastcc = true;
288 	int r;
289 
290 	__ath_cancel_work(sc);
291 
292 	disable_irq(sc->irq);
293 	tasklet_disable(&sc->intr_tq);
294 	tasklet_disable(&sc->bcon_tasklet);
295 	spin_lock_bh(&sc->sc_pcu_lock);
296 
297 	if (!sc->cur_chan->offchannel) {
298 		fastcc = false;
299 		caldata = &sc->cur_chan->caldata;
300 	}
301 
302 	if (!hchan) {
303 		fastcc = false;
304 		hchan = ah->curchan;
305 	}
306 
307 	if (!ath_prepare_reset(sc))
308 		fastcc = false;
309 
310 	if (ath9k_is_chanctx_enabled())
311 		fastcc = false;
312 
313 	spin_lock_bh(&sc->chan_lock);
314 	sc->cur_chandef = sc->cur_chan->chandef;
315 	spin_unlock_bh(&sc->chan_lock);
316 
317 	ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
318 		hchan->channel, IS_CHAN_HT40(hchan), fastcc);
319 
320 	r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
321 	if (r) {
322 		ath_err(common,
323 			"Unable to reset channel, reset status %d\n", r);
324 
325 		ath9k_hw_enable_interrupts(ah);
326 		ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
327 
328 		goto out;
329 	}
330 
331 	if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
332 	    sc->cur_chan->offchannel)
333 		ath9k_mci_set_txpower(sc, true, false);
334 
335 	if (!ath_complete_reset(sc, true))
336 		r = -EIO;
337 
338 out:
339 	enable_irq(sc->irq);
340 	spin_unlock_bh(&sc->sc_pcu_lock);
341 	tasklet_enable(&sc->bcon_tasklet);
342 	tasklet_enable(&sc->intr_tq);
343 
344 	return r;
345 }
346 
347 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
348 			    struct ieee80211_vif *vif)
349 {
350 	struct ath_node *an;
351 	an = (struct ath_node *)sta->drv_priv;
352 
353 	an->sc = sc;
354 	an->sta = sta;
355 	an->vif = vif;
356 	memset(&an->key_idx, 0, sizeof(an->key_idx));
357 
358 	ath_tx_node_init(sc, an);
359 
360 	ath_dynack_node_init(sc->sc_ah, an);
361 }
362 
363 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
364 {
365 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
366 	ath_tx_node_cleanup(sc, an);
367 
368 	ath_dynack_node_deinit(sc->sc_ah, an);
369 }
370 
371 void ath9k_tasklet(unsigned long data)
372 {
373 	struct ath_softc *sc = (struct ath_softc *)data;
374 	struct ath_hw *ah = sc->sc_ah;
375 	struct ath_common *common = ath9k_hw_common(ah);
376 	enum ath_reset_type type;
377 	unsigned long flags;
378 	u32 status;
379 	u32 rxmask;
380 
381 	spin_lock_irqsave(&sc->intr_lock, flags);
382 	status = sc->intrstatus;
383 	sc->intrstatus = 0;
384 	spin_unlock_irqrestore(&sc->intr_lock, flags);
385 
386 	ath9k_ps_wakeup(sc);
387 	spin_lock(&sc->sc_pcu_lock);
388 
389 	if (status & ATH9K_INT_FATAL) {
390 		type = RESET_TYPE_FATAL_INT;
391 		ath9k_queue_reset(sc, type);
392 		ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
393 		goto out;
394 	}
395 
396 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
397 	    (status & ATH9K_INT_BB_WATCHDOG)) {
398 		spin_lock_irqsave(&common->cc_lock, flags);
399 		ath_hw_cycle_counters_update(common);
400 		ar9003_hw_bb_watchdog_dbg_info(ah);
401 		spin_unlock_irqrestore(&common->cc_lock, flags);
402 
403 		if (ar9003_hw_bb_watchdog_check(ah)) {
404 			type = RESET_TYPE_BB_WATCHDOG;
405 			ath9k_queue_reset(sc, type);
406 
407 			ath_dbg(common, RESET,
408 				"BB_WATCHDOG: Skipping interrupts\n");
409 			goto out;
410 		}
411 	}
412 
413 	if (status & ATH9K_INT_GTT) {
414 		sc->gtt_cnt++;
415 
416 		if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
417 			type = RESET_TYPE_TX_GTT;
418 			ath9k_queue_reset(sc, type);
419 			ath_dbg(common, RESET,
420 				"GTT: Skipping interrupts\n");
421 			goto out;
422 		}
423 	}
424 
425 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
426 	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
427 		/*
428 		 * TSF sync does not look correct; remain awake to sync with
429 		 * the next Beacon.
430 		 */
431 		ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
432 		sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
433 	}
434 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
435 
436 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
437 		rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
438 			  ATH9K_INT_RXORN);
439 	else
440 		rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
441 
442 	if (status & rxmask) {
443 		/* Check for high priority Rx first */
444 		if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
445 		    (status & ATH9K_INT_RXHP))
446 			ath_rx_tasklet(sc, 0, true);
447 
448 		ath_rx_tasklet(sc, 0, false);
449 	}
450 
451 	if (status & ATH9K_INT_TX) {
452 		if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
453 			/*
454 			 * For EDMA chips, TX completion is enabled for the
455 			 * beacon queue, so if a beacon has been transmitted
456 			 * successfully after a GTT interrupt, the GTT counter
457 			 * gets reset to zero here.
458 			 */
459 			sc->gtt_cnt = 0;
460 
461 			ath_tx_edma_tasklet(sc);
462 		} else {
463 			ath_tx_tasklet(sc);
464 		}
465 
466 		wake_up(&sc->tx_wait);
467 	}
468 
469 	if (status & ATH9K_INT_GENTIMER)
470 		ath_gen_timer_isr(sc->sc_ah);
471 
472 	ath9k_btcoex_handle_interrupt(sc, status);
473 
474 	/* re-enable hardware interrupt */
475 	ath9k_hw_resume_interrupts(ah);
476 out:
477 	spin_unlock(&sc->sc_pcu_lock);
478 	ath9k_ps_restore(sc);
479 }
480 
481 irqreturn_t ath_isr(int irq, void *dev)
482 {
483 #define SCHED_INTR (				\
484 		ATH9K_INT_FATAL |		\
485 		ATH9K_INT_BB_WATCHDOG |		\
486 		ATH9K_INT_RXORN |		\
487 		ATH9K_INT_RXEOL |		\
488 		ATH9K_INT_RX |			\
489 		ATH9K_INT_RXLP |		\
490 		ATH9K_INT_RXHP |		\
491 		ATH9K_INT_TX |			\
492 		ATH9K_INT_BMISS |		\
493 		ATH9K_INT_CST |			\
494 		ATH9K_INT_GTT |			\
495 		ATH9K_INT_TSFOOR |		\
496 		ATH9K_INT_GENTIMER |		\
497 		ATH9K_INT_MCI)
498 
499 	struct ath_softc *sc = dev;
500 	struct ath_hw *ah = sc->sc_ah;
501 	struct ath_common *common = ath9k_hw_common(ah);
502 	enum ath9k_int status;
503 	u32 sync_cause = 0;
504 	bool sched = false;
505 
506 	/*
507 	 * The hardware is not ready/present, don't
508 	 * touch anything. Note this can happen early
509 	 * on if the IRQ is shared.
510 	 */
511 	if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
512 		return IRQ_NONE;
513 
514 	/* shared irq, not for us */
515 	if (!ath9k_hw_intrpend(ah))
516 		return IRQ_NONE;
517 
518 	/*
519 	 * Figure out the reason(s) for the interrupt.  Note
520 	 * that the hal returns a pseudo-ISR that may include
521 	 * bits we haven't explicitly enabled so we mask the
522 	 * value to insure we only process bits we requested.
523 	 */
524 	ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
525 	ath9k_debug_sync_cause(sc, sync_cause);
526 	status &= ah->imask;	/* discard unasked-for bits */
527 
528 	if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
529 		return IRQ_HANDLED;
530 
531 	/*
532 	 * If there are no status bits set, then this interrupt was not
533 	 * for me (should have been caught above).
534 	 */
535 	if (!status)
536 		return IRQ_NONE;
537 
538 	/* Cache the status */
539 	spin_lock(&sc->intr_lock);
540 	sc->intrstatus |= status;
541 	spin_unlock(&sc->intr_lock);
542 
543 	if (status & SCHED_INTR)
544 		sched = true;
545 
546 	/*
547 	 * If a FATAL interrupt is received, we have to reset the chip
548 	 * immediately.
549 	 */
550 	if (status & ATH9K_INT_FATAL)
551 		goto chip_reset;
552 
553 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
554 	    (status & ATH9K_INT_BB_WATCHDOG))
555 		goto chip_reset;
556 
557 	if (status & ATH9K_INT_SWBA)
558 		tasklet_schedule(&sc->bcon_tasklet);
559 
560 	if (status & ATH9K_INT_TXURN)
561 		ath9k_hw_updatetxtriglevel(ah, true);
562 
563 	if (status & ATH9K_INT_RXEOL) {
564 		ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
565 		ath9k_hw_set_interrupts(ah);
566 	}
567 
568 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
569 		if (status & ATH9K_INT_TIM_TIMER) {
570 			if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
571 				goto chip_reset;
572 			/* Clear RxAbort bit so that we can
573 			 * receive frames */
574 			ath9k_setpower(sc, ATH9K_PM_AWAKE);
575 			spin_lock(&sc->sc_pm_lock);
576 			ath9k_hw_setrxabort(sc->sc_ah, 0);
577 			sc->ps_flags |= PS_WAIT_FOR_BEACON;
578 			spin_unlock(&sc->sc_pm_lock);
579 		}
580 
581 chip_reset:
582 
583 	ath_debug_stat_interrupt(sc, status);
584 
585 	if (sched) {
586 		/* turn off every interrupt */
587 		ath9k_hw_kill_interrupts(ah);
588 		tasklet_schedule(&sc->intr_tq);
589 	}
590 
591 	return IRQ_HANDLED;
592 
593 #undef SCHED_INTR
594 }
595 
596 /*
597  * This function is called when a HW reset cannot be deferred
598  * and has to be immediate.
599  */
600 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
601 {
602 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
603 	int r;
604 
605 	ath9k_hw_kill_interrupts(sc->sc_ah);
606 	set_bit(ATH_OP_HW_RESET, &common->op_flags);
607 
608 	ath9k_ps_wakeup(sc);
609 	r = ath_reset_internal(sc, hchan);
610 	ath9k_ps_restore(sc);
611 
612 	return r;
613 }
614 
615 /*
616  * When a HW reset can be deferred, it is added to the
617  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
618  * queueing.
619  */
620 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
621 {
622 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
623 #ifdef CONFIG_ATH9K_DEBUGFS
624 	RESET_STAT_INC(sc, type);
625 #endif
626 	ath9k_hw_kill_interrupts(sc->sc_ah);
627 	set_bit(ATH_OP_HW_RESET, &common->op_flags);
628 	ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
629 }
630 
631 void ath_reset_work(struct work_struct *work)
632 {
633 	struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
634 
635 	ath9k_ps_wakeup(sc);
636 	ath_reset_internal(sc, NULL);
637 	ath9k_ps_restore(sc);
638 }
639 
640 /**********************/
641 /* mac80211 callbacks */
642 /**********************/
643 
644 static int ath9k_start(struct ieee80211_hw *hw)
645 {
646 	struct ath_softc *sc = hw->priv;
647 	struct ath_hw *ah = sc->sc_ah;
648 	struct ath_common *common = ath9k_hw_common(ah);
649 	struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
650 	struct ath_chanctx *ctx = sc->cur_chan;
651 	struct ath9k_channel *init_channel;
652 	int r;
653 
654 	ath_dbg(common, CONFIG,
655 		"Starting driver with initial channel: %d MHz\n",
656 		curchan->center_freq);
657 
658 	ath9k_ps_wakeup(sc);
659 	mutex_lock(&sc->mutex);
660 
661 	init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
662 	sc->cur_chandef = hw->conf.chandef;
663 
664 	/* Reset SERDES registers */
665 	ath9k_hw_configpcipowersave(ah, false);
666 
667 	/*
668 	 * The basic interface to setting the hardware in a good
669 	 * state is ``reset''.  On return the hardware is known to
670 	 * be powered up and with interrupts disabled.  This must
671 	 * be followed by initialization of the appropriate bits
672 	 * and then setup of the interrupt mask.
673 	 */
674 	spin_lock_bh(&sc->sc_pcu_lock);
675 
676 	atomic_set(&ah->intr_ref_cnt, -1);
677 
678 	r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
679 	if (r) {
680 		ath_err(common,
681 			"Unable to reset hardware; reset status %d (freq %u MHz)\n",
682 			r, curchan->center_freq);
683 		ah->reset_power_on = false;
684 	}
685 
686 	/* Setup our intr mask. */
687 	ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
688 		    ATH9K_INT_RXORN | ATH9K_INT_FATAL |
689 		    ATH9K_INT_GLOBAL;
690 
691 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
692 		ah->imask |= ATH9K_INT_RXHP |
693 			     ATH9K_INT_RXLP;
694 	else
695 		ah->imask |= ATH9K_INT_RX;
696 
697 	if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
698 		ah->imask |= ATH9K_INT_BB_WATCHDOG;
699 
700 	/*
701 	 * Enable GTT interrupts only for AR9003/AR9004 chips
702 	 * for now.
703 	 */
704 	if (AR_SREV_9300_20_OR_LATER(ah))
705 		ah->imask |= ATH9K_INT_GTT;
706 
707 	if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
708 		ah->imask |= ATH9K_INT_CST;
709 
710 	ath_mci_enable(sc);
711 
712 	clear_bit(ATH_OP_INVALID, &common->op_flags);
713 	sc->sc_ah->is_monitoring = false;
714 
715 	if (!ath_complete_reset(sc, false))
716 		ah->reset_power_on = false;
717 
718 	if (ah->led_pin >= 0) {
719 		ath9k_hw_set_gpio(ah, ah->led_pin,
720 				  (ah->config.led_active_high) ? 1 : 0);
721 		ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
722 					  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
723 	}
724 
725 	/*
726 	 * Reset key cache to sane defaults (all entries cleared) instead of
727 	 * semi-random values after suspend/resume.
728 	 */
729 	ath9k_cmn_init_crypto(sc->sc_ah);
730 
731 	ath9k_hw_reset_tsf(ah);
732 
733 	spin_unlock_bh(&sc->sc_pcu_lock);
734 
735 	ath9k_rng_start(sc);
736 
737 	mutex_unlock(&sc->mutex);
738 
739 	ath9k_ps_restore(sc);
740 
741 	return 0;
742 }
743 
744 static void ath9k_tx(struct ieee80211_hw *hw,
745 		     struct ieee80211_tx_control *control,
746 		     struct sk_buff *skb)
747 {
748 	struct ath_softc *sc = hw->priv;
749 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
750 	struct ath_tx_control txctl;
751 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
752 	unsigned long flags;
753 
754 	if (sc->ps_enabled) {
755 		/*
756 		 * mac80211 does not set PM field for normal data frames, so we
757 		 * need to update that based on the current PS mode.
758 		 */
759 		if (ieee80211_is_data(hdr->frame_control) &&
760 		    !ieee80211_is_nullfunc(hdr->frame_control) &&
761 		    !ieee80211_has_pm(hdr->frame_control)) {
762 			ath_dbg(common, PS,
763 				"Add PM=1 for a TX frame while in PS mode\n");
764 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
765 		}
766 	}
767 
768 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
769 		/*
770 		 * We are using PS-Poll and mac80211 can request TX while in
771 		 * power save mode. Need to wake up hardware for the TX to be
772 		 * completed and if needed, also for RX of buffered frames.
773 		 */
774 		ath9k_ps_wakeup(sc);
775 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
776 		if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
777 			ath9k_hw_setrxabort(sc->sc_ah, 0);
778 		if (ieee80211_is_pspoll(hdr->frame_control)) {
779 			ath_dbg(common, PS,
780 				"Sending PS-Poll to pick a buffered frame\n");
781 			sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
782 		} else {
783 			ath_dbg(common, PS, "Wake up to complete TX\n");
784 			sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
785 		}
786 		/*
787 		 * The actual restore operation will happen only after
788 		 * the ps_flags bit is cleared. We are just dropping
789 		 * the ps_usecount here.
790 		 */
791 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
792 		ath9k_ps_restore(sc);
793 	}
794 
795 	/*
796 	 * Cannot tx while the hardware is in full sleep, it first needs a full
797 	 * chip reset to recover from that
798 	 */
799 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
800 		ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
801 		goto exit;
802 	}
803 
804 	memset(&txctl, 0, sizeof(struct ath_tx_control));
805 	txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
806 	txctl.sta = control->sta;
807 
808 	ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
809 
810 	if (ath_tx_start(hw, skb, &txctl) != 0) {
811 		ath_dbg(common, XMIT, "TX failed\n");
812 		TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
813 		goto exit;
814 	}
815 
816 	return;
817 exit:
818 	ieee80211_free_txskb(hw, skb);
819 }
820 
821 static void ath9k_stop(struct ieee80211_hw *hw)
822 {
823 	struct ath_softc *sc = hw->priv;
824 	struct ath_hw *ah = sc->sc_ah;
825 	struct ath_common *common = ath9k_hw_common(ah);
826 	bool prev_idle;
827 
828 	ath9k_deinit_channel_context(sc);
829 
830 	mutex_lock(&sc->mutex);
831 
832 	ath9k_rng_stop(sc);
833 
834 	ath_cancel_work(sc);
835 
836 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
837 		ath_dbg(common, ANY, "Device not present\n");
838 		mutex_unlock(&sc->mutex);
839 		return;
840 	}
841 
842 	/* Ensure HW is awake when we try to shut it down. */
843 	ath9k_ps_wakeup(sc);
844 
845 	spin_lock_bh(&sc->sc_pcu_lock);
846 
847 	/* prevent tasklets to enable interrupts once we disable them */
848 	ah->imask &= ~ATH9K_INT_GLOBAL;
849 
850 	/* make sure h/w will not generate any interrupt
851 	 * before setting the invalid flag. */
852 	ath9k_hw_disable_interrupts(ah);
853 
854 	spin_unlock_bh(&sc->sc_pcu_lock);
855 
856 	/* we can now sync irq and kill any running tasklets, since we already
857 	 * disabled interrupts and not holding a spin lock */
858 	synchronize_irq(sc->irq);
859 	tasklet_kill(&sc->intr_tq);
860 	tasklet_kill(&sc->bcon_tasklet);
861 
862 	prev_idle = sc->ps_idle;
863 	sc->ps_idle = true;
864 
865 	spin_lock_bh(&sc->sc_pcu_lock);
866 
867 	if (ah->led_pin >= 0) {
868 		ath9k_hw_set_gpio(ah, ah->led_pin,
869 				  (ah->config.led_active_high) ? 0 : 1);
870 		ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
871 	}
872 
873 	ath_prepare_reset(sc);
874 
875 	if (sc->rx.frag) {
876 		dev_kfree_skb_any(sc->rx.frag);
877 		sc->rx.frag = NULL;
878 	}
879 
880 	if (!ah->curchan)
881 		ah->curchan = ath9k_cmn_get_channel(hw, ah,
882 						    &sc->cur_chan->chandef);
883 
884 	ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
885 
886 	set_bit(ATH_OP_INVALID, &common->op_flags);
887 
888 	ath9k_hw_phy_disable(ah);
889 
890 	ath9k_hw_configpcipowersave(ah, true);
891 
892 	spin_unlock_bh(&sc->sc_pcu_lock);
893 
894 	ath9k_ps_restore(sc);
895 
896 	sc->ps_idle = prev_idle;
897 
898 	mutex_unlock(&sc->mutex);
899 
900 	ath_dbg(common, CONFIG, "Driver halt\n");
901 }
902 
903 static bool ath9k_uses_beacons(int type)
904 {
905 	switch (type) {
906 	case NL80211_IFTYPE_AP:
907 	case NL80211_IFTYPE_ADHOC:
908 	case NL80211_IFTYPE_MESH_POINT:
909 		return true;
910 	default:
911 		return false;
912 	}
913 }
914 
915 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
916 				      struct ieee80211_vif *vif)
917 {
918 	/* Use the first (configured) interface, but prefering AP interfaces. */
919 	if (!iter_data->primary_beacon_vif) {
920 		iter_data->primary_beacon_vif = vif;
921 	} else {
922 		if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
923 		    vif->type == NL80211_IFTYPE_AP)
924 			iter_data->primary_beacon_vif = vif;
925 	}
926 
927 	iter_data->beacons = true;
928 	iter_data->nbcnvifs += 1;
929 }
930 
931 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
932 			   u8 *mac, struct ieee80211_vif *vif)
933 {
934 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
935 	int i;
936 
937 	if (iter_data->has_hw_macaddr) {
938 		for (i = 0; i < ETH_ALEN; i++)
939 			iter_data->mask[i] &=
940 				~(iter_data->hw_macaddr[i] ^ mac[i]);
941 	} else {
942 		memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
943 		iter_data->has_hw_macaddr = true;
944 	}
945 
946 	if (!vif->bss_conf.use_short_slot)
947 		iter_data->slottime = 20;
948 
949 	switch (vif->type) {
950 	case NL80211_IFTYPE_AP:
951 		iter_data->naps++;
952 		if (vif->bss_conf.enable_beacon)
953 			ath9k_vif_iter_set_beacon(iter_data, vif);
954 		break;
955 	case NL80211_IFTYPE_STATION:
956 		iter_data->nstations++;
957 		if (avp->assoc && !iter_data->primary_sta)
958 			iter_data->primary_sta = vif;
959 		break;
960 	case NL80211_IFTYPE_OCB:
961 		iter_data->nocbs++;
962 		break;
963 	case NL80211_IFTYPE_ADHOC:
964 		iter_data->nadhocs++;
965 		if (vif->bss_conf.enable_beacon)
966 			ath9k_vif_iter_set_beacon(iter_data, vif);
967 		break;
968 	case NL80211_IFTYPE_MESH_POINT:
969 		iter_data->nmeshes++;
970 		if (vif->bss_conf.enable_beacon)
971 			ath9k_vif_iter_set_beacon(iter_data, vif);
972 		break;
973 	case NL80211_IFTYPE_WDS:
974 		iter_data->nwds++;
975 		break;
976 	default:
977 		break;
978 	}
979 }
980 
981 static void ath9k_update_bssid_mask(struct ath_softc *sc,
982 				    struct ath_chanctx *ctx,
983 				    struct ath9k_vif_iter_data *iter_data)
984 {
985 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
986 	struct ath_vif *avp;
987 	int i;
988 
989 	if (!ath9k_is_chanctx_enabled())
990 		return;
991 
992 	list_for_each_entry(avp, &ctx->vifs, list) {
993 		if (ctx->nvifs_assigned != 1)
994 			continue;
995 
996 		if (!iter_data->has_hw_macaddr)
997 			continue;
998 
999 		ether_addr_copy(common->curbssid, avp->bssid);
1000 
1001 		/* perm_addr will be used as the p2p device address. */
1002 		for (i = 0; i < ETH_ALEN; i++)
1003 			iter_data->mask[i] &=
1004 				~(iter_data->hw_macaddr[i] ^
1005 				  sc->hw->wiphy->perm_addr[i]);
1006 	}
1007 }
1008 
1009 /* Called with sc->mutex held. */
1010 void ath9k_calculate_iter_data(struct ath_softc *sc,
1011 			       struct ath_chanctx *ctx,
1012 			       struct ath9k_vif_iter_data *iter_data)
1013 {
1014 	struct ath_vif *avp;
1015 
1016 	/*
1017 	 * The hardware will use primary station addr together with the
1018 	 * BSSID mask when matching addresses.
1019 	 */
1020 	memset(iter_data, 0, sizeof(*iter_data));
1021 	eth_broadcast_addr(iter_data->mask);
1022 	iter_data->slottime = 9;
1023 
1024 	list_for_each_entry(avp, &ctx->vifs, list)
1025 		ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1026 
1027 	ath9k_update_bssid_mask(sc, ctx, iter_data);
1028 }
1029 
1030 static void ath9k_set_assoc_state(struct ath_softc *sc,
1031 				  struct ieee80211_vif *vif, bool changed)
1032 {
1033 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1034 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1035 	unsigned long flags;
1036 
1037 	set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1038 
1039 	ether_addr_copy(common->curbssid, avp->bssid);
1040 	common->curaid = avp->aid;
1041 	ath9k_hw_write_associd(sc->sc_ah);
1042 
1043 	if (changed) {
1044 		common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1045 		sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1046 
1047 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
1048 		sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1049 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1050 	}
1051 
1052 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1053 		ath9k_mci_update_wlan_channels(sc, false);
1054 
1055 	ath_dbg(common, CONFIG,
1056 		"Primary Station interface: %pM, BSSID: %pM\n",
1057 		vif->addr, common->curbssid);
1058 }
1059 
1060 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1061 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1062 {
1063 	struct ath_hw *ah = sc->sc_ah;
1064 	struct ath_common *common = ath9k_hw_common(ah);
1065 	struct ieee80211_vif *vif = NULL;
1066 
1067 	ath9k_ps_wakeup(sc);
1068 
1069 	if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1070 		vif = sc->offchannel.scan_vif;
1071 	else
1072 		vif = sc->offchannel.roc_vif;
1073 
1074 	if (WARN_ON(!vif))
1075 		goto exit;
1076 
1077 	eth_zero_addr(common->curbssid);
1078 	eth_broadcast_addr(common->bssidmask);
1079 	memcpy(common->macaddr, vif->addr, ETH_ALEN);
1080 	common->curaid = 0;
1081 	ah->opmode = vif->type;
1082 	ah->imask &= ~ATH9K_INT_SWBA;
1083 	ah->imask &= ~ATH9K_INT_TSFOOR;
1084 	ah->slottime = 9;
1085 
1086 	ath_hw_setbssidmask(common);
1087 	ath9k_hw_setopmode(ah);
1088 	ath9k_hw_write_associd(sc->sc_ah);
1089 	ath9k_hw_set_interrupts(ah);
1090 	ath9k_hw_init_global_settings(ah);
1091 
1092 exit:
1093 	ath9k_ps_restore(sc);
1094 }
1095 #endif
1096 
1097 /* Called with sc->mutex held. */
1098 void ath9k_calculate_summary_state(struct ath_softc *sc,
1099 				   struct ath_chanctx *ctx)
1100 {
1101 	struct ath_hw *ah = sc->sc_ah;
1102 	struct ath_common *common = ath9k_hw_common(ah);
1103 	struct ath9k_vif_iter_data iter_data;
1104 
1105 	ath_chanctx_check_active(sc, ctx);
1106 
1107 	if (ctx != sc->cur_chan)
1108 		return;
1109 
1110 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1111 	if (ctx == &sc->offchannel.chan)
1112 		return ath9k_set_offchannel_state(sc);
1113 #endif
1114 
1115 	ath9k_ps_wakeup(sc);
1116 	ath9k_calculate_iter_data(sc, ctx, &iter_data);
1117 
1118 	if (iter_data.has_hw_macaddr)
1119 		memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1120 
1121 	memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1122 	ath_hw_setbssidmask(common);
1123 
1124 	if (iter_data.naps > 0) {
1125 		ath9k_hw_set_tsfadjust(ah, true);
1126 		ah->opmode = NL80211_IFTYPE_AP;
1127 	} else {
1128 		ath9k_hw_set_tsfadjust(ah, false);
1129 		if (iter_data.beacons)
1130 			ath9k_beacon_ensure_primary_slot(sc);
1131 
1132 		if (iter_data.nmeshes)
1133 			ah->opmode = NL80211_IFTYPE_MESH_POINT;
1134 		else if (iter_data.nocbs)
1135 			ah->opmode = NL80211_IFTYPE_OCB;
1136 		else if (iter_data.nwds)
1137 			ah->opmode = NL80211_IFTYPE_AP;
1138 		else if (iter_data.nadhocs)
1139 			ah->opmode = NL80211_IFTYPE_ADHOC;
1140 		else
1141 			ah->opmode = NL80211_IFTYPE_STATION;
1142 	}
1143 
1144 	ath9k_hw_setopmode(ah);
1145 
1146 	ctx->switch_after_beacon = false;
1147 	if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1148 		ah->imask |= ATH9K_INT_TSFOOR;
1149 	else {
1150 		ah->imask &= ~ATH9K_INT_TSFOOR;
1151 		if (iter_data.naps == 1 && iter_data.beacons)
1152 			ctx->switch_after_beacon = true;
1153 	}
1154 
1155 	if (ah->opmode == NL80211_IFTYPE_STATION) {
1156 		bool changed = (iter_data.primary_sta != ctx->primary_sta);
1157 
1158 		if (iter_data.primary_sta) {
1159 			iter_data.primary_beacon_vif = iter_data.primary_sta;
1160 			iter_data.beacons = true;
1161 			ath9k_set_assoc_state(sc, iter_data.primary_sta,
1162 					      changed);
1163 			ctx->primary_sta = iter_data.primary_sta;
1164 		} else {
1165 			ctx->primary_sta = NULL;
1166 			eth_zero_addr(common->curbssid);
1167 			common->curaid = 0;
1168 			ath9k_hw_write_associd(sc->sc_ah);
1169 			if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1170 				ath9k_mci_update_wlan_channels(sc, true);
1171 		}
1172 	}
1173 	sc->nbcnvifs = iter_data.nbcnvifs;
1174 	ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1175 			    iter_data.beacons);
1176 	ath9k_hw_set_interrupts(ah);
1177 
1178 	if (ah->slottime != iter_data.slottime) {
1179 		ah->slottime = iter_data.slottime;
1180 		ath9k_hw_init_global_settings(ah);
1181 	}
1182 
1183 	if (iter_data.primary_sta)
1184 		set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1185 	else
1186 		clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1187 
1188 	ath_dbg(common, CONFIG,
1189 		"macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1190 		common->macaddr, common->curbssid, common->bssidmask);
1191 
1192 	ath9k_ps_restore(sc);
1193 }
1194 
1195 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1196 {
1197 	int *power = data;
1198 
1199 	if (*power < vif->bss_conf.txpower)
1200 		*power = vif->bss_conf.txpower;
1201 }
1202 
1203 /* Called with sc->mutex held. */
1204 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1205 {
1206 	int power;
1207 	struct ath_hw *ah = sc->sc_ah;
1208 	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1209 
1210 	ath9k_ps_wakeup(sc);
1211 	if (ah->tpc_enabled) {
1212 		power = (vif) ? vif->bss_conf.txpower : -1;
1213 		ieee80211_iterate_active_interfaces_atomic(
1214 				sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1215 				ath9k_tpc_vif_iter, &power);
1216 		if (power == -1)
1217 			power = sc->hw->conf.power_level;
1218 	} else {
1219 		power = sc->hw->conf.power_level;
1220 	}
1221 	sc->cur_chan->txpower = 2 * power;
1222 	ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1223 	sc->cur_chan->cur_txpower = reg->max_power_level;
1224 	ath9k_ps_restore(sc);
1225 }
1226 
1227 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1228 				   struct ieee80211_vif *vif)
1229 {
1230 	int i;
1231 
1232 	if (!ath9k_is_chanctx_enabled())
1233 		return;
1234 
1235 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
1236 		vif->hw_queue[i] = i;
1237 
1238 	if (vif->type == NL80211_IFTYPE_AP ||
1239 	    vif->type == NL80211_IFTYPE_MESH_POINT)
1240 		vif->cab_queue = hw->queues - 2;
1241 	else
1242 		vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1243 }
1244 
1245 static int ath9k_add_interface(struct ieee80211_hw *hw,
1246 			       struct ieee80211_vif *vif)
1247 {
1248 	struct ath_softc *sc = hw->priv;
1249 	struct ath_hw *ah = sc->sc_ah;
1250 	struct ath_common *common = ath9k_hw_common(ah);
1251 	struct ath_vif *avp = (void *)vif->drv_priv;
1252 	struct ath_node *an = &avp->mcast_node;
1253 
1254 	mutex_lock(&sc->mutex);
1255 
1256 	if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1257 		if (sc->cur_chan->nvifs >= 1) {
1258 			mutex_unlock(&sc->mutex);
1259 			return -EOPNOTSUPP;
1260 		}
1261 		sc->tx99_vif = vif;
1262 	}
1263 
1264 	ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1265 	sc->cur_chan->nvifs++;
1266 
1267 	if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1268 		vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1269 
1270 	if (ath9k_uses_beacons(vif->type))
1271 		ath9k_beacon_assign_slot(sc, vif);
1272 
1273 	avp->vif = vif;
1274 	if (!ath9k_is_chanctx_enabled()) {
1275 		avp->chanctx = sc->cur_chan;
1276 		list_add_tail(&avp->list, &avp->chanctx->vifs);
1277 	}
1278 
1279 	ath9k_calculate_summary_state(sc, avp->chanctx);
1280 
1281 	ath9k_assign_hw_queues(hw, vif);
1282 
1283 	ath9k_set_txpower(sc, vif);
1284 
1285 	an->sc = sc;
1286 	an->sta = NULL;
1287 	an->vif = vif;
1288 	an->no_ps_filter = true;
1289 	ath_tx_node_init(sc, an);
1290 
1291 	mutex_unlock(&sc->mutex);
1292 	return 0;
1293 }
1294 
1295 static int ath9k_change_interface(struct ieee80211_hw *hw,
1296 				  struct ieee80211_vif *vif,
1297 				  enum nl80211_iftype new_type,
1298 				  bool p2p)
1299 {
1300 	struct ath_softc *sc = hw->priv;
1301 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1302 	struct ath_vif *avp = (void *)vif->drv_priv;
1303 
1304 	mutex_lock(&sc->mutex);
1305 
1306 	if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1307 		mutex_unlock(&sc->mutex);
1308 		return -EOPNOTSUPP;
1309 	}
1310 
1311 	ath_dbg(common, CONFIG, "Change Interface\n");
1312 
1313 	if (ath9k_uses_beacons(vif->type))
1314 		ath9k_beacon_remove_slot(sc, vif);
1315 
1316 	vif->type = new_type;
1317 	vif->p2p = p2p;
1318 
1319 	if (ath9k_uses_beacons(vif->type))
1320 		ath9k_beacon_assign_slot(sc, vif);
1321 
1322 	ath9k_assign_hw_queues(hw, vif);
1323 	ath9k_calculate_summary_state(sc, avp->chanctx);
1324 
1325 	ath9k_set_txpower(sc, vif);
1326 
1327 	mutex_unlock(&sc->mutex);
1328 	return 0;
1329 }
1330 
1331 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1332 				   struct ieee80211_vif *vif)
1333 {
1334 	struct ath_softc *sc = hw->priv;
1335 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1336 	struct ath_vif *avp = (void *)vif->drv_priv;
1337 
1338 	ath_dbg(common, CONFIG, "Detach Interface\n");
1339 
1340 	mutex_lock(&sc->mutex);
1341 
1342 	ath9k_p2p_remove_vif(sc, vif);
1343 
1344 	sc->cur_chan->nvifs--;
1345 	sc->tx99_vif = NULL;
1346 	if (!ath9k_is_chanctx_enabled())
1347 		list_del(&avp->list);
1348 
1349 	if (ath9k_uses_beacons(vif->type))
1350 		ath9k_beacon_remove_slot(sc, vif);
1351 
1352 	ath_tx_node_cleanup(sc, &avp->mcast_node);
1353 
1354 	ath9k_calculate_summary_state(sc, avp->chanctx);
1355 
1356 	ath9k_set_txpower(sc, NULL);
1357 
1358 	mutex_unlock(&sc->mutex);
1359 }
1360 
1361 static void ath9k_enable_ps(struct ath_softc *sc)
1362 {
1363 	struct ath_hw *ah = sc->sc_ah;
1364 	struct ath_common *common = ath9k_hw_common(ah);
1365 
1366 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
1367 		return;
1368 
1369 	sc->ps_enabled = true;
1370 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1371 		if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1372 			ah->imask |= ATH9K_INT_TIM_TIMER;
1373 			ath9k_hw_set_interrupts(ah);
1374 		}
1375 		ath9k_hw_setrxabort(ah, 1);
1376 	}
1377 	ath_dbg(common, PS, "PowerSave enabled\n");
1378 }
1379 
1380 static void ath9k_disable_ps(struct ath_softc *sc)
1381 {
1382 	struct ath_hw *ah = sc->sc_ah;
1383 	struct ath_common *common = ath9k_hw_common(ah);
1384 
1385 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
1386 		return;
1387 
1388 	sc->ps_enabled = false;
1389 	ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1390 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1391 		ath9k_hw_setrxabort(ah, 0);
1392 		sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1393 				  PS_WAIT_FOR_CAB |
1394 				  PS_WAIT_FOR_PSPOLL_DATA |
1395 				  PS_WAIT_FOR_TX_ACK);
1396 		if (ah->imask & ATH9K_INT_TIM_TIMER) {
1397 			ah->imask &= ~ATH9K_INT_TIM_TIMER;
1398 			ath9k_hw_set_interrupts(ah);
1399 		}
1400 	}
1401 	ath_dbg(common, PS, "PowerSave disabled\n");
1402 }
1403 
1404 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1405 {
1406 	struct ath_softc *sc = hw->priv;
1407 	struct ath_hw *ah = sc->sc_ah;
1408 	struct ath_common *common = ath9k_hw_common(ah);
1409 	struct ieee80211_conf *conf = &hw->conf;
1410 	struct ath_chanctx *ctx = sc->cur_chan;
1411 
1412 	ath9k_ps_wakeup(sc);
1413 	mutex_lock(&sc->mutex);
1414 
1415 	if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1416 		sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1417 		if (sc->ps_idle) {
1418 			ath_cancel_work(sc);
1419 			ath9k_stop_btcoex(sc);
1420 		} else {
1421 			ath9k_start_btcoex(sc);
1422 			/*
1423 			 * The chip needs a reset to properly wake up from
1424 			 * full sleep
1425 			 */
1426 			ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1427 		}
1428 	}
1429 
1430 	/*
1431 	 * We just prepare to enable PS. We have to wait until our AP has
1432 	 * ACK'd our null data frame to disable RX otherwise we'll ignore
1433 	 * those ACKs and end up retransmitting the same null data frames.
1434 	 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1435 	 */
1436 	if (changed & IEEE80211_CONF_CHANGE_PS) {
1437 		unsigned long flags;
1438 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
1439 		if (conf->flags & IEEE80211_CONF_PS)
1440 			ath9k_enable_ps(sc);
1441 		else
1442 			ath9k_disable_ps(sc);
1443 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1444 	}
1445 
1446 	if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1447 		if (conf->flags & IEEE80211_CONF_MONITOR) {
1448 			ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1449 			sc->sc_ah->is_monitoring = true;
1450 		} else {
1451 			ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1452 			sc->sc_ah->is_monitoring = false;
1453 		}
1454 	}
1455 
1456 	if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1457 		ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1458 		ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1459 	}
1460 
1461 	mutex_unlock(&sc->mutex);
1462 	ath9k_ps_restore(sc);
1463 
1464 	return 0;
1465 }
1466 
1467 #define SUPPORTED_FILTERS			\
1468 	(FIF_ALLMULTI |				\
1469 	FIF_CONTROL |				\
1470 	FIF_PSPOLL |				\
1471 	FIF_OTHER_BSS |				\
1472 	FIF_BCN_PRBRESP_PROMISC |		\
1473 	FIF_PROBE_REQ |				\
1474 	FIF_FCSFAIL)
1475 
1476 /* FIXME: sc->sc_full_reset ? */
1477 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1478 				   unsigned int changed_flags,
1479 				   unsigned int *total_flags,
1480 				   u64 multicast)
1481 {
1482 	struct ath_softc *sc = hw->priv;
1483 	struct ath_chanctx *ctx;
1484 	u32 rfilt;
1485 
1486 	changed_flags &= SUPPORTED_FILTERS;
1487 	*total_flags &= SUPPORTED_FILTERS;
1488 
1489 	spin_lock_bh(&sc->chan_lock);
1490 	ath_for_each_chanctx(sc, ctx)
1491 		ctx->rxfilter = *total_flags;
1492 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1493 	sc->offchannel.chan.rxfilter = *total_flags;
1494 #endif
1495 	spin_unlock_bh(&sc->chan_lock);
1496 
1497 	ath9k_ps_wakeup(sc);
1498 	rfilt = ath_calcrxfilter(sc);
1499 	ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1500 	ath9k_ps_restore(sc);
1501 
1502 	ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1503 		rfilt);
1504 }
1505 
1506 static int ath9k_sta_add(struct ieee80211_hw *hw,
1507 			 struct ieee80211_vif *vif,
1508 			 struct ieee80211_sta *sta)
1509 {
1510 	struct ath_softc *sc = hw->priv;
1511 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1512 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1513 	struct ieee80211_key_conf ps_key = { };
1514 	int key;
1515 
1516 	ath_node_attach(sc, sta, vif);
1517 
1518 	if (vif->type != NL80211_IFTYPE_AP &&
1519 	    vif->type != NL80211_IFTYPE_AP_VLAN)
1520 		return 0;
1521 
1522 	key = ath_key_config(common, vif, sta, &ps_key);
1523 	if (key > 0) {
1524 		an->ps_key = key;
1525 		an->key_idx[0] = key;
1526 	}
1527 
1528 	return 0;
1529 }
1530 
1531 static void ath9k_del_ps_key(struct ath_softc *sc,
1532 			     struct ieee80211_vif *vif,
1533 			     struct ieee80211_sta *sta)
1534 {
1535 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1536 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1537 	struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1538 
1539 	if (!an->ps_key)
1540 	    return;
1541 
1542 	ath_key_delete(common, &ps_key);
1543 	an->ps_key = 0;
1544 	an->key_idx[0] = 0;
1545 }
1546 
1547 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1548 			    struct ieee80211_vif *vif,
1549 			    struct ieee80211_sta *sta)
1550 {
1551 	struct ath_softc *sc = hw->priv;
1552 
1553 	ath9k_del_ps_key(sc, vif, sta);
1554 	ath_node_detach(sc, sta);
1555 
1556 	return 0;
1557 }
1558 
1559 static int ath9k_sta_state(struct ieee80211_hw *hw,
1560 			   struct ieee80211_vif *vif,
1561 			   struct ieee80211_sta *sta,
1562 			   enum ieee80211_sta_state old_state,
1563 			   enum ieee80211_sta_state new_state)
1564 {
1565 	struct ath_softc *sc = hw->priv;
1566 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1567 	int ret = 0;
1568 
1569 	if (old_state == IEEE80211_STA_NOTEXIST &&
1570 	    new_state == IEEE80211_STA_NONE) {
1571 		ret = ath9k_sta_add(hw, vif, sta);
1572 		ath_dbg(common, CONFIG,
1573 			"Add station: %pM\n", sta->addr);
1574 	} else if (old_state == IEEE80211_STA_NONE &&
1575 		   new_state == IEEE80211_STA_NOTEXIST) {
1576 		ret = ath9k_sta_remove(hw, vif, sta);
1577 		ath_dbg(common, CONFIG,
1578 			"Remove station: %pM\n", sta->addr);
1579 	}
1580 
1581 	if (ath9k_is_chanctx_enabled()) {
1582 		if (vif->type == NL80211_IFTYPE_STATION) {
1583 			if (old_state == IEEE80211_STA_ASSOC &&
1584 			    new_state == IEEE80211_STA_AUTHORIZED)
1585 				ath_chanctx_event(sc, vif,
1586 						  ATH_CHANCTX_EVENT_AUTHORIZED);
1587 		}
1588 	}
1589 
1590 	return ret;
1591 }
1592 
1593 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1594 				    struct ath_node *an,
1595 				    bool set)
1596 {
1597 	int i;
1598 
1599 	for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1600 		if (!an->key_idx[i])
1601 			continue;
1602 		ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1603 	}
1604 }
1605 
1606 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1607 			 struct ieee80211_vif *vif,
1608 			 enum sta_notify_cmd cmd,
1609 			 struct ieee80211_sta *sta)
1610 {
1611 	struct ath_softc *sc = hw->priv;
1612 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1613 
1614 	switch (cmd) {
1615 	case STA_NOTIFY_SLEEP:
1616 		an->sleeping = true;
1617 		ath_tx_aggr_sleep(sta, sc, an);
1618 		ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1619 		break;
1620 	case STA_NOTIFY_AWAKE:
1621 		ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1622 		an->sleeping = false;
1623 		ath_tx_aggr_wakeup(sc, an);
1624 		break;
1625 	}
1626 }
1627 
1628 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1629 			 struct ieee80211_vif *vif, u16 queue,
1630 			 const struct ieee80211_tx_queue_params *params)
1631 {
1632 	struct ath_softc *sc = hw->priv;
1633 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1634 	struct ath_txq *txq;
1635 	struct ath9k_tx_queue_info qi;
1636 	int ret = 0;
1637 
1638 	if (queue >= IEEE80211_NUM_ACS)
1639 		return 0;
1640 
1641 	txq = sc->tx.txq_map[queue];
1642 
1643 	ath9k_ps_wakeup(sc);
1644 	mutex_lock(&sc->mutex);
1645 
1646 	memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1647 
1648 	qi.tqi_aifs = params->aifs;
1649 	qi.tqi_cwmin = params->cw_min;
1650 	qi.tqi_cwmax = params->cw_max;
1651 	qi.tqi_burstTime = params->txop * 32;
1652 
1653 	ath_dbg(common, CONFIG,
1654 		"Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1655 		queue, txq->axq_qnum, params->aifs, params->cw_min,
1656 		params->cw_max, params->txop);
1657 
1658 	ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1659 	ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1660 	if (ret)
1661 		ath_err(common, "TXQ Update failed\n");
1662 
1663 	mutex_unlock(&sc->mutex);
1664 	ath9k_ps_restore(sc);
1665 
1666 	return ret;
1667 }
1668 
1669 static int ath9k_set_key(struct ieee80211_hw *hw,
1670 			 enum set_key_cmd cmd,
1671 			 struct ieee80211_vif *vif,
1672 			 struct ieee80211_sta *sta,
1673 			 struct ieee80211_key_conf *key)
1674 {
1675 	struct ath_softc *sc = hw->priv;
1676 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1677 	struct ath_node *an = NULL;
1678 	int ret = 0, i;
1679 
1680 	if (ath9k_modparam_nohwcrypt)
1681 		return -ENOSPC;
1682 
1683 	if ((vif->type == NL80211_IFTYPE_ADHOC ||
1684 	     vif->type == NL80211_IFTYPE_MESH_POINT) &&
1685 	    (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1686 	     key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1687 	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1688 		/*
1689 		 * For now, disable hw crypto for the RSN IBSS group keys. This
1690 		 * could be optimized in the future to use a modified key cache
1691 		 * design to support per-STA RX GTK, but until that gets
1692 		 * implemented, use of software crypto for group addressed
1693 		 * frames is a acceptable to allow RSN IBSS to be used.
1694 		 */
1695 		return -EOPNOTSUPP;
1696 	}
1697 
1698 	mutex_lock(&sc->mutex);
1699 	ath9k_ps_wakeup(sc);
1700 	ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1701 	if (sta)
1702 		an = (struct ath_node *)sta->drv_priv;
1703 
1704 	switch (cmd) {
1705 	case SET_KEY:
1706 		if (sta)
1707 			ath9k_del_ps_key(sc, vif, sta);
1708 
1709 		key->hw_key_idx = 0;
1710 		ret = ath_key_config(common, vif, sta, key);
1711 		if (ret >= 0) {
1712 			key->hw_key_idx = ret;
1713 			/* push IV and Michael MIC generation to stack */
1714 			key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1715 			if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1716 				key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1717 			if (sc->sc_ah->sw_mgmt_crypto_tx &&
1718 			    key->cipher == WLAN_CIPHER_SUITE_CCMP)
1719 				key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1720 			ret = 0;
1721 		}
1722 		if (an && key->hw_key_idx) {
1723 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1724 				if (an->key_idx[i])
1725 					continue;
1726 				an->key_idx[i] = key->hw_key_idx;
1727 				break;
1728 			}
1729 			WARN_ON(i == ARRAY_SIZE(an->key_idx));
1730 		}
1731 		break;
1732 	case DISABLE_KEY:
1733 		ath_key_delete(common, key);
1734 		if (an) {
1735 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1736 				if (an->key_idx[i] != key->hw_key_idx)
1737 					continue;
1738 				an->key_idx[i] = 0;
1739 				break;
1740 			}
1741 		}
1742 		key->hw_key_idx = 0;
1743 		break;
1744 	default:
1745 		ret = -EINVAL;
1746 	}
1747 
1748 	ath9k_ps_restore(sc);
1749 	mutex_unlock(&sc->mutex);
1750 
1751 	return ret;
1752 }
1753 
1754 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1755 				   struct ieee80211_vif *vif,
1756 				   struct ieee80211_bss_conf *bss_conf,
1757 				   u32 changed)
1758 {
1759 #define CHECK_ANI				\
1760 	(BSS_CHANGED_ASSOC |			\
1761 	 BSS_CHANGED_IBSS |			\
1762 	 BSS_CHANGED_BEACON_ENABLED)
1763 
1764 	struct ath_softc *sc = hw->priv;
1765 	struct ath_hw *ah = sc->sc_ah;
1766 	struct ath_common *common = ath9k_hw_common(ah);
1767 	struct ath_vif *avp = (void *)vif->drv_priv;
1768 	int slottime;
1769 
1770 	ath9k_ps_wakeup(sc);
1771 	mutex_lock(&sc->mutex);
1772 
1773 	if (changed & BSS_CHANGED_ASSOC) {
1774 		ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1775 			bss_conf->bssid, bss_conf->assoc);
1776 
1777 		memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1778 		avp->aid = bss_conf->aid;
1779 		avp->assoc = bss_conf->assoc;
1780 
1781 		ath9k_calculate_summary_state(sc, avp->chanctx);
1782 	}
1783 
1784 	if ((changed & BSS_CHANGED_IBSS) ||
1785 	      (changed & BSS_CHANGED_OCB)) {
1786 		memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1787 		common->curaid = bss_conf->aid;
1788 		ath9k_hw_write_associd(sc->sc_ah);
1789 	}
1790 
1791 	if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1792 	    (changed & BSS_CHANGED_BEACON_INT) ||
1793 	    (changed & BSS_CHANGED_BEACON_INFO)) {
1794 		ath9k_calculate_summary_state(sc, avp->chanctx);
1795 	}
1796 
1797 	if ((avp->chanctx == sc->cur_chan) &&
1798 	    (changed & BSS_CHANGED_ERP_SLOT)) {
1799 		if (bss_conf->use_short_slot)
1800 			slottime = 9;
1801 		else
1802 			slottime = 20;
1803 
1804 		if (vif->type == NL80211_IFTYPE_AP) {
1805 			/*
1806 			 * Defer update, so that connected stations can adjust
1807 			 * their settings at the same time.
1808 			 * See beacon.c for more details
1809 			 */
1810 			sc->beacon.slottime = slottime;
1811 			sc->beacon.updateslot = UPDATE;
1812 		} else {
1813 			ah->slottime = slottime;
1814 			ath9k_hw_init_global_settings(ah);
1815 		}
1816 	}
1817 
1818 	if (changed & BSS_CHANGED_P2P_PS)
1819 		ath9k_p2p_bss_info_changed(sc, vif);
1820 
1821 	if (changed & CHECK_ANI)
1822 		ath_check_ani(sc);
1823 
1824 	if (changed & BSS_CHANGED_TXPOWER) {
1825 		ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1826 			vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1827 		ath9k_set_txpower(sc, vif);
1828 	}
1829 
1830 	mutex_unlock(&sc->mutex);
1831 	ath9k_ps_restore(sc);
1832 
1833 #undef CHECK_ANI
1834 }
1835 
1836 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1837 {
1838 	struct ath_softc *sc = hw->priv;
1839 	struct ath_vif *avp = (void *)vif->drv_priv;
1840 	u64 tsf;
1841 
1842 	mutex_lock(&sc->mutex);
1843 	ath9k_ps_wakeup(sc);
1844 	/* Get current TSF either from HW or kernel time. */
1845 	if (sc->cur_chan == avp->chanctx) {
1846 		tsf = ath9k_hw_gettsf64(sc->sc_ah);
1847 	} else {
1848 		tsf = sc->cur_chan->tsf_val +
1849 		      ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1850 	}
1851 	tsf += le64_to_cpu(avp->tsf_adjust);
1852 	ath9k_ps_restore(sc);
1853 	mutex_unlock(&sc->mutex);
1854 
1855 	return tsf;
1856 }
1857 
1858 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1859 			  struct ieee80211_vif *vif,
1860 			  u64 tsf)
1861 {
1862 	struct ath_softc *sc = hw->priv;
1863 	struct ath_vif *avp = (void *)vif->drv_priv;
1864 
1865 	mutex_lock(&sc->mutex);
1866 	ath9k_ps_wakeup(sc);
1867 	tsf -= le64_to_cpu(avp->tsf_adjust);
1868 	ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1869 	if (sc->cur_chan == avp->chanctx)
1870 		ath9k_hw_settsf64(sc->sc_ah, tsf);
1871 	avp->chanctx->tsf_val = tsf;
1872 	ath9k_ps_restore(sc);
1873 	mutex_unlock(&sc->mutex);
1874 }
1875 
1876 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1877 {
1878 	struct ath_softc *sc = hw->priv;
1879 	struct ath_vif *avp = (void *)vif->drv_priv;
1880 
1881 	mutex_lock(&sc->mutex);
1882 
1883 	ath9k_ps_wakeup(sc);
1884 	ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1885 	if (sc->cur_chan == avp->chanctx)
1886 		ath9k_hw_reset_tsf(sc->sc_ah);
1887 	avp->chanctx->tsf_val = 0;
1888 	ath9k_ps_restore(sc);
1889 
1890 	mutex_unlock(&sc->mutex);
1891 }
1892 
1893 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1894 			      struct ieee80211_vif *vif,
1895 			      struct ieee80211_ampdu_params *params)
1896 {
1897 	struct ath_softc *sc = hw->priv;
1898 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1899 	bool flush = false;
1900 	int ret = 0;
1901 	struct ieee80211_sta *sta = params->sta;
1902 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1903 	enum ieee80211_ampdu_mlme_action action = params->action;
1904 	u16 tid = params->tid;
1905 	u16 *ssn = &params->ssn;
1906 	struct ath_atx_tid *atid;
1907 
1908 	mutex_lock(&sc->mutex);
1909 
1910 	switch (action) {
1911 	case IEEE80211_AMPDU_RX_START:
1912 		break;
1913 	case IEEE80211_AMPDU_RX_STOP:
1914 		break;
1915 	case IEEE80211_AMPDU_TX_START:
1916 		if (ath9k_is_chanctx_enabled()) {
1917 			if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1918 				ret = -EBUSY;
1919 				break;
1920 			}
1921 		}
1922 		ath9k_ps_wakeup(sc);
1923 		ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1924 		if (!ret)
1925 			ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1926 		ath9k_ps_restore(sc);
1927 		break;
1928 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
1929 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1930 		flush = true;
1931 		/* fall through */
1932 	case IEEE80211_AMPDU_TX_STOP_CONT:
1933 		ath9k_ps_wakeup(sc);
1934 		ath_tx_aggr_stop(sc, sta, tid);
1935 		if (!flush)
1936 			ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1937 		ath9k_ps_restore(sc);
1938 		break;
1939 	case IEEE80211_AMPDU_TX_OPERATIONAL:
1940 		atid = ath_node_to_tid(an, tid);
1941 		atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
1942 			        sta->ht_cap.ampdu_factor;
1943 		break;
1944 	default:
1945 		ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1946 	}
1947 
1948 	mutex_unlock(&sc->mutex);
1949 
1950 	return ret;
1951 }
1952 
1953 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1954 			     struct survey_info *survey)
1955 {
1956 	struct ath_softc *sc = hw->priv;
1957 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1958 	struct ieee80211_supported_band *sband;
1959 	struct ieee80211_channel *chan;
1960 	unsigned long flags;
1961 	int pos;
1962 
1963 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
1964 		return -EOPNOTSUPP;
1965 
1966 	spin_lock_irqsave(&common->cc_lock, flags);
1967 	if (idx == 0)
1968 		ath_update_survey_stats(sc);
1969 
1970 	sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
1971 	if (sband && idx >= sband->n_channels) {
1972 		idx -= sband->n_channels;
1973 		sband = NULL;
1974 	}
1975 
1976 	if (!sband)
1977 		sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
1978 
1979 	if (!sband || idx >= sband->n_channels) {
1980 		spin_unlock_irqrestore(&common->cc_lock, flags);
1981 		return -ENOENT;
1982 	}
1983 
1984 	chan = &sband->channels[idx];
1985 	pos = chan->hw_value;
1986 	memcpy(survey, &sc->survey[pos], sizeof(*survey));
1987 	survey->channel = chan;
1988 	spin_unlock_irqrestore(&common->cc_lock, flags);
1989 
1990 	return 0;
1991 }
1992 
1993 static void ath9k_enable_dynack(struct ath_softc *sc)
1994 {
1995 #ifdef CONFIG_ATH9K_DYNACK
1996 	u32 rfilt;
1997 	struct ath_hw *ah = sc->sc_ah;
1998 
1999 	ath_dynack_reset(ah);
2000 
2001 	ah->dynack.enabled = true;
2002 	rfilt = ath_calcrxfilter(sc);
2003 	ath9k_hw_setrxfilter(ah, rfilt);
2004 #endif
2005 }
2006 
2007 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2008 				     s16 coverage_class)
2009 {
2010 	struct ath_softc *sc = hw->priv;
2011 	struct ath_hw *ah = sc->sc_ah;
2012 
2013 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
2014 		return;
2015 
2016 	mutex_lock(&sc->mutex);
2017 
2018 	if (coverage_class >= 0) {
2019 		ah->coverage_class = coverage_class;
2020 		if (ah->dynack.enabled) {
2021 			u32 rfilt;
2022 
2023 			ah->dynack.enabled = false;
2024 			rfilt = ath_calcrxfilter(sc);
2025 			ath9k_hw_setrxfilter(ah, rfilt);
2026 		}
2027 		ath9k_ps_wakeup(sc);
2028 		ath9k_hw_init_global_settings(ah);
2029 		ath9k_ps_restore(sc);
2030 	} else if (!ah->dynack.enabled) {
2031 		ath9k_enable_dynack(sc);
2032 	}
2033 
2034 	mutex_unlock(&sc->mutex);
2035 }
2036 
2037 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2038 				 bool sw_pending)
2039 {
2040 	int i, npend = 0;
2041 
2042 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2043 		if (!ATH_TXQ_SETUP(sc, i))
2044 			continue;
2045 
2046 		npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2047 						 sw_pending);
2048 		if (npend)
2049 			break;
2050 	}
2051 
2052 	return !!npend;
2053 }
2054 
2055 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2056 			u32 queues, bool drop)
2057 {
2058 	struct ath_softc *sc = hw->priv;
2059 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2060 
2061 	if (ath9k_is_chanctx_enabled()) {
2062 		if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2063 			goto flush;
2064 
2065 		/*
2066 		 * If MCC is active, extend the flush timeout
2067 		 * and wait for the HW/SW queues to become
2068 		 * empty. This needs to be done outside the
2069 		 * sc->mutex lock to allow the channel scheduler
2070 		 * to switch channel contexts.
2071 		 *
2072 		 * The vif queues have been stopped in mac80211,
2073 		 * so there won't be any incoming frames.
2074 		 */
2075 		__ath9k_flush(hw, queues, drop, true, true);
2076 		return;
2077 	}
2078 flush:
2079 	mutex_lock(&sc->mutex);
2080 	__ath9k_flush(hw, queues, drop, true, false);
2081 	mutex_unlock(&sc->mutex);
2082 }
2083 
2084 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2085 		   bool sw_pending, bool timeout_override)
2086 {
2087 	struct ath_softc *sc = hw->priv;
2088 	struct ath_hw *ah = sc->sc_ah;
2089 	struct ath_common *common = ath9k_hw_common(ah);
2090 	int timeout;
2091 	bool drain_txq;
2092 
2093 	cancel_delayed_work_sync(&sc->hw_check_work);
2094 
2095 	if (ah->ah_flags & AH_UNPLUGGED) {
2096 		ath_dbg(common, ANY, "Device has been unplugged!\n");
2097 		return;
2098 	}
2099 
2100 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2101 		ath_dbg(common, ANY, "Device not present\n");
2102 		return;
2103 	}
2104 
2105 	spin_lock_bh(&sc->chan_lock);
2106 	if (timeout_override)
2107 		timeout = HZ / 5;
2108 	else
2109 		timeout = sc->cur_chan->flush_timeout;
2110 	spin_unlock_bh(&sc->chan_lock);
2111 
2112 	ath_dbg(common, CHAN_CTX,
2113 		"Flush timeout: %d\n", jiffies_to_msecs(timeout));
2114 
2115 	if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2116 			       timeout) > 0)
2117 		drop = false;
2118 
2119 	if (drop) {
2120 		ath9k_ps_wakeup(sc);
2121 		spin_lock_bh(&sc->sc_pcu_lock);
2122 		drain_txq = ath_drain_all_txq(sc);
2123 		spin_unlock_bh(&sc->sc_pcu_lock);
2124 
2125 		if (!drain_txq)
2126 			ath_reset(sc, NULL);
2127 
2128 		ath9k_ps_restore(sc);
2129 	}
2130 
2131 	ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2132 				     ATH_HW_CHECK_POLL_INT);
2133 }
2134 
2135 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2136 {
2137 	struct ath_softc *sc = hw->priv;
2138 
2139 	return ath9k_has_tx_pending(sc, true);
2140 }
2141 
2142 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2143 {
2144 	struct ath_softc *sc = hw->priv;
2145 	struct ath_hw *ah = sc->sc_ah;
2146 	struct ieee80211_vif *vif;
2147 	struct ath_vif *avp;
2148 	struct ath_buf *bf;
2149 	struct ath_tx_status ts;
2150 	bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2151 	int status;
2152 
2153 	vif = sc->beacon.bslot[0];
2154 	if (!vif)
2155 		return 0;
2156 
2157 	if (!vif->bss_conf.enable_beacon)
2158 		return 0;
2159 
2160 	avp = (void *)vif->drv_priv;
2161 
2162 	if (!sc->beacon.tx_processed && !edma) {
2163 		tasklet_disable(&sc->bcon_tasklet);
2164 
2165 		bf = avp->av_bcbuf;
2166 		if (!bf || !bf->bf_mpdu)
2167 			goto skip;
2168 
2169 		status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2170 		if (status == -EINPROGRESS)
2171 			goto skip;
2172 
2173 		sc->beacon.tx_processed = true;
2174 		sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2175 
2176 skip:
2177 		tasklet_enable(&sc->bcon_tasklet);
2178 	}
2179 
2180 	return sc->beacon.tx_last;
2181 }
2182 
2183 static int ath9k_get_stats(struct ieee80211_hw *hw,
2184 			   struct ieee80211_low_level_stats *stats)
2185 {
2186 	struct ath_softc *sc = hw->priv;
2187 	struct ath_hw *ah = sc->sc_ah;
2188 	struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2189 
2190 	stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2191 	stats->dot11RTSFailureCount = mib_stats->rts_bad;
2192 	stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2193 	stats->dot11RTSSuccessCount = mib_stats->rts_good;
2194 	return 0;
2195 }
2196 
2197 static u32 fill_chainmask(u32 cap, u32 new)
2198 {
2199 	u32 filled = 0;
2200 	int i;
2201 
2202 	for (i = 0; cap && new; i++, cap >>= 1) {
2203 		if (!(cap & BIT(0)))
2204 			continue;
2205 
2206 		if (new & BIT(0))
2207 			filled |= BIT(i);
2208 
2209 		new >>= 1;
2210 	}
2211 
2212 	return filled;
2213 }
2214 
2215 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2216 {
2217 	if (AR_SREV_9300_20_OR_LATER(ah))
2218 		return true;
2219 
2220 	switch (val & 0x7) {
2221 	case 0x1:
2222 	case 0x3:
2223 	case 0x7:
2224 		return true;
2225 	case 0x2:
2226 		return (ah->caps.rx_chainmask == 1);
2227 	default:
2228 		return false;
2229 	}
2230 }
2231 
2232 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2233 {
2234 	struct ath_softc *sc = hw->priv;
2235 	struct ath_hw *ah = sc->sc_ah;
2236 
2237 	if (ah->caps.rx_chainmask != 1)
2238 		rx_ant |= tx_ant;
2239 
2240 	if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2241 		return -EINVAL;
2242 
2243 	sc->ant_rx = rx_ant;
2244 	sc->ant_tx = tx_ant;
2245 
2246 	if (ah->caps.rx_chainmask == 1)
2247 		return 0;
2248 
2249 	/* AR9100 runs into calibration issues if not all rx chains are enabled */
2250 	if (AR_SREV_9100(ah))
2251 		ah->rxchainmask = 0x7;
2252 	else
2253 		ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2254 
2255 	ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2256 	ath9k_cmn_reload_chainmask(ah);
2257 
2258 	return 0;
2259 }
2260 
2261 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2262 {
2263 	struct ath_softc *sc = hw->priv;
2264 
2265 	*tx_ant = sc->ant_tx;
2266 	*rx_ant = sc->ant_rx;
2267 	return 0;
2268 }
2269 
2270 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2271 				struct ieee80211_vif *vif,
2272 				const u8 *mac_addr)
2273 {
2274 	struct ath_softc *sc = hw->priv;
2275 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2276 	set_bit(ATH_OP_SCANNING, &common->op_flags);
2277 }
2278 
2279 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2280 				   struct ieee80211_vif *vif)
2281 {
2282 	struct ath_softc *sc = hw->priv;
2283 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2284 	clear_bit(ATH_OP_SCANNING, &common->op_flags);
2285 }
2286 
2287 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2288 
2289 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2290 {
2291 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2292 
2293 	if (sc->offchannel.roc_vif) {
2294 		ath_dbg(common, CHAN_CTX,
2295 			"%s: Aborting RoC\n", __func__);
2296 
2297 		del_timer_sync(&sc->offchannel.timer);
2298 		if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2299 			ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2300 	}
2301 
2302 	if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2303 		ath_dbg(common, CHAN_CTX,
2304 			"%s: Aborting HW scan\n", __func__);
2305 
2306 		del_timer_sync(&sc->offchannel.timer);
2307 		ath_scan_complete(sc, true);
2308 	}
2309 }
2310 
2311 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2312 			 struct ieee80211_scan_request *hw_req)
2313 {
2314 	struct cfg80211_scan_request *req = &hw_req->req;
2315 	struct ath_softc *sc = hw->priv;
2316 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2317 	int ret = 0;
2318 
2319 	mutex_lock(&sc->mutex);
2320 
2321 	if (WARN_ON(sc->offchannel.scan_req)) {
2322 		ret = -EBUSY;
2323 		goto out;
2324 	}
2325 
2326 	ath9k_ps_wakeup(sc);
2327 	set_bit(ATH_OP_SCANNING, &common->op_flags);
2328 	sc->offchannel.scan_vif = vif;
2329 	sc->offchannel.scan_req = req;
2330 	sc->offchannel.scan_idx = 0;
2331 
2332 	ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2333 		vif->addr);
2334 
2335 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2336 		ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2337 		ath_offchannel_next(sc);
2338 	}
2339 
2340 out:
2341 	mutex_unlock(&sc->mutex);
2342 
2343 	return ret;
2344 }
2345 
2346 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2347 				 struct ieee80211_vif *vif)
2348 {
2349 	struct ath_softc *sc = hw->priv;
2350 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2351 
2352 	ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2353 
2354 	mutex_lock(&sc->mutex);
2355 	del_timer_sync(&sc->offchannel.timer);
2356 	ath_scan_complete(sc, true);
2357 	mutex_unlock(&sc->mutex);
2358 }
2359 
2360 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2361 				   struct ieee80211_vif *vif,
2362 				   struct ieee80211_channel *chan, int duration,
2363 				   enum ieee80211_roc_type type)
2364 {
2365 	struct ath_softc *sc = hw->priv;
2366 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2367 	int ret = 0;
2368 
2369 	mutex_lock(&sc->mutex);
2370 
2371 	if (WARN_ON(sc->offchannel.roc_vif)) {
2372 		ret = -EBUSY;
2373 		goto out;
2374 	}
2375 
2376 	ath9k_ps_wakeup(sc);
2377 	sc->offchannel.roc_vif = vif;
2378 	sc->offchannel.roc_chan = chan;
2379 	sc->offchannel.roc_duration = duration;
2380 
2381 	ath_dbg(common, CHAN_CTX,
2382 		"RoC request on vif: %pM, type: %d duration: %d\n",
2383 		vif->addr, type, duration);
2384 
2385 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2386 		ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2387 		ath_offchannel_next(sc);
2388 	}
2389 
2390 out:
2391 	mutex_unlock(&sc->mutex);
2392 
2393 	return ret;
2394 }
2395 
2396 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2397 {
2398 	struct ath_softc *sc = hw->priv;
2399 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2400 
2401 	mutex_lock(&sc->mutex);
2402 
2403 	ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2404 	del_timer_sync(&sc->offchannel.timer);
2405 
2406 	if (sc->offchannel.roc_vif) {
2407 		if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2408 			ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2409 	}
2410 
2411 	mutex_unlock(&sc->mutex);
2412 
2413 	return 0;
2414 }
2415 
2416 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2417 			     struct ieee80211_chanctx_conf *conf)
2418 {
2419 	struct ath_softc *sc = hw->priv;
2420 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2421 	struct ath_chanctx *ctx, **ptr;
2422 	int pos;
2423 
2424 	mutex_lock(&sc->mutex);
2425 
2426 	ath_for_each_chanctx(sc, ctx) {
2427 		if (ctx->assigned)
2428 			continue;
2429 
2430 		ptr = (void *) conf->drv_priv;
2431 		*ptr = ctx;
2432 		ctx->assigned = true;
2433 		pos = ctx - &sc->chanctx[0];
2434 		ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2435 
2436 		ath_dbg(common, CHAN_CTX,
2437 			"Add channel context: %d MHz\n",
2438 			conf->def.chan->center_freq);
2439 
2440 		ath_chanctx_set_channel(sc, ctx, &conf->def);
2441 
2442 		mutex_unlock(&sc->mutex);
2443 		return 0;
2444 	}
2445 
2446 	mutex_unlock(&sc->mutex);
2447 	return -ENOSPC;
2448 }
2449 
2450 
2451 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2452 				 struct ieee80211_chanctx_conf *conf)
2453 {
2454 	struct ath_softc *sc = hw->priv;
2455 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2456 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2457 
2458 	mutex_lock(&sc->mutex);
2459 
2460 	ath_dbg(common, CHAN_CTX,
2461 		"Remove channel context: %d MHz\n",
2462 		conf->def.chan->center_freq);
2463 
2464 	ctx->assigned = false;
2465 	ctx->hw_queue_base = 0;
2466 	ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2467 
2468 	mutex_unlock(&sc->mutex);
2469 }
2470 
2471 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2472 				 struct ieee80211_chanctx_conf *conf,
2473 				 u32 changed)
2474 {
2475 	struct ath_softc *sc = hw->priv;
2476 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2477 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2478 
2479 	mutex_lock(&sc->mutex);
2480 	ath_dbg(common, CHAN_CTX,
2481 		"Change channel context: %d MHz\n",
2482 		conf->def.chan->center_freq);
2483 	ath_chanctx_set_channel(sc, ctx, &conf->def);
2484 	mutex_unlock(&sc->mutex);
2485 }
2486 
2487 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2488 				    struct ieee80211_vif *vif,
2489 				    struct ieee80211_chanctx_conf *conf)
2490 {
2491 	struct ath_softc *sc = hw->priv;
2492 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2493 	struct ath_vif *avp = (void *)vif->drv_priv;
2494 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2495 	int i;
2496 
2497 	ath9k_cancel_pending_offchannel(sc);
2498 
2499 	mutex_lock(&sc->mutex);
2500 
2501 	ath_dbg(common, CHAN_CTX,
2502 		"Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2503 		vif->addr, vif->type, vif->p2p,
2504 		conf->def.chan->center_freq);
2505 
2506 	avp->chanctx = ctx;
2507 	ctx->nvifs_assigned++;
2508 	list_add_tail(&avp->list, &ctx->vifs);
2509 	ath9k_calculate_summary_state(sc, ctx);
2510 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
2511 		vif->hw_queue[i] = ctx->hw_queue_base + i;
2512 
2513 	mutex_unlock(&sc->mutex);
2514 
2515 	return 0;
2516 }
2517 
2518 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2519 				       struct ieee80211_vif *vif,
2520 				       struct ieee80211_chanctx_conf *conf)
2521 {
2522 	struct ath_softc *sc = hw->priv;
2523 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2524 	struct ath_vif *avp = (void *)vif->drv_priv;
2525 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2526 	int ac;
2527 
2528 	ath9k_cancel_pending_offchannel(sc);
2529 
2530 	mutex_lock(&sc->mutex);
2531 
2532 	ath_dbg(common, CHAN_CTX,
2533 		"Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2534 		vif->addr, vif->type, vif->p2p,
2535 		conf->def.chan->center_freq);
2536 
2537 	avp->chanctx = NULL;
2538 	ctx->nvifs_assigned--;
2539 	list_del(&avp->list);
2540 	ath9k_calculate_summary_state(sc, ctx);
2541 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2542 		vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2543 
2544 	mutex_unlock(&sc->mutex);
2545 }
2546 
2547 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2548 				 struct ieee80211_vif *vif,
2549 				 u16 duration)
2550 {
2551 	struct ath_softc *sc = hw->priv;
2552 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2553 	struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2554 	struct ath_beacon_config *cur_conf;
2555 	struct ath_chanctx *go_ctx;
2556 	unsigned long timeout;
2557 	bool changed = false;
2558 	u32 beacon_int;
2559 
2560 	if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2561 		return;
2562 
2563 	if (!avp->chanctx)
2564 		return;
2565 
2566 	mutex_lock(&sc->mutex);
2567 
2568 	spin_lock_bh(&sc->chan_lock);
2569 	if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2570 		changed = true;
2571 	spin_unlock_bh(&sc->chan_lock);
2572 
2573 	if (!changed)
2574 		goto out;
2575 
2576 	ath9k_cancel_pending_offchannel(sc);
2577 
2578 	go_ctx = ath_is_go_chanctx_present(sc);
2579 
2580 	if (go_ctx) {
2581 		/*
2582 		 * Wait till the GO interface gets a chance
2583 		 * to send out an NoA.
2584 		 */
2585 		spin_lock_bh(&sc->chan_lock);
2586 		sc->sched.mgd_prepare_tx = true;
2587 		cur_conf = &go_ctx->beacon;
2588 		beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2589 		spin_unlock_bh(&sc->chan_lock);
2590 
2591 		timeout = usecs_to_jiffies(beacon_int * 2);
2592 		init_completion(&sc->go_beacon);
2593 
2594 		mutex_unlock(&sc->mutex);
2595 
2596 		if (wait_for_completion_timeout(&sc->go_beacon,
2597 						timeout) == 0) {
2598 			ath_dbg(common, CHAN_CTX,
2599 				"Failed to send new NoA\n");
2600 
2601 			spin_lock_bh(&sc->chan_lock);
2602 			sc->sched.mgd_prepare_tx = false;
2603 			spin_unlock_bh(&sc->chan_lock);
2604 		}
2605 
2606 		mutex_lock(&sc->mutex);
2607 	}
2608 
2609 	ath_dbg(common, CHAN_CTX,
2610 		"%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2611 		__func__, vif->addr);
2612 
2613 	spin_lock_bh(&sc->chan_lock);
2614 	sc->next_chan = avp->chanctx;
2615 	sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2616 	spin_unlock_bh(&sc->chan_lock);
2617 
2618 	ath_chanctx_set_next(sc, true);
2619 out:
2620 	mutex_unlock(&sc->mutex);
2621 }
2622 
2623 void ath9k_fill_chanctx_ops(void)
2624 {
2625 	if (!ath9k_is_chanctx_enabled())
2626 		return;
2627 
2628 	ath9k_ops.hw_scan                  = ath9k_hw_scan;
2629 	ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2630 	ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2631 	ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2632 	ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2633 	ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2634 	ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2635 	ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2636 	ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2637 	ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2638 }
2639 
2640 #endif
2641 
2642 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2643 			     int *dbm)
2644 {
2645 	struct ath_softc *sc = hw->priv;
2646 	struct ath_vif *avp = (void *)vif->drv_priv;
2647 
2648 	mutex_lock(&sc->mutex);
2649 	if (avp->chanctx)
2650 		*dbm = avp->chanctx->cur_txpower;
2651 	else
2652 		*dbm = sc->cur_chan->cur_txpower;
2653 	mutex_unlock(&sc->mutex);
2654 
2655 	*dbm /= 2;
2656 
2657 	return 0;
2658 }
2659 
2660 struct ieee80211_ops ath9k_ops = {
2661 	.tx 		    = ath9k_tx,
2662 	.start 		    = ath9k_start,
2663 	.stop 		    = ath9k_stop,
2664 	.add_interface 	    = ath9k_add_interface,
2665 	.change_interface   = ath9k_change_interface,
2666 	.remove_interface   = ath9k_remove_interface,
2667 	.config 	    = ath9k_config,
2668 	.configure_filter   = ath9k_configure_filter,
2669 	.sta_state          = ath9k_sta_state,
2670 	.sta_notify         = ath9k_sta_notify,
2671 	.conf_tx 	    = ath9k_conf_tx,
2672 	.bss_info_changed   = ath9k_bss_info_changed,
2673 	.set_key            = ath9k_set_key,
2674 	.get_tsf 	    = ath9k_get_tsf,
2675 	.set_tsf 	    = ath9k_set_tsf,
2676 	.reset_tsf 	    = ath9k_reset_tsf,
2677 	.ampdu_action       = ath9k_ampdu_action,
2678 	.get_survey	    = ath9k_get_survey,
2679 	.rfkill_poll        = ath9k_rfkill_poll_state,
2680 	.set_coverage_class = ath9k_set_coverage_class,
2681 	.flush		    = ath9k_flush,
2682 	.tx_frames_pending  = ath9k_tx_frames_pending,
2683 	.tx_last_beacon     = ath9k_tx_last_beacon,
2684 	.release_buffered_frames = ath9k_release_buffered_frames,
2685 	.get_stats	    = ath9k_get_stats,
2686 	.set_antenna	    = ath9k_set_antenna,
2687 	.get_antenna	    = ath9k_get_antenna,
2688 
2689 #ifdef CONFIG_ATH9K_WOW
2690 	.suspend	    = ath9k_suspend,
2691 	.resume		    = ath9k_resume,
2692 	.set_wakeup	    = ath9k_set_wakeup,
2693 #endif
2694 
2695 #ifdef CONFIG_ATH9K_DEBUGFS
2696 	.get_et_sset_count  = ath9k_get_et_sset_count,
2697 	.get_et_stats       = ath9k_get_et_stats,
2698 	.get_et_strings     = ath9k_get_et_strings,
2699 #endif
2700 
2701 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2702 	.sta_add_debugfs    = ath9k_sta_add_debugfs,
2703 #endif
2704 	.sw_scan_start	    = ath9k_sw_scan_start,
2705 	.sw_scan_complete   = ath9k_sw_scan_complete,
2706 	.get_txpower        = ath9k_get_txpower,
2707 	.wake_tx_queue      = ath9k_wake_tx_queue,
2708 };
2709