1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK | 135 PS_WAIT_FOR_ANI))) { 136 mode = ATH9K_PM_NETWORK_SLEEP; 137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 138 ath9k_btcoex_stop_gen_timer(sc); 139 } else { 140 goto unlock; 141 } 142 143 spin_lock(&common->cc_lock); 144 ath_hw_cycle_counters_update(common); 145 spin_unlock(&common->cc_lock); 146 147 ath9k_hw_setpower(sc->sc_ah, mode); 148 149 unlock: 150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 151 } 152 153 static void __ath_cancel_work(struct ath_softc *sc) 154 { 155 cancel_work_sync(&sc->paprd_work); 156 cancel_work_sync(&sc->hw_check_work); 157 cancel_delayed_work_sync(&sc->tx_complete_work); 158 cancel_delayed_work_sync(&sc->hw_pll_work); 159 160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 161 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 162 cancel_work_sync(&sc->mci_work); 163 #endif 164 } 165 166 static void ath_cancel_work(struct ath_softc *sc) 167 { 168 __ath_cancel_work(sc); 169 cancel_work_sync(&sc->hw_reset_work); 170 } 171 172 static void ath_restart_work(struct ath_softc *sc) 173 { 174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 175 176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 177 AR_SREV_9550(sc->sc_ah)) 178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 180 181 ath_start_rx_poll(sc, 3); 182 ath_start_ani(sc); 183 } 184 185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx) 186 { 187 struct ath_hw *ah = sc->sc_ah; 188 bool ret = true; 189 190 ieee80211_stop_queues(sc->hw); 191 192 sc->hw_busy_count = 0; 193 ath_stop_ani(sc); 194 del_timer_sync(&sc->rx_poll_timer); 195 196 ath9k_debug_samp_bb_mac(sc); 197 ath9k_hw_disable_interrupts(ah); 198 199 if (!ath_stoprecv(sc)) 200 ret = false; 201 202 if (!ath_drain_all_txq(sc, retry_tx)) 203 ret = false; 204 205 return ret; 206 } 207 208 static bool ath_complete_reset(struct ath_softc *sc, bool start) 209 { 210 struct ath_hw *ah = sc->sc_ah; 211 struct ath_common *common = ath9k_hw_common(ah); 212 unsigned long flags; 213 214 if (ath_startrecv(sc) != 0) { 215 ath_err(common, "Unable to restart recv logic\n"); 216 return false; 217 } 218 219 ath9k_cmn_update_txpow(ah, sc->curtxpow, 220 sc->config.txpowlimit, &sc->curtxpow); 221 222 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 223 ath9k_hw_set_interrupts(ah); 224 ath9k_hw_enable_interrupts(ah); 225 226 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 227 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 228 goto work; 229 230 ath9k_set_beacon(sc); 231 232 if (ah->opmode == NL80211_IFTYPE_STATION && 233 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 234 spin_lock_irqsave(&sc->sc_pm_lock, flags); 235 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 236 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 237 } 238 work: 239 ath_restart_work(sc); 240 } 241 242 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) 243 ath_ant_comb_update(sc); 244 245 ieee80211_wake_queues(sc->hw); 246 247 return true; 248 } 249 250 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, 251 bool retry_tx) 252 { 253 struct ath_hw *ah = sc->sc_ah; 254 struct ath_common *common = ath9k_hw_common(ah); 255 struct ath9k_hw_cal_data *caldata = NULL; 256 bool fastcc = true; 257 int r; 258 259 __ath_cancel_work(sc); 260 261 tasklet_disable(&sc->intr_tq); 262 spin_lock_bh(&sc->sc_pcu_lock); 263 264 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 265 fastcc = false; 266 caldata = &sc->caldata; 267 } 268 269 if (!hchan) { 270 fastcc = false; 271 hchan = ah->curchan; 272 } 273 274 if (!ath_prepare_reset(sc, retry_tx)) 275 fastcc = false; 276 277 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 278 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 279 280 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 281 if (r) { 282 ath_err(common, 283 "Unable to reset channel, reset status %d\n", r); 284 goto out; 285 } 286 287 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 288 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 289 ath9k_mci_set_txpower(sc, true, false); 290 291 if (!ath_complete_reset(sc, true)) 292 r = -EIO; 293 294 out: 295 spin_unlock_bh(&sc->sc_pcu_lock); 296 tasklet_enable(&sc->intr_tq); 297 298 return r; 299 } 300 301 302 /* 303 * Set/change channels. If the channel is really being changed, it's done 304 * by reseting the chip. To accomplish this we must first cleanup any pending 305 * DMA, then restart stuff. 306 */ 307 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 308 struct ath9k_channel *hchan) 309 { 310 int r; 311 312 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 313 return -EIO; 314 315 r = ath_reset_internal(sc, hchan, false); 316 317 return r; 318 } 319 320 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 321 struct ieee80211_vif *vif) 322 { 323 struct ath_node *an; 324 u8 density; 325 an = (struct ath_node *)sta->drv_priv; 326 327 an->sc = sc; 328 an->sta = sta; 329 an->vif = vif; 330 331 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 332 ath_tx_node_init(sc, an); 333 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 334 sta->ht_cap.ampdu_factor); 335 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 336 an->mpdudensity = density; 337 } 338 } 339 340 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 341 { 342 struct ath_node *an = (struct ath_node *)sta->drv_priv; 343 344 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 345 ath_tx_node_cleanup(sc, an); 346 } 347 348 void ath9k_tasklet(unsigned long data) 349 { 350 struct ath_softc *sc = (struct ath_softc *)data; 351 struct ath_hw *ah = sc->sc_ah; 352 struct ath_common *common = ath9k_hw_common(ah); 353 enum ath_reset_type type; 354 unsigned long flags; 355 u32 status = sc->intrstatus; 356 u32 rxmask; 357 358 ath9k_ps_wakeup(sc); 359 spin_lock(&sc->sc_pcu_lock); 360 361 if ((status & ATH9K_INT_FATAL) || 362 (status & ATH9K_INT_BB_WATCHDOG)) { 363 364 if (status & ATH9K_INT_FATAL) 365 type = RESET_TYPE_FATAL_INT; 366 else 367 type = RESET_TYPE_BB_WATCHDOG; 368 369 ath9k_queue_reset(sc, type); 370 goto out; 371 } 372 373 spin_lock_irqsave(&sc->sc_pm_lock, flags); 374 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 375 /* 376 * TSF sync does not look correct; remain awake to sync with 377 * the next Beacon. 378 */ 379 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 380 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 381 } 382 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 383 384 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 385 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 386 ATH9K_INT_RXORN); 387 else 388 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 389 390 if (status & rxmask) { 391 /* Check for high priority Rx first */ 392 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 393 (status & ATH9K_INT_RXHP)) 394 ath_rx_tasklet(sc, 0, true); 395 396 ath_rx_tasklet(sc, 0, false); 397 } 398 399 if (status & ATH9K_INT_TX) { 400 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 401 ath_tx_edma_tasklet(sc); 402 else 403 ath_tx_tasklet(sc); 404 } 405 406 ath9k_btcoex_handle_interrupt(sc, status); 407 408 out: 409 /* re-enable hardware interrupt */ 410 ath9k_hw_enable_interrupts(ah); 411 412 spin_unlock(&sc->sc_pcu_lock); 413 ath9k_ps_restore(sc); 414 } 415 416 irqreturn_t ath_isr(int irq, void *dev) 417 { 418 #define SCHED_INTR ( \ 419 ATH9K_INT_FATAL | \ 420 ATH9K_INT_BB_WATCHDOG | \ 421 ATH9K_INT_RXORN | \ 422 ATH9K_INT_RXEOL | \ 423 ATH9K_INT_RX | \ 424 ATH9K_INT_RXLP | \ 425 ATH9K_INT_RXHP | \ 426 ATH9K_INT_TX | \ 427 ATH9K_INT_BMISS | \ 428 ATH9K_INT_CST | \ 429 ATH9K_INT_TSFOOR | \ 430 ATH9K_INT_GENTIMER | \ 431 ATH9K_INT_MCI) 432 433 struct ath_softc *sc = dev; 434 struct ath_hw *ah = sc->sc_ah; 435 struct ath_common *common = ath9k_hw_common(ah); 436 enum ath9k_int status; 437 bool sched = false; 438 439 /* 440 * The hardware is not ready/present, don't 441 * touch anything. Note this can happen early 442 * on if the IRQ is shared. 443 */ 444 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 445 return IRQ_NONE; 446 447 /* shared irq, not for us */ 448 449 if (!ath9k_hw_intrpend(ah)) 450 return IRQ_NONE; 451 452 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 453 ath9k_hw_kill_interrupts(ah); 454 return IRQ_HANDLED; 455 } 456 457 /* 458 * Figure out the reason(s) for the interrupt. Note 459 * that the hal returns a pseudo-ISR that may include 460 * bits we haven't explicitly enabled so we mask the 461 * value to insure we only process bits we requested. 462 */ 463 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 464 status &= ah->imask; /* discard unasked-for bits */ 465 466 /* 467 * If there are no status bits set, then this interrupt was not 468 * for me (should have been caught above). 469 */ 470 if (!status) 471 return IRQ_NONE; 472 473 /* Cache the status */ 474 sc->intrstatus = status; 475 476 if (status & SCHED_INTR) 477 sched = true; 478 479 /* 480 * If a FATAL or RXORN interrupt is received, we have to reset the 481 * chip immediately. 482 */ 483 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 484 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 485 goto chip_reset; 486 487 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 488 (status & ATH9K_INT_BB_WATCHDOG)) { 489 490 spin_lock(&common->cc_lock); 491 ath_hw_cycle_counters_update(common); 492 ar9003_hw_bb_watchdog_dbg_info(ah); 493 spin_unlock(&common->cc_lock); 494 495 goto chip_reset; 496 } 497 #ifdef CONFIG_PM_SLEEP 498 if (status & ATH9K_INT_BMISS) { 499 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 500 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 501 atomic_inc(&sc->wow_got_bmiss_intr); 502 atomic_dec(&sc->wow_sleep_proc_intr); 503 } 504 } 505 #endif 506 if (status & ATH9K_INT_SWBA) 507 tasklet_schedule(&sc->bcon_tasklet); 508 509 if (status & ATH9K_INT_TXURN) 510 ath9k_hw_updatetxtriglevel(ah, true); 511 512 if (status & ATH9K_INT_RXEOL) { 513 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 514 ath9k_hw_set_interrupts(ah); 515 } 516 517 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 518 if (status & ATH9K_INT_TIM_TIMER) { 519 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 520 goto chip_reset; 521 /* Clear RxAbort bit so that we can 522 * receive frames */ 523 ath9k_setpower(sc, ATH9K_PM_AWAKE); 524 spin_lock(&sc->sc_pm_lock); 525 ath9k_hw_setrxabort(sc->sc_ah, 0); 526 sc->ps_flags |= PS_WAIT_FOR_BEACON; 527 spin_unlock(&sc->sc_pm_lock); 528 } 529 530 chip_reset: 531 532 ath_debug_stat_interrupt(sc, status); 533 534 if (sched) { 535 /* turn off every interrupt */ 536 ath9k_hw_disable_interrupts(ah); 537 tasklet_schedule(&sc->intr_tq); 538 } 539 540 return IRQ_HANDLED; 541 542 #undef SCHED_INTR 543 } 544 545 static int ath_reset(struct ath_softc *sc, bool retry_tx) 546 { 547 int r; 548 549 ath9k_ps_wakeup(sc); 550 551 r = ath_reset_internal(sc, NULL, retry_tx); 552 553 if (retry_tx) { 554 int i; 555 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 556 if (ATH_TXQ_SETUP(sc, i)) { 557 spin_lock_bh(&sc->tx.txq[i].axq_lock); 558 ath_txq_schedule(sc, &sc->tx.txq[i]); 559 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 560 } 561 } 562 } 563 564 ath9k_ps_restore(sc); 565 566 return r; 567 } 568 569 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 570 { 571 #ifdef CONFIG_ATH9K_DEBUGFS 572 RESET_STAT_INC(sc, type); 573 #endif 574 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 575 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 576 } 577 578 void ath_reset_work(struct work_struct *work) 579 { 580 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 581 582 ath_reset(sc, true); 583 } 584 585 /**********************/ 586 /* mac80211 callbacks */ 587 /**********************/ 588 589 static int ath9k_start(struct ieee80211_hw *hw) 590 { 591 struct ath_softc *sc = hw->priv; 592 struct ath_hw *ah = sc->sc_ah; 593 struct ath_common *common = ath9k_hw_common(ah); 594 struct ieee80211_channel *curchan = hw->conf.channel; 595 struct ath9k_channel *init_channel; 596 int r; 597 598 ath_dbg(common, CONFIG, 599 "Starting driver with initial channel: %d MHz\n", 600 curchan->center_freq); 601 602 ath9k_ps_wakeup(sc); 603 mutex_lock(&sc->mutex); 604 605 init_channel = ath9k_cmn_get_curchannel(hw, ah); 606 607 /* Reset SERDES registers */ 608 ath9k_hw_configpcipowersave(ah, false); 609 610 /* 611 * The basic interface to setting the hardware in a good 612 * state is ``reset''. On return the hardware is known to 613 * be powered up and with interrupts disabled. This must 614 * be followed by initialization of the appropriate bits 615 * and then setup of the interrupt mask. 616 */ 617 spin_lock_bh(&sc->sc_pcu_lock); 618 619 atomic_set(&ah->intr_ref_cnt, -1); 620 621 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 622 if (r) { 623 ath_err(common, 624 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 625 r, curchan->center_freq); 626 ah->reset_power_on = false; 627 } 628 629 /* Setup our intr mask. */ 630 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 631 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 632 ATH9K_INT_GLOBAL; 633 634 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 635 ah->imask |= ATH9K_INT_RXHP | 636 ATH9K_INT_RXLP | 637 ATH9K_INT_BB_WATCHDOG; 638 else 639 ah->imask |= ATH9K_INT_RX; 640 641 ah->imask |= ATH9K_INT_GTT; 642 643 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 644 ah->imask |= ATH9K_INT_CST; 645 646 ath_mci_enable(sc); 647 648 clear_bit(SC_OP_INVALID, &sc->sc_flags); 649 sc->sc_ah->is_monitoring = false; 650 651 if (!ath_complete_reset(sc, false)) 652 ah->reset_power_on = false; 653 654 if (ah->led_pin >= 0) { 655 ath9k_hw_cfg_output(ah, ah->led_pin, 656 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 657 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 658 } 659 660 /* 661 * Reset key cache to sane defaults (all entries cleared) instead of 662 * semi-random values after suspend/resume. 663 */ 664 ath9k_cmn_init_crypto(sc->sc_ah); 665 666 spin_unlock_bh(&sc->sc_pcu_lock); 667 668 mutex_unlock(&sc->mutex); 669 670 ath9k_ps_restore(sc); 671 672 return 0; 673 } 674 675 static void ath9k_tx(struct ieee80211_hw *hw, 676 struct ieee80211_tx_control *control, 677 struct sk_buff *skb) 678 { 679 struct ath_softc *sc = hw->priv; 680 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 681 struct ath_tx_control txctl; 682 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 683 unsigned long flags; 684 685 if (sc->ps_enabled) { 686 /* 687 * mac80211 does not set PM field for normal data frames, so we 688 * need to update that based on the current PS mode. 689 */ 690 if (ieee80211_is_data(hdr->frame_control) && 691 !ieee80211_is_nullfunc(hdr->frame_control) && 692 !ieee80211_has_pm(hdr->frame_control)) { 693 ath_dbg(common, PS, 694 "Add PM=1 for a TX frame while in PS mode\n"); 695 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 696 } 697 } 698 699 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 700 /* 701 * We are using PS-Poll and mac80211 can request TX while in 702 * power save mode. Need to wake up hardware for the TX to be 703 * completed and if needed, also for RX of buffered frames. 704 */ 705 ath9k_ps_wakeup(sc); 706 spin_lock_irqsave(&sc->sc_pm_lock, flags); 707 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 708 ath9k_hw_setrxabort(sc->sc_ah, 0); 709 if (ieee80211_is_pspoll(hdr->frame_control)) { 710 ath_dbg(common, PS, 711 "Sending PS-Poll to pick a buffered frame\n"); 712 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 713 } else { 714 ath_dbg(common, PS, "Wake up to complete TX\n"); 715 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 716 } 717 /* 718 * The actual restore operation will happen only after 719 * the ps_flags bit is cleared. We are just dropping 720 * the ps_usecount here. 721 */ 722 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 723 ath9k_ps_restore(sc); 724 } 725 726 /* 727 * Cannot tx while the hardware is in full sleep, it first needs a full 728 * chip reset to recover from that 729 */ 730 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 731 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 732 goto exit; 733 } 734 735 memset(&txctl, 0, sizeof(struct ath_tx_control)); 736 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 737 txctl.sta = control->sta; 738 739 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 740 741 if (ath_tx_start(hw, skb, &txctl) != 0) { 742 ath_dbg(common, XMIT, "TX failed\n"); 743 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 744 goto exit; 745 } 746 747 return; 748 exit: 749 ieee80211_free_txskb(hw, skb); 750 } 751 752 static void ath9k_stop(struct ieee80211_hw *hw) 753 { 754 struct ath_softc *sc = hw->priv; 755 struct ath_hw *ah = sc->sc_ah; 756 struct ath_common *common = ath9k_hw_common(ah); 757 bool prev_idle; 758 759 mutex_lock(&sc->mutex); 760 761 ath_cancel_work(sc); 762 del_timer_sync(&sc->rx_poll_timer); 763 764 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 765 ath_dbg(common, ANY, "Device not present\n"); 766 mutex_unlock(&sc->mutex); 767 return; 768 } 769 770 /* Ensure HW is awake when we try to shut it down. */ 771 ath9k_ps_wakeup(sc); 772 773 spin_lock_bh(&sc->sc_pcu_lock); 774 775 /* prevent tasklets to enable interrupts once we disable them */ 776 ah->imask &= ~ATH9K_INT_GLOBAL; 777 778 /* make sure h/w will not generate any interrupt 779 * before setting the invalid flag. */ 780 ath9k_hw_disable_interrupts(ah); 781 782 spin_unlock_bh(&sc->sc_pcu_lock); 783 784 /* we can now sync irq and kill any running tasklets, since we already 785 * disabled interrupts and not holding a spin lock */ 786 synchronize_irq(sc->irq); 787 tasklet_kill(&sc->intr_tq); 788 tasklet_kill(&sc->bcon_tasklet); 789 790 prev_idle = sc->ps_idle; 791 sc->ps_idle = true; 792 793 spin_lock_bh(&sc->sc_pcu_lock); 794 795 if (ah->led_pin >= 0) { 796 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 797 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 798 } 799 800 ath_prepare_reset(sc, false); 801 802 if (sc->rx.frag) { 803 dev_kfree_skb_any(sc->rx.frag); 804 sc->rx.frag = NULL; 805 } 806 807 if (!ah->curchan) 808 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 809 810 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 811 ath9k_hw_phy_disable(ah); 812 813 ath9k_hw_configpcipowersave(ah, true); 814 815 spin_unlock_bh(&sc->sc_pcu_lock); 816 817 ath9k_ps_restore(sc); 818 819 set_bit(SC_OP_INVALID, &sc->sc_flags); 820 sc->ps_idle = prev_idle; 821 822 mutex_unlock(&sc->mutex); 823 824 ath_dbg(common, CONFIG, "Driver halt\n"); 825 } 826 827 bool ath9k_uses_beacons(int type) 828 { 829 switch (type) { 830 case NL80211_IFTYPE_AP: 831 case NL80211_IFTYPE_ADHOC: 832 case NL80211_IFTYPE_MESH_POINT: 833 return true; 834 default: 835 return false; 836 } 837 } 838 839 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 840 { 841 struct ath9k_vif_iter_data *iter_data = data; 842 int i; 843 844 if (iter_data->hw_macaddr) 845 for (i = 0; i < ETH_ALEN; i++) 846 iter_data->mask[i] &= 847 ~(iter_data->hw_macaddr[i] ^ mac[i]); 848 849 switch (vif->type) { 850 case NL80211_IFTYPE_AP: 851 iter_data->naps++; 852 break; 853 case NL80211_IFTYPE_STATION: 854 iter_data->nstations++; 855 break; 856 case NL80211_IFTYPE_ADHOC: 857 iter_data->nadhocs++; 858 break; 859 case NL80211_IFTYPE_MESH_POINT: 860 iter_data->nmeshes++; 861 break; 862 case NL80211_IFTYPE_WDS: 863 iter_data->nwds++; 864 break; 865 default: 866 break; 867 } 868 } 869 870 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 871 { 872 struct ath_softc *sc = data; 873 struct ath_vif *avp = (void *)vif->drv_priv; 874 875 if (vif->type != NL80211_IFTYPE_STATION) 876 return; 877 878 if (avp->primary_sta_vif) 879 ath9k_set_assoc_state(sc, vif); 880 } 881 882 /* Called with sc->mutex held. */ 883 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 884 struct ieee80211_vif *vif, 885 struct ath9k_vif_iter_data *iter_data) 886 { 887 struct ath_softc *sc = hw->priv; 888 struct ath_hw *ah = sc->sc_ah; 889 struct ath_common *common = ath9k_hw_common(ah); 890 891 /* 892 * Use the hardware MAC address as reference, the hardware uses it 893 * together with the BSSID mask when matching addresses. 894 */ 895 memset(iter_data, 0, sizeof(*iter_data)); 896 iter_data->hw_macaddr = common->macaddr; 897 memset(&iter_data->mask, 0xff, ETH_ALEN); 898 899 if (vif) 900 ath9k_vif_iter(iter_data, vif->addr, vif); 901 902 /* Get list of all active MAC addresses */ 903 ieee80211_iterate_active_interfaces_atomic( 904 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 905 ath9k_vif_iter, iter_data); 906 } 907 908 /* Called with sc->mutex held. */ 909 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 910 struct ieee80211_vif *vif) 911 { 912 struct ath_softc *sc = hw->priv; 913 struct ath_hw *ah = sc->sc_ah; 914 struct ath_common *common = ath9k_hw_common(ah); 915 struct ath9k_vif_iter_data iter_data; 916 enum nl80211_iftype old_opmode = ah->opmode; 917 918 ath9k_calculate_iter_data(hw, vif, &iter_data); 919 920 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 921 ath_hw_setbssidmask(common); 922 923 if (iter_data.naps > 0) { 924 ath9k_hw_set_tsfadjust(ah, true); 925 ah->opmode = NL80211_IFTYPE_AP; 926 } else { 927 ath9k_hw_set_tsfadjust(ah, false); 928 929 if (iter_data.nmeshes) 930 ah->opmode = NL80211_IFTYPE_MESH_POINT; 931 else if (iter_data.nwds) 932 ah->opmode = NL80211_IFTYPE_AP; 933 else if (iter_data.nadhocs) 934 ah->opmode = NL80211_IFTYPE_ADHOC; 935 else 936 ah->opmode = NL80211_IFTYPE_STATION; 937 } 938 939 ath9k_hw_setopmode(ah); 940 941 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 942 ah->imask |= ATH9K_INT_TSFOOR; 943 else 944 ah->imask &= ~ATH9K_INT_TSFOOR; 945 946 ath9k_hw_set_interrupts(ah); 947 948 /* 949 * If we are changing the opmode to STATION, 950 * a beacon sync needs to be done. 951 */ 952 if (ah->opmode == NL80211_IFTYPE_STATION && 953 old_opmode == NL80211_IFTYPE_AP && 954 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 955 ieee80211_iterate_active_interfaces_atomic( 956 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 957 ath9k_sta_vif_iter, sc); 958 } 959 } 960 961 static int ath9k_add_interface(struct ieee80211_hw *hw, 962 struct ieee80211_vif *vif) 963 { 964 struct ath_softc *sc = hw->priv; 965 struct ath_hw *ah = sc->sc_ah; 966 struct ath_common *common = ath9k_hw_common(ah); 967 968 mutex_lock(&sc->mutex); 969 970 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 971 sc->nvifs++; 972 973 ath9k_ps_wakeup(sc); 974 ath9k_calculate_summary_state(hw, vif); 975 ath9k_ps_restore(sc); 976 977 if (ath9k_uses_beacons(vif->type)) 978 ath9k_beacon_assign_slot(sc, vif); 979 980 mutex_unlock(&sc->mutex); 981 return 0; 982 } 983 984 static int ath9k_change_interface(struct ieee80211_hw *hw, 985 struct ieee80211_vif *vif, 986 enum nl80211_iftype new_type, 987 bool p2p) 988 { 989 struct ath_softc *sc = hw->priv; 990 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 991 992 ath_dbg(common, CONFIG, "Change Interface\n"); 993 mutex_lock(&sc->mutex); 994 995 if (ath9k_uses_beacons(vif->type)) 996 ath9k_beacon_remove_slot(sc, vif); 997 998 vif->type = new_type; 999 vif->p2p = p2p; 1000 1001 ath9k_ps_wakeup(sc); 1002 ath9k_calculate_summary_state(hw, vif); 1003 ath9k_ps_restore(sc); 1004 1005 if (ath9k_uses_beacons(vif->type)) 1006 ath9k_beacon_assign_slot(sc, vif); 1007 1008 mutex_unlock(&sc->mutex); 1009 return 0; 1010 } 1011 1012 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1013 struct ieee80211_vif *vif) 1014 { 1015 struct ath_softc *sc = hw->priv; 1016 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1017 1018 ath_dbg(common, CONFIG, "Detach Interface\n"); 1019 1020 mutex_lock(&sc->mutex); 1021 1022 sc->nvifs--; 1023 1024 if (ath9k_uses_beacons(vif->type)) 1025 ath9k_beacon_remove_slot(sc, vif); 1026 1027 ath9k_ps_wakeup(sc); 1028 ath9k_calculate_summary_state(hw, NULL); 1029 ath9k_ps_restore(sc); 1030 1031 mutex_unlock(&sc->mutex); 1032 } 1033 1034 static void ath9k_enable_ps(struct ath_softc *sc) 1035 { 1036 struct ath_hw *ah = sc->sc_ah; 1037 struct ath_common *common = ath9k_hw_common(ah); 1038 1039 sc->ps_enabled = true; 1040 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1041 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1042 ah->imask |= ATH9K_INT_TIM_TIMER; 1043 ath9k_hw_set_interrupts(ah); 1044 } 1045 ath9k_hw_setrxabort(ah, 1); 1046 } 1047 ath_dbg(common, PS, "PowerSave enabled\n"); 1048 } 1049 1050 static void ath9k_disable_ps(struct ath_softc *sc) 1051 { 1052 struct ath_hw *ah = sc->sc_ah; 1053 struct ath_common *common = ath9k_hw_common(ah); 1054 1055 sc->ps_enabled = false; 1056 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1057 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1058 ath9k_hw_setrxabort(ah, 0); 1059 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1060 PS_WAIT_FOR_CAB | 1061 PS_WAIT_FOR_PSPOLL_DATA | 1062 PS_WAIT_FOR_TX_ACK); 1063 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1064 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1065 ath9k_hw_set_interrupts(ah); 1066 } 1067 } 1068 ath_dbg(common, PS, "PowerSave disabled\n"); 1069 } 1070 1071 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1072 { 1073 struct ath_softc *sc = hw->priv; 1074 struct ath_hw *ah = sc->sc_ah; 1075 struct ath_common *common = ath9k_hw_common(ah); 1076 struct ieee80211_conf *conf = &hw->conf; 1077 bool reset_channel = false; 1078 1079 ath9k_ps_wakeup(sc); 1080 mutex_lock(&sc->mutex); 1081 1082 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1083 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1084 if (sc->ps_idle) { 1085 ath_cancel_work(sc); 1086 ath9k_stop_btcoex(sc); 1087 } else { 1088 ath9k_start_btcoex(sc); 1089 /* 1090 * The chip needs a reset to properly wake up from 1091 * full sleep 1092 */ 1093 reset_channel = ah->chip_fullsleep; 1094 } 1095 } 1096 1097 /* 1098 * We just prepare to enable PS. We have to wait until our AP has 1099 * ACK'd our null data frame to disable RX otherwise we'll ignore 1100 * those ACKs and end up retransmitting the same null data frames. 1101 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1102 */ 1103 if (changed & IEEE80211_CONF_CHANGE_PS) { 1104 unsigned long flags; 1105 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1106 if (conf->flags & IEEE80211_CONF_PS) 1107 ath9k_enable_ps(sc); 1108 else 1109 ath9k_disable_ps(sc); 1110 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1111 } 1112 1113 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1114 if (conf->flags & IEEE80211_CONF_MONITOR) { 1115 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1116 sc->sc_ah->is_monitoring = true; 1117 } else { 1118 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1119 sc->sc_ah->is_monitoring = false; 1120 } 1121 } 1122 1123 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1124 struct ieee80211_channel *curchan = hw->conf.channel; 1125 int pos = curchan->hw_value; 1126 int old_pos = -1; 1127 unsigned long flags; 1128 1129 if (ah->curchan) 1130 old_pos = ah->curchan - &ah->channels[0]; 1131 1132 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1133 curchan->center_freq, conf->channel_type); 1134 1135 /* update survey stats for the old channel before switching */ 1136 spin_lock_irqsave(&common->cc_lock, flags); 1137 ath_update_survey_stats(sc); 1138 spin_unlock_irqrestore(&common->cc_lock, flags); 1139 1140 /* 1141 * Preserve the current channel values, before updating 1142 * the same channel 1143 */ 1144 if (ah->curchan && (old_pos == pos)) 1145 ath9k_hw_getnf(ah, ah->curchan); 1146 1147 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1148 curchan, conf->channel_type); 1149 1150 /* 1151 * If the operating channel changes, change the survey in-use flags 1152 * along with it. 1153 * Reset the survey data for the new channel, unless we're switching 1154 * back to the operating channel from an off-channel operation. 1155 */ 1156 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1157 sc->cur_survey != &sc->survey[pos]) { 1158 1159 if (sc->cur_survey) 1160 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1161 1162 sc->cur_survey = &sc->survey[pos]; 1163 1164 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1165 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1166 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1167 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1168 } 1169 1170 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1171 ath_err(common, "Unable to set channel\n"); 1172 mutex_unlock(&sc->mutex); 1173 ath9k_ps_restore(sc); 1174 return -EINVAL; 1175 } 1176 1177 /* 1178 * The most recent snapshot of channel->noisefloor for the old 1179 * channel is only available after the hardware reset. Copy it to 1180 * the survey stats now. 1181 */ 1182 if (old_pos >= 0) 1183 ath_update_survey_nf(sc, old_pos); 1184 } 1185 1186 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1187 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1188 sc->config.txpowlimit = 2 * conf->power_level; 1189 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1190 sc->config.txpowlimit, &sc->curtxpow); 1191 } 1192 1193 mutex_unlock(&sc->mutex); 1194 ath9k_ps_restore(sc); 1195 1196 return 0; 1197 } 1198 1199 #define SUPPORTED_FILTERS \ 1200 (FIF_PROMISC_IN_BSS | \ 1201 FIF_ALLMULTI | \ 1202 FIF_CONTROL | \ 1203 FIF_PSPOLL | \ 1204 FIF_OTHER_BSS | \ 1205 FIF_BCN_PRBRESP_PROMISC | \ 1206 FIF_PROBE_REQ | \ 1207 FIF_FCSFAIL) 1208 1209 /* FIXME: sc->sc_full_reset ? */ 1210 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1211 unsigned int changed_flags, 1212 unsigned int *total_flags, 1213 u64 multicast) 1214 { 1215 struct ath_softc *sc = hw->priv; 1216 u32 rfilt; 1217 1218 changed_flags &= SUPPORTED_FILTERS; 1219 *total_flags &= SUPPORTED_FILTERS; 1220 1221 sc->rx.rxfilter = *total_flags; 1222 ath9k_ps_wakeup(sc); 1223 rfilt = ath_calcrxfilter(sc); 1224 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1225 ath9k_ps_restore(sc); 1226 1227 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1228 rfilt); 1229 } 1230 1231 static int ath9k_sta_add(struct ieee80211_hw *hw, 1232 struct ieee80211_vif *vif, 1233 struct ieee80211_sta *sta) 1234 { 1235 struct ath_softc *sc = hw->priv; 1236 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1237 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1238 struct ieee80211_key_conf ps_key = { }; 1239 1240 ath_node_attach(sc, sta, vif); 1241 1242 if (vif->type != NL80211_IFTYPE_AP && 1243 vif->type != NL80211_IFTYPE_AP_VLAN) 1244 return 0; 1245 1246 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1247 1248 return 0; 1249 } 1250 1251 static void ath9k_del_ps_key(struct ath_softc *sc, 1252 struct ieee80211_vif *vif, 1253 struct ieee80211_sta *sta) 1254 { 1255 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1256 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1257 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1258 1259 if (!an->ps_key) 1260 return; 1261 1262 ath_key_delete(common, &ps_key); 1263 } 1264 1265 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1266 struct ieee80211_vif *vif, 1267 struct ieee80211_sta *sta) 1268 { 1269 struct ath_softc *sc = hw->priv; 1270 1271 ath9k_del_ps_key(sc, vif, sta); 1272 ath_node_detach(sc, sta); 1273 1274 return 0; 1275 } 1276 1277 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1278 struct ieee80211_vif *vif, 1279 enum sta_notify_cmd cmd, 1280 struct ieee80211_sta *sta) 1281 { 1282 struct ath_softc *sc = hw->priv; 1283 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1284 1285 if (!sta->ht_cap.ht_supported) 1286 return; 1287 1288 switch (cmd) { 1289 case STA_NOTIFY_SLEEP: 1290 an->sleeping = true; 1291 ath_tx_aggr_sleep(sta, sc, an); 1292 break; 1293 case STA_NOTIFY_AWAKE: 1294 an->sleeping = false; 1295 ath_tx_aggr_wakeup(sc, an); 1296 break; 1297 } 1298 } 1299 1300 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1301 struct ieee80211_vif *vif, u16 queue, 1302 const struct ieee80211_tx_queue_params *params) 1303 { 1304 struct ath_softc *sc = hw->priv; 1305 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1306 struct ath_txq *txq; 1307 struct ath9k_tx_queue_info qi; 1308 int ret = 0; 1309 1310 if (queue >= IEEE80211_NUM_ACS) 1311 return 0; 1312 1313 txq = sc->tx.txq_map[queue]; 1314 1315 ath9k_ps_wakeup(sc); 1316 mutex_lock(&sc->mutex); 1317 1318 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1319 1320 qi.tqi_aifs = params->aifs; 1321 qi.tqi_cwmin = params->cw_min; 1322 qi.tqi_cwmax = params->cw_max; 1323 qi.tqi_burstTime = params->txop * 32; 1324 1325 ath_dbg(common, CONFIG, 1326 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1327 queue, txq->axq_qnum, params->aifs, params->cw_min, 1328 params->cw_max, params->txop); 1329 1330 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1331 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1332 if (ret) 1333 ath_err(common, "TXQ Update failed\n"); 1334 1335 mutex_unlock(&sc->mutex); 1336 ath9k_ps_restore(sc); 1337 1338 return ret; 1339 } 1340 1341 static int ath9k_set_key(struct ieee80211_hw *hw, 1342 enum set_key_cmd cmd, 1343 struct ieee80211_vif *vif, 1344 struct ieee80211_sta *sta, 1345 struct ieee80211_key_conf *key) 1346 { 1347 struct ath_softc *sc = hw->priv; 1348 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1349 int ret = 0; 1350 1351 if (ath9k_modparam_nohwcrypt) 1352 return -ENOSPC; 1353 1354 if ((vif->type == NL80211_IFTYPE_ADHOC || 1355 vif->type == NL80211_IFTYPE_MESH_POINT) && 1356 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1357 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1358 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1359 /* 1360 * For now, disable hw crypto for the RSN IBSS group keys. This 1361 * could be optimized in the future to use a modified key cache 1362 * design to support per-STA RX GTK, but until that gets 1363 * implemented, use of software crypto for group addressed 1364 * frames is a acceptable to allow RSN IBSS to be used. 1365 */ 1366 return -EOPNOTSUPP; 1367 } 1368 1369 mutex_lock(&sc->mutex); 1370 ath9k_ps_wakeup(sc); 1371 ath_dbg(common, CONFIG, "Set HW Key\n"); 1372 1373 switch (cmd) { 1374 case SET_KEY: 1375 if (sta) 1376 ath9k_del_ps_key(sc, vif, sta); 1377 1378 ret = ath_key_config(common, vif, sta, key); 1379 if (ret >= 0) { 1380 key->hw_key_idx = ret; 1381 /* push IV and Michael MIC generation to stack */ 1382 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1383 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1384 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1385 if (sc->sc_ah->sw_mgmt_crypto && 1386 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1387 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1388 ret = 0; 1389 } 1390 break; 1391 case DISABLE_KEY: 1392 ath_key_delete(common, key); 1393 break; 1394 default: 1395 ret = -EINVAL; 1396 } 1397 1398 ath9k_ps_restore(sc); 1399 mutex_unlock(&sc->mutex); 1400 1401 return ret; 1402 } 1403 1404 static void ath9k_set_assoc_state(struct ath_softc *sc, 1405 struct ieee80211_vif *vif) 1406 { 1407 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1408 struct ath_vif *avp = (void *)vif->drv_priv; 1409 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1410 unsigned long flags; 1411 1412 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1413 avp->primary_sta_vif = true; 1414 1415 /* 1416 * Set the AID, BSSID and do beacon-sync only when 1417 * the HW opmode is STATION. 1418 * 1419 * But the primary bit is set above in any case. 1420 */ 1421 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1422 return; 1423 1424 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1425 common->curaid = bss_conf->aid; 1426 ath9k_hw_write_associd(sc->sc_ah); 1427 1428 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1429 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1430 1431 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1432 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1433 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1434 1435 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1436 ath9k_mci_update_wlan_channels(sc, false); 1437 1438 ath_dbg(common, CONFIG, 1439 "Primary Station interface: %pM, BSSID: %pM\n", 1440 vif->addr, common->curbssid); 1441 } 1442 1443 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1444 { 1445 struct ath_softc *sc = data; 1446 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1447 1448 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1449 return; 1450 1451 if (bss_conf->assoc) 1452 ath9k_set_assoc_state(sc, vif); 1453 } 1454 1455 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1456 struct ieee80211_vif *vif, 1457 struct ieee80211_bss_conf *bss_conf, 1458 u32 changed) 1459 { 1460 #define CHECK_ANI \ 1461 (BSS_CHANGED_ASSOC | \ 1462 BSS_CHANGED_IBSS | \ 1463 BSS_CHANGED_BEACON_ENABLED) 1464 1465 struct ath_softc *sc = hw->priv; 1466 struct ath_hw *ah = sc->sc_ah; 1467 struct ath_common *common = ath9k_hw_common(ah); 1468 struct ath_vif *avp = (void *)vif->drv_priv; 1469 int slottime; 1470 1471 ath9k_ps_wakeup(sc); 1472 mutex_lock(&sc->mutex); 1473 1474 if (changed & BSS_CHANGED_ASSOC) { 1475 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1476 bss_conf->bssid, bss_conf->assoc); 1477 1478 if (avp->primary_sta_vif && !bss_conf->assoc) { 1479 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1480 avp->primary_sta_vif = false; 1481 1482 if (ah->opmode == NL80211_IFTYPE_STATION) 1483 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1484 } 1485 1486 ieee80211_iterate_active_interfaces_atomic( 1487 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1488 ath9k_bss_assoc_iter, sc); 1489 1490 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1491 ah->opmode == NL80211_IFTYPE_STATION) { 1492 memset(common->curbssid, 0, ETH_ALEN); 1493 common->curaid = 0; 1494 ath9k_hw_write_associd(sc->sc_ah); 1495 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1496 ath9k_mci_update_wlan_channels(sc, true); 1497 } 1498 } 1499 1500 if (changed & BSS_CHANGED_IBSS) { 1501 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1502 common->curaid = bss_conf->aid; 1503 ath9k_hw_write_associd(sc->sc_ah); 1504 } 1505 1506 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1507 (changed & BSS_CHANGED_BEACON_INT)) { 1508 if (ah->opmode == NL80211_IFTYPE_AP && 1509 bss_conf->enable_beacon) 1510 ath9k_set_tsfadjust(sc, vif); 1511 if (ath9k_allow_beacon_config(sc, vif)) 1512 ath9k_beacon_config(sc, vif, changed); 1513 } 1514 1515 if (changed & BSS_CHANGED_ERP_SLOT) { 1516 if (bss_conf->use_short_slot) 1517 slottime = 9; 1518 else 1519 slottime = 20; 1520 if (vif->type == NL80211_IFTYPE_AP) { 1521 /* 1522 * Defer update, so that connected stations can adjust 1523 * their settings at the same time. 1524 * See beacon.c for more details 1525 */ 1526 sc->beacon.slottime = slottime; 1527 sc->beacon.updateslot = UPDATE; 1528 } else { 1529 ah->slottime = slottime; 1530 ath9k_hw_init_global_settings(ah); 1531 } 1532 } 1533 1534 if (changed & CHECK_ANI) 1535 ath_check_ani(sc); 1536 1537 mutex_unlock(&sc->mutex); 1538 ath9k_ps_restore(sc); 1539 1540 #undef CHECK_ANI 1541 } 1542 1543 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1544 { 1545 struct ath_softc *sc = hw->priv; 1546 u64 tsf; 1547 1548 mutex_lock(&sc->mutex); 1549 ath9k_ps_wakeup(sc); 1550 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1551 ath9k_ps_restore(sc); 1552 mutex_unlock(&sc->mutex); 1553 1554 return tsf; 1555 } 1556 1557 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1558 struct ieee80211_vif *vif, 1559 u64 tsf) 1560 { 1561 struct ath_softc *sc = hw->priv; 1562 1563 mutex_lock(&sc->mutex); 1564 ath9k_ps_wakeup(sc); 1565 ath9k_hw_settsf64(sc->sc_ah, tsf); 1566 ath9k_ps_restore(sc); 1567 mutex_unlock(&sc->mutex); 1568 } 1569 1570 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1571 { 1572 struct ath_softc *sc = hw->priv; 1573 1574 mutex_lock(&sc->mutex); 1575 1576 ath9k_ps_wakeup(sc); 1577 ath9k_hw_reset_tsf(sc->sc_ah); 1578 ath9k_ps_restore(sc); 1579 1580 mutex_unlock(&sc->mutex); 1581 } 1582 1583 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1584 struct ieee80211_vif *vif, 1585 enum ieee80211_ampdu_mlme_action action, 1586 struct ieee80211_sta *sta, 1587 u16 tid, u16 *ssn, u8 buf_size) 1588 { 1589 struct ath_softc *sc = hw->priv; 1590 int ret = 0; 1591 1592 local_bh_disable(); 1593 1594 switch (action) { 1595 case IEEE80211_AMPDU_RX_START: 1596 break; 1597 case IEEE80211_AMPDU_RX_STOP: 1598 break; 1599 case IEEE80211_AMPDU_TX_START: 1600 ath9k_ps_wakeup(sc); 1601 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1602 if (!ret) 1603 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1604 ath9k_ps_restore(sc); 1605 break; 1606 case IEEE80211_AMPDU_TX_STOP: 1607 ath9k_ps_wakeup(sc); 1608 ath_tx_aggr_stop(sc, sta, tid); 1609 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1610 ath9k_ps_restore(sc); 1611 break; 1612 case IEEE80211_AMPDU_TX_OPERATIONAL: 1613 ath9k_ps_wakeup(sc); 1614 ath_tx_aggr_resume(sc, sta, tid); 1615 ath9k_ps_restore(sc); 1616 break; 1617 default: 1618 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1619 } 1620 1621 local_bh_enable(); 1622 1623 return ret; 1624 } 1625 1626 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1627 struct survey_info *survey) 1628 { 1629 struct ath_softc *sc = hw->priv; 1630 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1631 struct ieee80211_supported_band *sband; 1632 struct ieee80211_channel *chan; 1633 unsigned long flags; 1634 int pos; 1635 1636 spin_lock_irqsave(&common->cc_lock, flags); 1637 if (idx == 0) 1638 ath_update_survey_stats(sc); 1639 1640 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1641 if (sband && idx >= sband->n_channels) { 1642 idx -= sband->n_channels; 1643 sband = NULL; 1644 } 1645 1646 if (!sband) 1647 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1648 1649 if (!sband || idx >= sband->n_channels) { 1650 spin_unlock_irqrestore(&common->cc_lock, flags); 1651 return -ENOENT; 1652 } 1653 1654 chan = &sband->channels[idx]; 1655 pos = chan->hw_value; 1656 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1657 survey->channel = chan; 1658 spin_unlock_irqrestore(&common->cc_lock, flags); 1659 1660 return 0; 1661 } 1662 1663 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1664 { 1665 struct ath_softc *sc = hw->priv; 1666 struct ath_hw *ah = sc->sc_ah; 1667 1668 mutex_lock(&sc->mutex); 1669 ah->coverage_class = coverage_class; 1670 1671 ath9k_ps_wakeup(sc); 1672 ath9k_hw_init_global_settings(ah); 1673 ath9k_ps_restore(sc); 1674 1675 mutex_unlock(&sc->mutex); 1676 } 1677 1678 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 1679 { 1680 struct ath_softc *sc = hw->priv; 1681 struct ath_hw *ah = sc->sc_ah; 1682 struct ath_common *common = ath9k_hw_common(ah); 1683 int timeout = 200; /* ms */ 1684 int i, j; 1685 bool drain_txq; 1686 1687 mutex_lock(&sc->mutex); 1688 cancel_delayed_work_sync(&sc->tx_complete_work); 1689 1690 if (ah->ah_flags & AH_UNPLUGGED) { 1691 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1692 mutex_unlock(&sc->mutex); 1693 return; 1694 } 1695 1696 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1697 ath_dbg(common, ANY, "Device not present\n"); 1698 mutex_unlock(&sc->mutex); 1699 return; 1700 } 1701 1702 for (j = 0; j < timeout; j++) { 1703 bool npend = false; 1704 1705 if (j) 1706 usleep_range(1000, 2000); 1707 1708 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1709 if (!ATH_TXQ_SETUP(sc, i)) 1710 continue; 1711 1712 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1713 1714 if (npend) 1715 break; 1716 } 1717 1718 if (!npend) 1719 break; 1720 } 1721 1722 if (drop) { 1723 ath9k_ps_wakeup(sc); 1724 spin_lock_bh(&sc->sc_pcu_lock); 1725 drain_txq = ath_drain_all_txq(sc, false); 1726 spin_unlock_bh(&sc->sc_pcu_lock); 1727 1728 if (!drain_txq) 1729 ath_reset(sc, false); 1730 1731 ath9k_ps_restore(sc); 1732 ieee80211_wake_queues(hw); 1733 } 1734 1735 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1736 mutex_unlock(&sc->mutex); 1737 } 1738 1739 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1740 { 1741 struct ath_softc *sc = hw->priv; 1742 int i; 1743 1744 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1745 if (!ATH_TXQ_SETUP(sc, i)) 1746 continue; 1747 1748 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1749 return true; 1750 } 1751 return false; 1752 } 1753 1754 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1755 { 1756 struct ath_softc *sc = hw->priv; 1757 struct ath_hw *ah = sc->sc_ah; 1758 struct ieee80211_vif *vif; 1759 struct ath_vif *avp; 1760 struct ath_buf *bf; 1761 struct ath_tx_status ts; 1762 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1763 int status; 1764 1765 vif = sc->beacon.bslot[0]; 1766 if (!vif) 1767 return 0; 1768 1769 if (!vif->bss_conf.enable_beacon) 1770 return 0; 1771 1772 avp = (void *)vif->drv_priv; 1773 1774 if (!sc->beacon.tx_processed && !edma) { 1775 tasklet_disable(&sc->bcon_tasklet); 1776 1777 bf = avp->av_bcbuf; 1778 if (!bf || !bf->bf_mpdu) 1779 goto skip; 1780 1781 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1782 if (status == -EINPROGRESS) 1783 goto skip; 1784 1785 sc->beacon.tx_processed = true; 1786 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1787 1788 skip: 1789 tasklet_enable(&sc->bcon_tasklet); 1790 } 1791 1792 return sc->beacon.tx_last; 1793 } 1794 1795 static int ath9k_get_stats(struct ieee80211_hw *hw, 1796 struct ieee80211_low_level_stats *stats) 1797 { 1798 struct ath_softc *sc = hw->priv; 1799 struct ath_hw *ah = sc->sc_ah; 1800 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1801 1802 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1803 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1804 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1805 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1806 return 0; 1807 } 1808 1809 static u32 fill_chainmask(u32 cap, u32 new) 1810 { 1811 u32 filled = 0; 1812 int i; 1813 1814 for (i = 0; cap && new; i++, cap >>= 1) { 1815 if (!(cap & BIT(0))) 1816 continue; 1817 1818 if (new & BIT(0)) 1819 filled |= BIT(i); 1820 1821 new >>= 1; 1822 } 1823 1824 return filled; 1825 } 1826 1827 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1828 { 1829 if (AR_SREV_9300_20_OR_LATER(ah)) 1830 return true; 1831 1832 switch (val & 0x7) { 1833 case 0x1: 1834 case 0x3: 1835 case 0x7: 1836 return true; 1837 case 0x2: 1838 return (ah->caps.rx_chainmask == 1); 1839 default: 1840 return false; 1841 } 1842 } 1843 1844 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1845 { 1846 struct ath_softc *sc = hw->priv; 1847 struct ath_hw *ah = sc->sc_ah; 1848 1849 if (ah->caps.rx_chainmask != 1) 1850 rx_ant |= tx_ant; 1851 1852 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1853 return -EINVAL; 1854 1855 sc->ant_rx = rx_ant; 1856 sc->ant_tx = tx_ant; 1857 1858 if (ah->caps.rx_chainmask == 1) 1859 return 0; 1860 1861 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 1862 if (AR_SREV_9100(ah)) 1863 ah->rxchainmask = 0x7; 1864 else 1865 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 1866 1867 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 1868 ath9k_reload_chainmask_settings(sc); 1869 1870 return 0; 1871 } 1872 1873 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 1874 { 1875 struct ath_softc *sc = hw->priv; 1876 1877 *tx_ant = sc->ant_tx; 1878 *rx_ant = sc->ant_rx; 1879 return 0; 1880 } 1881 1882 #ifdef CONFIG_PM_SLEEP 1883 1884 static void ath9k_wow_map_triggers(struct ath_softc *sc, 1885 struct cfg80211_wowlan *wowlan, 1886 u32 *wow_triggers) 1887 { 1888 if (wowlan->disconnect) 1889 *wow_triggers |= AH_WOW_LINK_CHANGE | 1890 AH_WOW_BEACON_MISS; 1891 if (wowlan->magic_pkt) 1892 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 1893 1894 if (wowlan->n_patterns) 1895 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 1896 1897 sc->wow_enabled = *wow_triggers; 1898 1899 } 1900 1901 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 1902 { 1903 struct ath_hw *ah = sc->sc_ah; 1904 struct ath_common *common = ath9k_hw_common(ah); 1905 struct ath9k_hw_capabilities *pcaps = &ah->caps; 1906 int pattern_count = 0; 1907 int i, byte_cnt; 1908 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 1909 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 1910 1911 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 1912 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 1913 1914 /* 1915 * Create Dissassociate / Deauthenticate packet filter 1916 * 1917 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 1918 * +--------------+----------+---------+--------+--------+---- 1919 * + Frame Control+ Duration + DA + SA + BSSID + 1920 * +--------------+----------+---------+--------+--------+---- 1921 * 1922 * The above is the management frame format for disassociate/ 1923 * deauthenticate pattern, from this we need to match the first byte 1924 * of 'Frame Control' and DA, SA, and BSSID fields 1925 * (skipping 2nd byte of FC and Duration feild. 1926 * 1927 * Disassociate pattern 1928 * -------------------- 1929 * Frame control = 00 00 1010 1930 * DA, SA, BSSID = x:x:x:x:x:x 1931 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1932 * | x:x:x:x:x:x -- 22 bytes 1933 * 1934 * Deauthenticate pattern 1935 * ---------------------- 1936 * Frame control = 00 00 1100 1937 * DA, SA, BSSID = x:x:x:x:x:x 1938 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1939 * | x:x:x:x:x:x -- 22 bytes 1940 */ 1941 1942 /* Create Disassociate Pattern first */ 1943 1944 byte_cnt = 0; 1945 1946 /* Fill out the mask with all FF's */ 1947 1948 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 1949 dis_deauth_mask[i] = 0xff; 1950 1951 /* copy the first byte of frame control field */ 1952 dis_deauth_pattern[byte_cnt] = 0xa0; 1953 byte_cnt++; 1954 1955 /* skip 2nd byte of frame control and Duration field */ 1956 byte_cnt += 3; 1957 1958 /* 1959 * need not match the destination mac address, it can be a broadcast 1960 * mac address or an unicast to this station 1961 */ 1962 byte_cnt += 6; 1963 1964 /* copy the source mac address */ 1965 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1966 1967 byte_cnt += 6; 1968 1969 /* copy the bssid, its same as the source mac address */ 1970 1971 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1972 1973 /* Create Disassociate pattern mask */ 1974 1975 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { 1976 1977 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { 1978 /* 1979 * for AR9280, because of hardware limitation, the 1980 * first 4 bytes have to be matched for all patterns. 1981 * the mask for disassociation and de-auth pattern 1982 * matching need to enable the first 4 bytes. 1983 * also the duration field needs to be filled. 1984 */ 1985 dis_deauth_mask[0] = 0xf0; 1986 1987 /* 1988 * fill in duration field 1989 FIXME: what is the exact value ? 1990 */ 1991 dis_deauth_pattern[2] = 0xff; 1992 dis_deauth_pattern[3] = 0xff; 1993 } else { 1994 dis_deauth_mask[0] = 0xfe; 1995 } 1996 1997 dis_deauth_mask[1] = 0x03; 1998 dis_deauth_mask[2] = 0xc0; 1999 } else { 2000 dis_deauth_mask[0] = 0xef; 2001 dis_deauth_mask[1] = 0x3f; 2002 dis_deauth_mask[2] = 0x00; 2003 dis_deauth_mask[3] = 0xfc; 2004 } 2005 2006 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2007 2008 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2009 pattern_count, byte_cnt); 2010 2011 pattern_count++; 2012 /* 2013 * for de-authenticate pattern, only the first byte of the frame 2014 * control field gets changed from 0xA0 to 0xC0 2015 */ 2016 dis_deauth_pattern[0] = 0xC0; 2017 2018 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2019 pattern_count, byte_cnt); 2020 2021 } 2022 2023 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2024 struct cfg80211_wowlan *wowlan) 2025 { 2026 struct ath_hw *ah = sc->sc_ah; 2027 struct ath9k_wow_pattern *wow_pattern = NULL; 2028 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; 2029 int mask_len; 2030 s8 i = 0; 2031 2032 if (!wowlan->n_patterns) 2033 return; 2034 2035 /* 2036 * Add the new user configured patterns 2037 */ 2038 for (i = 0; i < wowlan->n_patterns; i++) { 2039 2040 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2041 2042 if (!wow_pattern) 2043 return; 2044 2045 /* 2046 * TODO: convert the generic user space pattern to 2047 * appropriate chip specific/802.11 pattern. 2048 */ 2049 2050 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2051 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2052 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2053 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2054 patterns[i].pattern_len); 2055 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2056 wow_pattern->pattern_len = patterns[i].pattern_len; 2057 2058 /* 2059 * just need to take care of deauth and disssoc pattern, 2060 * make sure we don't overwrite them. 2061 */ 2062 2063 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2064 wow_pattern->mask_bytes, 2065 i + 2, 2066 wow_pattern->pattern_len); 2067 kfree(wow_pattern); 2068 2069 } 2070 2071 } 2072 2073 static int ath9k_suspend(struct ieee80211_hw *hw, 2074 struct cfg80211_wowlan *wowlan) 2075 { 2076 struct ath_softc *sc = hw->priv; 2077 struct ath_hw *ah = sc->sc_ah; 2078 struct ath_common *common = ath9k_hw_common(ah); 2079 u32 wow_triggers_enabled = 0; 2080 int ret = 0; 2081 2082 mutex_lock(&sc->mutex); 2083 2084 ath_cancel_work(sc); 2085 ath_stop_ani(sc); 2086 del_timer_sync(&sc->rx_poll_timer); 2087 2088 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2089 ath_dbg(common, ANY, "Device not present\n"); 2090 ret = -EINVAL; 2091 goto fail_wow; 2092 } 2093 2094 if (WARN_ON(!wowlan)) { 2095 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2096 ret = -EINVAL; 2097 goto fail_wow; 2098 } 2099 2100 if (!device_can_wakeup(sc->dev)) { 2101 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2102 ret = 1; 2103 goto fail_wow; 2104 } 2105 2106 /* 2107 * none of the sta vifs are associated 2108 * and we are not currently handling multivif 2109 * cases, for instance we have to seperately 2110 * configure 'keep alive frame' for each 2111 * STA. 2112 */ 2113 2114 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2115 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2116 ret = 1; 2117 goto fail_wow; 2118 } 2119 2120 if (sc->nvifs > 1) { 2121 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2122 ret = 1; 2123 goto fail_wow; 2124 } 2125 2126 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2127 2128 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2129 wow_triggers_enabled); 2130 2131 ath9k_ps_wakeup(sc); 2132 2133 ath9k_stop_btcoex(sc); 2134 2135 /* 2136 * Enable wake up on recieving disassoc/deauth 2137 * frame by default. 2138 */ 2139 ath9k_wow_add_disassoc_deauth_pattern(sc); 2140 2141 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2142 ath9k_wow_add_pattern(sc, wowlan); 2143 2144 spin_lock_bh(&sc->sc_pcu_lock); 2145 /* 2146 * To avoid false wake, we enable beacon miss interrupt only 2147 * when we go to sleep. We save the current interrupt mask 2148 * so we can restore it after the system wakes up 2149 */ 2150 sc->wow_intr_before_sleep = ah->imask; 2151 ah->imask &= ~ATH9K_INT_GLOBAL; 2152 ath9k_hw_disable_interrupts(ah); 2153 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2154 ath9k_hw_set_interrupts(ah); 2155 ath9k_hw_enable_interrupts(ah); 2156 2157 spin_unlock_bh(&sc->sc_pcu_lock); 2158 2159 /* 2160 * we can now sync irq and kill any running tasklets, since we already 2161 * disabled interrupts and not holding a spin lock 2162 */ 2163 synchronize_irq(sc->irq); 2164 tasklet_kill(&sc->intr_tq); 2165 2166 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2167 2168 ath9k_ps_restore(sc); 2169 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2170 atomic_inc(&sc->wow_sleep_proc_intr); 2171 2172 fail_wow: 2173 mutex_unlock(&sc->mutex); 2174 return ret; 2175 } 2176 2177 static int ath9k_resume(struct ieee80211_hw *hw) 2178 { 2179 struct ath_softc *sc = hw->priv; 2180 struct ath_hw *ah = sc->sc_ah; 2181 struct ath_common *common = ath9k_hw_common(ah); 2182 u32 wow_status; 2183 2184 mutex_lock(&sc->mutex); 2185 2186 ath9k_ps_wakeup(sc); 2187 2188 spin_lock_bh(&sc->sc_pcu_lock); 2189 2190 ath9k_hw_disable_interrupts(ah); 2191 ah->imask = sc->wow_intr_before_sleep; 2192 ath9k_hw_set_interrupts(ah); 2193 ath9k_hw_enable_interrupts(ah); 2194 2195 spin_unlock_bh(&sc->sc_pcu_lock); 2196 2197 wow_status = ath9k_hw_wow_wakeup(ah); 2198 2199 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2200 /* 2201 * some devices may not pick beacon miss 2202 * as the reason they woke up so we add 2203 * that here for that shortcoming. 2204 */ 2205 wow_status |= AH_WOW_BEACON_MISS; 2206 atomic_dec(&sc->wow_got_bmiss_intr); 2207 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2208 } 2209 2210 atomic_dec(&sc->wow_sleep_proc_intr); 2211 2212 if (wow_status) { 2213 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2214 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2215 } 2216 2217 ath_restart_work(sc); 2218 ath9k_start_btcoex(sc); 2219 2220 ath9k_ps_restore(sc); 2221 mutex_unlock(&sc->mutex); 2222 2223 return 0; 2224 } 2225 2226 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2227 { 2228 struct ath_softc *sc = hw->priv; 2229 2230 mutex_lock(&sc->mutex); 2231 device_init_wakeup(sc->dev, 1); 2232 device_set_wakeup_enable(sc->dev, enabled); 2233 mutex_unlock(&sc->mutex); 2234 } 2235 2236 #endif 2237 2238 struct ieee80211_ops ath9k_ops = { 2239 .tx = ath9k_tx, 2240 .start = ath9k_start, 2241 .stop = ath9k_stop, 2242 .add_interface = ath9k_add_interface, 2243 .change_interface = ath9k_change_interface, 2244 .remove_interface = ath9k_remove_interface, 2245 .config = ath9k_config, 2246 .configure_filter = ath9k_configure_filter, 2247 .sta_add = ath9k_sta_add, 2248 .sta_remove = ath9k_sta_remove, 2249 .sta_notify = ath9k_sta_notify, 2250 .conf_tx = ath9k_conf_tx, 2251 .bss_info_changed = ath9k_bss_info_changed, 2252 .set_key = ath9k_set_key, 2253 .get_tsf = ath9k_get_tsf, 2254 .set_tsf = ath9k_set_tsf, 2255 .reset_tsf = ath9k_reset_tsf, 2256 .ampdu_action = ath9k_ampdu_action, 2257 .get_survey = ath9k_get_survey, 2258 .rfkill_poll = ath9k_rfkill_poll_state, 2259 .set_coverage_class = ath9k_set_coverage_class, 2260 .flush = ath9k_flush, 2261 .tx_frames_pending = ath9k_tx_frames_pending, 2262 .tx_last_beacon = ath9k_tx_last_beacon, 2263 .get_stats = ath9k_get_stats, 2264 .set_antenna = ath9k_set_antenna, 2265 .get_antenna = ath9k_get_antenna, 2266 2267 #ifdef CONFIG_PM_SLEEP 2268 .suspend = ath9k_suspend, 2269 .resume = ath9k_resume, 2270 .set_wakeup = ath9k_set_wakeup, 2271 #endif 2272 2273 #ifdef CONFIG_ATH9K_DEBUGFS 2274 .get_et_sset_count = ath9k_get_et_sset_count, 2275 .get_et_stats = ath9k_get_et_stats, 2276 .get_et_strings = ath9k_get_et_strings, 2277 #endif 2278 2279 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2280 .sta_add_debugfs = ath9k_sta_add_debugfs, 2281 .sta_remove_debugfs = ath9k_sta_remove_debugfs, 2282 #endif 2283 }; 2284