1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK | 135 PS_WAIT_FOR_ANI))) { 136 mode = ATH9K_PM_NETWORK_SLEEP; 137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 138 ath9k_btcoex_stop_gen_timer(sc); 139 } else { 140 goto unlock; 141 } 142 143 spin_lock(&common->cc_lock); 144 ath_hw_cycle_counters_update(common); 145 spin_unlock(&common->cc_lock); 146 147 ath9k_hw_setpower(sc->sc_ah, mode); 148 149 unlock: 150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 151 } 152 153 static void __ath_cancel_work(struct ath_softc *sc) 154 { 155 cancel_work_sync(&sc->paprd_work); 156 cancel_work_sync(&sc->hw_check_work); 157 cancel_delayed_work_sync(&sc->tx_complete_work); 158 cancel_delayed_work_sync(&sc->hw_pll_work); 159 160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 161 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 162 cancel_work_sync(&sc->mci_work); 163 #endif 164 } 165 166 static void ath_cancel_work(struct ath_softc *sc) 167 { 168 __ath_cancel_work(sc); 169 cancel_work_sync(&sc->hw_reset_work); 170 } 171 172 static void ath_restart_work(struct ath_softc *sc) 173 { 174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 175 176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 177 AR_SREV_9550(sc->sc_ah)) 178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 180 181 ath_start_rx_poll(sc, 3); 182 ath_start_ani(sc); 183 } 184 185 static bool ath_prepare_reset(struct ath_softc *sc) 186 { 187 struct ath_hw *ah = sc->sc_ah; 188 bool ret = true; 189 190 ieee80211_stop_queues(sc->hw); 191 192 sc->hw_busy_count = 0; 193 ath_stop_ani(sc); 194 del_timer_sync(&sc->rx_poll_timer); 195 196 ath9k_debug_samp_bb_mac(sc); 197 ath9k_hw_disable_interrupts(ah); 198 199 if (!ath_drain_all_txq(sc)) 200 ret = false; 201 202 if (!ath_stoprecv(sc)) 203 ret = false; 204 205 return ret; 206 } 207 208 static bool ath_complete_reset(struct ath_softc *sc, bool start) 209 { 210 struct ath_hw *ah = sc->sc_ah; 211 struct ath_common *common = ath9k_hw_common(ah); 212 unsigned long flags; 213 214 if (ath_startrecv(sc) != 0) { 215 ath_err(common, "Unable to restart recv logic\n"); 216 return false; 217 } 218 219 ath9k_cmn_update_txpow(ah, sc->curtxpow, 220 sc->config.txpowlimit, &sc->curtxpow); 221 222 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 223 ath9k_hw_set_interrupts(ah); 224 ath9k_hw_enable_interrupts(ah); 225 226 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 227 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 228 goto work; 229 230 ath9k_set_beacon(sc); 231 232 if (ah->opmode == NL80211_IFTYPE_STATION && 233 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 234 spin_lock_irqsave(&sc->sc_pm_lock, flags); 235 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 236 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 237 } 238 work: 239 ath_restart_work(sc); 240 } 241 242 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) 243 ath_ant_comb_update(sc); 244 245 ieee80211_wake_queues(sc->hw); 246 247 return true; 248 } 249 250 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 251 { 252 struct ath_hw *ah = sc->sc_ah; 253 struct ath_common *common = ath9k_hw_common(ah); 254 struct ath9k_hw_cal_data *caldata = NULL; 255 bool fastcc = true; 256 int r; 257 258 __ath_cancel_work(sc); 259 260 tasklet_disable(&sc->intr_tq); 261 spin_lock_bh(&sc->sc_pcu_lock); 262 263 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 264 fastcc = false; 265 caldata = &sc->caldata; 266 } 267 268 if (!hchan) { 269 fastcc = false; 270 hchan = ah->curchan; 271 } 272 273 if (!ath_prepare_reset(sc)) 274 fastcc = false; 275 276 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 277 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 278 279 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 280 if (r) { 281 ath_err(common, 282 "Unable to reset channel, reset status %d\n", r); 283 goto out; 284 } 285 286 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 287 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 288 ath9k_mci_set_txpower(sc, true, false); 289 290 if (!ath_complete_reset(sc, true)) 291 r = -EIO; 292 293 out: 294 spin_unlock_bh(&sc->sc_pcu_lock); 295 tasklet_enable(&sc->intr_tq); 296 297 return r; 298 } 299 300 301 /* 302 * Set/change channels. If the channel is really being changed, it's done 303 * by reseting the chip. To accomplish this we must first cleanup any pending 304 * DMA, then restart stuff. 305 */ 306 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 307 struct ath9k_channel *hchan) 308 { 309 int r; 310 311 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 312 return -EIO; 313 314 r = ath_reset_internal(sc, hchan); 315 316 return r; 317 } 318 319 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 320 struct ieee80211_vif *vif) 321 { 322 struct ath_node *an; 323 an = (struct ath_node *)sta->drv_priv; 324 325 an->sc = sc; 326 an->sta = sta; 327 an->vif = vif; 328 329 ath_tx_node_init(sc, an); 330 331 if (sta->ht_cap.ht_supported) { 332 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 333 sta->ht_cap.ampdu_factor); 334 an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 335 } 336 } 337 338 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 339 { 340 struct ath_node *an = (struct ath_node *)sta->drv_priv; 341 ath_tx_node_cleanup(sc, an); 342 } 343 344 void ath9k_tasklet(unsigned long data) 345 { 346 struct ath_softc *sc = (struct ath_softc *)data; 347 struct ath_hw *ah = sc->sc_ah; 348 struct ath_common *common = ath9k_hw_common(ah); 349 enum ath_reset_type type; 350 unsigned long flags; 351 u32 status = sc->intrstatus; 352 u32 rxmask; 353 354 ath9k_ps_wakeup(sc); 355 spin_lock(&sc->sc_pcu_lock); 356 357 if ((status & ATH9K_INT_FATAL) || 358 (status & ATH9K_INT_BB_WATCHDOG)) { 359 360 if (status & ATH9K_INT_FATAL) 361 type = RESET_TYPE_FATAL_INT; 362 else 363 type = RESET_TYPE_BB_WATCHDOG; 364 365 ath9k_queue_reset(sc, type); 366 goto out; 367 } 368 369 spin_lock_irqsave(&sc->sc_pm_lock, flags); 370 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 371 /* 372 * TSF sync does not look correct; remain awake to sync with 373 * the next Beacon. 374 */ 375 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 376 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 377 } 378 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 379 380 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 381 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 382 ATH9K_INT_RXORN); 383 else 384 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 385 386 if (status & rxmask) { 387 /* Check for high priority Rx first */ 388 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 389 (status & ATH9K_INT_RXHP)) 390 ath_rx_tasklet(sc, 0, true); 391 392 ath_rx_tasklet(sc, 0, false); 393 } 394 395 if (status & ATH9K_INT_TX) { 396 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 397 ath_tx_edma_tasklet(sc); 398 else 399 ath_tx_tasklet(sc); 400 } 401 402 ath9k_btcoex_handle_interrupt(sc, status); 403 404 out: 405 /* re-enable hardware interrupt */ 406 ath9k_hw_enable_interrupts(ah); 407 408 spin_unlock(&sc->sc_pcu_lock); 409 ath9k_ps_restore(sc); 410 } 411 412 irqreturn_t ath_isr(int irq, void *dev) 413 { 414 #define SCHED_INTR ( \ 415 ATH9K_INT_FATAL | \ 416 ATH9K_INT_BB_WATCHDOG | \ 417 ATH9K_INT_RXORN | \ 418 ATH9K_INT_RXEOL | \ 419 ATH9K_INT_RX | \ 420 ATH9K_INT_RXLP | \ 421 ATH9K_INT_RXHP | \ 422 ATH9K_INT_TX | \ 423 ATH9K_INT_BMISS | \ 424 ATH9K_INT_CST | \ 425 ATH9K_INT_TSFOOR | \ 426 ATH9K_INT_GENTIMER | \ 427 ATH9K_INT_MCI) 428 429 struct ath_softc *sc = dev; 430 struct ath_hw *ah = sc->sc_ah; 431 struct ath_common *common = ath9k_hw_common(ah); 432 enum ath9k_int status; 433 bool sched = false; 434 435 /* 436 * The hardware is not ready/present, don't 437 * touch anything. Note this can happen early 438 * on if the IRQ is shared. 439 */ 440 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 441 return IRQ_NONE; 442 443 /* shared irq, not for us */ 444 445 if (!ath9k_hw_intrpend(ah)) 446 return IRQ_NONE; 447 448 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 449 ath9k_hw_kill_interrupts(ah); 450 return IRQ_HANDLED; 451 } 452 453 /* 454 * Figure out the reason(s) for the interrupt. Note 455 * that the hal returns a pseudo-ISR that may include 456 * bits we haven't explicitly enabled so we mask the 457 * value to insure we only process bits we requested. 458 */ 459 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 460 status &= ah->imask; /* discard unasked-for bits */ 461 462 /* 463 * If there are no status bits set, then this interrupt was not 464 * for me (should have been caught above). 465 */ 466 if (!status) 467 return IRQ_NONE; 468 469 /* Cache the status */ 470 sc->intrstatus = status; 471 472 if (status & SCHED_INTR) 473 sched = true; 474 475 /* 476 * If a FATAL or RXORN interrupt is received, we have to reset the 477 * chip immediately. 478 */ 479 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 480 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 481 goto chip_reset; 482 483 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 484 (status & ATH9K_INT_BB_WATCHDOG)) { 485 486 spin_lock(&common->cc_lock); 487 ath_hw_cycle_counters_update(common); 488 ar9003_hw_bb_watchdog_dbg_info(ah); 489 spin_unlock(&common->cc_lock); 490 491 goto chip_reset; 492 } 493 #ifdef CONFIG_PM_SLEEP 494 if (status & ATH9K_INT_BMISS) { 495 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 496 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 497 atomic_inc(&sc->wow_got_bmiss_intr); 498 atomic_dec(&sc->wow_sleep_proc_intr); 499 } 500 } 501 #endif 502 if (status & ATH9K_INT_SWBA) 503 tasklet_schedule(&sc->bcon_tasklet); 504 505 if (status & ATH9K_INT_TXURN) 506 ath9k_hw_updatetxtriglevel(ah, true); 507 508 if (status & ATH9K_INT_RXEOL) { 509 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 510 ath9k_hw_set_interrupts(ah); 511 } 512 513 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 514 if (status & ATH9K_INT_TIM_TIMER) { 515 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 516 goto chip_reset; 517 /* Clear RxAbort bit so that we can 518 * receive frames */ 519 ath9k_setpower(sc, ATH9K_PM_AWAKE); 520 spin_lock(&sc->sc_pm_lock); 521 ath9k_hw_setrxabort(sc->sc_ah, 0); 522 sc->ps_flags |= PS_WAIT_FOR_BEACON; 523 spin_unlock(&sc->sc_pm_lock); 524 } 525 526 chip_reset: 527 528 ath_debug_stat_interrupt(sc, status); 529 530 if (sched) { 531 /* turn off every interrupt */ 532 ath9k_hw_disable_interrupts(ah); 533 tasklet_schedule(&sc->intr_tq); 534 } 535 536 return IRQ_HANDLED; 537 538 #undef SCHED_INTR 539 } 540 541 static int ath_reset(struct ath_softc *sc) 542 { 543 int i, r; 544 545 ath9k_ps_wakeup(sc); 546 547 r = ath_reset_internal(sc, NULL); 548 549 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 550 if (!ATH_TXQ_SETUP(sc, i)) 551 continue; 552 553 spin_lock_bh(&sc->tx.txq[i].axq_lock); 554 ath_txq_schedule(sc, &sc->tx.txq[i]); 555 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 556 } 557 558 ath9k_ps_restore(sc); 559 560 return r; 561 } 562 563 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 564 { 565 #ifdef CONFIG_ATH9K_DEBUGFS 566 RESET_STAT_INC(sc, type); 567 #endif 568 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 569 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 570 } 571 572 void ath_reset_work(struct work_struct *work) 573 { 574 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 575 576 ath_reset(sc); 577 } 578 579 /**********************/ 580 /* mac80211 callbacks */ 581 /**********************/ 582 583 static int ath9k_start(struct ieee80211_hw *hw) 584 { 585 struct ath_softc *sc = hw->priv; 586 struct ath_hw *ah = sc->sc_ah; 587 struct ath_common *common = ath9k_hw_common(ah); 588 struct ieee80211_channel *curchan = hw->conf.channel; 589 struct ath9k_channel *init_channel; 590 int r; 591 592 ath_dbg(common, CONFIG, 593 "Starting driver with initial channel: %d MHz\n", 594 curchan->center_freq); 595 596 ath9k_ps_wakeup(sc); 597 mutex_lock(&sc->mutex); 598 599 init_channel = ath9k_cmn_get_curchannel(hw, ah); 600 601 /* Reset SERDES registers */ 602 ath9k_hw_configpcipowersave(ah, false); 603 604 /* 605 * The basic interface to setting the hardware in a good 606 * state is ``reset''. On return the hardware is known to 607 * be powered up and with interrupts disabled. This must 608 * be followed by initialization of the appropriate bits 609 * and then setup of the interrupt mask. 610 */ 611 spin_lock_bh(&sc->sc_pcu_lock); 612 613 atomic_set(&ah->intr_ref_cnt, -1); 614 615 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 616 if (r) { 617 ath_err(common, 618 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 619 r, curchan->center_freq); 620 ah->reset_power_on = false; 621 } 622 623 /* Setup our intr mask. */ 624 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 625 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 626 ATH9K_INT_GLOBAL; 627 628 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 629 ah->imask |= ATH9K_INT_RXHP | 630 ATH9K_INT_RXLP | 631 ATH9K_INT_BB_WATCHDOG; 632 else 633 ah->imask |= ATH9K_INT_RX; 634 635 ah->imask |= ATH9K_INT_GTT; 636 637 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 638 ah->imask |= ATH9K_INT_CST; 639 640 ath_mci_enable(sc); 641 642 clear_bit(SC_OP_INVALID, &sc->sc_flags); 643 sc->sc_ah->is_monitoring = false; 644 645 if (!ath_complete_reset(sc, false)) 646 ah->reset_power_on = false; 647 648 if (ah->led_pin >= 0) { 649 ath9k_hw_cfg_output(ah, ah->led_pin, 650 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 651 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 652 } 653 654 /* 655 * Reset key cache to sane defaults (all entries cleared) instead of 656 * semi-random values after suspend/resume. 657 */ 658 ath9k_cmn_init_crypto(sc->sc_ah); 659 660 spin_unlock_bh(&sc->sc_pcu_lock); 661 662 mutex_unlock(&sc->mutex); 663 664 ath9k_ps_restore(sc); 665 666 return 0; 667 } 668 669 static void ath9k_tx(struct ieee80211_hw *hw, 670 struct ieee80211_tx_control *control, 671 struct sk_buff *skb) 672 { 673 struct ath_softc *sc = hw->priv; 674 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 675 struct ath_tx_control txctl; 676 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 677 unsigned long flags; 678 679 if (sc->ps_enabled) { 680 /* 681 * mac80211 does not set PM field for normal data frames, so we 682 * need to update that based on the current PS mode. 683 */ 684 if (ieee80211_is_data(hdr->frame_control) && 685 !ieee80211_is_nullfunc(hdr->frame_control) && 686 !ieee80211_has_pm(hdr->frame_control)) { 687 ath_dbg(common, PS, 688 "Add PM=1 for a TX frame while in PS mode\n"); 689 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 690 } 691 } 692 693 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 694 /* 695 * We are using PS-Poll and mac80211 can request TX while in 696 * power save mode. Need to wake up hardware for the TX to be 697 * completed and if needed, also for RX of buffered frames. 698 */ 699 ath9k_ps_wakeup(sc); 700 spin_lock_irqsave(&sc->sc_pm_lock, flags); 701 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 702 ath9k_hw_setrxabort(sc->sc_ah, 0); 703 if (ieee80211_is_pspoll(hdr->frame_control)) { 704 ath_dbg(common, PS, 705 "Sending PS-Poll to pick a buffered frame\n"); 706 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 707 } else { 708 ath_dbg(common, PS, "Wake up to complete TX\n"); 709 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 710 } 711 /* 712 * The actual restore operation will happen only after 713 * the ps_flags bit is cleared. We are just dropping 714 * the ps_usecount here. 715 */ 716 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 717 ath9k_ps_restore(sc); 718 } 719 720 /* 721 * Cannot tx while the hardware is in full sleep, it first needs a full 722 * chip reset to recover from that 723 */ 724 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 725 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 726 goto exit; 727 } 728 729 memset(&txctl, 0, sizeof(struct ath_tx_control)); 730 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 731 txctl.sta = control->sta; 732 733 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 734 735 if (ath_tx_start(hw, skb, &txctl) != 0) { 736 ath_dbg(common, XMIT, "TX failed\n"); 737 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 738 goto exit; 739 } 740 741 return; 742 exit: 743 ieee80211_free_txskb(hw, skb); 744 } 745 746 static void ath9k_stop(struct ieee80211_hw *hw) 747 { 748 struct ath_softc *sc = hw->priv; 749 struct ath_hw *ah = sc->sc_ah; 750 struct ath_common *common = ath9k_hw_common(ah); 751 bool prev_idle; 752 753 mutex_lock(&sc->mutex); 754 755 ath_cancel_work(sc); 756 del_timer_sync(&sc->rx_poll_timer); 757 758 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 759 ath_dbg(common, ANY, "Device not present\n"); 760 mutex_unlock(&sc->mutex); 761 return; 762 } 763 764 /* Ensure HW is awake when we try to shut it down. */ 765 ath9k_ps_wakeup(sc); 766 767 spin_lock_bh(&sc->sc_pcu_lock); 768 769 /* prevent tasklets to enable interrupts once we disable them */ 770 ah->imask &= ~ATH9K_INT_GLOBAL; 771 772 /* make sure h/w will not generate any interrupt 773 * before setting the invalid flag. */ 774 ath9k_hw_disable_interrupts(ah); 775 776 spin_unlock_bh(&sc->sc_pcu_lock); 777 778 /* we can now sync irq and kill any running tasklets, since we already 779 * disabled interrupts and not holding a spin lock */ 780 synchronize_irq(sc->irq); 781 tasklet_kill(&sc->intr_tq); 782 tasklet_kill(&sc->bcon_tasklet); 783 784 prev_idle = sc->ps_idle; 785 sc->ps_idle = true; 786 787 spin_lock_bh(&sc->sc_pcu_lock); 788 789 if (ah->led_pin >= 0) { 790 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 791 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 792 } 793 794 ath_prepare_reset(sc); 795 796 if (sc->rx.frag) { 797 dev_kfree_skb_any(sc->rx.frag); 798 sc->rx.frag = NULL; 799 } 800 801 if (!ah->curchan) 802 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 803 804 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 805 ath9k_hw_phy_disable(ah); 806 807 ath9k_hw_configpcipowersave(ah, true); 808 809 spin_unlock_bh(&sc->sc_pcu_lock); 810 811 ath9k_ps_restore(sc); 812 813 set_bit(SC_OP_INVALID, &sc->sc_flags); 814 sc->ps_idle = prev_idle; 815 816 mutex_unlock(&sc->mutex); 817 818 ath_dbg(common, CONFIG, "Driver halt\n"); 819 } 820 821 bool ath9k_uses_beacons(int type) 822 { 823 switch (type) { 824 case NL80211_IFTYPE_AP: 825 case NL80211_IFTYPE_ADHOC: 826 case NL80211_IFTYPE_MESH_POINT: 827 return true; 828 default: 829 return false; 830 } 831 } 832 833 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 834 { 835 struct ath9k_vif_iter_data *iter_data = data; 836 int i; 837 838 if (iter_data->hw_macaddr) 839 for (i = 0; i < ETH_ALEN; i++) 840 iter_data->mask[i] &= 841 ~(iter_data->hw_macaddr[i] ^ mac[i]); 842 843 switch (vif->type) { 844 case NL80211_IFTYPE_AP: 845 iter_data->naps++; 846 break; 847 case NL80211_IFTYPE_STATION: 848 iter_data->nstations++; 849 break; 850 case NL80211_IFTYPE_ADHOC: 851 iter_data->nadhocs++; 852 break; 853 case NL80211_IFTYPE_MESH_POINT: 854 iter_data->nmeshes++; 855 break; 856 case NL80211_IFTYPE_WDS: 857 iter_data->nwds++; 858 break; 859 default: 860 break; 861 } 862 } 863 864 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 865 { 866 struct ath_softc *sc = data; 867 struct ath_vif *avp = (void *)vif->drv_priv; 868 869 if (vif->type != NL80211_IFTYPE_STATION) 870 return; 871 872 if (avp->primary_sta_vif) 873 ath9k_set_assoc_state(sc, vif); 874 } 875 876 /* Called with sc->mutex held. */ 877 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 878 struct ieee80211_vif *vif, 879 struct ath9k_vif_iter_data *iter_data) 880 { 881 struct ath_softc *sc = hw->priv; 882 struct ath_hw *ah = sc->sc_ah; 883 struct ath_common *common = ath9k_hw_common(ah); 884 885 /* 886 * Use the hardware MAC address as reference, the hardware uses it 887 * together with the BSSID mask when matching addresses. 888 */ 889 memset(iter_data, 0, sizeof(*iter_data)); 890 iter_data->hw_macaddr = common->macaddr; 891 memset(&iter_data->mask, 0xff, ETH_ALEN); 892 893 if (vif) 894 ath9k_vif_iter(iter_data, vif->addr, vif); 895 896 /* Get list of all active MAC addresses */ 897 ieee80211_iterate_active_interfaces_atomic( 898 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 899 ath9k_vif_iter, iter_data); 900 } 901 902 /* Called with sc->mutex held. */ 903 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 904 struct ieee80211_vif *vif) 905 { 906 struct ath_softc *sc = hw->priv; 907 struct ath_hw *ah = sc->sc_ah; 908 struct ath_common *common = ath9k_hw_common(ah); 909 struct ath9k_vif_iter_data iter_data; 910 enum nl80211_iftype old_opmode = ah->opmode; 911 912 ath9k_calculate_iter_data(hw, vif, &iter_data); 913 914 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 915 ath_hw_setbssidmask(common); 916 917 if (iter_data.naps > 0) { 918 ath9k_hw_set_tsfadjust(ah, true); 919 ah->opmode = NL80211_IFTYPE_AP; 920 } else { 921 ath9k_hw_set_tsfadjust(ah, false); 922 923 if (iter_data.nmeshes) 924 ah->opmode = NL80211_IFTYPE_MESH_POINT; 925 else if (iter_data.nwds) 926 ah->opmode = NL80211_IFTYPE_AP; 927 else if (iter_data.nadhocs) 928 ah->opmode = NL80211_IFTYPE_ADHOC; 929 else 930 ah->opmode = NL80211_IFTYPE_STATION; 931 } 932 933 ath9k_hw_setopmode(ah); 934 935 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 936 ah->imask |= ATH9K_INT_TSFOOR; 937 else 938 ah->imask &= ~ATH9K_INT_TSFOOR; 939 940 ath9k_hw_set_interrupts(ah); 941 942 /* 943 * If we are changing the opmode to STATION, 944 * a beacon sync needs to be done. 945 */ 946 if (ah->opmode == NL80211_IFTYPE_STATION && 947 old_opmode == NL80211_IFTYPE_AP && 948 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 949 ieee80211_iterate_active_interfaces_atomic( 950 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 951 ath9k_sta_vif_iter, sc); 952 } 953 } 954 955 static int ath9k_add_interface(struct ieee80211_hw *hw, 956 struct ieee80211_vif *vif) 957 { 958 struct ath_softc *sc = hw->priv; 959 struct ath_hw *ah = sc->sc_ah; 960 struct ath_common *common = ath9k_hw_common(ah); 961 962 mutex_lock(&sc->mutex); 963 964 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 965 sc->nvifs++; 966 967 ath9k_ps_wakeup(sc); 968 ath9k_calculate_summary_state(hw, vif); 969 ath9k_ps_restore(sc); 970 971 if (ath9k_uses_beacons(vif->type)) 972 ath9k_beacon_assign_slot(sc, vif); 973 974 mutex_unlock(&sc->mutex); 975 return 0; 976 } 977 978 static int ath9k_change_interface(struct ieee80211_hw *hw, 979 struct ieee80211_vif *vif, 980 enum nl80211_iftype new_type, 981 bool p2p) 982 { 983 struct ath_softc *sc = hw->priv; 984 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 985 986 ath_dbg(common, CONFIG, "Change Interface\n"); 987 mutex_lock(&sc->mutex); 988 989 if (ath9k_uses_beacons(vif->type)) 990 ath9k_beacon_remove_slot(sc, vif); 991 992 vif->type = new_type; 993 vif->p2p = p2p; 994 995 ath9k_ps_wakeup(sc); 996 ath9k_calculate_summary_state(hw, vif); 997 ath9k_ps_restore(sc); 998 999 if (ath9k_uses_beacons(vif->type)) 1000 ath9k_beacon_assign_slot(sc, vif); 1001 1002 mutex_unlock(&sc->mutex); 1003 return 0; 1004 } 1005 1006 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1007 struct ieee80211_vif *vif) 1008 { 1009 struct ath_softc *sc = hw->priv; 1010 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1011 1012 ath_dbg(common, CONFIG, "Detach Interface\n"); 1013 1014 mutex_lock(&sc->mutex); 1015 1016 sc->nvifs--; 1017 1018 if (ath9k_uses_beacons(vif->type)) 1019 ath9k_beacon_remove_slot(sc, vif); 1020 1021 ath9k_ps_wakeup(sc); 1022 ath9k_calculate_summary_state(hw, NULL); 1023 ath9k_ps_restore(sc); 1024 1025 mutex_unlock(&sc->mutex); 1026 } 1027 1028 static void ath9k_enable_ps(struct ath_softc *sc) 1029 { 1030 struct ath_hw *ah = sc->sc_ah; 1031 struct ath_common *common = ath9k_hw_common(ah); 1032 1033 sc->ps_enabled = true; 1034 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1035 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1036 ah->imask |= ATH9K_INT_TIM_TIMER; 1037 ath9k_hw_set_interrupts(ah); 1038 } 1039 ath9k_hw_setrxabort(ah, 1); 1040 } 1041 ath_dbg(common, PS, "PowerSave enabled\n"); 1042 } 1043 1044 static void ath9k_disable_ps(struct ath_softc *sc) 1045 { 1046 struct ath_hw *ah = sc->sc_ah; 1047 struct ath_common *common = ath9k_hw_common(ah); 1048 1049 sc->ps_enabled = false; 1050 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1051 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1052 ath9k_hw_setrxabort(ah, 0); 1053 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1054 PS_WAIT_FOR_CAB | 1055 PS_WAIT_FOR_PSPOLL_DATA | 1056 PS_WAIT_FOR_TX_ACK); 1057 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1058 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1059 ath9k_hw_set_interrupts(ah); 1060 } 1061 } 1062 ath_dbg(common, PS, "PowerSave disabled\n"); 1063 } 1064 1065 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1066 { 1067 struct ath_softc *sc = hw->priv; 1068 struct ath_hw *ah = sc->sc_ah; 1069 struct ath_common *common = ath9k_hw_common(ah); 1070 u32 rxfilter; 1071 1072 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1073 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1074 return; 1075 } 1076 1077 ath9k_ps_wakeup(sc); 1078 rxfilter = ath9k_hw_getrxfilter(ah); 1079 ath9k_hw_setrxfilter(ah, rxfilter | 1080 ATH9K_RX_FILTER_PHYRADAR | 1081 ATH9K_RX_FILTER_PHYERR); 1082 1083 /* TODO: usually this should not be neccesary, but for some reason 1084 * (or in some mode?) the trigger must be called after the 1085 * configuration, otherwise the register will have its values reset 1086 * (on my ar9220 to value 0x01002310) 1087 */ 1088 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1089 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1090 ath9k_ps_restore(sc); 1091 } 1092 1093 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1094 enum spectral_mode spectral_mode) 1095 { 1096 struct ath_softc *sc = hw->priv; 1097 struct ath_hw *ah = sc->sc_ah; 1098 struct ath_common *common = ath9k_hw_common(ah); 1099 1100 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1101 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1102 return -1; 1103 } 1104 1105 switch (spectral_mode) { 1106 case SPECTRAL_DISABLED: 1107 sc->spec_config.enabled = 0; 1108 break; 1109 case SPECTRAL_BACKGROUND: 1110 /* send endless samples. 1111 * TODO: is this really useful for "background"? 1112 */ 1113 sc->spec_config.endless = 1; 1114 sc->spec_config.enabled = 1; 1115 break; 1116 case SPECTRAL_CHANSCAN: 1117 case SPECTRAL_MANUAL: 1118 sc->spec_config.endless = 0; 1119 sc->spec_config.enabled = 1; 1120 break; 1121 default: 1122 return -1; 1123 } 1124 1125 ath9k_ps_wakeup(sc); 1126 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1127 ath9k_ps_restore(sc); 1128 1129 sc->spectral_mode = spectral_mode; 1130 1131 return 0; 1132 } 1133 1134 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1135 { 1136 struct ath_softc *sc = hw->priv; 1137 struct ath_hw *ah = sc->sc_ah; 1138 struct ath_common *common = ath9k_hw_common(ah); 1139 struct ieee80211_conf *conf = &hw->conf; 1140 bool reset_channel = false; 1141 1142 ath9k_ps_wakeup(sc); 1143 mutex_lock(&sc->mutex); 1144 1145 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1146 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1147 if (sc->ps_idle) { 1148 ath_cancel_work(sc); 1149 ath9k_stop_btcoex(sc); 1150 } else { 1151 ath9k_start_btcoex(sc); 1152 /* 1153 * The chip needs a reset to properly wake up from 1154 * full sleep 1155 */ 1156 reset_channel = ah->chip_fullsleep; 1157 } 1158 } 1159 1160 /* 1161 * We just prepare to enable PS. We have to wait until our AP has 1162 * ACK'd our null data frame to disable RX otherwise we'll ignore 1163 * those ACKs and end up retransmitting the same null data frames. 1164 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1165 */ 1166 if (changed & IEEE80211_CONF_CHANGE_PS) { 1167 unsigned long flags; 1168 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1169 if (conf->flags & IEEE80211_CONF_PS) 1170 ath9k_enable_ps(sc); 1171 else 1172 ath9k_disable_ps(sc); 1173 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1174 } 1175 1176 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1177 if (conf->flags & IEEE80211_CONF_MONITOR) { 1178 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1179 sc->sc_ah->is_monitoring = true; 1180 } else { 1181 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1182 sc->sc_ah->is_monitoring = false; 1183 } 1184 } 1185 1186 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1187 struct ieee80211_channel *curchan = hw->conf.channel; 1188 int pos = curchan->hw_value; 1189 int old_pos = -1; 1190 unsigned long flags; 1191 1192 if (ah->curchan) 1193 old_pos = ah->curchan - &ah->channels[0]; 1194 1195 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1196 curchan->center_freq, conf->channel_type); 1197 1198 /* update survey stats for the old channel before switching */ 1199 spin_lock_irqsave(&common->cc_lock, flags); 1200 ath_update_survey_stats(sc); 1201 spin_unlock_irqrestore(&common->cc_lock, flags); 1202 1203 /* 1204 * Preserve the current channel values, before updating 1205 * the same channel 1206 */ 1207 if (ah->curchan && (old_pos == pos)) 1208 ath9k_hw_getnf(ah, ah->curchan); 1209 1210 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1211 curchan, conf->channel_type); 1212 1213 /* 1214 * If the operating channel changes, change the survey in-use flags 1215 * along with it. 1216 * Reset the survey data for the new channel, unless we're switching 1217 * back to the operating channel from an off-channel operation. 1218 */ 1219 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1220 sc->cur_survey != &sc->survey[pos]) { 1221 1222 if (sc->cur_survey) 1223 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1224 1225 sc->cur_survey = &sc->survey[pos]; 1226 1227 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1228 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1229 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1230 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1231 } 1232 1233 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1234 ath_err(common, "Unable to set channel\n"); 1235 mutex_unlock(&sc->mutex); 1236 ath9k_ps_restore(sc); 1237 return -EINVAL; 1238 } 1239 1240 /* 1241 * The most recent snapshot of channel->noisefloor for the old 1242 * channel is only available after the hardware reset. Copy it to 1243 * the survey stats now. 1244 */ 1245 if (old_pos >= 0) 1246 ath_update_survey_nf(sc, old_pos); 1247 1248 /* perform spectral scan if requested. */ 1249 if (sc->scanning && sc->spectral_mode == SPECTRAL_CHANSCAN) 1250 ath9k_spectral_scan_trigger(hw); 1251 1252 } 1253 1254 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1255 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1256 sc->config.txpowlimit = 2 * conf->power_level; 1257 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1258 sc->config.txpowlimit, &sc->curtxpow); 1259 } 1260 1261 mutex_unlock(&sc->mutex); 1262 ath9k_ps_restore(sc); 1263 1264 return 0; 1265 } 1266 1267 #define SUPPORTED_FILTERS \ 1268 (FIF_PROMISC_IN_BSS | \ 1269 FIF_ALLMULTI | \ 1270 FIF_CONTROL | \ 1271 FIF_PSPOLL | \ 1272 FIF_OTHER_BSS | \ 1273 FIF_BCN_PRBRESP_PROMISC | \ 1274 FIF_PROBE_REQ | \ 1275 FIF_FCSFAIL) 1276 1277 /* FIXME: sc->sc_full_reset ? */ 1278 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1279 unsigned int changed_flags, 1280 unsigned int *total_flags, 1281 u64 multicast) 1282 { 1283 struct ath_softc *sc = hw->priv; 1284 u32 rfilt; 1285 1286 changed_flags &= SUPPORTED_FILTERS; 1287 *total_flags &= SUPPORTED_FILTERS; 1288 1289 sc->rx.rxfilter = *total_flags; 1290 ath9k_ps_wakeup(sc); 1291 rfilt = ath_calcrxfilter(sc); 1292 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1293 ath9k_ps_restore(sc); 1294 1295 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1296 rfilt); 1297 } 1298 1299 static int ath9k_sta_add(struct ieee80211_hw *hw, 1300 struct ieee80211_vif *vif, 1301 struct ieee80211_sta *sta) 1302 { 1303 struct ath_softc *sc = hw->priv; 1304 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1305 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1306 struct ieee80211_key_conf ps_key = { }; 1307 1308 ath_node_attach(sc, sta, vif); 1309 1310 if (vif->type != NL80211_IFTYPE_AP && 1311 vif->type != NL80211_IFTYPE_AP_VLAN) 1312 return 0; 1313 1314 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1315 1316 return 0; 1317 } 1318 1319 static void ath9k_del_ps_key(struct ath_softc *sc, 1320 struct ieee80211_vif *vif, 1321 struct ieee80211_sta *sta) 1322 { 1323 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1324 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1325 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1326 1327 if (!an->ps_key) 1328 return; 1329 1330 ath_key_delete(common, &ps_key); 1331 } 1332 1333 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1334 struct ieee80211_vif *vif, 1335 struct ieee80211_sta *sta) 1336 { 1337 struct ath_softc *sc = hw->priv; 1338 1339 ath9k_del_ps_key(sc, vif, sta); 1340 ath_node_detach(sc, sta); 1341 1342 return 0; 1343 } 1344 1345 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1346 struct ieee80211_vif *vif, 1347 enum sta_notify_cmd cmd, 1348 struct ieee80211_sta *sta) 1349 { 1350 struct ath_softc *sc = hw->priv; 1351 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1352 1353 if (!sta->ht_cap.ht_supported) 1354 return; 1355 1356 switch (cmd) { 1357 case STA_NOTIFY_SLEEP: 1358 an->sleeping = true; 1359 ath_tx_aggr_sleep(sta, sc, an); 1360 break; 1361 case STA_NOTIFY_AWAKE: 1362 an->sleeping = false; 1363 ath_tx_aggr_wakeup(sc, an); 1364 break; 1365 } 1366 } 1367 1368 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1369 struct ieee80211_vif *vif, u16 queue, 1370 const struct ieee80211_tx_queue_params *params) 1371 { 1372 struct ath_softc *sc = hw->priv; 1373 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1374 struct ath_txq *txq; 1375 struct ath9k_tx_queue_info qi; 1376 int ret = 0; 1377 1378 if (queue >= IEEE80211_NUM_ACS) 1379 return 0; 1380 1381 txq = sc->tx.txq_map[queue]; 1382 1383 ath9k_ps_wakeup(sc); 1384 mutex_lock(&sc->mutex); 1385 1386 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1387 1388 qi.tqi_aifs = params->aifs; 1389 qi.tqi_cwmin = params->cw_min; 1390 qi.tqi_cwmax = params->cw_max; 1391 qi.tqi_burstTime = params->txop * 32; 1392 1393 ath_dbg(common, CONFIG, 1394 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1395 queue, txq->axq_qnum, params->aifs, params->cw_min, 1396 params->cw_max, params->txop); 1397 1398 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1399 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1400 if (ret) 1401 ath_err(common, "TXQ Update failed\n"); 1402 1403 mutex_unlock(&sc->mutex); 1404 ath9k_ps_restore(sc); 1405 1406 return ret; 1407 } 1408 1409 static int ath9k_set_key(struct ieee80211_hw *hw, 1410 enum set_key_cmd cmd, 1411 struct ieee80211_vif *vif, 1412 struct ieee80211_sta *sta, 1413 struct ieee80211_key_conf *key) 1414 { 1415 struct ath_softc *sc = hw->priv; 1416 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1417 int ret = 0; 1418 1419 if (ath9k_modparam_nohwcrypt) 1420 return -ENOSPC; 1421 1422 if ((vif->type == NL80211_IFTYPE_ADHOC || 1423 vif->type == NL80211_IFTYPE_MESH_POINT) && 1424 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1425 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1426 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1427 /* 1428 * For now, disable hw crypto for the RSN IBSS group keys. This 1429 * could be optimized in the future to use a modified key cache 1430 * design to support per-STA RX GTK, but until that gets 1431 * implemented, use of software crypto for group addressed 1432 * frames is a acceptable to allow RSN IBSS to be used. 1433 */ 1434 return -EOPNOTSUPP; 1435 } 1436 1437 mutex_lock(&sc->mutex); 1438 ath9k_ps_wakeup(sc); 1439 ath_dbg(common, CONFIG, "Set HW Key\n"); 1440 1441 switch (cmd) { 1442 case SET_KEY: 1443 if (sta) 1444 ath9k_del_ps_key(sc, vif, sta); 1445 1446 ret = ath_key_config(common, vif, sta, key); 1447 if (ret >= 0) { 1448 key->hw_key_idx = ret; 1449 /* push IV and Michael MIC generation to stack */ 1450 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1451 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1452 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1453 if (sc->sc_ah->sw_mgmt_crypto && 1454 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1455 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1456 ret = 0; 1457 } 1458 break; 1459 case DISABLE_KEY: 1460 ath_key_delete(common, key); 1461 break; 1462 default: 1463 ret = -EINVAL; 1464 } 1465 1466 ath9k_ps_restore(sc); 1467 mutex_unlock(&sc->mutex); 1468 1469 return ret; 1470 } 1471 1472 static void ath9k_set_assoc_state(struct ath_softc *sc, 1473 struct ieee80211_vif *vif) 1474 { 1475 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1476 struct ath_vif *avp = (void *)vif->drv_priv; 1477 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1478 unsigned long flags; 1479 1480 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1481 avp->primary_sta_vif = true; 1482 1483 /* 1484 * Set the AID, BSSID and do beacon-sync only when 1485 * the HW opmode is STATION. 1486 * 1487 * But the primary bit is set above in any case. 1488 */ 1489 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1490 return; 1491 1492 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1493 common->curaid = bss_conf->aid; 1494 ath9k_hw_write_associd(sc->sc_ah); 1495 1496 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1497 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1498 1499 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1500 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1501 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1502 1503 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1504 ath9k_mci_update_wlan_channels(sc, false); 1505 1506 ath_dbg(common, CONFIG, 1507 "Primary Station interface: %pM, BSSID: %pM\n", 1508 vif->addr, common->curbssid); 1509 } 1510 1511 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1512 { 1513 struct ath_softc *sc = data; 1514 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1515 1516 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1517 return; 1518 1519 if (bss_conf->assoc) 1520 ath9k_set_assoc_state(sc, vif); 1521 } 1522 1523 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1524 struct ieee80211_vif *vif, 1525 struct ieee80211_bss_conf *bss_conf, 1526 u32 changed) 1527 { 1528 #define CHECK_ANI \ 1529 (BSS_CHANGED_ASSOC | \ 1530 BSS_CHANGED_IBSS | \ 1531 BSS_CHANGED_BEACON_ENABLED) 1532 1533 struct ath_softc *sc = hw->priv; 1534 struct ath_hw *ah = sc->sc_ah; 1535 struct ath_common *common = ath9k_hw_common(ah); 1536 struct ath_vif *avp = (void *)vif->drv_priv; 1537 int slottime; 1538 1539 ath9k_ps_wakeup(sc); 1540 mutex_lock(&sc->mutex); 1541 1542 if (changed & BSS_CHANGED_ASSOC) { 1543 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1544 bss_conf->bssid, bss_conf->assoc); 1545 1546 if (avp->primary_sta_vif && !bss_conf->assoc) { 1547 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1548 avp->primary_sta_vif = false; 1549 1550 if (ah->opmode == NL80211_IFTYPE_STATION) 1551 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1552 } 1553 1554 ieee80211_iterate_active_interfaces_atomic( 1555 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1556 ath9k_bss_assoc_iter, sc); 1557 1558 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1559 ah->opmode == NL80211_IFTYPE_STATION) { 1560 memset(common->curbssid, 0, ETH_ALEN); 1561 common->curaid = 0; 1562 ath9k_hw_write_associd(sc->sc_ah); 1563 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1564 ath9k_mci_update_wlan_channels(sc, true); 1565 } 1566 } 1567 1568 if (changed & BSS_CHANGED_IBSS) { 1569 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1570 common->curaid = bss_conf->aid; 1571 ath9k_hw_write_associd(sc->sc_ah); 1572 } 1573 1574 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1575 (changed & BSS_CHANGED_BEACON_INT)) { 1576 if (ah->opmode == NL80211_IFTYPE_AP && 1577 bss_conf->enable_beacon) 1578 ath9k_set_tsfadjust(sc, vif); 1579 if (ath9k_allow_beacon_config(sc, vif)) 1580 ath9k_beacon_config(sc, vif, changed); 1581 } 1582 1583 if (changed & BSS_CHANGED_ERP_SLOT) { 1584 if (bss_conf->use_short_slot) 1585 slottime = 9; 1586 else 1587 slottime = 20; 1588 if (vif->type == NL80211_IFTYPE_AP) { 1589 /* 1590 * Defer update, so that connected stations can adjust 1591 * their settings at the same time. 1592 * See beacon.c for more details 1593 */ 1594 sc->beacon.slottime = slottime; 1595 sc->beacon.updateslot = UPDATE; 1596 } else { 1597 ah->slottime = slottime; 1598 ath9k_hw_init_global_settings(ah); 1599 } 1600 } 1601 1602 if (changed & CHECK_ANI) 1603 ath_check_ani(sc); 1604 1605 mutex_unlock(&sc->mutex); 1606 ath9k_ps_restore(sc); 1607 1608 #undef CHECK_ANI 1609 } 1610 1611 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1612 { 1613 struct ath_softc *sc = hw->priv; 1614 u64 tsf; 1615 1616 mutex_lock(&sc->mutex); 1617 ath9k_ps_wakeup(sc); 1618 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1619 ath9k_ps_restore(sc); 1620 mutex_unlock(&sc->mutex); 1621 1622 return tsf; 1623 } 1624 1625 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1626 struct ieee80211_vif *vif, 1627 u64 tsf) 1628 { 1629 struct ath_softc *sc = hw->priv; 1630 1631 mutex_lock(&sc->mutex); 1632 ath9k_ps_wakeup(sc); 1633 ath9k_hw_settsf64(sc->sc_ah, tsf); 1634 ath9k_ps_restore(sc); 1635 mutex_unlock(&sc->mutex); 1636 } 1637 1638 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1639 { 1640 struct ath_softc *sc = hw->priv; 1641 1642 mutex_lock(&sc->mutex); 1643 1644 ath9k_ps_wakeup(sc); 1645 ath9k_hw_reset_tsf(sc->sc_ah); 1646 ath9k_ps_restore(sc); 1647 1648 mutex_unlock(&sc->mutex); 1649 } 1650 1651 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1652 struct ieee80211_vif *vif, 1653 enum ieee80211_ampdu_mlme_action action, 1654 struct ieee80211_sta *sta, 1655 u16 tid, u16 *ssn, u8 buf_size) 1656 { 1657 struct ath_softc *sc = hw->priv; 1658 int ret = 0; 1659 1660 local_bh_disable(); 1661 1662 switch (action) { 1663 case IEEE80211_AMPDU_RX_START: 1664 break; 1665 case IEEE80211_AMPDU_RX_STOP: 1666 break; 1667 case IEEE80211_AMPDU_TX_START: 1668 ath9k_ps_wakeup(sc); 1669 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1670 if (!ret) 1671 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1672 ath9k_ps_restore(sc); 1673 break; 1674 case IEEE80211_AMPDU_TX_STOP_CONT: 1675 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1676 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1677 ath9k_ps_wakeup(sc); 1678 ath_tx_aggr_stop(sc, sta, tid); 1679 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1680 ath9k_ps_restore(sc); 1681 break; 1682 case IEEE80211_AMPDU_TX_OPERATIONAL: 1683 ath9k_ps_wakeup(sc); 1684 ath_tx_aggr_resume(sc, sta, tid); 1685 ath9k_ps_restore(sc); 1686 break; 1687 default: 1688 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1689 } 1690 1691 local_bh_enable(); 1692 1693 return ret; 1694 } 1695 1696 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1697 struct survey_info *survey) 1698 { 1699 struct ath_softc *sc = hw->priv; 1700 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1701 struct ieee80211_supported_band *sband; 1702 struct ieee80211_channel *chan; 1703 unsigned long flags; 1704 int pos; 1705 1706 spin_lock_irqsave(&common->cc_lock, flags); 1707 if (idx == 0) 1708 ath_update_survey_stats(sc); 1709 1710 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1711 if (sband && idx >= sband->n_channels) { 1712 idx -= sband->n_channels; 1713 sband = NULL; 1714 } 1715 1716 if (!sband) 1717 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1718 1719 if (!sband || idx >= sband->n_channels) { 1720 spin_unlock_irqrestore(&common->cc_lock, flags); 1721 return -ENOENT; 1722 } 1723 1724 chan = &sband->channels[idx]; 1725 pos = chan->hw_value; 1726 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1727 survey->channel = chan; 1728 spin_unlock_irqrestore(&common->cc_lock, flags); 1729 1730 return 0; 1731 } 1732 1733 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1734 { 1735 struct ath_softc *sc = hw->priv; 1736 struct ath_hw *ah = sc->sc_ah; 1737 1738 mutex_lock(&sc->mutex); 1739 ah->coverage_class = coverage_class; 1740 1741 ath9k_ps_wakeup(sc); 1742 ath9k_hw_init_global_settings(ah); 1743 ath9k_ps_restore(sc); 1744 1745 mutex_unlock(&sc->mutex); 1746 } 1747 1748 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 1749 { 1750 struct ath_softc *sc = hw->priv; 1751 struct ath_hw *ah = sc->sc_ah; 1752 struct ath_common *common = ath9k_hw_common(ah); 1753 int timeout = 200; /* ms */ 1754 int i, j; 1755 bool drain_txq; 1756 1757 mutex_lock(&sc->mutex); 1758 cancel_delayed_work_sync(&sc->tx_complete_work); 1759 1760 if (ah->ah_flags & AH_UNPLUGGED) { 1761 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1762 mutex_unlock(&sc->mutex); 1763 return; 1764 } 1765 1766 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1767 ath_dbg(common, ANY, "Device not present\n"); 1768 mutex_unlock(&sc->mutex); 1769 return; 1770 } 1771 1772 for (j = 0; j < timeout; j++) { 1773 bool npend = false; 1774 1775 if (j) 1776 usleep_range(1000, 2000); 1777 1778 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1779 if (!ATH_TXQ_SETUP(sc, i)) 1780 continue; 1781 1782 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1783 1784 if (npend) 1785 break; 1786 } 1787 1788 if (!npend) 1789 break; 1790 } 1791 1792 if (drop) { 1793 ath9k_ps_wakeup(sc); 1794 spin_lock_bh(&sc->sc_pcu_lock); 1795 drain_txq = ath_drain_all_txq(sc); 1796 spin_unlock_bh(&sc->sc_pcu_lock); 1797 1798 if (!drain_txq) 1799 ath_reset(sc); 1800 1801 ath9k_ps_restore(sc); 1802 ieee80211_wake_queues(hw); 1803 } 1804 1805 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1806 mutex_unlock(&sc->mutex); 1807 } 1808 1809 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1810 { 1811 struct ath_softc *sc = hw->priv; 1812 int i; 1813 1814 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1815 if (!ATH_TXQ_SETUP(sc, i)) 1816 continue; 1817 1818 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1819 return true; 1820 } 1821 return false; 1822 } 1823 1824 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1825 { 1826 struct ath_softc *sc = hw->priv; 1827 struct ath_hw *ah = sc->sc_ah; 1828 struct ieee80211_vif *vif; 1829 struct ath_vif *avp; 1830 struct ath_buf *bf; 1831 struct ath_tx_status ts; 1832 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1833 int status; 1834 1835 vif = sc->beacon.bslot[0]; 1836 if (!vif) 1837 return 0; 1838 1839 if (!vif->bss_conf.enable_beacon) 1840 return 0; 1841 1842 avp = (void *)vif->drv_priv; 1843 1844 if (!sc->beacon.tx_processed && !edma) { 1845 tasklet_disable(&sc->bcon_tasklet); 1846 1847 bf = avp->av_bcbuf; 1848 if (!bf || !bf->bf_mpdu) 1849 goto skip; 1850 1851 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1852 if (status == -EINPROGRESS) 1853 goto skip; 1854 1855 sc->beacon.tx_processed = true; 1856 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1857 1858 skip: 1859 tasklet_enable(&sc->bcon_tasklet); 1860 } 1861 1862 return sc->beacon.tx_last; 1863 } 1864 1865 static int ath9k_get_stats(struct ieee80211_hw *hw, 1866 struct ieee80211_low_level_stats *stats) 1867 { 1868 struct ath_softc *sc = hw->priv; 1869 struct ath_hw *ah = sc->sc_ah; 1870 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1871 1872 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1873 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1874 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1875 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1876 return 0; 1877 } 1878 1879 static u32 fill_chainmask(u32 cap, u32 new) 1880 { 1881 u32 filled = 0; 1882 int i; 1883 1884 for (i = 0; cap && new; i++, cap >>= 1) { 1885 if (!(cap & BIT(0))) 1886 continue; 1887 1888 if (new & BIT(0)) 1889 filled |= BIT(i); 1890 1891 new >>= 1; 1892 } 1893 1894 return filled; 1895 } 1896 1897 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1898 { 1899 if (AR_SREV_9300_20_OR_LATER(ah)) 1900 return true; 1901 1902 switch (val & 0x7) { 1903 case 0x1: 1904 case 0x3: 1905 case 0x7: 1906 return true; 1907 case 0x2: 1908 return (ah->caps.rx_chainmask == 1); 1909 default: 1910 return false; 1911 } 1912 } 1913 1914 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1915 { 1916 struct ath_softc *sc = hw->priv; 1917 struct ath_hw *ah = sc->sc_ah; 1918 1919 if (ah->caps.rx_chainmask != 1) 1920 rx_ant |= tx_ant; 1921 1922 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1923 return -EINVAL; 1924 1925 sc->ant_rx = rx_ant; 1926 sc->ant_tx = tx_ant; 1927 1928 if (ah->caps.rx_chainmask == 1) 1929 return 0; 1930 1931 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 1932 if (AR_SREV_9100(ah)) 1933 ah->rxchainmask = 0x7; 1934 else 1935 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 1936 1937 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 1938 ath9k_reload_chainmask_settings(sc); 1939 1940 return 0; 1941 } 1942 1943 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 1944 { 1945 struct ath_softc *sc = hw->priv; 1946 1947 *tx_ant = sc->ant_tx; 1948 *rx_ant = sc->ant_rx; 1949 return 0; 1950 } 1951 1952 #ifdef CONFIG_PM_SLEEP 1953 1954 static void ath9k_wow_map_triggers(struct ath_softc *sc, 1955 struct cfg80211_wowlan *wowlan, 1956 u32 *wow_triggers) 1957 { 1958 if (wowlan->disconnect) 1959 *wow_triggers |= AH_WOW_LINK_CHANGE | 1960 AH_WOW_BEACON_MISS; 1961 if (wowlan->magic_pkt) 1962 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 1963 1964 if (wowlan->n_patterns) 1965 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 1966 1967 sc->wow_enabled = *wow_triggers; 1968 1969 } 1970 1971 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 1972 { 1973 struct ath_hw *ah = sc->sc_ah; 1974 struct ath_common *common = ath9k_hw_common(ah); 1975 struct ath9k_hw_capabilities *pcaps = &ah->caps; 1976 int pattern_count = 0; 1977 int i, byte_cnt; 1978 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 1979 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 1980 1981 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 1982 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 1983 1984 /* 1985 * Create Dissassociate / Deauthenticate packet filter 1986 * 1987 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 1988 * +--------------+----------+---------+--------+--------+---- 1989 * + Frame Control+ Duration + DA + SA + BSSID + 1990 * +--------------+----------+---------+--------+--------+---- 1991 * 1992 * The above is the management frame format for disassociate/ 1993 * deauthenticate pattern, from this we need to match the first byte 1994 * of 'Frame Control' and DA, SA, and BSSID fields 1995 * (skipping 2nd byte of FC and Duration feild. 1996 * 1997 * Disassociate pattern 1998 * -------------------- 1999 * Frame control = 00 00 1010 2000 * DA, SA, BSSID = x:x:x:x:x:x 2001 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2002 * | x:x:x:x:x:x -- 22 bytes 2003 * 2004 * Deauthenticate pattern 2005 * ---------------------- 2006 * Frame control = 00 00 1100 2007 * DA, SA, BSSID = x:x:x:x:x:x 2008 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2009 * | x:x:x:x:x:x -- 22 bytes 2010 */ 2011 2012 /* Create Disassociate Pattern first */ 2013 2014 byte_cnt = 0; 2015 2016 /* Fill out the mask with all FF's */ 2017 2018 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 2019 dis_deauth_mask[i] = 0xff; 2020 2021 /* copy the first byte of frame control field */ 2022 dis_deauth_pattern[byte_cnt] = 0xa0; 2023 byte_cnt++; 2024 2025 /* skip 2nd byte of frame control and Duration field */ 2026 byte_cnt += 3; 2027 2028 /* 2029 * need not match the destination mac address, it can be a broadcast 2030 * mac address or an unicast to this station 2031 */ 2032 byte_cnt += 6; 2033 2034 /* copy the source mac address */ 2035 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2036 2037 byte_cnt += 6; 2038 2039 /* copy the bssid, its same as the source mac address */ 2040 2041 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2042 2043 /* Create Disassociate pattern mask */ 2044 2045 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { 2046 2047 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { 2048 /* 2049 * for AR9280, because of hardware limitation, the 2050 * first 4 bytes have to be matched for all patterns. 2051 * the mask for disassociation and de-auth pattern 2052 * matching need to enable the first 4 bytes. 2053 * also the duration field needs to be filled. 2054 */ 2055 dis_deauth_mask[0] = 0xf0; 2056 2057 /* 2058 * fill in duration field 2059 FIXME: what is the exact value ? 2060 */ 2061 dis_deauth_pattern[2] = 0xff; 2062 dis_deauth_pattern[3] = 0xff; 2063 } else { 2064 dis_deauth_mask[0] = 0xfe; 2065 } 2066 2067 dis_deauth_mask[1] = 0x03; 2068 dis_deauth_mask[2] = 0xc0; 2069 } else { 2070 dis_deauth_mask[0] = 0xef; 2071 dis_deauth_mask[1] = 0x3f; 2072 dis_deauth_mask[2] = 0x00; 2073 dis_deauth_mask[3] = 0xfc; 2074 } 2075 2076 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2077 2078 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2079 pattern_count, byte_cnt); 2080 2081 pattern_count++; 2082 /* 2083 * for de-authenticate pattern, only the first byte of the frame 2084 * control field gets changed from 0xA0 to 0xC0 2085 */ 2086 dis_deauth_pattern[0] = 0xC0; 2087 2088 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2089 pattern_count, byte_cnt); 2090 2091 } 2092 2093 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2094 struct cfg80211_wowlan *wowlan) 2095 { 2096 struct ath_hw *ah = sc->sc_ah; 2097 struct ath9k_wow_pattern *wow_pattern = NULL; 2098 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; 2099 int mask_len; 2100 s8 i = 0; 2101 2102 if (!wowlan->n_patterns) 2103 return; 2104 2105 /* 2106 * Add the new user configured patterns 2107 */ 2108 for (i = 0; i < wowlan->n_patterns; i++) { 2109 2110 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2111 2112 if (!wow_pattern) 2113 return; 2114 2115 /* 2116 * TODO: convert the generic user space pattern to 2117 * appropriate chip specific/802.11 pattern. 2118 */ 2119 2120 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2121 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2122 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2123 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2124 patterns[i].pattern_len); 2125 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2126 wow_pattern->pattern_len = patterns[i].pattern_len; 2127 2128 /* 2129 * just need to take care of deauth and disssoc pattern, 2130 * make sure we don't overwrite them. 2131 */ 2132 2133 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2134 wow_pattern->mask_bytes, 2135 i + 2, 2136 wow_pattern->pattern_len); 2137 kfree(wow_pattern); 2138 2139 } 2140 2141 } 2142 2143 static int ath9k_suspend(struct ieee80211_hw *hw, 2144 struct cfg80211_wowlan *wowlan) 2145 { 2146 struct ath_softc *sc = hw->priv; 2147 struct ath_hw *ah = sc->sc_ah; 2148 struct ath_common *common = ath9k_hw_common(ah); 2149 u32 wow_triggers_enabled = 0; 2150 int ret = 0; 2151 2152 mutex_lock(&sc->mutex); 2153 2154 ath_cancel_work(sc); 2155 ath_stop_ani(sc); 2156 del_timer_sync(&sc->rx_poll_timer); 2157 2158 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2159 ath_dbg(common, ANY, "Device not present\n"); 2160 ret = -EINVAL; 2161 goto fail_wow; 2162 } 2163 2164 if (WARN_ON(!wowlan)) { 2165 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2166 ret = -EINVAL; 2167 goto fail_wow; 2168 } 2169 2170 if (!device_can_wakeup(sc->dev)) { 2171 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2172 ret = 1; 2173 goto fail_wow; 2174 } 2175 2176 /* 2177 * none of the sta vifs are associated 2178 * and we are not currently handling multivif 2179 * cases, for instance we have to seperately 2180 * configure 'keep alive frame' for each 2181 * STA. 2182 */ 2183 2184 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2185 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2186 ret = 1; 2187 goto fail_wow; 2188 } 2189 2190 if (sc->nvifs > 1) { 2191 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2192 ret = 1; 2193 goto fail_wow; 2194 } 2195 2196 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2197 2198 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2199 wow_triggers_enabled); 2200 2201 ath9k_ps_wakeup(sc); 2202 2203 ath9k_stop_btcoex(sc); 2204 2205 /* 2206 * Enable wake up on recieving disassoc/deauth 2207 * frame by default. 2208 */ 2209 ath9k_wow_add_disassoc_deauth_pattern(sc); 2210 2211 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2212 ath9k_wow_add_pattern(sc, wowlan); 2213 2214 spin_lock_bh(&sc->sc_pcu_lock); 2215 /* 2216 * To avoid false wake, we enable beacon miss interrupt only 2217 * when we go to sleep. We save the current interrupt mask 2218 * so we can restore it after the system wakes up 2219 */ 2220 sc->wow_intr_before_sleep = ah->imask; 2221 ah->imask &= ~ATH9K_INT_GLOBAL; 2222 ath9k_hw_disable_interrupts(ah); 2223 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2224 ath9k_hw_set_interrupts(ah); 2225 ath9k_hw_enable_interrupts(ah); 2226 2227 spin_unlock_bh(&sc->sc_pcu_lock); 2228 2229 /* 2230 * we can now sync irq and kill any running tasklets, since we already 2231 * disabled interrupts and not holding a spin lock 2232 */ 2233 synchronize_irq(sc->irq); 2234 tasklet_kill(&sc->intr_tq); 2235 2236 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2237 2238 ath9k_ps_restore(sc); 2239 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2240 atomic_inc(&sc->wow_sleep_proc_intr); 2241 2242 fail_wow: 2243 mutex_unlock(&sc->mutex); 2244 return ret; 2245 } 2246 2247 static int ath9k_resume(struct ieee80211_hw *hw) 2248 { 2249 struct ath_softc *sc = hw->priv; 2250 struct ath_hw *ah = sc->sc_ah; 2251 struct ath_common *common = ath9k_hw_common(ah); 2252 u32 wow_status; 2253 2254 mutex_lock(&sc->mutex); 2255 2256 ath9k_ps_wakeup(sc); 2257 2258 spin_lock_bh(&sc->sc_pcu_lock); 2259 2260 ath9k_hw_disable_interrupts(ah); 2261 ah->imask = sc->wow_intr_before_sleep; 2262 ath9k_hw_set_interrupts(ah); 2263 ath9k_hw_enable_interrupts(ah); 2264 2265 spin_unlock_bh(&sc->sc_pcu_lock); 2266 2267 wow_status = ath9k_hw_wow_wakeup(ah); 2268 2269 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2270 /* 2271 * some devices may not pick beacon miss 2272 * as the reason they woke up so we add 2273 * that here for that shortcoming. 2274 */ 2275 wow_status |= AH_WOW_BEACON_MISS; 2276 atomic_dec(&sc->wow_got_bmiss_intr); 2277 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2278 } 2279 2280 atomic_dec(&sc->wow_sleep_proc_intr); 2281 2282 if (wow_status) { 2283 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2284 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2285 } 2286 2287 ath_restart_work(sc); 2288 ath9k_start_btcoex(sc); 2289 2290 ath9k_ps_restore(sc); 2291 mutex_unlock(&sc->mutex); 2292 2293 return 0; 2294 } 2295 2296 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2297 { 2298 struct ath_softc *sc = hw->priv; 2299 2300 mutex_lock(&sc->mutex); 2301 device_init_wakeup(sc->dev, 1); 2302 device_set_wakeup_enable(sc->dev, enabled); 2303 mutex_unlock(&sc->mutex); 2304 } 2305 2306 #endif 2307 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2308 { 2309 struct ath_softc *sc = hw->priv; 2310 2311 sc->scanning = 1; 2312 } 2313 2314 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2315 { 2316 struct ath_softc *sc = hw->priv; 2317 2318 sc->scanning = 0; 2319 } 2320 2321 struct ieee80211_ops ath9k_ops = { 2322 .tx = ath9k_tx, 2323 .start = ath9k_start, 2324 .stop = ath9k_stop, 2325 .add_interface = ath9k_add_interface, 2326 .change_interface = ath9k_change_interface, 2327 .remove_interface = ath9k_remove_interface, 2328 .config = ath9k_config, 2329 .configure_filter = ath9k_configure_filter, 2330 .sta_add = ath9k_sta_add, 2331 .sta_remove = ath9k_sta_remove, 2332 .sta_notify = ath9k_sta_notify, 2333 .conf_tx = ath9k_conf_tx, 2334 .bss_info_changed = ath9k_bss_info_changed, 2335 .set_key = ath9k_set_key, 2336 .get_tsf = ath9k_get_tsf, 2337 .set_tsf = ath9k_set_tsf, 2338 .reset_tsf = ath9k_reset_tsf, 2339 .ampdu_action = ath9k_ampdu_action, 2340 .get_survey = ath9k_get_survey, 2341 .rfkill_poll = ath9k_rfkill_poll_state, 2342 .set_coverage_class = ath9k_set_coverage_class, 2343 .flush = ath9k_flush, 2344 .tx_frames_pending = ath9k_tx_frames_pending, 2345 .tx_last_beacon = ath9k_tx_last_beacon, 2346 .get_stats = ath9k_get_stats, 2347 .set_antenna = ath9k_set_antenna, 2348 .get_antenna = ath9k_get_antenna, 2349 2350 #ifdef CONFIG_PM_SLEEP 2351 .suspend = ath9k_suspend, 2352 .resume = ath9k_resume, 2353 .set_wakeup = ath9k_set_wakeup, 2354 #endif 2355 2356 #ifdef CONFIG_ATH9K_DEBUGFS 2357 .get_et_sset_count = ath9k_get_et_sset_count, 2358 .get_et_stats = ath9k_get_et_stats, 2359 .get_et_strings = ath9k_get_et_strings, 2360 #endif 2361 2362 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2363 .sta_add_debugfs = ath9k_sta_add_debugfs, 2364 .sta_remove_debugfs = ath9k_sta_remove_debugfs, 2365 #endif 2366 .sw_scan_start = ath9k_sw_scan_start, 2367 .sw_scan_complete = ath9k_sw_scan_complete, 2368 }; 2369