1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth) { 64 pending = true; 65 goto out; 66 } 67 68 if (txq->mac80211_qnum >= 0) { 69 struct list_head *list; 70 71 list = &sc->cur_chan->acq[txq->mac80211_qnum]; 72 if (!list_empty(list)) 73 pending = true; 74 } 75 out: 76 spin_unlock_bh(&txq->axq_lock); 77 return pending; 78 } 79 80 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 81 { 82 unsigned long flags; 83 bool ret; 84 85 spin_lock_irqsave(&sc->sc_pm_lock, flags); 86 ret = ath9k_hw_setpower(sc->sc_ah, mode); 87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 88 89 return ret; 90 } 91 92 void ath_ps_full_sleep(unsigned long data) 93 { 94 struct ath_softc *sc = (struct ath_softc *) data; 95 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 96 bool reset; 97 98 spin_lock(&common->cc_lock); 99 ath_hw_cycle_counters_update(common); 100 spin_unlock(&common->cc_lock); 101 102 ath9k_hw_setrxabort(sc->sc_ah, 1); 103 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 104 105 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 106 } 107 108 void ath9k_ps_wakeup(struct ath_softc *sc) 109 { 110 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 111 unsigned long flags; 112 enum ath9k_power_mode power_mode; 113 114 spin_lock_irqsave(&sc->sc_pm_lock, flags); 115 if (++sc->ps_usecount != 1) 116 goto unlock; 117 118 del_timer_sync(&sc->sleep_timer); 119 power_mode = sc->sc_ah->power_mode; 120 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 121 122 /* 123 * While the hardware is asleep, the cycle counters contain no 124 * useful data. Better clear them now so that they don't mess up 125 * survey data results. 126 */ 127 if (power_mode != ATH9K_PM_AWAKE) { 128 spin_lock(&common->cc_lock); 129 ath_hw_cycle_counters_update(common); 130 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 131 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 132 spin_unlock(&common->cc_lock); 133 } 134 135 unlock: 136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 137 } 138 139 void ath9k_ps_restore(struct ath_softc *sc) 140 { 141 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 142 enum ath9k_power_mode mode; 143 unsigned long flags; 144 145 spin_lock_irqsave(&sc->sc_pm_lock, flags); 146 if (--sc->ps_usecount != 0) 147 goto unlock; 148 149 if (sc->ps_idle) { 150 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 151 goto unlock; 152 } 153 154 if (sc->ps_enabled && 155 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 156 PS_WAIT_FOR_CAB | 157 PS_WAIT_FOR_PSPOLL_DATA | 158 PS_WAIT_FOR_TX_ACK | 159 PS_WAIT_FOR_ANI))) { 160 mode = ATH9K_PM_NETWORK_SLEEP; 161 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 162 ath9k_btcoex_stop_gen_timer(sc); 163 } else { 164 goto unlock; 165 } 166 167 spin_lock(&common->cc_lock); 168 ath_hw_cycle_counters_update(common); 169 spin_unlock(&common->cc_lock); 170 171 ath9k_hw_setpower(sc->sc_ah, mode); 172 173 unlock: 174 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 175 } 176 177 static void __ath_cancel_work(struct ath_softc *sc) 178 { 179 cancel_work_sync(&sc->paprd_work); 180 cancel_delayed_work_sync(&sc->tx_complete_work); 181 cancel_delayed_work_sync(&sc->hw_pll_work); 182 183 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 184 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 185 cancel_work_sync(&sc->mci_work); 186 #endif 187 } 188 189 void ath_cancel_work(struct ath_softc *sc) 190 { 191 __ath_cancel_work(sc); 192 cancel_work_sync(&sc->hw_reset_work); 193 } 194 195 void ath_restart_work(struct ath_softc *sc) 196 { 197 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 198 199 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 200 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 201 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 202 203 ath_start_ani(sc); 204 } 205 206 static bool ath_prepare_reset(struct ath_softc *sc) 207 { 208 struct ath_hw *ah = sc->sc_ah; 209 bool ret = true; 210 211 ieee80211_stop_queues(sc->hw); 212 ath_stop_ani(sc); 213 ath9k_hw_disable_interrupts(ah); 214 215 if (!ath_drain_all_txq(sc)) 216 ret = false; 217 218 if (!ath_stoprecv(sc)) 219 ret = false; 220 221 return ret; 222 } 223 224 static bool ath_complete_reset(struct ath_softc *sc, bool start) 225 { 226 struct ath_hw *ah = sc->sc_ah; 227 struct ath_common *common = ath9k_hw_common(ah); 228 unsigned long flags; 229 230 ath9k_calculate_summary_state(sc, sc->cur_chan); 231 ath_startrecv(sc); 232 ath9k_cmn_update_txpow(ah, sc->curtxpow, 233 sc->cur_chan->txpower, &sc->curtxpow); 234 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 235 236 if (!sc->cur_chan->offchannel && start) { 237 /* restore per chanctx TSF timer */ 238 if (sc->cur_chan->tsf_val) { 239 u32 offset; 240 241 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 242 NULL); 243 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 244 } 245 246 247 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 248 goto work; 249 250 if (ah->opmode == NL80211_IFTYPE_STATION && 251 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 252 spin_lock_irqsave(&sc->sc_pm_lock, flags); 253 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 254 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 255 } else { 256 ath9k_set_beacon(sc); 257 } 258 work: 259 ath_restart_work(sc); 260 ath_txq_schedule_all(sc); 261 } 262 263 sc->gtt_cnt = 0; 264 265 ath9k_hw_set_interrupts(ah); 266 ath9k_hw_enable_interrupts(ah); 267 ieee80211_wake_queues(sc->hw); 268 ath9k_p2p_ps_timer(sc); 269 270 return true; 271 } 272 273 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 274 { 275 struct ath_hw *ah = sc->sc_ah; 276 struct ath_common *common = ath9k_hw_common(ah); 277 struct ath9k_hw_cal_data *caldata = NULL; 278 bool fastcc = true; 279 int r; 280 281 __ath_cancel_work(sc); 282 283 tasklet_disable(&sc->intr_tq); 284 spin_lock_bh(&sc->sc_pcu_lock); 285 286 if (!sc->cur_chan->offchannel) { 287 fastcc = false; 288 caldata = &sc->cur_chan->caldata; 289 } 290 291 if (!hchan) { 292 fastcc = false; 293 hchan = ah->curchan; 294 } 295 296 if (!ath_prepare_reset(sc)) 297 fastcc = false; 298 299 if (ath9k_is_chanctx_enabled()) 300 fastcc = false; 301 302 spin_lock_bh(&sc->chan_lock); 303 sc->cur_chandef = sc->cur_chan->chandef; 304 spin_unlock_bh(&sc->chan_lock); 305 306 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 307 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 308 309 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 310 if (r) { 311 ath_err(common, 312 "Unable to reset channel, reset status %d\n", r); 313 314 ath9k_hw_enable_interrupts(ah); 315 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 316 317 goto out; 318 } 319 320 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 321 sc->cur_chan->offchannel) 322 ath9k_mci_set_txpower(sc, true, false); 323 324 if (!ath_complete_reset(sc, true)) 325 r = -EIO; 326 327 out: 328 spin_unlock_bh(&sc->sc_pcu_lock); 329 tasklet_enable(&sc->intr_tq); 330 331 return r; 332 } 333 334 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 335 struct ieee80211_vif *vif) 336 { 337 struct ath_node *an; 338 an = (struct ath_node *)sta->drv_priv; 339 340 an->sc = sc; 341 an->sta = sta; 342 an->vif = vif; 343 memset(&an->key_idx, 0, sizeof(an->key_idx)); 344 345 ath_tx_node_init(sc, an); 346 347 ath_dynack_node_init(sc->sc_ah, an); 348 } 349 350 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 351 { 352 struct ath_node *an = (struct ath_node *)sta->drv_priv; 353 ath_tx_node_cleanup(sc, an); 354 355 ath_dynack_node_deinit(sc->sc_ah, an); 356 } 357 358 void ath9k_tasklet(unsigned long data) 359 { 360 struct ath_softc *sc = (struct ath_softc *)data; 361 struct ath_hw *ah = sc->sc_ah; 362 struct ath_common *common = ath9k_hw_common(ah); 363 enum ath_reset_type type; 364 unsigned long flags; 365 u32 status = sc->intrstatus; 366 u32 rxmask; 367 368 ath9k_ps_wakeup(sc); 369 spin_lock(&sc->sc_pcu_lock); 370 371 if (status & ATH9K_INT_FATAL) { 372 type = RESET_TYPE_FATAL_INT; 373 ath9k_queue_reset(sc, type); 374 375 /* 376 * Increment the ref. counter here so that 377 * interrupts are enabled in the reset routine. 378 */ 379 atomic_inc(&ah->intr_ref_cnt); 380 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 381 goto out; 382 } 383 384 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 385 (status & ATH9K_INT_BB_WATCHDOG)) { 386 spin_lock(&common->cc_lock); 387 ath_hw_cycle_counters_update(common); 388 ar9003_hw_bb_watchdog_dbg_info(ah); 389 spin_unlock(&common->cc_lock); 390 391 if (ar9003_hw_bb_watchdog_check(ah)) { 392 type = RESET_TYPE_BB_WATCHDOG; 393 ath9k_queue_reset(sc, type); 394 395 /* 396 * Increment the ref. counter here so that 397 * interrupts are enabled in the reset routine. 398 */ 399 atomic_inc(&ah->intr_ref_cnt); 400 ath_dbg(common, RESET, 401 "BB_WATCHDOG: Skipping interrupts\n"); 402 goto out; 403 } 404 } 405 406 if (status & ATH9K_INT_GTT) { 407 sc->gtt_cnt++; 408 409 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 410 type = RESET_TYPE_TX_GTT; 411 ath9k_queue_reset(sc, type); 412 atomic_inc(&ah->intr_ref_cnt); 413 ath_dbg(common, RESET, 414 "GTT: Skipping interrupts\n"); 415 goto out; 416 } 417 } 418 419 spin_lock_irqsave(&sc->sc_pm_lock, flags); 420 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 421 /* 422 * TSF sync does not look correct; remain awake to sync with 423 * the next Beacon. 424 */ 425 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 426 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 427 } 428 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 429 430 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 431 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 432 ATH9K_INT_RXORN); 433 else 434 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 435 436 if (status & rxmask) { 437 /* Check for high priority Rx first */ 438 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 439 (status & ATH9K_INT_RXHP)) 440 ath_rx_tasklet(sc, 0, true); 441 442 ath_rx_tasklet(sc, 0, false); 443 } 444 445 if (status & ATH9K_INT_TX) { 446 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 447 /* 448 * For EDMA chips, TX completion is enabled for the 449 * beacon queue, so if a beacon has been transmitted 450 * successfully after a GTT interrupt, the GTT counter 451 * gets reset to zero here. 452 */ 453 sc->gtt_cnt = 0; 454 455 ath_tx_edma_tasklet(sc); 456 } else { 457 ath_tx_tasklet(sc); 458 } 459 460 wake_up(&sc->tx_wait); 461 } 462 463 if (status & ATH9K_INT_GENTIMER) 464 ath_gen_timer_isr(sc->sc_ah); 465 466 ath9k_btcoex_handle_interrupt(sc, status); 467 468 /* re-enable hardware interrupt */ 469 ath9k_hw_enable_interrupts(ah); 470 out: 471 spin_unlock(&sc->sc_pcu_lock); 472 ath9k_ps_restore(sc); 473 } 474 475 irqreturn_t ath_isr(int irq, void *dev) 476 { 477 #define SCHED_INTR ( \ 478 ATH9K_INT_FATAL | \ 479 ATH9K_INT_BB_WATCHDOG | \ 480 ATH9K_INT_RXORN | \ 481 ATH9K_INT_RXEOL | \ 482 ATH9K_INT_RX | \ 483 ATH9K_INT_RXLP | \ 484 ATH9K_INT_RXHP | \ 485 ATH9K_INT_TX | \ 486 ATH9K_INT_BMISS | \ 487 ATH9K_INT_CST | \ 488 ATH9K_INT_GTT | \ 489 ATH9K_INT_TSFOOR | \ 490 ATH9K_INT_GENTIMER | \ 491 ATH9K_INT_MCI) 492 493 struct ath_softc *sc = dev; 494 struct ath_hw *ah = sc->sc_ah; 495 struct ath_common *common = ath9k_hw_common(ah); 496 enum ath9k_int status; 497 u32 sync_cause = 0; 498 bool sched = false; 499 500 /* 501 * The hardware is not ready/present, don't 502 * touch anything. Note this can happen early 503 * on if the IRQ is shared. 504 */ 505 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 506 return IRQ_NONE; 507 508 /* shared irq, not for us */ 509 510 if (!ath9k_hw_intrpend(ah)) 511 return IRQ_NONE; 512 513 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 514 ath9k_hw_kill_interrupts(ah); 515 return IRQ_HANDLED; 516 } 517 518 /* 519 * Figure out the reason(s) for the interrupt. Note 520 * that the hal returns a pseudo-ISR that may include 521 * bits we haven't explicitly enabled so we mask the 522 * value to insure we only process bits we requested. 523 */ 524 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 525 ath9k_debug_sync_cause(sc, sync_cause); 526 status &= ah->imask; /* discard unasked-for bits */ 527 528 /* 529 * If there are no status bits set, then this interrupt was not 530 * for me (should have been caught above). 531 */ 532 if (!status) 533 return IRQ_NONE; 534 535 /* Cache the status */ 536 sc->intrstatus = status; 537 538 if (status & SCHED_INTR) 539 sched = true; 540 541 /* 542 * If a FATAL or RXORN interrupt is received, we have to reset the 543 * chip immediately. 544 */ 545 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 546 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 547 goto chip_reset; 548 549 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 550 (status & ATH9K_INT_BB_WATCHDOG)) 551 goto chip_reset; 552 553 #ifdef CONFIG_ATH9K_WOW 554 if (status & ATH9K_INT_BMISS) { 555 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 556 atomic_inc(&sc->wow_got_bmiss_intr); 557 atomic_dec(&sc->wow_sleep_proc_intr); 558 } 559 } 560 #endif 561 562 if (status & ATH9K_INT_SWBA) 563 tasklet_schedule(&sc->bcon_tasklet); 564 565 if (status & ATH9K_INT_TXURN) 566 ath9k_hw_updatetxtriglevel(ah, true); 567 568 if (status & ATH9K_INT_RXEOL) { 569 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 570 ath9k_hw_set_interrupts(ah); 571 } 572 573 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 574 if (status & ATH9K_INT_TIM_TIMER) { 575 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 576 goto chip_reset; 577 /* Clear RxAbort bit so that we can 578 * receive frames */ 579 ath9k_setpower(sc, ATH9K_PM_AWAKE); 580 spin_lock(&sc->sc_pm_lock); 581 ath9k_hw_setrxabort(sc->sc_ah, 0); 582 sc->ps_flags |= PS_WAIT_FOR_BEACON; 583 spin_unlock(&sc->sc_pm_lock); 584 } 585 586 chip_reset: 587 588 ath_debug_stat_interrupt(sc, status); 589 590 if (sched) { 591 /* turn off every interrupt */ 592 ath9k_hw_disable_interrupts(ah); 593 tasklet_schedule(&sc->intr_tq); 594 } 595 596 return IRQ_HANDLED; 597 598 #undef SCHED_INTR 599 } 600 601 int ath_reset(struct ath_softc *sc) 602 { 603 int r; 604 605 ath9k_ps_wakeup(sc); 606 r = ath_reset_internal(sc, NULL); 607 ath9k_ps_restore(sc); 608 609 return r; 610 } 611 612 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 613 { 614 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 615 #ifdef CONFIG_ATH9K_DEBUGFS 616 RESET_STAT_INC(sc, type); 617 #endif 618 set_bit(ATH_OP_HW_RESET, &common->op_flags); 619 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 620 } 621 622 void ath_reset_work(struct work_struct *work) 623 { 624 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 625 626 ath_reset(sc); 627 } 628 629 /**********************/ 630 /* mac80211 callbacks */ 631 /**********************/ 632 633 static int ath9k_start(struct ieee80211_hw *hw) 634 { 635 struct ath_softc *sc = hw->priv; 636 struct ath_hw *ah = sc->sc_ah; 637 struct ath_common *common = ath9k_hw_common(ah); 638 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 639 struct ath_chanctx *ctx = sc->cur_chan; 640 struct ath9k_channel *init_channel; 641 int r; 642 643 ath_dbg(common, CONFIG, 644 "Starting driver with initial channel: %d MHz\n", 645 curchan->center_freq); 646 647 ath9k_ps_wakeup(sc); 648 mutex_lock(&sc->mutex); 649 650 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 651 sc->cur_chandef = hw->conf.chandef; 652 653 /* Reset SERDES registers */ 654 ath9k_hw_configpcipowersave(ah, false); 655 656 /* 657 * The basic interface to setting the hardware in a good 658 * state is ``reset''. On return the hardware is known to 659 * be powered up and with interrupts disabled. This must 660 * be followed by initialization of the appropriate bits 661 * and then setup of the interrupt mask. 662 */ 663 spin_lock_bh(&sc->sc_pcu_lock); 664 665 atomic_set(&ah->intr_ref_cnt, -1); 666 667 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 668 if (r) { 669 ath_err(common, 670 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 671 r, curchan->center_freq); 672 ah->reset_power_on = false; 673 } 674 675 /* Setup our intr mask. */ 676 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 677 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 678 ATH9K_INT_GLOBAL; 679 680 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 681 ah->imask |= ATH9K_INT_RXHP | 682 ATH9K_INT_RXLP; 683 else 684 ah->imask |= ATH9K_INT_RX; 685 686 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 687 ah->imask |= ATH9K_INT_BB_WATCHDOG; 688 689 /* 690 * Enable GTT interrupts only for AR9003/AR9004 chips 691 * for now. 692 */ 693 if (AR_SREV_9300_20_OR_LATER(ah)) 694 ah->imask |= ATH9K_INT_GTT; 695 696 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 697 ah->imask |= ATH9K_INT_CST; 698 699 ath_mci_enable(sc); 700 701 clear_bit(ATH_OP_INVALID, &common->op_flags); 702 sc->sc_ah->is_monitoring = false; 703 704 if (!ath_complete_reset(sc, false)) 705 ah->reset_power_on = false; 706 707 if (ah->led_pin >= 0) { 708 ath9k_hw_cfg_output(ah, ah->led_pin, 709 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 710 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 711 } 712 713 /* 714 * Reset key cache to sane defaults (all entries cleared) instead of 715 * semi-random values after suspend/resume. 716 */ 717 ath9k_cmn_init_crypto(sc->sc_ah); 718 719 ath9k_hw_reset_tsf(ah); 720 721 spin_unlock_bh(&sc->sc_pcu_lock); 722 723 mutex_unlock(&sc->mutex); 724 725 ath9k_ps_restore(sc); 726 727 return 0; 728 } 729 730 static void ath9k_tx(struct ieee80211_hw *hw, 731 struct ieee80211_tx_control *control, 732 struct sk_buff *skb) 733 { 734 struct ath_softc *sc = hw->priv; 735 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 736 struct ath_tx_control txctl; 737 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 738 unsigned long flags; 739 740 if (sc->ps_enabled) { 741 /* 742 * mac80211 does not set PM field for normal data frames, so we 743 * need to update that based on the current PS mode. 744 */ 745 if (ieee80211_is_data(hdr->frame_control) && 746 !ieee80211_is_nullfunc(hdr->frame_control) && 747 !ieee80211_has_pm(hdr->frame_control)) { 748 ath_dbg(common, PS, 749 "Add PM=1 for a TX frame while in PS mode\n"); 750 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 751 } 752 } 753 754 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 755 /* 756 * We are using PS-Poll and mac80211 can request TX while in 757 * power save mode. Need to wake up hardware for the TX to be 758 * completed and if needed, also for RX of buffered frames. 759 */ 760 ath9k_ps_wakeup(sc); 761 spin_lock_irqsave(&sc->sc_pm_lock, flags); 762 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 763 ath9k_hw_setrxabort(sc->sc_ah, 0); 764 if (ieee80211_is_pspoll(hdr->frame_control)) { 765 ath_dbg(common, PS, 766 "Sending PS-Poll to pick a buffered frame\n"); 767 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 768 } else { 769 ath_dbg(common, PS, "Wake up to complete TX\n"); 770 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 771 } 772 /* 773 * The actual restore operation will happen only after 774 * the ps_flags bit is cleared. We are just dropping 775 * the ps_usecount here. 776 */ 777 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 778 ath9k_ps_restore(sc); 779 } 780 781 /* 782 * Cannot tx while the hardware is in full sleep, it first needs a full 783 * chip reset to recover from that 784 */ 785 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 786 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 787 goto exit; 788 } 789 790 memset(&txctl, 0, sizeof(struct ath_tx_control)); 791 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 792 txctl.sta = control->sta; 793 794 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 795 796 if (ath_tx_start(hw, skb, &txctl) != 0) { 797 ath_dbg(common, XMIT, "TX failed\n"); 798 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 799 goto exit; 800 } 801 802 return; 803 exit: 804 ieee80211_free_txskb(hw, skb); 805 } 806 807 static void ath9k_stop(struct ieee80211_hw *hw) 808 { 809 struct ath_softc *sc = hw->priv; 810 struct ath_hw *ah = sc->sc_ah; 811 struct ath_common *common = ath9k_hw_common(ah); 812 bool prev_idle; 813 814 ath9k_deinit_channel_context(sc); 815 816 mutex_lock(&sc->mutex); 817 818 ath_cancel_work(sc); 819 820 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 821 ath_dbg(common, ANY, "Device not present\n"); 822 mutex_unlock(&sc->mutex); 823 return; 824 } 825 826 /* Ensure HW is awake when we try to shut it down. */ 827 ath9k_ps_wakeup(sc); 828 829 spin_lock_bh(&sc->sc_pcu_lock); 830 831 /* prevent tasklets to enable interrupts once we disable them */ 832 ah->imask &= ~ATH9K_INT_GLOBAL; 833 834 /* make sure h/w will not generate any interrupt 835 * before setting the invalid flag. */ 836 ath9k_hw_disable_interrupts(ah); 837 838 spin_unlock_bh(&sc->sc_pcu_lock); 839 840 /* we can now sync irq and kill any running tasklets, since we already 841 * disabled interrupts and not holding a spin lock */ 842 synchronize_irq(sc->irq); 843 tasklet_kill(&sc->intr_tq); 844 tasklet_kill(&sc->bcon_tasklet); 845 846 prev_idle = sc->ps_idle; 847 sc->ps_idle = true; 848 849 spin_lock_bh(&sc->sc_pcu_lock); 850 851 if (ah->led_pin >= 0) { 852 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 853 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 854 } 855 856 ath_prepare_reset(sc); 857 858 if (sc->rx.frag) { 859 dev_kfree_skb_any(sc->rx.frag); 860 sc->rx.frag = NULL; 861 } 862 863 if (!ah->curchan) 864 ah->curchan = ath9k_cmn_get_channel(hw, ah, 865 &sc->cur_chan->chandef); 866 867 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 868 ath9k_hw_phy_disable(ah); 869 870 ath9k_hw_configpcipowersave(ah, true); 871 872 spin_unlock_bh(&sc->sc_pcu_lock); 873 874 ath9k_ps_restore(sc); 875 876 set_bit(ATH_OP_INVALID, &common->op_flags); 877 sc->ps_idle = prev_idle; 878 879 mutex_unlock(&sc->mutex); 880 881 ath_dbg(common, CONFIG, "Driver halt\n"); 882 } 883 884 static bool ath9k_uses_beacons(int type) 885 { 886 switch (type) { 887 case NL80211_IFTYPE_AP: 888 case NL80211_IFTYPE_ADHOC: 889 case NL80211_IFTYPE_MESH_POINT: 890 return true; 891 default: 892 return false; 893 } 894 } 895 896 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 897 u8 *mac, struct ieee80211_vif *vif) 898 { 899 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 900 int i; 901 902 if (iter_data->has_hw_macaddr) { 903 for (i = 0; i < ETH_ALEN; i++) 904 iter_data->mask[i] &= 905 ~(iter_data->hw_macaddr[i] ^ mac[i]); 906 } else { 907 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 908 iter_data->has_hw_macaddr = true; 909 } 910 911 if (!vif->bss_conf.use_short_slot) 912 iter_data->slottime = ATH9K_SLOT_TIME_20; 913 914 switch (vif->type) { 915 case NL80211_IFTYPE_AP: 916 iter_data->naps++; 917 break; 918 case NL80211_IFTYPE_STATION: 919 iter_data->nstations++; 920 if (avp->assoc && !iter_data->primary_sta) 921 iter_data->primary_sta = vif; 922 break; 923 case NL80211_IFTYPE_ADHOC: 924 iter_data->nadhocs++; 925 if (vif->bss_conf.enable_beacon) 926 iter_data->beacons = true; 927 break; 928 case NL80211_IFTYPE_MESH_POINT: 929 iter_data->nmeshes++; 930 if (vif->bss_conf.enable_beacon) 931 iter_data->beacons = true; 932 break; 933 case NL80211_IFTYPE_WDS: 934 iter_data->nwds++; 935 break; 936 default: 937 break; 938 } 939 } 940 941 static void ath9k_update_bssid_mask(struct ath_softc *sc, 942 struct ath_chanctx *ctx, 943 struct ath9k_vif_iter_data *iter_data) 944 { 945 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 946 struct ath_vif *avp; 947 int i; 948 949 if (!ath9k_is_chanctx_enabled()) 950 return; 951 952 list_for_each_entry(avp, &ctx->vifs, list) { 953 if (ctx->nvifs_assigned != 1) 954 continue; 955 956 if (!avp->vif->p2p || !iter_data->has_hw_macaddr) 957 continue; 958 959 ether_addr_copy(common->curbssid, avp->bssid); 960 961 /* perm_addr will be used as the p2p device address. */ 962 for (i = 0; i < ETH_ALEN; i++) 963 iter_data->mask[i] &= 964 ~(iter_data->hw_macaddr[i] ^ 965 sc->hw->wiphy->perm_addr[i]); 966 } 967 } 968 969 /* Called with sc->mutex held. */ 970 void ath9k_calculate_iter_data(struct ath_softc *sc, 971 struct ath_chanctx *ctx, 972 struct ath9k_vif_iter_data *iter_data) 973 { 974 struct ath_vif *avp; 975 976 /* 977 * The hardware will use primary station addr together with the 978 * BSSID mask when matching addresses. 979 */ 980 memset(iter_data, 0, sizeof(*iter_data)); 981 memset(&iter_data->mask, 0xff, ETH_ALEN); 982 iter_data->slottime = ATH9K_SLOT_TIME_9; 983 984 list_for_each_entry(avp, &ctx->vifs, list) 985 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 986 987 ath9k_update_bssid_mask(sc, ctx, iter_data); 988 } 989 990 static void ath9k_set_assoc_state(struct ath_softc *sc, 991 struct ieee80211_vif *vif, bool changed) 992 { 993 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 994 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 995 unsigned long flags; 996 997 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 998 999 ether_addr_copy(common->curbssid, avp->bssid); 1000 common->curaid = avp->aid; 1001 ath9k_hw_write_associd(sc->sc_ah); 1002 1003 if (changed) { 1004 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1005 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1006 1007 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1008 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1009 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1010 } 1011 1012 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1013 ath9k_mci_update_wlan_channels(sc, false); 1014 1015 ath_dbg(common, CONFIG, 1016 "Primary Station interface: %pM, BSSID: %pM\n", 1017 vif->addr, common->curbssid); 1018 } 1019 1020 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1021 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1022 { 1023 struct ath_hw *ah = sc->sc_ah; 1024 struct ath_common *common = ath9k_hw_common(ah); 1025 struct ieee80211_vif *vif = NULL; 1026 1027 ath9k_ps_wakeup(sc); 1028 1029 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1030 vif = sc->offchannel.scan_vif; 1031 else 1032 vif = sc->offchannel.roc_vif; 1033 1034 if (WARN_ON(!vif)) 1035 goto exit; 1036 1037 eth_zero_addr(common->curbssid); 1038 eth_broadcast_addr(common->bssidmask); 1039 ether_addr_copy(common->macaddr, vif->addr); 1040 common->curaid = 0; 1041 ah->opmode = vif->type; 1042 ah->imask &= ~ATH9K_INT_SWBA; 1043 ah->imask &= ~ATH9K_INT_TSFOOR; 1044 ah->slottime = ATH9K_SLOT_TIME_9; 1045 1046 ath_hw_setbssidmask(common); 1047 ath9k_hw_setopmode(ah); 1048 ath9k_hw_write_associd(sc->sc_ah); 1049 ath9k_hw_set_interrupts(ah); 1050 ath9k_hw_init_global_settings(ah); 1051 1052 exit: 1053 ath9k_ps_restore(sc); 1054 } 1055 #endif 1056 1057 /* Called with sc->mutex held. */ 1058 void ath9k_calculate_summary_state(struct ath_softc *sc, 1059 struct ath_chanctx *ctx) 1060 { 1061 struct ath_hw *ah = sc->sc_ah; 1062 struct ath_common *common = ath9k_hw_common(ah); 1063 struct ath9k_vif_iter_data iter_data; 1064 struct ath_beacon_config *cur_conf; 1065 1066 ath_chanctx_check_active(sc, ctx); 1067 1068 if (ctx != sc->cur_chan) 1069 return; 1070 1071 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1072 if (ctx == &sc->offchannel.chan) 1073 return ath9k_set_offchannel_state(sc); 1074 #endif 1075 1076 ath9k_ps_wakeup(sc); 1077 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1078 1079 if (iter_data.has_hw_macaddr) 1080 ether_addr_copy(common->macaddr, iter_data.hw_macaddr); 1081 1082 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1083 ath_hw_setbssidmask(common); 1084 1085 if (iter_data.naps > 0) { 1086 cur_conf = &ctx->beacon; 1087 ath9k_hw_set_tsfadjust(ah, true); 1088 ah->opmode = NL80211_IFTYPE_AP; 1089 if (cur_conf->enable_beacon) 1090 iter_data.beacons = true; 1091 } else { 1092 ath9k_hw_set_tsfadjust(ah, false); 1093 1094 if (iter_data.nmeshes) 1095 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1096 else if (iter_data.nwds) 1097 ah->opmode = NL80211_IFTYPE_AP; 1098 else if (iter_data.nadhocs) 1099 ah->opmode = NL80211_IFTYPE_ADHOC; 1100 else 1101 ah->opmode = NL80211_IFTYPE_STATION; 1102 } 1103 1104 ath9k_hw_setopmode(ah); 1105 1106 ctx->switch_after_beacon = false; 1107 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1108 ah->imask |= ATH9K_INT_TSFOOR; 1109 else { 1110 ah->imask &= ~ATH9K_INT_TSFOOR; 1111 if (iter_data.naps == 1 && iter_data.beacons) 1112 ctx->switch_after_beacon = true; 1113 } 1114 1115 ah->imask &= ~ATH9K_INT_SWBA; 1116 if (ah->opmode == NL80211_IFTYPE_STATION) { 1117 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1118 1119 if (iter_data.primary_sta) { 1120 iter_data.beacons = true; 1121 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1122 changed); 1123 ctx->primary_sta = iter_data.primary_sta; 1124 } else { 1125 ctx->primary_sta = NULL; 1126 memset(common->curbssid, 0, ETH_ALEN); 1127 common->curaid = 0; 1128 ath9k_hw_write_associd(sc->sc_ah); 1129 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1130 ath9k_mci_update_wlan_channels(sc, true); 1131 } 1132 } else if (iter_data.beacons) { 1133 ah->imask |= ATH9K_INT_SWBA; 1134 } 1135 ath9k_hw_set_interrupts(ah); 1136 1137 if (iter_data.beacons) 1138 set_bit(ATH_OP_BEACONS, &common->op_flags); 1139 else 1140 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1141 1142 if (ah->slottime != iter_data.slottime) { 1143 ah->slottime = iter_data.slottime; 1144 ath9k_hw_init_global_settings(ah); 1145 } 1146 1147 if (iter_data.primary_sta) 1148 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1149 else 1150 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1151 1152 ath_dbg(common, CONFIG, 1153 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1154 common->macaddr, common->curbssid, common->bssidmask); 1155 1156 ath9k_ps_restore(sc); 1157 } 1158 1159 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1160 struct ieee80211_vif *vif) 1161 { 1162 int i; 1163 1164 if (!ath9k_is_chanctx_enabled()) 1165 return; 1166 1167 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1168 vif->hw_queue[i] = i; 1169 1170 if (vif->type == NL80211_IFTYPE_AP) 1171 vif->cab_queue = hw->queues - 2; 1172 else 1173 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1174 } 1175 1176 static int ath9k_add_interface(struct ieee80211_hw *hw, 1177 struct ieee80211_vif *vif) 1178 { 1179 struct ath_softc *sc = hw->priv; 1180 struct ath_hw *ah = sc->sc_ah; 1181 struct ath_common *common = ath9k_hw_common(ah); 1182 struct ath_vif *avp = (void *)vif->drv_priv; 1183 struct ath_node *an = &avp->mcast_node; 1184 1185 mutex_lock(&sc->mutex); 1186 1187 if (config_enabled(CONFIG_ATH9K_TX99)) { 1188 if (sc->cur_chan->nvifs >= 1) { 1189 mutex_unlock(&sc->mutex); 1190 return -EOPNOTSUPP; 1191 } 1192 sc->tx99_vif = vif; 1193 } 1194 1195 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1196 sc->cur_chan->nvifs++; 1197 1198 if (ath9k_uses_beacons(vif->type)) 1199 ath9k_beacon_assign_slot(sc, vif); 1200 1201 avp->vif = vif; 1202 if (!ath9k_is_chanctx_enabled()) { 1203 avp->chanctx = sc->cur_chan; 1204 list_add_tail(&avp->list, &avp->chanctx->vifs); 1205 } 1206 1207 ath9k_calculate_summary_state(sc, avp->chanctx); 1208 1209 ath9k_assign_hw_queues(hw, vif); 1210 1211 an->sc = sc; 1212 an->sta = NULL; 1213 an->vif = vif; 1214 an->no_ps_filter = true; 1215 ath_tx_node_init(sc, an); 1216 1217 mutex_unlock(&sc->mutex); 1218 return 0; 1219 } 1220 1221 static int ath9k_change_interface(struct ieee80211_hw *hw, 1222 struct ieee80211_vif *vif, 1223 enum nl80211_iftype new_type, 1224 bool p2p) 1225 { 1226 struct ath_softc *sc = hw->priv; 1227 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1228 struct ath_vif *avp = (void *)vif->drv_priv; 1229 1230 mutex_lock(&sc->mutex); 1231 1232 if (config_enabled(CONFIG_ATH9K_TX99)) { 1233 mutex_unlock(&sc->mutex); 1234 return -EOPNOTSUPP; 1235 } 1236 1237 ath_dbg(common, CONFIG, "Change Interface\n"); 1238 1239 if (ath9k_uses_beacons(vif->type)) 1240 ath9k_beacon_remove_slot(sc, vif); 1241 1242 vif->type = new_type; 1243 vif->p2p = p2p; 1244 1245 if (ath9k_uses_beacons(vif->type)) 1246 ath9k_beacon_assign_slot(sc, vif); 1247 1248 ath9k_assign_hw_queues(hw, vif); 1249 ath9k_calculate_summary_state(sc, avp->chanctx); 1250 1251 mutex_unlock(&sc->mutex); 1252 return 0; 1253 } 1254 1255 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1256 struct ieee80211_vif *vif) 1257 { 1258 struct ath_softc *sc = hw->priv; 1259 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1260 struct ath_vif *avp = (void *)vif->drv_priv; 1261 1262 ath_dbg(common, CONFIG, "Detach Interface\n"); 1263 1264 mutex_lock(&sc->mutex); 1265 1266 ath9k_p2p_remove_vif(sc, vif); 1267 1268 sc->cur_chan->nvifs--; 1269 sc->tx99_vif = NULL; 1270 if (!ath9k_is_chanctx_enabled()) 1271 list_del(&avp->list); 1272 1273 if (ath9k_uses_beacons(vif->type)) 1274 ath9k_beacon_remove_slot(sc, vif); 1275 1276 ath_tx_node_cleanup(sc, &avp->mcast_node); 1277 1278 ath9k_calculate_summary_state(sc, avp->chanctx); 1279 1280 mutex_unlock(&sc->mutex); 1281 } 1282 1283 static void ath9k_enable_ps(struct ath_softc *sc) 1284 { 1285 struct ath_hw *ah = sc->sc_ah; 1286 struct ath_common *common = ath9k_hw_common(ah); 1287 1288 if (config_enabled(CONFIG_ATH9K_TX99)) 1289 return; 1290 1291 sc->ps_enabled = true; 1292 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1293 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1294 ah->imask |= ATH9K_INT_TIM_TIMER; 1295 ath9k_hw_set_interrupts(ah); 1296 } 1297 ath9k_hw_setrxabort(ah, 1); 1298 } 1299 ath_dbg(common, PS, "PowerSave enabled\n"); 1300 } 1301 1302 static void ath9k_disable_ps(struct ath_softc *sc) 1303 { 1304 struct ath_hw *ah = sc->sc_ah; 1305 struct ath_common *common = ath9k_hw_common(ah); 1306 1307 if (config_enabled(CONFIG_ATH9K_TX99)) 1308 return; 1309 1310 sc->ps_enabled = false; 1311 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1312 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1313 ath9k_hw_setrxabort(ah, 0); 1314 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1315 PS_WAIT_FOR_CAB | 1316 PS_WAIT_FOR_PSPOLL_DATA | 1317 PS_WAIT_FOR_TX_ACK); 1318 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1319 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1320 ath9k_hw_set_interrupts(ah); 1321 } 1322 } 1323 ath_dbg(common, PS, "PowerSave disabled\n"); 1324 } 1325 1326 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1327 { 1328 struct ath_softc *sc = hw->priv; 1329 struct ath_hw *ah = sc->sc_ah; 1330 struct ath_common *common = ath9k_hw_common(ah); 1331 u32 rxfilter; 1332 1333 if (config_enabled(CONFIG_ATH9K_TX99)) 1334 return; 1335 1336 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1337 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1338 return; 1339 } 1340 1341 ath9k_ps_wakeup(sc); 1342 rxfilter = ath9k_hw_getrxfilter(ah); 1343 ath9k_hw_setrxfilter(ah, rxfilter | 1344 ATH9K_RX_FILTER_PHYRADAR | 1345 ATH9K_RX_FILTER_PHYERR); 1346 1347 /* TODO: usually this should not be neccesary, but for some reason 1348 * (or in some mode?) the trigger must be called after the 1349 * configuration, otherwise the register will have its values reset 1350 * (on my ar9220 to value 0x01002310) 1351 */ 1352 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1353 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1354 ath9k_ps_restore(sc); 1355 } 1356 1357 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1358 enum spectral_mode spectral_mode) 1359 { 1360 struct ath_softc *sc = hw->priv; 1361 struct ath_hw *ah = sc->sc_ah; 1362 struct ath_common *common = ath9k_hw_common(ah); 1363 1364 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1365 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1366 return -1; 1367 } 1368 1369 switch (spectral_mode) { 1370 case SPECTRAL_DISABLED: 1371 sc->spec_config.enabled = 0; 1372 break; 1373 case SPECTRAL_BACKGROUND: 1374 /* send endless samples. 1375 * TODO: is this really useful for "background"? 1376 */ 1377 sc->spec_config.endless = 1; 1378 sc->spec_config.enabled = 1; 1379 break; 1380 case SPECTRAL_CHANSCAN: 1381 case SPECTRAL_MANUAL: 1382 sc->spec_config.endless = 0; 1383 sc->spec_config.enabled = 1; 1384 break; 1385 default: 1386 return -1; 1387 } 1388 1389 ath9k_ps_wakeup(sc); 1390 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1391 ath9k_ps_restore(sc); 1392 1393 sc->spectral_mode = spectral_mode; 1394 1395 return 0; 1396 } 1397 1398 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1399 { 1400 struct ath_softc *sc = hw->priv; 1401 struct ath_hw *ah = sc->sc_ah; 1402 struct ath_common *common = ath9k_hw_common(ah); 1403 struct ieee80211_conf *conf = &hw->conf; 1404 struct ath_chanctx *ctx = sc->cur_chan; 1405 1406 ath9k_ps_wakeup(sc); 1407 mutex_lock(&sc->mutex); 1408 1409 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1410 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1411 if (sc->ps_idle) { 1412 ath_cancel_work(sc); 1413 ath9k_stop_btcoex(sc); 1414 } else { 1415 ath9k_start_btcoex(sc); 1416 /* 1417 * The chip needs a reset to properly wake up from 1418 * full sleep 1419 */ 1420 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1421 } 1422 } 1423 1424 /* 1425 * We just prepare to enable PS. We have to wait until our AP has 1426 * ACK'd our null data frame to disable RX otherwise we'll ignore 1427 * those ACKs and end up retransmitting the same null data frames. 1428 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1429 */ 1430 if (changed & IEEE80211_CONF_CHANGE_PS) { 1431 unsigned long flags; 1432 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1433 if (conf->flags & IEEE80211_CONF_PS) 1434 ath9k_enable_ps(sc); 1435 else 1436 ath9k_disable_ps(sc); 1437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1438 } 1439 1440 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1441 if (conf->flags & IEEE80211_CONF_MONITOR) { 1442 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1443 sc->sc_ah->is_monitoring = true; 1444 } else { 1445 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1446 sc->sc_ah->is_monitoring = false; 1447 } 1448 } 1449 1450 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1451 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1452 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1453 } 1454 1455 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1456 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1457 sc->cur_chan->txpower = 2 * conf->power_level; 1458 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1459 sc->cur_chan->txpower, &sc->curtxpow); 1460 } 1461 1462 mutex_unlock(&sc->mutex); 1463 ath9k_ps_restore(sc); 1464 1465 return 0; 1466 } 1467 1468 #define SUPPORTED_FILTERS \ 1469 (FIF_PROMISC_IN_BSS | \ 1470 FIF_ALLMULTI | \ 1471 FIF_CONTROL | \ 1472 FIF_PSPOLL | \ 1473 FIF_OTHER_BSS | \ 1474 FIF_BCN_PRBRESP_PROMISC | \ 1475 FIF_PROBE_REQ | \ 1476 FIF_FCSFAIL) 1477 1478 /* FIXME: sc->sc_full_reset ? */ 1479 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1480 unsigned int changed_flags, 1481 unsigned int *total_flags, 1482 u64 multicast) 1483 { 1484 struct ath_softc *sc = hw->priv; 1485 u32 rfilt; 1486 1487 changed_flags &= SUPPORTED_FILTERS; 1488 *total_flags &= SUPPORTED_FILTERS; 1489 1490 spin_lock_bh(&sc->chan_lock); 1491 sc->cur_chan->rxfilter = *total_flags; 1492 spin_unlock_bh(&sc->chan_lock); 1493 1494 ath9k_ps_wakeup(sc); 1495 rfilt = ath_calcrxfilter(sc); 1496 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1497 ath9k_ps_restore(sc); 1498 1499 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1500 rfilt); 1501 } 1502 1503 static int ath9k_sta_add(struct ieee80211_hw *hw, 1504 struct ieee80211_vif *vif, 1505 struct ieee80211_sta *sta) 1506 { 1507 struct ath_softc *sc = hw->priv; 1508 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1509 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1510 struct ieee80211_key_conf ps_key = { }; 1511 int key; 1512 1513 ath_node_attach(sc, sta, vif); 1514 1515 if (vif->type != NL80211_IFTYPE_AP && 1516 vif->type != NL80211_IFTYPE_AP_VLAN) 1517 return 0; 1518 1519 key = ath_key_config(common, vif, sta, &ps_key); 1520 if (key > 0) { 1521 an->ps_key = key; 1522 an->key_idx[0] = key; 1523 } 1524 1525 return 0; 1526 } 1527 1528 static void ath9k_del_ps_key(struct ath_softc *sc, 1529 struct ieee80211_vif *vif, 1530 struct ieee80211_sta *sta) 1531 { 1532 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1533 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1534 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1535 1536 if (!an->ps_key) 1537 return; 1538 1539 ath_key_delete(common, &ps_key); 1540 an->ps_key = 0; 1541 an->key_idx[0] = 0; 1542 } 1543 1544 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1545 struct ieee80211_vif *vif, 1546 struct ieee80211_sta *sta) 1547 { 1548 struct ath_softc *sc = hw->priv; 1549 1550 ath9k_del_ps_key(sc, vif, sta); 1551 ath_node_detach(sc, sta); 1552 1553 return 0; 1554 } 1555 1556 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1557 struct ath_node *an, 1558 bool set) 1559 { 1560 int i; 1561 1562 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1563 if (!an->key_idx[i]) 1564 continue; 1565 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1566 } 1567 } 1568 1569 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1570 struct ieee80211_vif *vif, 1571 enum sta_notify_cmd cmd, 1572 struct ieee80211_sta *sta) 1573 { 1574 struct ath_softc *sc = hw->priv; 1575 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1576 1577 switch (cmd) { 1578 case STA_NOTIFY_SLEEP: 1579 an->sleeping = true; 1580 ath_tx_aggr_sleep(sta, sc, an); 1581 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1582 break; 1583 case STA_NOTIFY_AWAKE: 1584 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1585 an->sleeping = false; 1586 ath_tx_aggr_wakeup(sc, an); 1587 break; 1588 } 1589 } 1590 1591 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1592 struct ieee80211_vif *vif, u16 queue, 1593 const struct ieee80211_tx_queue_params *params) 1594 { 1595 struct ath_softc *sc = hw->priv; 1596 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1597 struct ath_txq *txq; 1598 struct ath9k_tx_queue_info qi; 1599 int ret = 0; 1600 1601 if (queue >= IEEE80211_NUM_ACS) 1602 return 0; 1603 1604 txq = sc->tx.txq_map[queue]; 1605 1606 ath9k_ps_wakeup(sc); 1607 mutex_lock(&sc->mutex); 1608 1609 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1610 1611 qi.tqi_aifs = params->aifs; 1612 qi.tqi_cwmin = params->cw_min; 1613 qi.tqi_cwmax = params->cw_max; 1614 qi.tqi_burstTime = params->txop * 32; 1615 1616 ath_dbg(common, CONFIG, 1617 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1618 queue, txq->axq_qnum, params->aifs, params->cw_min, 1619 params->cw_max, params->txop); 1620 1621 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1622 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1623 if (ret) 1624 ath_err(common, "TXQ Update failed\n"); 1625 1626 mutex_unlock(&sc->mutex); 1627 ath9k_ps_restore(sc); 1628 1629 return ret; 1630 } 1631 1632 static int ath9k_set_key(struct ieee80211_hw *hw, 1633 enum set_key_cmd cmd, 1634 struct ieee80211_vif *vif, 1635 struct ieee80211_sta *sta, 1636 struct ieee80211_key_conf *key) 1637 { 1638 struct ath_softc *sc = hw->priv; 1639 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1640 struct ath_node *an = NULL; 1641 int ret = 0, i; 1642 1643 if (ath9k_modparam_nohwcrypt) 1644 return -ENOSPC; 1645 1646 if ((vif->type == NL80211_IFTYPE_ADHOC || 1647 vif->type == NL80211_IFTYPE_MESH_POINT) && 1648 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1649 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1650 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1651 /* 1652 * For now, disable hw crypto for the RSN IBSS group keys. This 1653 * could be optimized in the future to use a modified key cache 1654 * design to support per-STA RX GTK, but until that gets 1655 * implemented, use of software crypto for group addressed 1656 * frames is a acceptable to allow RSN IBSS to be used. 1657 */ 1658 return -EOPNOTSUPP; 1659 } 1660 1661 mutex_lock(&sc->mutex); 1662 ath9k_ps_wakeup(sc); 1663 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1664 if (sta) 1665 an = (struct ath_node *)sta->drv_priv; 1666 1667 switch (cmd) { 1668 case SET_KEY: 1669 if (sta) 1670 ath9k_del_ps_key(sc, vif, sta); 1671 1672 key->hw_key_idx = 0; 1673 ret = ath_key_config(common, vif, sta, key); 1674 if (ret >= 0) { 1675 key->hw_key_idx = ret; 1676 /* push IV and Michael MIC generation to stack */ 1677 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1678 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1679 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1680 if (sc->sc_ah->sw_mgmt_crypto && 1681 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1682 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1683 ret = 0; 1684 } 1685 if (an && key->hw_key_idx) { 1686 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1687 if (an->key_idx[i]) 1688 continue; 1689 an->key_idx[i] = key->hw_key_idx; 1690 break; 1691 } 1692 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1693 } 1694 break; 1695 case DISABLE_KEY: 1696 ath_key_delete(common, key); 1697 if (an) { 1698 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1699 if (an->key_idx[i] != key->hw_key_idx) 1700 continue; 1701 an->key_idx[i] = 0; 1702 break; 1703 } 1704 } 1705 key->hw_key_idx = 0; 1706 break; 1707 default: 1708 ret = -EINVAL; 1709 } 1710 1711 ath9k_ps_restore(sc); 1712 mutex_unlock(&sc->mutex); 1713 1714 return ret; 1715 } 1716 1717 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1718 struct ieee80211_vif *vif, 1719 struct ieee80211_bss_conf *bss_conf, 1720 u32 changed) 1721 { 1722 #define CHECK_ANI \ 1723 (BSS_CHANGED_ASSOC | \ 1724 BSS_CHANGED_IBSS | \ 1725 BSS_CHANGED_BEACON_ENABLED) 1726 1727 struct ath_softc *sc = hw->priv; 1728 struct ath_hw *ah = sc->sc_ah; 1729 struct ath_common *common = ath9k_hw_common(ah); 1730 struct ath_vif *avp = (void *)vif->drv_priv; 1731 int slottime; 1732 1733 ath9k_ps_wakeup(sc); 1734 mutex_lock(&sc->mutex); 1735 1736 if (changed & BSS_CHANGED_ASSOC) { 1737 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1738 bss_conf->bssid, bss_conf->assoc); 1739 1740 ether_addr_copy(avp->bssid, bss_conf->bssid); 1741 avp->aid = bss_conf->aid; 1742 avp->assoc = bss_conf->assoc; 1743 1744 ath9k_calculate_summary_state(sc, avp->chanctx); 1745 1746 if (ath9k_is_chanctx_enabled()) { 1747 if (bss_conf->assoc) 1748 ath_chanctx_event(sc, vif, 1749 ATH_CHANCTX_EVENT_ASSOC); 1750 } 1751 } 1752 1753 if (changed & BSS_CHANGED_IBSS) { 1754 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1755 common->curaid = bss_conf->aid; 1756 ath9k_hw_write_associd(sc->sc_ah); 1757 } 1758 1759 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1760 (changed & BSS_CHANGED_BEACON_INT) || 1761 (changed & BSS_CHANGED_BEACON_INFO)) { 1762 ath9k_beacon_config(sc, vif, changed); 1763 if (changed & BSS_CHANGED_BEACON_ENABLED) 1764 ath9k_calculate_summary_state(sc, avp->chanctx); 1765 } 1766 1767 if ((avp->chanctx == sc->cur_chan) && 1768 (changed & BSS_CHANGED_ERP_SLOT)) { 1769 if (bss_conf->use_short_slot) 1770 slottime = 9; 1771 else 1772 slottime = 20; 1773 if (vif->type == NL80211_IFTYPE_AP) { 1774 /* 1775 * Defer update, so that connected stations can adjust 1776 * their settings at the same time. 1777 * See beacon.c for more details 1778 */ 1779 sc->beacon.slottime = slottime; 1780 sc->beacon.updateslot = UPDATE; 1781 } else { 1782 ah->slottime = slottime; 1783 ath9k_hw_init_global_settings(ah); 1784 } 1785 } 1786 1787 if (changed & BSS_CHANGED_P2P_PS) 1788 ath9k_p2p_bss_info_changed(sc, vif); 1789 1790 if (changed & CHECK_ANI) 1791 ath_check_ani(sc); 1792 1793 mutex_unlock(&sc->mutex); 1794 ath9k_ps_restore(sc); 1795 1796 #undef CHECK_ANI 1797 } 1798 1799 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1800 { 1801 struct ath_softc *sc = hw->priv; 1802 u64 tsf; 1803 1804 mutex_lock(&sc->mutex); 1805 ath9k_ps_wakeup(sc); 1806 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1807 ath9k_ps_restore(sc); 1808 mutex_unlock(&sc->mutex); 1809 1810 return tsf; 1811 } 1812 1813 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1814 struct ieee80211_vif *vif, 1815 u64 tsf) 1816 { 1817 struct ath_softc *sc = hw->priv; 1818 1819 mutex_lock(&sc->mutex); 1820 ath9k_ps_wakeup(sc); 1821 ath9k_hw_settsf64(sc->sc_ah, tsf); 1822 ath9k_ps_restore(sc); 1823 mutex_unlock(&sc->mutex); 1824 } 1825 1826 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1827 { 1828 struct ath_softc *sc = hw->priv; 1829 1830 mutex_lock(&sc->mutex); 1831 1832 ath9k_ps_wakeup(sc); 1833 ath9k_hw_reset_tsf(sc->sc_ah); 1834 ath9k_ps_restore(sc); 1835 1836 mutex_unlock(&sc->mutex); 1837 } 1838 1839 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1840 struct ieee80211_vif *vif, 1841 enum ieee80211_ampdu_mlme_action action, 1842 struct ieee80211_sta *sta, 1843 u16 tid, u16 *ssn, u8 buf_size) 1844 { 1845 struct ath_softc *sc = hw->priv; 1846 bool flush = false; 1847 int ret = 0; 1848 1849 mutex_lock(&sc->mutex); 1850 1851 switch (action) { 1852 case IEEE80211_AMPDU_RX_START: 1853 break; 1854 case IEEE80211_AMPDU_RX_STOP: 1855 break; 1856 case IEEE80211_AMPDU_TX_START: 1857 ath9k_ps_wakeup(sc); 1858 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1859 if (!ret) 1860 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1861 ath9k_ps_restore(sc); 1862 break; 1863 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1864 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1865 flush = true; 1866 case IEEE80211_AMPDU_TX_STOP_CONT: 1867 ath9k_ps_wakeup(sc); 1868 ath_tx_aggr_stop(sc, sta, tid); 1869 if (!flush) 1870 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1871 ath9k_ps_restore(sc); 1872 break; 1873 case IEEE80211_AMPDU_TX_OPERATIONAL: 1874 ath9k_ps_wakeup(sc); 1875 ath_tx_aggr_resume(sc, sta, tid); 1876 ath9k_ps_restore(sc); 1877 break; 1878 default: 1879 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1880 } 1881 1882 mutex_unlock(&sc->mutex); 1883 1884 return ret; 1885 } 1886 1887 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1888 struct survey_info *survey) 1889 { 1890 struct ath_softc *sc = hw->priv; 1891 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1892 struct ieee80211_supported_band *sband; 1893 struct ieee80211_channel *chan; 1894 int pos; 1895 1896 if (config_enabled(CONFIG_ATH9K_TX99)) 1897 return -EOPNOTSUPP; 1898 1899 spin_lock_bh(&common->cc_lock); 1900 if (idx == 0) 1901 ath_update_survey_stats(sc); 1902 1903 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1904 if (sband && idx >= sband->n_channels) { 1905 idx -= sband->n_channels; 1906 sband = NULL; 1907 } 1908 1909 if (!sband) 1910 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1911 1912 if (!sband || idx >= sband->n_channels) { 1913 spin_unlock_bh(&common->cc_lock); 1914 return -ENOENT; 1915 } 1916 1917 chan = &sband->channels[idx]; 1918 pos = chan->hw_value; 1919 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1920 survey->channel = chan; 1921 spin_unlock_bh(&common->cc_lock); 1922 1923 return 0; 1924 } 1925 1926 static void ath9k_enable_dynack(struct ath_softc *sc) 1927 { 1928 #ifdef CONFIG_ATH9K_DYNACK 1929 u32 rfilt; 1930 struct ath_hw *ah = sc->sc_ah; 1931 1932 ath_dynack_reset(ah); 1933 1934 ah->dynack.enabled = true; 1935 rfilt = ath_calcrxfilter(sc); 1936 ath9k_hw_setrxfilter(ah, rfilt); 1937 #endif 1938 } 1939 1940 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 1941 s16 coverage_class) 1942 { 1943 struct ath_softc *sc = hw->priv; 1944 struct ath_hw *ah = sc->sc_ah; 1945 1946 if (config_enabled(CONFIG_ATH9K_TX99)) 1947 return; 1948 1949 mutex_lock(&sc->mutex); 1950 1951 if (coverage_class >= 0) { 1952 ah->coverage_class = coverage_class; 1953 if (ah->dynack.enabled) { 1954 u32 rfilt; 1955 1956 ah->dynack.enabled = false; 1957 rfilt = ath_calcrxfilter(sc); 1958 ath9k_hw_setrxfilter(ah, rfilt); 1959 } 1960 ath9k_ps_wakeup(sc); 1961 ath9k_hw_init_global_settings(ah); 1962 ath9k_ps_restore(sc); 1963 } else if (!ah->dynack.enabled) { 1964 ath9k_enable_dynack(sc); 1965 } 1966 1967 mutex_unlock(&sc->mutex); 1968 } 1969 1970 static bool ath9k_has_tx_pending(struct ath_softc *sc) 1971 { 1972 int i, npend = 0; 1973 1974 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1975 if (!ATH_TXQ_SETUP(sc, i)) 1976 continue; 1977 1978 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1979 if (npend) 1980 break; 1981 } 1982 1983 return !!npend; 1984 } 1985 1986 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1987 u32 queues, bool drop) 1988 { 1989 struct ath_softc *sc = hw->priv; 1990 1991 mutex_lock(&sc->mutex); 1992 __ath9k_flush(hw, queues, drop); 1993 mutex_unlock(&sc->mutex); 1994 } 1995 1996 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1997 { 1998 struct ath_softc *sc = hw->priv; 1999 struct ath_hw *ah = sc->sc_ah; 2000 struct ath_common *common = ath9k_hw_common(ah); 2001 int timeout = HZ / 5; /* 200 ms */ 2002 bool drain_txq; 2003 2004 cancel_delayed_work_sync(&sc->tx_complete_work); 2005 2006 if (ah->ah_flags & AH_UNPLUGGED) { 2007 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2008 return; 2009 } 2010 2011 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2012 ath_dbg(common, ANY, "Device not present\n"); 2013 return; 2014 } 2015 2016 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 2017 timeout) > 0) 2018 drop = false; 2019 2020 if (drop) { 2021 ath9k_ps_wakeup(sc); 2022 spin_lock_bh(&sc->sc_pcu_lock); 2023 drain_txq = ath_drain_all_txq(sc); 2024 spin_unlock_bh(&sc->sc_pcu_lock); 2025 2026 if (!drain_txq) 2027 ath_reset(sc); 2028 2029 ath9k_ps_restore(sc); 2030 } 2031 2032 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2033 } 2034 2035 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2036 { 2037 struct ath_softc *sc = hw->priv; 2038 2039 return ath9k_has_tx_pending(sc); 2040 } 2041 2042 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2043 { 2044 struct ath_softc *sc = hw->priv; 2045 struct ath_hw *ah = sc->sc_ah; 2046 struct ieee80211_vif *vif; 2047 struct ath_vif *avp; 2048 struct ath_buf *bf; 2049 struct ath_tx_status ts; 2050 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2051 int status; 2052 2053 vif = sc->beacon.bslot[0]; 2054 if (!vif) 2055 return 0; 2056 2057 if (!vif->bss_conf.enable_beacon) 2058 return 0; 2059 2060 avp = (void *)vif->drv_priv; 2061 2062 if (!sc->beacon.tx_processed && !edma) { 2063 tasklet_disable(&sc->bcon_tasklet); 2064 2065 bf = avp->av_bcbuf; 2066 if (!bf || !bf->bf_mpdu) 2067 goto skip; 2068 2069 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2070 if (status == -EINPROGRESS) 2071 goto skip; 2072 2073 sc->beacon.tx_processed = true; 2074 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2075 2076 skip: 2077 tasklet_enable(&sc->bcon_tasklet); 2078 } 2079 2080 return sc->beacon.tx_last; 2081 } 2082 2083 static int ath9k_get_stats(struct ieee80211_hw *hw, 2084 struct ieee80211_low_level_stats *stats) 2085 { 2086 struct ath_softc *sc = hw->priv; 2087 struct ath_hw *ah = sc->sc_ah; 2088 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2089 2090 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2091 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2092 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2093 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2094 return 0; 2095 } 2096 2097 static u32 fill_chainmask(u32 cap, u32 new) 2098 { 2099 u32 filled = 0; 2100 int i; 2101 2102 for (i = 0; cap && new; i++, cap >>= 1) { 2103 if (!(cap & BIT(0))) 2104 continue; 2105 2106 if (new & BIT(0)) 2107 filled |= BIT(i); 2108 2109 new >>= 1; 2110 } 2111 2112 return filled; 2113 } 2114 2115 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2116 { 2117 if (AR_SREV_9300_20_OR_LATER(ah)) 2118 return true; 2119 2120 switch (val & 0x7) { 2121 case 0x1: 2122 case 0x3: 2123 case 0x7: 2124 return true; 2125 case 0x2: 2126 return (ah->caps.rx_chainmask == 1); 2127 default: 2128 return false; 2129 } 2130 } 2131 2132 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2133 { 2134 struct ath_softc *sc = hw->priv; 2135 struct ath_hw *ah = sc->sc_ah; 2136 2137 if (ah->caps.rx_chainmask != 1) 2138 rx_ant |= tx_ant; 2139 2140 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2141 return -EINVAL; 2142 2143 sc->ant_rx = rx_ant; 2144 sc->ant_tx = tx_ant; 2145 2146 if (ah->caps.rx_chainmask == 1) 2147 return 0; 2148 2149 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2150 if (AR_SREV_9100(ah)) 2151 ah->rxchainmask = 0x7; 2152 else 2153 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2154 2155 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2156 ath9k_cmn_reload_chainmask(ah); 2157 2158 return 0; 2159 } 2160 2161 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2162 { 2163 struct ath_softc *sc = hw->priv; 2164 2165 *tx_ant = sc->ant_tx; 2166 *rx_ant = sc->ant_rx; 2167 return 0; 2168 } 2169 2170 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2171 { 2172 struct ath_softc *sc = hw->priv; 2173 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2174 set_bit(ATH_OP_SCANNING, &common->op_flags); 2175 } 2176 2177 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2178 { 2179 struct ath_softc *sc = hw->priv; 2180 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2181 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2182 } 2183 2184 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2185 2186 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2187 struct ieee80211_scan_request *hw_req) 2188 { 2189 struct cfg80211_scan_request *req = &hw_req->req; 2190 struct ath_softc *sc = hw->priv; 2191 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2192 int ret = 0; 2193 2194 mutex_lock(&sc->mutex); 2195 2196 if (WARN_ON(sc->offchannel.scan_req)) { 2197 ret = -EBUSY; 2198 goto out; 2199 } 2200 2201 ath9k_ps_wakeup(sc); 2202 set_bit(ATH_OP_SCANNING, &common->op_flags); 2203 sc->offchannel.scan_vif = vif; 2204 sc->offchannel.scan_req = req; 2205 sc->offchannel.scan_idx = 0; 2206 2207 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2208 vif->addr); 2209 2210 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2211 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2212 ath_offchannel_next(sc); 2213 } 2214 2215 out: 2216 mutex_unlock(&sc->mutex); 2217 2218 return ret; 2219 } 2220 2221 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2222 struct ieee80211_vif *vif) 2223 { 2224 struct ath_softc *sc = hw->priv; 2225 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2226 2227 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2228 2229 mutex_lock(&sc->mutex); 2230 del_timer_sync(&sc->offchannel.timer); 2231 ath_scan_complete(sc, true); 2232 mutex_unlock(&sc->mutex); 2233 } 2234 2235 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2236 struct ieee80211_vif *vif, 2237 struct ieee80211_channel *chan, int duration, 2238 enum ieee80211_roc_type type) 2239 { 2240 struct ath_softc *sc = hw->priv; 2241 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2242 int ret = 0; 2243 2244 mutex_lock(&sc->mutex); 2245 2246 if (WARN_ON(sc->offchannel.roc_vif)) { 2247 ret = -EBUSY; 2248 goto out; 2249 } 2250 2251 ath9k_ps_wakeup(sc); 2252 sc->offchannel.roc_vif = vif; 2253 sc->offchannel.roc_chan = chan; 2254 sc->offchannel.roc_duration = duration; 2255 2256 ath_dbg(common, CHAN_CTX, 2257 "RoC request on vif: %pM, type: %d duration: %d\n", 2258 vif->addr, type, duration); 2259 2260 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2261 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2262 ath_offchannel_next(sc); 2263 } 2264 2265 out: 2266 mutex_unlock(&sc->mutex); 2267 2268 return ret; 2269 } 2270 2271 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) 2272 { 2273 struct ath_softc *sc = hw->priv; 2274 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2275 2276 mutex_lock(&sc->mutex); 2277 2278 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2279 del_timer_sync(&sc->offchannel.timer); 2280 2281 if (sc->offchannel.roc_vif) { 2282 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2283 ath_roc_complete(sc, true); 2284 } 2285 2286 mutex_unlock(&sc->mutex); 2287 2288 return 0; 2289 } 2290 2291 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2292 struct ieee80211_chanctx_conf *conf) 2293 { 2294 struct ath_softc *sc = hw->priv; 2295 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2296 struct ath_chanctx *ctx, **ptr; 2297 int pos; 2298 2299 mutex_lock(&sc->mutex); 2300 2301 ath_for_each_chanctx(sc, ctx) { 2302 if (ctx->assigned) 2303 continue; 2304 2305 ptr = (void *) conf->drv_priv; 2306 *ptr = ctx; 2307 ctx->assigned = true; 2308 pos = ctx - &sc->chanctx[0]; 2309 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2310 2311 ath_dbg(common, CHAN_CTX, 2312 "Add channel context: %d MHz\n", 2313 conf->def.chan->center_freq); 2314 2315 ath_chanctx_set_channel(sc, ctx, &conf->def); 2316 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN); 2317 2318 mutex_unlock(&sc->mutex); 2319 return 0; 2320 } 2321 2322 mutex_unlock(&sc->mutex); 2323 return -ENOSPC; 2324 } 2325 2326 2327 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2328 struct ieee80211_chanctx_conf *conf) 2329 { 2330 struct ath_softc *sc = hw->priv; 2331 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2332 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2333 2334 mutex_lock(&sc->mutex); 2335 2336 ath_dbg(common, CHAN_CTX, 2337 "Remove channel context: %d MHz\n", 2338 conf->def.chan->center_freq); 2339 2340 ctx->assigned = false; 2341 ctx->hw_queue_base = 0; 2342 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2343 2344 mutex_unlock(&sc->mutex); 2345 } 2346 2347 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2348 struct ieee80211_chanctx_conf *conf, 2349 u32 changed) 2350 { 2351 struct ath_softc *sc = hw->priv; 2352 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2353 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2354 2355 mutex_lock(&sc->mutex); 2356 ath_dbg(common, CHAN_CTX, 2357 "Change channel context: %d MHz\n", 2358 conf->def.chan->center_freq); 2359 ath_chanctx_set_channel(sc, ctx, &conf->def); 2360 mutex_unlock(&sc->mutex); 2361 } 2362 2363 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2364 struct ieee80211_vif *vif, 2365 struct ieee80211_chanctx_conf *conf) 2366 { 2367 struct ath_softc *sc = hw->priv; 2368 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2369 struct ath_vif *avp = (void *)vif->drv_priv; 2370 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2371 int i; 2372 2373 mutex_lock(&sc->mutex); 2374 2375 ath_dbg(common, CHAN_CTX, 2376 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2377 vif->addr, vif->type, vif->p2p, 2378 conf->def.chan->center_freq); 2379 2380 avp->chanctx = ctx; 2381 ctx->nvifs_assigned++; 2382 list_add_tail(&avp->list, &ctx->vifs); 2383 ath9k_calculate_summary_state(sc, ctx); 2384 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2385 vif->hw_queue[i] = ctx->hw_queue_base + i; 2386 2387 mutex_unlock(&sc->mutex); 2388 2389 return 0; 2390 } 2391 2392 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2393 struct ieee80211_vif *vif, 2394 struct ieee80211_chanctx_conf *conf) 2395 { 2396 struct ath_softc *sc = hw->priv; 2397 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2398 struct ath_vif *avp = (void *)vif->drv_priv; 2399 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2400 int ac; 2401 2402 mutex_lock(&sc->mutex); 2403 2404 ath_dbg(common, CHAN_CTX, 2405 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2406 vif->addr, vif->type, vif->p2p, 2407 conf->def.chan->center_freq); 2408 2409 avp->chanctx = NULL; 2410 ctx->nvifs_assigned--; 2411 list_del(&avp->list); 2412 ath9k_calculate_summary_state(sc, ctx); 2413 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2414 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2415 2416 mutex_unlock(&sc->mutex); 2417 } 2418 2419 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2420 struct ieee80211_vif *vif) 2421 { 2422 struct ath_softc *sc = hw->priv; 2423 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2424 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2425 bool changed = false; 2426 2427 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2428 return; 2429 2430 if (!avp->chanctx) 2431 return; 2432 2433 mutex_lock(&sc->mutex); 2434 2435 spin_lock_bh(&sc->chan_lock); 2436 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) { 2437 sc->next_chan = avp->chanctx; 2438 changed = true; 2439 } 2440 ath_dbg(common, CHAN_CTX, 2441 "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n", 2442 __func__, changed); 2443 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2444 spin_unlock_bh(&sc->chan_lock); 2445 2446 if (changed) 2447 ath_chanctx_set_next(sc, true); 2448 2449 mutex_unlock(&sc->mutex); 2450 } 2451 2452 void ath9k_fill_chanctx_ops(void) 2453 { 2454 if (!ath9k_is_chanctx_enabled()) 2455 return; 2456 2457 ath9k_ops.hw_scan = ath9k_hw_scan; 2458 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2459 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2460 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2461 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2462 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2463 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2464 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2465 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2466 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2467 } 2468 2469 #endif 2470 2471 struct ieee80211_ops ath9k_ops = { 2472 .tx = ath9k_tx, 2473 .start = ath9k_start, 2474 .stop = ath9k_stop, 2475 .add_interface = ath9k_add_interface, 2476 .change_interface = ath9k_change_interface, 2477 .remove_interface = ath9k_remove_interface, 2478 .config = ath9k_config, 2479 .configure_filter = ath9k_configure_filter, 2480 .sta_add = ath9k_sta_add, 2481 .sta_remove = ath9k_sta_remove, 2482 .sta_notify = ath9k_sta_notify, 2483 .conf_tx = ath9k_conf_tx, 2484 .bss_info_changed = ath9k_bss_info_changed, 2485 .set_key = ath9k_set_key, 2486 .get_tsf = ath9k_get_tsf, 2487 .set_tsf = ath9k_set_tsf, 2488 .reset_tsf = ath9k_reset_tsf, 2489 .ampdu_action = ath9k_ampdu_action, 2490 .get_survey = ath9k_get_survey, 2491 .rfkill_poll = ath9k_rfkill_poll_state, 2492 .set_coverage_class = ath9k_set_coverage_class, 2493 .flush = ath9k_flush, 2494 .tx_frames_pending = ath9k_tx_frames_pending, 2495 .tx_last_beacon = ath9k_tx_last_beacon, 2496 .release_buffered_frames = ath9k_release_buffered_frames, 2497 .get_stats = ath9k_get_stats, 2498 .set_antenna = ath9k_set_antenna, 2499 .get_antenna = ath9k_get_antenna, 2500 2501 #ifdef CONFIG_ATH9K_WOW 2502 .suspend = ath9k_suspend, 2503 .resume = ath9k_resume, 2504 .set_wakeup = ath9k_set_wakeup, 2505 #endif 2506 2507 #ifdef CONFIG_ATH9K_DEBUGFS 2508 .get_et_sset_count = ath9k_get_et_sset_count, 2509 .get_et_stats = ath9k_get_et_stats, 2510 .get_et_strings = ath9k_get_et_strings, 2511 #endif 2512 2513 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2514 .sta_add_debugfs = ath9k_sta_add_debugfs, 2515 #endif 2516 .sw_scan_start = ath9k_sw_scan_start, 2517 .sw_scan_complete = ath9k_sw_scan_complete, 2518 }; 2519