1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK | 135 PS_WAIT_FOR_ANI))) { 136 mode = ATH9K_PM_NETWORK_SLEEP; 137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 138 ath9k_btcoex_stop_gen_timer(sc); 139 } else { 140 goto unlock; 141 } 142 143 spin_lock(&common->cc_lock); 144 ath_hw_cycle_counters_update(common); 145 spin_unlock(&common->cc_lock); 146 147 ath9k_hw_setpower(sc->sc_ah, mode); 148 149 unlock: 150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 151 } 152 153 static void __ath_cancel_work(struct ath_softc *sc) 154 { 155 cancel_work_sync(&sc->paprd_work); 156 cancel_work_sync(&sc->hw_check_work); 157 cancel_delayed_work_sync(&sc->tx_complete_work); 158 cancel_delayed_work_sync(&sc->hw_pll_work); 159 160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 161 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 162 cancel_work_sync(&sc->mci_work); 163 #endif 164 } 165 166 static void ath_cancel_work(struct ath_softc *sc) 167 { 168 __ath_cancel_work(sc); 169 cancel_work_sync(&sc->hw_reset_work); 170 } 171 172 static void ath_restart_work(struct ath_softc *sc) 173 { 174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 175 176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 177 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 179 180 ath_start_rx_poll(sc, 3); 181 ath_start_ani(sc); 182 } 183 184 static bool ath_prepare_reset(struct ath_softc *sc) 185 { 186 struct ath_hw *ah = sc->sc_ah; 187 bool ret = true; 188 189 ieee80211_stop_queues(sc->hw); 190 191 sc->hw_busy_count = 0; 192 ath_stop_ani(sc); 193 del_timer_sync(&sc->rx_poll_timer); 194 195 ath9k_hw_disable_interrupts(ah); 196 197 if (!ath_drain_all_txq(sc)) 198 ret = false; 199 200 if (!ath_stoprecv(sc)) 201 ret = false; 202 203 return ret; 204 } 205 206 static bool ath_complete_reset(struct ath_softc *sc, bool start) 207 { 208 struct ath_hw *ah = sc->sc_ah; 209 struct ath_common *common = ath9k_hw_common(ah); 210 unsigned long flags; 211 int i; 212 213 if (ath_startrecv(sc) != 0) { 214 ath_err(common, "Unable to restart recv logic\n"); 215 return false; 216 } 217 218 ath9k_cmn_update_txpow(ah, sc->curtxpow, 219 sc->config.txpowlimit, &sc->curtxpow); 220 221 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 222 ath9k_hw_set_interrupts(ah); 223 ath9k_hw_enable_interrupts(ah); 224 225 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 226 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 227 goto work; 228 229 if (ah->opmode == NL80211_IFTYPE_STATION && 230 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 231 spin_lock_irqsave(&sc->sc_pm_lock, flags); 232 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 233 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 234 } else { 235 ath9k_set_beacon(sc); 236 } 237 work: 238 ath_restart_work(sc); 239 240 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 241 if (!ATH_TXQ_SETUP(sc, i)) 242 continue; 243 244 spin_lock_bh(&sc->tx.txq[i].axq_lock); 245 ath_txq_schedule(sc, &sc->tx.txq[i]); 246 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 247 } 248 } 249 250 ieee80211_wake_queues(sc->hw); 251 252 return true; 253 } 254 255 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 256 { 257 struct ath_hw *ah = sc->sc_ah; 258 struct ath_common *common = ath9k_hw_common(ah); 259 struct ath9k_hw_cal_data *caldata = NULL; 260 bool fastcc = true; 261 int r; 262 263 __ath_cancel_work(sc); 264 265 tasklet_disable(&sc->intr_tq); 266 spin_lock_bh(&sc->sc_pcu_lock); 267 268 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 269 fastcc = false; 270 caldata = &sc->caldata; 271 } 272 273 if (!hchan) { 274 fastcc = false; 275 hchan = ah->curchan; 276 } 277 278 if (!ath_prepare_reset(sc)) 279 fastcc = false; 280 281 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 282 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 283 284 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 285 if (r) { 286 ath_err(common, 287 "Unable to reset channel, reset status %d\n", r); 288 289 ath9k_hw_enable_interrupts(ah); 290 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 291 292 goto out; 293 } 294 295 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 296 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 297 ath9k_mci_set_txpower(sc, true, false); 298 299 if (!ath_complete_reset(sc, true)) 300 r = -EIO; 301 302 out: 303 spin_unlock_bh(&sc->sc_pcu_lock); 304 tasklet_enable(&sc->intr_tq); 305 306 return r; 307 } 308 309 310 /* 311 * Set/change channels. If the channel is really being changed, it's done 312 * by reseting the chip. To accomplish this we must first cleanup any pending 313 * DMA, then restart stuff. 314 */ 315 static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef) 316 { 317 struct ath_hw *ah = sc->sc_ah; 318 struct ath_common *common = ath9k_hw_common(ah); 319 struct ieee80211_hw *hw = sc->hw; 320 struct ath9k_channel *hchan; 321 struct ieee80211_channel *chan = chandef->chan; 322 unsigned long flags; 323 bool offchannel; 324 int pos = chan->hw_value; 325 int old_pos = -1; 326 int r; 327 328 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 329 return -EIO; 330 331 offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); 332 333 if (ah->curchan) 334 old_pos = ah->curchan - &ah->channels[0]; 335 336 ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n", 337 chan->center_freq, chandef->width); 338 339 /* update survey stats for the old channel before switching */ 340 spin_lock_irqsave(&common->cc_lock, flags); 341 ath_update_survey_stats(sc); 342 spin_unlock_irqrestore(&common->cc_lock, flags); 343 344 ath9k_cmn_get_channel(hw, ah, chandef); 345 346 /* 347 * If the operating channel changes, change the survey in-use flags 348 * along with it. 349 * Reset the survey data for the new channel, unless we're switching 350 * back to the operating channel from an off-channel operation. 351 */ 352 if (!offchannel && sc->cur_survey != &sc->survey[pos]) { 353 if (sc->cur_survey) 354 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 355 356 sc->cur_survey = &sc->survey[pos]; 357 358 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 359 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 360 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 361 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 362 } 363 364 hchan = &sc->sc_ah->channels[pos]; 365 r = ath_reset_internal(sc, hchan); 366 if (r) 367 return r; 368 369 /* 370 * The most recent snapshot of channel->noisefloor for the old 371 * channel is only available after the hardware reset. Copy it to 372 * the survey stats now. 373 */ 374 if (old_pos >= 0) 375 ath_update_survey_nf(sc, old_pos); 376 377 /* 378 * Enable radar pulse detection if on a DFS channel. Spectral 379 * scanning and radar detection can not be used concurrently. 380 */ 381 if (hw->conf.radar_enabled) { 382 u32 rxfilter; 383 384 /* set HW specific DFS configuration */ 385 ath9k_hw_set_radar_params(ah); 386 rxfilter = ath9k_hw_getrxfilter(ah); 387 rxfilter |= ATH9K_RX_FILTER_PHYRADAR | 388 ATH9K_RX_FILTER_PHYERR; 389 ath9k_hw_setrxfilter(ah, rxfilter); 390 ath_dbg(common, DFS, "DFS enabled at freq %d\n", 391 chan->center_freq); 392 } else { 393 /* perform spectral scan if requested. */ 394 if (test_bit(SC_OP_SCANNING, &sc->sc_flags) && 395 sc->spectral_mode == SPECTRAL_CHANSCAN) 396 ath9k_spectral_scan_trigger(hw); 397 } 398 399 return 0; 400 } 401 402 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 403 struct ieee80211_vif *vif) 404 { 405 struct ath_node *an; 406 an = (struct ath_node *)sta->drv_priv; 407 408 an->sc = sc; 409 an->sta = sta; 410 an->vif = vif; 411 412 ath_tx_node_init(sc, an); 413 414 if (sta->ht_cap.ht_supported) { 415 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 416 sta->ht_cap.ampdu_factor); 417 an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 418 } 419 } 420 421 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 422 { 423 struct ath_node *an = (struct ath_node *)sta->drv_priv; 424 ath_tx_node_cleanup(sc, an); 425 } 426 427 void ath9k_tasklet(unsigned long data) 428 { 429 struct ath_softc *sc = (struct ath_softc *)data; 430 struct ath_hw *ah = sc->sc_ah; 431 struct ath_common *common = ath9k_hw_common(ah); 432 enum ath_reset_type type; 433 unsigned long flags; 434 u32 status = sc->intrstatus; 435 u32 rxmask; 436 437 ath9k_ps_wakeup(sc); 438 spin_lock(&sc->sc_pcu_lock); 439 440 if ((status & ATH9K_INT_FATAL) || 441 (status & ATH9K_INT_BB_WATCHDOG)) { 442 443 if (status & ATH9K_INT_FATAL) 444 type = RESET_TYPE_FATAL_INT; 445 else 446 type = RESET_TYPE_BB_WATCHDOG; 447 448 ath9k_queue_reset(sc, type); 449 450 /* 451 * Increment the ref. counter here so that 452 * interrupts are enabled in the reset routine. 453 */ 454 atomic_inc(&ah->intr_ref_cnt); 455 ath_dbg(common, ANY, "FATAL: Skipping interrupts\n"); 456 goto out; 457 } 458 459 spin_lock_irqsave(&sc->sc_pm_lock, flags); 460 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 461 /* 462 * TSF sync does not look correct; remain awake to sync with 463 * the next Beacon. 464 */ 465 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 466 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 467 } 468 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 469 470 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 471 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 472 ATH9K_INT_RXORN); 473 else 474 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 475 476 if (status & rxmask) { 477 /* Check for high priority Rx first */ 478 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 479 (status & ATH9K_INT_RXHP)) 480 ath_rx_tasklet(sc, 0, true); 481 482 ath_rx_tasklet(sc, 0, false); 483 } 484 485 if (status & ATH9K_INT_TX) { 486 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 487 ath_tx_edma_tasklet(sc); 488 else 489 ath_tx_tasklet(sc); 490 } 491 492 ath9k_btcoex_handle_interrupt(sc, status); 493 494 /* re-enable hardware interrupt */ 495 ath9k_hw_enable_interrupts(ah); 496 out: 497 spin_unlock(&sc->sc_pcu_lock); 498 ath9k_ps_restore(sc); 499 } 500 501 irqreturn_t ath_isr(int irq, void *dev) 502 { 503 #define SCHED_INTR ( \ 504 ATH9K_INT_FATAL | \ 505 ATH9K_INT_BB_WATCHDOG | \ 506 ATH9K_INT_RXORN | \ 507 ATH9K_INT_RXEOL | \ 508 ATH9K_INT_RX | \ 509 ATH9K_INT_RXLP | \ 510 ATH9K_INT_RXHP | \ 511 ATH9K_INT_TX | \ 512 ATH9K_INT_BMISS | \ 513 ATH9K_INT_CST | \ 514 ATH9K_INT_TSFOOR | \ 515 ATH9K_INT_GENTIMER | \ 516 ATH9K_INT_MCI) 517 518 struct ath_softc *sc = dev; 519 struct ath_hw *ah = sc->sc_ah; 520 struct ath_common *common = ath9k_hw_common(ah); 521 enum ath9k_int status; 522 bool sched = false; 523 524 /* 525 * The hardware is not ready/present, don't 526 * touch anything. Note this can happen early 527 * on if the IRQ is shared. 528 */ 529 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 530 return IRQ_NONE; 531 532 /* shared irq, not for us */ 533 534 if (!ath9k_hw_intrpend(ah)) 535 return IRQ_NONE; 536 537 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 538 ath9k_hw_kill_interrupts(ah); 539 return IRQ_HANDLED; 540 } 541 542 /* 543 * Figure out the reason(s) for the interrupt. Note 544 * that the hal returns a pseudo-ISR that may include 545 * bits we haven't explicitly enabled so we mask the 546 * value to insure we only process bits we requested. 547 */ 548 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 549 status &= ah->imask; /* discard unasked-for bits */ 550 551 /* 552 * If there are no status bits set, then this interrupt was not 553 * for me (should have been caught above). 554 */ 555 if (!status) 556 return IRQ_NONE; 557 558 /* Cache the status */ 559 sc->intrstatus = status; 560 561 if (status & SCHED_INTR) 562 sched = true; 563 564 /* 565 * If a FATAL or RXORN interrupt is received, we have to reset the 566 * chip immediately. 567 */ 568 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 569 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 570 goto chip_reset; 571 572 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 573 (status & ATH9K_INT_BB_WATCHDOG)) { 574 575 spin_lock(&common->cc_lock); 576 ath_hw_cycle_counters_update(common); 577 ar9003_hw_bb_watchdog_dbg_info(ah); 578 spin_unlock(&common->cc_lock); 579 580 goto chip_reset; 581 } 582 #ifdef CONFIG_PM_SLEEP 583 if (status & ATH9K_INT_BMISS) { 584 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 585 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 586 atomic_inc(&sc->wow_got_bmiss_intr); 587 atomic_dec(&sc->wow_sleep_proc_intr); 588 } 589 } 590 #endif 591 if (status & ATH9K_INT_SWBA) 592 tasklet_schedule(&sc->bcon_tasklet); 593 594 if (status & ATH9K_INT_TXURN) 595 ath9k_hw_updatetxtriglevel(ah, true); 596 597 if (status & ATH9K_INT_RXEOL) { 598 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 599 ath9k_hw_set_interrupts(ah); 600 } 601 602 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 603 if (status & ATH9K_INT_TIM_TIMER) { 604 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 605 goto chip_reset; 606 /* Clear RxAbort bit so that we can 607 * receive frames */ 608 ath9k_setpower(sc, ATH9K_PM_AWAKE); 609 spin_lock(&sc->sc_pm_lock); 610 ath9k_hw_setrxabort(sc->sc_ah, 0); 611 sc->ps_flags |= PS_WAIT_FOR_BEACON; 612 spin_unlock(&sc->sc_pm_lock); 613 } 614 615 chip_reset: 616 617 ath_debug_stat_interrupt(sc, status); 618 619 if (sched) { 620 /* turn off every interrupt */ 621 ath9k_hw_disable_interrupts(ah); 622 tasklet_schedule(&sc->intr_tq); 623 } 624 625 return IRQ_HANDLED; 626 627 #undef SCHED_INTR 628 } 629 630 static int ath_reset(struct ath_softc *sc) 631 { 632 int r; 633 634 ath9k_ps_wakeup(sc); 635 r = ath_reset_internal(sc, NULL); 636 ath9k_ps_restore(sc); 637 638 return r; 639 } 640 641 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 642 { 643 #ifdef CONFIG_ATH9K_DEBUGFS 644 RESET_STAT_INC(sc, type); 645 #endif 646 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 647 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 648 } 649 650 void ath_reset_work(struct work_struct *work) 651 { 652 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 653 654 ath_reset(sc); 655 } 656 657 /**********************/ 658 /* mac80211 callbacks */ 659 /**********************/ 660 661 static int ath9k_start(struct ieee80211_hw *hw) 662 { 663 struct ath_softc *sc = hw->priv; 664 struct ath_hw *ah = sc->sc_ah; 665 struct ath_common *common = ath9k_hw_common(ah); 666 struct ieee80211_channel *curchan = hw->conf.chandef.chan; 667 struct ath9k_channel *init_channel; 668 int r; 669 670 ath_dbg(common, CONFIG, 671 "Starting driver with initial channel: %d MHz\n", 672 curchan->center_freq); 673 674 ath9k_ps_wakeup(sc); 675 mutex_lock(&sc->mutex); 676 677 init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 678 679 /* Reset SERDES registers */ 680 ath9k_hw_configpcipowersave(ah, false); 681 682 /* 683 * The basic interface to setting the hardware in a good 684 * state is ``reset''. On return the hardware is known to 685 * be powered up and with interrupts disabled. This must 686 * be followed by initialization of the appropriate bits 687 * and then setup of the interrupt mask. 688 */ 689 spin_lock_bh(&sc->sc_pcu_lock); 690 691 atomic_set(&ah->intr_ref_cnt, -1); 692 693 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 694 if (r) { 695 ath_err(common, 696 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 697 r, curchan->center_freq); 698 ah->reset_power_on = false; 699 } 700 701 /* Setup our intr mask. */ 702 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 703 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 704 ATH9K_INT_GLOBAL; 705 706 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 707 ah->imask |= ATH9K_INT_RXHP | 708 ATH9K_INT_RXLP | 709 ATH9K_INT_BB_WATCHDOG; 710 else 711 ah->imask |= ATH9K_INT_RX; 712 713 ah->imask |= ATH9K_INT_GTT; 714 715 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 716 ah->imask |= ATH9K_INT_CST; 717 718 ath_mci_enable(sc); 719 720 clear_bit(SC_OP_INVALID, &sc->sc_flags); 721 sc->sc_ah->is_monitoring = false; 722 723 if (!ath_complete_reset(sc, false)) 724 ah->reset_power_on = false; 725 726 if (ah->led_pin >= 0) { 727 ath9k_hw_cfg_output(ah, ah->led_pin, 728 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 729 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 730 } 731 732 /* 733 * Reset key cache to sane defaults (all entries cleared) instead of 734 * semi-random values after suspend/resume. 735 */ 736 ath9k_cmn_init_crypto(sc->sc_ah); 737 738 spin_unlock_bh(&sc->sc_pcu_lock); 739 740 mutex_unlock(&sc->mutex); 741 742 ath9k_ps_restore(sc); 743 744 return 0; 745 } 746 747 static void ath9k_tx(struct ieee80211_hw *hw, 748 struct ieee80211_tx_control *control, 749 struct sk_buff *skb) 750 { 751 struct ath_softc *sc = hw->priv; 752 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 753 struct ath_tx_control txctl; 754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 755 unsigned long flags; 756 757 if (sc->ps_enabled) { 758 /* 759 * mac80211 does not set PM field for normal data frames, so we 760 * need to update that based on the current PS mode. 761 */ 762 if (ieee80211_is_data(hdr->frame_control) && 763 !ieee80211_is_nullfunc(hdr->frame_control) && 764 !ieee80211_has_pm(hdr->frame_control)) { 765 ath_dbg(common, PS, 766 "Add PM=1 for a TX frame while in PS mode\n"); 767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 768 } 769 } 770 771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 772 /* 773 * We are using PS-Poll and mac80211 can request TX while in 774 * power save mode. Need to wake up hardware for the TX to be 775 * completed and if needed, also for RX of buffered frames. 776 */ 777 ath9k_ps_wakeup(sc); 778 spin_lock_irqsave(&sc->sc_pm_lock, flags); 779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 780 ath9k_hw_setrxabort(sc->sc_ah, 0); 781 if (ieee80211_is_pspoll(hdr->frame_control)) { 782 ath_dbg(common, PS, 783 "Sending PS-Poll to pick a buffered frame\n"); 784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 785 } else { 786 ath_dbg(common, PS, "Wake up to complete TX\n"); 787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 788 } 789 /* 790 * The actual restore operation will happen only after 791 * the ps_flags bit is cleared. We are just dropping 792 * the ps_usecount here. 793 */ 794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 795 ath9k_ps_restore(sc); 796 } 797 798 /* 799 * Cannot tx while the hardware is in full sleep, it first needs a full 800 * chip reset to recover from that 801 */ 802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 804 goto exit; 805 } 806 807 memset(&txctl, 0, sizeof(struct ath_tx_control)); 808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 809 txctl.sta = control->sta; 810 811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 812 813 if (ath_tx_start(hw, skb, &txctl) != 0) { 814 ath_dbg(common, XMIT, "TX failed\n"); 815 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 816 goto exit; 817 } 818 819 return; 820 exit: 821 ieee80211_free_txskb(hw, skb); 822 } 823 824 static void ath9k_stop(struct ieee80211_hw *hw) 825 { 826 struct ath_softc *sc = hw->priv; 827 struct ath_hw *ah = sc->sc_ah; 828 struct ath_common *common = ath9k_hw_common(ah); 829 bool prev_idle; 830 831 mutex_lock(&sc->mutex); 832 833 ath_cancel_work(sc); 834 del_timer_sync(&sc->rx_poll_timer); 835 836 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 837 ath_dbg(common, ANY, "Device not present\n"); 838 mutex_unlock(&sc->mutex); 839 return; 840 } 841 842 /* Ensure HW is awake when we try to shut it down. */ 843 ath9k_ps_wakeup(sc); 844 845 spin_lock_bh(&sc->sc_pcu_lock); 846 847 /* prevent tasklets to enable interrupts once we disable them */ 848 ah->imask &= ~ATH9K_INT_GLOBAL; 849 850 /* make sure h/w will not generate any interrupt 851 * before setting the invalid flag. */ 852 ath9k_hw_disable_interrupts(ah); 853 854 spin_unlock_bh(&sc->sc_pcu_lock); 855 856 /* we can now sync irq and kill any running tasklets, since we already 857 * disabled interrupts and not holding a spin lock */ 858 synchronize_irq(sc->irq); 859 tasklet_kill(&sc->intr_tq); 860 tasklet_kill(&sc->bcon_tasklet); 861 862 prev_idle = sc->ps_idle; 863 sc->ps_idle = true; 864 865 spin_lock_bh(&sc->sc_pcu_lock); 866 867 if (ah->led_pin >= 0) { 868 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 869 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 870 } 871 872 ath_prepare_reset(sc); 873 874 if (sc->rx.frag) { 875 dev_kfree_skb_any(sc->rx.frag); 876 sc->rx.frag = NULL; 877 } 878 879 if (!ah->curchan) 880 ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 881 882 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 883 ath9k_hw_phy_disable(ah); 884 885 ath9k_hw_configpcipowersave(ah, true); 886 887 spin_unlock_bh(&sc->sc_pcu_lock); 888 889 ath9k_ps_restore(sc); 890 891 set_bit(SC_OP_INVALID, &sc->sc_flags); 892 sc->ps_idle = prev_idle; 893 894 mutex_unlock(&sc->mutex); 895 896 ath_dbg(common, CONFIG, "Driver halt\n"); 897 } 898 899 static bool ath9k_uses_beacons(int type) 900 { 901 switch (type) { 902 case NL80211_IFTYPE_AP: 903 case NL80211_IFTYPE_ADHOC: 904 case NL80211_IFTYPE_MESH_POINT: 905 return true; 906 default: 907 return false; 908 } 909 } 910 911 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 912 { 913 struct ath9k_vif_iter_data *iter_data = data; 914 int i; 915 916 if (iter_data->has_hw_macaddr) { 917 for (i = 0; i < ETH_ALEN; i++) 918 iter_data->mask[i] &= 919 ~(iter_data->hw_macaddr[i] ^ mac[i]); 920 } else { 921 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 922 iter_data->has_hw_macaddr = true; 923 } 924 925 switch (vif->type) { 926 case NL80211_IFTYPE_AP: 927 iter_data->naps++; 928 break; 929 case NL80211_IFTYPE_STATION: 930 iter_data->nstations++; 931 break; 932 case NL80211_IFTYPE_ADHOC: 933 iter_data->nadhocs++; 934 break; 935 case NL80211_IFTYPE_MESH_POINT: 936 iter_data->nmeshes++; 937 break; 938 case NL80211_IFTYPE_WDS: 939 iter_data->nwds++; 940 break; 941 default: 942 break; 943 } 944 } 945 946 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 947 { 948 struct ath_softc *sc = data; 949 struct ath_vif *avp = (void *)vif->drv_priv; 950 951 if (vif->type != NL80211_IFTYPE_STATION) 952 return; 953 954 if (avp->primary_sta_vif) 955 ath9k_set_assoc_state(sc, vif); 956 } 957 958 /* Called with sc->mutex held. */ 959 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 960 struct ieee80211_vif *vif, 961 struct ath9k_vif_iter_data *iter_data) 962 { 963 struct ath_softc *sc = hw->priv; 964 struct ath_hw *ah = sc->sc_ah; 965 struct ath_common *common = ath9k_hw_common(ah); 966 967 /* 968 * Pick the MAC address of the first interface as the new hardware 969 * MAC address. The hardware will use it together with the BSSID mask 970 * when matching addresses. 971 */ 972 memset(iter_data, 0, sizeof(*iter_data)); 973 memset(&iter_data->mask, 0xff, ETH_ALEN); 974 975 if (vif) 976 ath9k_vif_iter(iter_data, vif->addr, vif); 977 978 /* Get list of all active MAC addresses */ 979 ieee80211_iterate_active_interfaces_atomic( 980 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 981 ath9k_vif_iter, iter_data); 982 983 memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN); 984 } 985 986 /* Called with sc->mutex held. */ 987 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 988 struct ieee80211_vif *vif) 989 { 990 struct ath_softc *sc = hw->priv; 991 struct ath_hw *ah = sc->sc_ah; 992 struct ath_common *common = ath9k_hw_common(ah); 993 struct ath9k_vif_iter_data iter_data; 994 enum nl80211_iftype old_opmode = ah->opmode; 995 996 ath9k_calculate_iter_data(hw, vif, &iter_data); 997 998 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 999 ath_hw_setbssidmask(common); 1000 1001 if (iter_data.naps > 0) { 1002 ath9k_hw_set_tsfadjust(ah, true); 1003 ah->opmode = NL80211_IFTYPE_AP; 1004 } else { 1005 ath9k_hw_set_tsfadjust(ah, false); 1006 1007 if (iter_data.nmeshes) 1008 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1009 else if (iter_data.nwds) 1010 ah->opmode = NL80211_IFTYPE_AP; 1011 else if (iter_data.nadhocs) 1012 ah->opmode = NL80211_IFTYPE_ADHOC; 1013 else 1014 ah->opmode = NL80211_IFTYPE_STATION; 1015 } 1016 1017 ath9k_hw_setopmode(ah); 1018 1019 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1020 ah->imask |= ATH9K_INT_TSFOOR; 1021 else 1022 ah->imask &= ~ATH9K_INT_TSFOOR; 1023 1024 ath9k_hw_set_interrupts(ah); 1025 1026 /* 1027 * If we are changing the opmode to STATION, 1028 * a beacon sync needs to be done. 1029 */ 1030 if (ah->opmode == NL80211_IFTYPE_STATION && 1031 old_opmode == NL80211_IFTYPE_AP && 1032 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 1033 ieee80211_iterate_active_interfaces_atomic( 1034 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1035 ath9k_sta_vif_iter, sc); 1036 } 1037 } 1038 1039 static int ath9k_add_interface(struct ieee80211_hw *hw, 1040 struct ieee80211_vif *vif) 1041 { 1042 struct ath_softc *sc = hw->priv; 1043 struct ath_hw *ah = sc->sc_ah; 1044 struct ath_common *common = ath9k_hw_common(ah); 1045 struct ath_vif *avp = (void *)vif->drv_priv; 1046 struct ath_node *an = &avp->mcast_node; 1047 1048 mutex_lock(&sc->mutex); 1049 1050 if (config_enabled(CONFIG_ATH9K_TX99)) { 1051 if (sc->nvifs >= 1) { 1052 mutex_unlock(&sc->mutex); 1053 return -EOPNOTSUPP; 1054 } 1055 sc->tx99_vif = vif; 1056 } 1057 1058 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1059 sc->nvifs++; 1060 1061 ath9k_ps_wakeup(sc); 1062 ath9k_calculate_summary_state(hw, vif); 1063 ath9k_ps_restore(sc); 1064 1065 if (ath9k_uses_beacons(vif->type)) 1066 ath9k_beacon_assign_slot(sc, vif); 1067 1068 an->sc = sc; 1069 an->sta = NULL; 1070 an->vif = vif; 1071 an->no_ps_filter = true; 1072 ath_tx_node_init(sc, an); 1073 1074 mutex_unlock(&sc->mutex); 1075 return 0; 1076 } 1077 1078 static int ath9k_change_interface(struct ieee80211_hw *hw, 1079 struct ieee80211_vif *vif, 1080 enum nl80211_iftype new_type, 1081 bool p2p) 1082 { 1083 struct ath_softc *sc = hw->priv; 1084 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1085 1086 mutex_lock(&sc->mutex); 1087 1088 if (config_enabled(CONFIG_ATH9K_TX99)) { 1089 mutex_unlock(&sc->mutex); 1090 return -EOPNOTSUPP; 1091 } 1092 1093 ath_dbg(common, CONFIG, "Change Interface\n"); 1094 1095 if (ath9k_uses_beacons(vif->type)) 1096 ath9k_beacon_remove_slot(sc, vif); 1097 1098 vif->type = new_type; 1099 vif->p2p = p2p; 1100 1101 ath9k_ps_wakeup(sc); 1102 ath9k_calculate_summary_state(hw, vif); 1103 ath9k_ps_restore(sc); 1104 1105 if (ath9k_uses_beacons(vif->type)) 1106 ath9k_beacon_assign_slot(sc, vif); 1107 1108 mutex_unlock(&sc->mutex); 1109 return 0; 1110 } 1111 1112 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1113 struct ieee80211_vif *vif) 1114 { 1115 struct ath_softc *sc = hw->priv; 1116 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1117 struct ath_vif *avp = (void *)vif->drv_priv; 1118 1119 ath_dbg(common, CONFIG, "Detach Interface\n"); 1120 1121 mutex_lock(&sc->mutex); 1122 1123 sc->nvifs--; 1124 sc->tx99_vif = NULL; 1125 1126 if (ath9k_uses_beacons(vif->type)) 1127 ath9k_beacon_remove_slot(sc, vif); 1128 1129 if (sc->csa_vif == vif) 1130 sc->csa_vif = NULL; 1131 1132 ath9k_ps_wakeup(sc); 1133 ath9k_calculate_summary_state(hw, NULL); 1134 ath9k_ps_restore(sc); 1135 1136 ath_tx_node_cleanup(sc, &avp->mcast_node); 1137 1138 mutex_unlock(&sc->mutex); 1139 } 1140 1141 static void ath9k_enable_ps(struct ath_softc *sc) 1142 { 1143 struct ath_hw *ah = sc->sc_ah; 1144 struct ath_common *common = ath9k_hw_common(ah); 1145 1146 if (config_enabled(CONFIG_ATH9K_TX99)) 1147 return; 1148 1149 sc->ps_enabled = true; 1150 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1151 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1152 ah->imask |= ATH9K_INT_TIM_TIMER; 1153 ath9k_hw_set_interrupts(ah); 1154 } 1155 ath9k_hw_setrxabort(ah, 1); 1156 } 1157 ath_dbg(common, PS, "PowerSave enabled\n"); 1158 } 1159 1160 static void ath9k_disable_ps(struct ath_softc *sc) 1161 { 1162 struct ath_hw *ah = sc->sc_ah; 1163 struct ath_common *common = ath9k_hw_common(ah); 1164 1165 if (config_enabled(CONFIG_ATH9K_TX99)) 1166 return; 1167 1168 sc->ps_enabled = false; 1169 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1170 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1171 ath9k_hw_setrxabort(ah, 0); 1172 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1173 PS_WAIT_FOR_CAB | 1174 PS_WAIT_FOR_PSPOLL_DATA | 1175 PS_WAIT_FOR_TX_ACK); 1176 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1177 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1178 ath9k_hw_set_interrupts(ah); 1179 } 1180 } 1181 ath_dbg(common, PS, "PowerSave disabled\n"); 1182 } 1183 1184 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1185 { 1186 struct ath_softc *sc = hw->priv; 1187 struct ath_hw *ah = sc->sc_ah; 1188 struct ath_common *common = ath9k_hw_common(ah); 1189 u32 rxfilter; 1190 1191 if (config_enabled(CONFIG_ATH9K_TX99)) 1192 return; 1193 1194 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1195 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1196 return; 1197 } 1198 1199 ath9k_ps_wakeup(sc); 1200 rxfilter = ath9k_hw_getrxfilter(ah); 1201 ath9k_hw_setrxfilter(ah, rxfilter | 1202 ATH9K_RX_FILTER_PHYRADAR | 1203 ATH9K_RX_FILTER_PHYERR); 1204 1205 /* TODO: usually this should not be neccesary, but for some reason 1206 * (or in some mode?) the trigger must be called after the 1207 * configuration, otherwise the register will have its values reset 1208 * (on my ar9220 to value 0x01002310) 1209 */ 1210 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1211 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1212 ath9k_ps_restore(sc); 1213 } 1214 1215 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1216 enum spectral_mode spectral_mode) 1217 { 1218 struct ath_softc *sc = hw->priv; 1219 struct ath_hw *ah = sc->sc_ah; 1220 struct ath_common *common = ath9k_hw_common(ah); 1221 1222 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1223 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1224 return -1; 1225 } 1226 1227 switch (spectral_mode) { 1228 case SPECTRAL_DISABLED: 1229 sc->spec_config.enabled = 0; 1230 break; 1231 case SPECTRAL_BACKGROUND: 1232 /* send endless samples. 1233 * TODO: is this really useful for "background"? 1234 */ 1235 sc->spec_config.endless = 1; 1236 sc->spec_config.enabled = 1; 1237 break; 1238 case SPECTRAL_CHANSCAN: 1239 case SPECTRAL_MANUAL: 1240 sc->spec_config.endless = 0; 1241 sc->spec_config.enabled = 1; 1242 break; 1243 default: 1244 return -1; 1245 } 1246 1247 ath9k_ps_wakeup(sc); 1248 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1249 ath9k_ps_restore(sc); 1250 1251 sc->spectral_mode = spectral_mode; 1252 1253 return 0; 1254 } 1255 1256 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1257 { 1258 struct ath_softc *sc = hw->priv; 1259 struct ath_hw *ah = sc->sc_ah; 1260 struct ath_common *common = ath9k_hw_common(ah); 1261 struct ieee80211_conf *conf = &hw->conf; 1262 bool reset_channel = false; 1263 1264 ath9k_ps_wakeup(sc); 1265 mutex_lock(&sc->mutex); 1266 1267 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1268 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1269 if (sc->ps_idle) { 1270 ath_cancel_work(sc); 1271 ath9k_stop_btcoex(sc); 1272 } else { 1273 ath9k_start_btcoex(sc); 1274 /* 1275 * The chip needs a reset to properly wake up from 1276 * full sleep 1277 */ 1278 reset_channel = ah->chip_fullsleep; 1279 } 1280 } 1281 1282 /* 1283 * We just prepare to enable PS. We have to wait until our AP has 1284 * ACK'd our null data frame to disable RX otherwise we'll ignore 1285 * those ACKs and end up retransmitting the same null data frames. 1286 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1287 */ 1288 if (changed & IEEE80211_CONF_CHANGE_PS) { 1289 unsigned long flags; 1290 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1291 if (conf->flags & IEEE80211_CONF_PS) 1292 ath9k_enable_ps(sc); 1293 else 1294 ath9k_disable_ps(sc); 1295 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1296 } 1297 1298 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1299 if (conf->flags & IEEE80211_CONF_MONITOR) { 1300 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1301 sc->sc_ah->is_monitoring = true; 1302 } else { 1303 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1304 sc->sc_ah->is_monitoring = false; 1305 } 1306 } 1307 1308 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1309 if (ath_set_channel(sc, &hw->conf.chandef) < 0) { 1310 ath_err(common, "Unable to set channel\n"); 1311 mutex_unlock(&sc->mutex); 1312 ath9k_ps_restore(sc); 1313 return -EINVAL; 1314 } 1315 } 1316 1317 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1318 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1319 sc->config.txpowlimit = 2 * conf->power_level; 1320 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1321 sc->config.txpowlimit, &sc->curtxpow); 1322 } 1323 1324 mutex_unlock(&sc->mutex); 1325 ath9k_ps_restore(sc); 1326 1327 return 0; 1328 } 1329 1330 #define SUPPORTED_FILTERS \ 1331 (FIF_PROMISC_IN_BSS | \ 1332 FIF_ALLMULTI | \ 1333 FIF_CONTROL | \ 1334 FIF_PSPOLL | \ 1335 FIF_OTHER_BSS | \ 1336 FIF_BCN_PRBRESP_PROMISC | \ 1337 FIF_PROBE_REQ | \ 1338 FIF_FCSFAIL) 1339 1340 /* FIXME: sc->sc_full_reset ? */ 1341 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1342 unsigned int changed_flags, 1343 unsigned int *total_flags, 1344 u64 multicast) 1345 { 1346 struct ath_softc *sc = hw->priv; 1347 u32 rfilt; 1348 1349 changed_flags &= SUPPORTED_FILTERS; 1350 *total_flags &= SUPPORTED_FILTERS; 1351 1352 sc->rx.rxfilter = *total_flags; 1353 ath9k_ps_wakeup(sc); 1354 rfilt = ath_calcrxfilter(sc); 1355 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1356 ath9k_ps_restore(sc); 1357 1358 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1359 rfilt); 1360 } 1361 1362 static int ath9k_sta_add(struct ieee80211_hw *hw, 1363 struct ieee80211_vif *vif, 1364 struct ieee80211_sta *sta) 1365 { 1366 struct ath_softc *sc = hw->priv; 1367 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1368 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1369 struct ieee80211_key_conf ps_key = { }; 1370 int key; 1371 1372 ath_node_attach(sc, sta, vif); 1373 1374 if (vif->type != NL80211_IFTYPE_AP && 1375 vif->type != NL80211_IFTYPE_AP_VLAN) 1376 return 0; 1377 1378 key = ath_key_config(common, vif, sta, &ps_key); 1379 if (key > 0) 1380 an->ps_key = key; 1381 1382 return 0; 1383 } 1384 1385 static void ath9k_del_ps_key(struct ath_softc *sc, 1386 struct ieee80211_vif *vif, 1387 struct ieee80211_sta *sta) 1388 { 1389 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1390 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1391 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1392 1393 if (!an->ps_key) 1394 return; 1395 1396 ath_key_delete(common, &ps_key); 1397 an->ps_key = 0; 1398 } 1399 1400 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1401 struct ieee80211_vif *vif, 1402 struct ieee80211_sta *sta) 1403 { 1404 struct ath_softc *sc = hw->priv; 1405 1406 ath9k_del_ps_key(sc, vif, sta); 1407 ath_node_detach(sc, sta); 1408 1409 return 0; 1410 } 1411 1412 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1413 struct ieee80211_vif *vif, 1414 enum sta_notify_cmd cmd, 1415 struct ieee80211_sta *sta) 1416 { 1417 struct ath_softc *sc = hw->priv; 1418 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1419 1420 switch (cmd) { 1421 case STA_NOTIFY_SLEEP: 1422 an->sleeping = true; 1423 ath_tx_aggr_sleep(sta, sc, an); 1424 break; 1425 case STA_NOTIFY_AWAKE: 1426 an->sleeping = false; 1427 ath_tx_aggr_wakeup(sc, an); 1428 break; 1429 } 1430 } 1431 1432 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1433 struct ieee80211_vif *vif, u16 queue, 1434 const struct ieee80211_tx_queue_params *params) 1435 { 1436 struct ath_softc *sc = hw->priv; 1437 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1438 struct ath_txq *txq; 1439 struct ath9k_tx_queue_info qi; 1440 int ret = 0; 1441 1442 if (queue >= IEEE80211_NUM_ACS) 1443 return 0; 1444 1445 txq = sc->tx.txq_map[queue]; 1446 1447 ath9k_ps_wakeup(sc); 1448 mutex_lock(&sc->mutex); 1449 1450 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1451 1452 qi.tqi_aifs = params->aifs; 1453 qi.tqi_cwmin = params->cw_min; 1454 qi.tqi_cwmax = params->cw_max; 1455 qi.tqi_burstTime = params->txop * 32; 1456 1457 ath_dbg(common, CONFIG, 1458 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1459 queue, txq->axq_qnum, params->aifs, params->cw_min, 1460 params->cw_max, params->txop); 1461 1462 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1463 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1464 if (ret) 1465 ath_err(common, "TXQ Update failed\n"); 1466 1467 mutex_unlock(&sc->mutex); 1468 ath9k_ps_restore(sc); 1469 1470 return ret; 1471 } 1472 1473 static int ath9k_set_key(struct ieee80211_hw *hw, 1474 enum set_key_cmd cmd, 1475 struct ieee80211_vif *vif, 1476 struct ieee80211_sta *sta, 1477 struct ieee80211_key_conf *key) 1478 { 1479 struct ath_softc *sc = hw->priv; 1480 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1481 int ret = 0; 1482 1483 if (ath9k_modparam_nohwcrypt) 1484 return -ENOSPC; 1485 1486 if ((vif->type == NL80211_IFTYPE_ADHOC || 1487 vif->type == NL80211_IFTYPE_MESH_POINT) && 1488 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1489 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1490 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1491 /* 1492 * For now, disable hw crypto for the RSN IBSS group keys. This 1493 * could be optimized in the future to use a modified key cache 1494 * design to support per-STA RX GTK, but until that gets 1495 * implemented, use of software crypto for group addressed 1496 * frames is a acceptable to allow RSN IBSS to be used. 1497 */ 1498 return -EOPNOTSUPP; 1499 } 1500 1501 mutex_lock(&sc->mutex); 1502 ath9k_ps_wakeup(sc); 1503 ath_dbg(common, CONFIG, "Set HW Key\n"); 1504 1505 switch (cmd) { 1506 case SET_KEY: 1507 if (sta) 1508 ath9k_del_ps_key(sc, vif, sta); 1509 1510 ret = ath_key_config(common, vif, sta, key); 1511 if (ret >= 0) { 1512 key->hw_key_idx = ret; 1513 /* push IV and Michael MIC generation to stack */ 1514 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1515 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1516 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1517 if (sc->sc_ah->sw_mgmt_crypto && 1518 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1519 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1520 ret = 0; 1521 } 1522 break; 1523 case DISABLE_KEY: 1524 ath_key_delete(common, key); 1525 break; 1526 default: 1527 ret = -EINVAL; 1528 } 1529 1530 ath9k_ps_restore(sc); 1531 mutex_unlock(&sc->mutex); 1532 1533 return ret; 1534 } 1535 1536 static void ath9k_set_assoc_state(struct ath_softc *sc, 1537 struct ieee80211_vif *vif) 1538 { 1539 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1540 struct ath_vif *avp = (void *)vif->drv_priv; 1541 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1542 unsigned long flags; 1543 1544 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1545 avp->primary_sta_vif = true; 1546 1547 /* 1548 * Set the AID, BSSID and do beacon-sync only when 1549 * the HW opmode is STATION. 1550 * 1551 * But the primary bit is set above in any case. 1552 */ 1553 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1554 return; 1555 1556 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1557 common->curaid = bss_conf->aid; 1558 ath9k_hw_write_associd(sc->sc_ah); 1559 1560 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1561 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1562 1563 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1564 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1565 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1566 1567 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1568 ath9k_mci_update_wlan_channels(sc, false); 1569 1570 ath_dbg(common, CONFIG, 1571 "Primary Station interface: %pM, BSSID: %pM\n", 1572 vif->addr, common->curbssid); 1573 } 1574 1575 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1576 { 1577 struct ath_softc *sc = data; 1578 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1579 1580 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1581 return; 1582 1583 if (bss_conf->assoc) 1584 ath9k_set_assoc_state(sc, vif); 1585 } 1586 1587 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1588 struct ieee80211_vif *vif, 1589 struct ieee80211_bss_conf *bss_conf, 1590 u32 changed) 1591 { 1592 #define CHECK_ANI \ 1593 (BSS_CHANGED_ASSOC | \ 1594 BSS_CHANGED_IBSS | \ 1595 BSS_CHANGED_BEACON_ENABLED) 1596 1597 struct ath_softc *sc = hw->priv; 1598 struct ath_hw *ah = sc->sc_ah; 1599 struct ath_common *common = ath9k_hw_common(ah); 1600 struct ath_vif *avp = (void *)vif->drv_priv; 1601 int slottime; 1602 1603 ath9k_ps_wakeup(sc); 1604 mutex_lock(&sc->mutex); 1605 1606 if (changed & BSS_CHANGED_ASSOC) { 1607 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1608 bss_conf->bssid, bss_conf->assoc); 1609 1610 if (avp->primary_sta_vif && !bss_conf->assoc) { 1611 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1612 avp->primary_sta_vif = false; 1613 1614 if (ah->opmode == NL80211_IFTYPE_STATION) 1615 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1616 } 1617 1618 ieee80211_iterate_active_interfaces_atomic( 1619 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1620 ath9k_bss_assoc_iter, sc); 1621 1622 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1623 ah->opmode == NL80211_IFTYPE_STATION) { 1624 memset(common->curbssid, 0, ETH_ALEN); 1625 common->curaid = 0; 1626 ath9k_hw_write_associd(sc->sc_ah); 1627 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1628 ath9k_mci_update_wlan_channels(sc, true); 1629 } 1630 } 1631 1632 if (changed & BSS_CHANGED_IBSS) { 1633 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1634 common->curaid = bss_conf->aid; 1635 ath9k_hw_write_associd(sc->sc_ah); 1636 } 1637 1638 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1639 (changed & BSS_CHANGED_BEACON_INT)) { 1640 if (ah->opmode == NL80211_IFTYPE_AP && 1641 bss_conf->enable_beacon) 1642 ath9k_set_tsfadjust(sc, vif); 1643 if (ath9k_allow_beacon_config(sc, vif)) 1644 ath9k_beacon_config(sc, vif, changed); 1645 } 1646 1647 if (changed & BSS_CHANGED_ERP_SLOT) { 1648 if (bss_conf->use_short_slot) 1649 slottime = 9; 1650 else 1651 slottime = 20; 1652 if (vif->type == NL80211_IFTYPE_AP) { 1653 /* 1654 * Defer update, so that connected stations can adjust 1655 * their settings at the same time. 1656 * See beacon.c for more details 1657 */ 1658 sc->beacon.slottime = slottime; 1659 sc->beacon.updateslot = UPDATE; 1660 } else { 1661 ah->slottime = slottime; 1662 ath9k_hw_init_global_settings(ah); 1663 } 1664 } 1665 1666 if (changed & CHECK_ANI) 1667 ath_check_ani(sc); 1668 1669 mutex_unlock(&sc->mutex); 1670 ath9k_ps_restore(sc); 1671 1672 #undef CHECK_ANI 1673 } 1674 1675 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1676 { 1677 struct ath_softc *sc = hw->priv; 1678 u64 tsf; 1679 1680 mutex_lock(&sc->mutex); 1681 ath9k_ps_wakeup(sc); 1682 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1683 ath9k_ps_restore(sc); 1684 mutex_unlock(&sc->mutex); 1685 1686 return tsf; 1687 } 1688 1689 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1690 struct ieee80211_vif *vif, 1691 u64 tsf) 1692 { 1693 struct ath_softc *sc = hw->priv; 1694 1695 mutex_lock(&sc->mutex); 1696 ath9k_ps_wakeup(sc); 1697 ath9k_hw_settsf64(sc->sc_ah, tsf); 1698 ath9k_ps_restore(sc); 1699 mutex_unlock(&sc->mutex); 1700 } 1701 1702 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1703 { 1704 struct ath_softc *sc = hw->priv; 1705 1706 mutex_lock(&sc->mutex); 1707 1708 ath9k_ps_wakeup(sc); 1709 ath9k_hw_reset_tsf(sc->sc_ah); 1710 ath9k_ps_restore(sc); 1711 1712 mutex_unlock(&sc->mutex); 1713 } 1714 1715 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1716 struct ieee80211_vif *vif, 1717 enum ieee80211_ampdu_mlme_action action, 1718 struct ieee80211_sta *sta, 1719 u16 tid, u16 *ssn, u8 buf_size) 1720 { 1721 struct ath_softc *sc = hw->priv; 1722 bool flush = false; 1723 int ret = 0; 1724 1725 mutex_lock(&sc->mutex); 1726 1727 switch (action) { 1728 case IEEE80211_AMPDU_RX_START: 1729 break; 1730 case IEEE80211_AMPDU_RX_STOP: 1731 break; 1732 case IEEE80211_AMPDU_TX_START: 1733 ath9k_ps_wakeup(sc); 1734 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1735 if (!ret) 1736 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1737 ath9k_ps_restore(sc); 1738 break; 1739 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1740 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1741 flush = true; 1742 case IEEE80211_AMPDU_TX_STOP_CONT: 1743 ath9k_ps_wakeup(sc); 1744 ath_tx_aggr_stop(sc, sta, tid); 1745 if (!flush) 1746 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1747 ath9k_ps_restore(sc); 1748 break; 1749 case IEEE80211_AMPDU_TX_OPERATIONAL: 1750 ath9k_ps_wakeup(sc); 1751 ath_tx_aggr_resume(sc, sta, tid); 1752 ath9k_ps_restore(sc); 1753 break; 1754 default: 1755 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1756 } 1757 1758 mutex_unlock(&sc->mutex); 1759 1760 return ret; 1761 } 1762 1763 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1764 struct survey_info *survey) 1765 { 1766 struct ath_softc *sc = hw->priv; 1767 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1768 struct ieee80211_supported_band *sband; 1769 struct ieee80211_channel *chan; 1770 unsigned long flags; 1771 int pos; 1772 1773 if (config_enabled(CONFIG_ATH9K_TX99)) 1774 return -EOPNOTSUPP; 1775 1776 spin_lock_irqsave(&common->cc_lock, flags); 1777 if (idx == 0) 1778 ath_update_survey_stats(sc); 1779 1780 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1781 if (sband && idx >= sband->n_channels) { 1782 idx -= sband->n_channels; 1783 sband = NULL; 1784 } 1785 1786 if (!sband) 1787 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1788 1789 if (!sband || idx >= sband->n_channels) { 1790 spin_unlock_irqrestore(&common->cc_lock, flags); 1791 return -ENOENT; 1792 } 1793 1794 chan = &sband->channels[idx]; 1795 pos = chan->hw_value; 1796 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1797 survey->channel = chan; 1798 spin_unlock_irqrestore(&common->cc_lock, flags); 1799 1800 return 0; 1801 } 1802 1803 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1804 { 1805 struct ath_softc *sc = hw->priv; 1806 struct ath_hw *ah = sc->sc_ah; 1807 1808 if (config_enabled(CONFIG_ATH9K_TX99)) 1809 return; 1810 1811 mutex_lock(&sc->mutex); 1812 ah->coverage_class = coverage_class; 1813 1814 ath9k_ps_wakeup(sc); 1815 ath9k_hw_init_global_settings(ah); 1816 ath9k_ps_restore(sc); 1817 1818 mutex_unlock(&sc->mutex); 1819 } 1820 1821 static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1822 { 1823 struct ath_softc *sc = hw->priv; 1824 struct ath_hw *ah = sc->sc_ah; 1825 struct ath_common *common = ath9k_hw_common(ah); 1826 int timeout = 200; /* ms */ 1827 int i, j; 1828 bool drain_txq; 1829 1830 mutex_lock(&sc->mutex); 1831 cancel_delayed_work_sync(&sc->tx_complete_work); 1832 1833 if (ah->ah_flags & AH_UNPLUGGED) { 1834 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1835 mutex_unlock(&sc->mutex); 1836 return; 1837 } 1838 1839 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1840 ath_dbg(common, ANY, "Device not present\n"); 1841 mutex_unlock(&sc->mutex); 1842 return; 1843 } 1844 1845 for (j = 0; j < timeout; j++) { 1846 bool npend = false; 1847 1848 if (j) 1849 usleep_range(1000, 2000); 1850 1851 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1852 if (!ATH_TXQ_SETUP(sc, i)) 1853 continue; 1854 1855 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1856 1857 if (npend) 1858 break; 1859 } 1860 1861 if (!npend) 1862 break; 1863 } 1864 1865 if (drop) { 1866 ath9k_ps_wakeup(sc); 1867 spin_lock_bh(&sc->sc_pcu_lock); 1868 drain_txq = ath_drain_all_txq(sc); 1869 spin_unlock_bh(&sc->sc_pcu_lock); 1870 1871 if (!drain_txq) 1872 ath_reset(sc); 1873 1874 ath9k_ps_restore(sc); 1875 ieee80211_wake_queues(hw); 1876 } 1877 1878 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1879 mutex_unlock(&sc->mutex); 1880 } 1881 1882 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1883 { 1884 struct ath_softc *sc = hw->priv; 1885 int i; 1886 1887 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1888 if (!ATH_TXQ_SETUP(sc, i)) 1889 continue; 1890 1891 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1892 return true; 1893 } 1894 return false; 1895 } 1896 1897 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1898 { 1899 struct ath_softc *sc = hw->priv; 1900 struct ath_hw *ah = sc->sc_ah; 1901 struct ieee80211_vif *vif; 1902 struct ath_vif *avp; 1903 struct ath_buf *bf; 1904 struct ath_tx_status ts; 1905 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1906 int status; 1907 1908 vif = sc->beacon.bslot[0]; 1909 if (!vif) 1910 return 0; 1911 1912 if (!vif->bss_conf.enable_beacon) 1913 return 0; 1914 1915 avp = (void *)vif->drv_priv; 1916 1917 if (!sc->beacon.tx_processed && !edma) { 1918 tasklet_disable(&sc->bcon_tasklet); 1919 1920 bf = avp->av_bcbuf; 1921 if (!bf || !bf->bf_mpdu) 1922 goto skip; 1923 1924 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1925 if (status == -EINPROGRESS) 1926 goto skip; 1927 1928 sc->beacon.tx_processed = true; 1929 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1930 1931 skip: 1932 tasklet_enable(&sc->bcon_tasklet); 1933 } 1934 1935 return sc->beacon.tx_last; 1936 } 1937 1938 static int ath9k_get_stats(struct ieee80211_hw *hw, 1939 struct ieee80211_low_level_stats *stats) 1940 { 1941 struct ath_softc *sc = hw->priv; 1942 struct ath_hw *ah = sc->sc_ah; 1943 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1944 1945 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1946 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1947 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1948 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1949 return 0; 1950 } 1951 1952 static u32 fill_chainmask(u32 cap, u32 new) 1953 { 1954 u32 filled = 0; 1955 int i; 1956 1957 for (i = 0; cap && new; i++, cap >>= 1) { 1958 if (!(cap & BIT(0))) 1959 continue; 1960 1961 if (new & BIT(0)) 1962 filled |= BIT(i); 1963 1964 new >>= 1; 1965 } 1966 1967 return filled; 1968 } 1969 1970 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1971 { 1972 if (AR_SREV_9300_20_OR_LATER(ah)) 1973 return true; 1974 1975 switch (val & 0x7) { 1976 case 0x1: 1977 case 0x3: 1978 case 0x7: 1979 return true; 1980 case 0x2: 1981 return (ah->caps.rx_chainmask == 1); 1982 default: 1983 return false; 1984 } 1985 } 1986 1987 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1988 { 1989 struct ath_softc *sc = hw->priv; 1990 struct ath_hw *ah = sc->sc_ah; 1991 1992 if (ah->caps.rx_chainmask != 1) 1993 rx_ant |= tx_ant; 1994 1995 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1996 return -EINVAL; 1997 1998 sc->ant_rx = rx_ant; 1999 sc->ant_tx = tx_ant; 2000 2001 if (ah->caps.rx_chainmask == 1) 2002 return 0; 2003 2004 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2005 if (AR_SREV_9100(ah)) 2006 ah->rxchainmask = 0x7; 2007 else 2008 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2009 2010 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2011 ath9k_reload_chainmask_settings(sc); 2012 2013 return 0; 2014 } 2015 2016 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2017 { 2018 struct ath_softc *sc = hw->priv; 2019 2020 *tx_ant = sc->ant_tx; 2021 *rx_ant = sc->ant_rx; 2022 return 0; 2023 } 2024 2025 #ifdef CONFIG_PM_SLEEP 2026 2027 static void ath9k_wow_map_triggers(struct ath_softc *sc, 2028 struct cfg80211_wowlan *wowlan, 2029 u32 *wow_triggers) 2030 { 2031 if (wowlan->disconnect) 2032 *wow_triggers |= AH_WOW_LINK_CHANGE | 2033 AH_WOW_BEACON_MISS; 2034 if (wowlan->magic_pkt) 2035 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 2036 2037 if (wowlan->n_patterns) 2038 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 2039 2040 sc->wow_enabled = *wow_triggers; 2041 2042 } 2043 2044 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 2045 { 2046 struct ath_hw *ah = sc->sc_ah; 2047 struct ath_common *common = ath9k_hw_common(ah); 2048 int pattern_count = 0; 2049 int i, byte_cnt; 2050 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 2051 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 2052 2053 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 2054 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 2055 2056 /* 2057 * Create Dissassociate / Deauthenticate packet filter 2058 * 2059 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 2060 * +--------------+----------+---------+--------+--------+---- 2061 * + Frame Control+ Duration + DA + SA + BSSID + 2062 * +--------------+----------+---------+--------+--------+---- 2063 * 2064 * The above is the management frame format for disassociate/ 2065 * deauthenticate pattern, from this we need to match the first byte 2066 * of 'Frame Control' and DA, SA, and BSSID fields 2067 * (skipping 2nd byte of FC and Duration feild. 2068 * 2069 * Disassociate pattern 2070 * -------------------- 2071 * Frame control = 00 00 1010 2072 * DA, SA, BSSID = x:x:x:x:x:x 2073 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2074 * | x:x:x:x:x:x -- 22 bytes 2075 * 2076 * Deauthenticate pattern 2077 * ---------------------- 2078 * Frame control = 00 00 1100 2079 * DA, SA, BSSID = x:x:x:x:x:x 2080 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2081 * | x:x:x:x:x:x -- 22 bytes 2082 */ 2083 2084 /* Create Disassociate Pattern first */ 2085 2086 byte_cnt = 0; 2087 2088 /* Fill out the mask with all FF's */ 2089 2090 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 2091 dis_deauth_mask[i] = 0xff; 2092 2093 /* copy the first byte of frame control field */ 2094 dis_deauth_pattern[byte_cnt] = 0xa0; 2095 byte_cnt++; 2096 2097 /* skip 2nd byte of frame control and Duration field */ 2098 byte_cnt += 3; 2099 2100 /* 2101 * need not match the destination mac address, it can be a broadcast 2102 * mac address or an unicast to this station 2103 */ 2104 byte_cnt += 6; 2105 2106 /* copy the source mac address */ 2107 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2108 2109 byte_cnt += 6; 2110 2111 /* copy the bssid, its same as the source mac address */ 2112 2113 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2114 2115 /* Create Disassociate pattern mask */ 2116 2117 dis_deauth_mask[0] = 0xfe; 2118 dis_deauth_mask[1] = 0x03; 2119 dis_deauth_mask[2] = 0xc0; 2120 2121 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2122 2123 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2124 pattern_count, byte_cnt); 2125 2126 pattern_count++; 2127 /* 2128 * for de-authenticate pattern, only the first byte of the frame 2129 * control field gets changed from 0xA0 to 0xC0 2130 */ 2131 dis_deauth_pattern[0] = 0xC0; 2132 2133 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2134 pattern_count, byte_cnt); 2135 2136 } 2137 2138 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2139 struct cfg80211_wowlan *wowlan) 2140 { 2141 struct ath_hw *ah = sc->sc_ah; 2142 struct ath9k_wow_pattern *wow_pattern = NULL; 2143 struct cfg80211_pkt_pattern *patterns = wowlan->patterns; 2144 int mask_len; 2145 s8 i = 0; 2146 2147 if (!wowlan->n_patterns) 2148 return; 2149 2150 /* 2151 * Add the new user configured patterns 2152 */ 2153 for (i = 0; i < wowlan->n_patterns; i++) { 2154 2155 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2156 2157 if (!wow_pattern) 2158 return; 2159 2160 /* 2161 * TODO: convert the generic user space pattern to 2162 * appropriate chip specific/802.11 pattern. 2163 */ 2164 2165 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2166 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2167 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2168 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2169 patterns[i].pattern_len); 2170 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2171 wow_pattern->pattern_len = patterns[i].pattern_len; 2172 2173 /* 2174 * just need to take care of deauth and disssoc pattern, 2175 * make sure we don't overwrite them. 2176 */ 2177 2178 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2179 wow_pattern->mask_bytes, 2180 i + 2, 2181 wow_pattern->pattern_len); 2182 kfree(wow_pattern); 2183 2184 } 2185 2186 } 2187 2188 static int ath9k_suspend(struct ieee80211_hw *hw, 2189 struct cfg80211_wowlan *wowlan) 2190 { 2191 struct ath_softc *sc = hw->priv; 2192 struct ath_hw *ah = sc->sc_ah; 2193 struct ath_common *common = ath9k_hw_common(ah); 2194 u32 wow_triggers_enabled = 0; 2195 int ret = 0; 2196 2197 mutex_lock(&sc->mutex); 2198 2199 ath_cancel_work(sc); 2200 ath_stop_ani(sc); 2201 del_timer_sync(&sc->rx_poll_timer); 2202 2203 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2204 ath_dbg(common, ANY, "Device not present\n"); 2205 ret = -EINVAL; 2206 goto fail_wow; 2207 } 2208 2209 if (WARN_ON(!wowlan)) { 2210 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2211 ret = -EINVAL; 2212 goto fail_wow; 2213 } 2214 2215 if (!device_can_wakeup(sc->dev)) { 2216 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2217 ret = 1; 2218 goto fail_wow; 2219 } 2220 2221 /* 2222 * none of the sta vifs are associated 2223 * and we are not currently handling multivif 2224 * cases, for instance we have to seperately 2225 * configure 'keep alive frame' for each 2226 * STA. 2227 */ 2228 2229 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2230 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2231 ret = 1; 2232 goto fail_wow; 2233 } 2234 2235 if (sc->nvifs > 1) { 2236 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2237 ret = 1; 2238 goto fail_wow; 2239 } 2240 2241 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2242 2243 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2244 wow_triggers_enabled); 2245 2246 ath9k_ps_wakeup(sc); 2247 2248 ath9k_stop_btcoex(sc); 2249 2250 /* 2251 * Enable wake up on recieving disassoc/deauth 2252 * frame by default. 2253 */ 2254 ath9k_wow_add_disassoc_deauth_pattern(sc); 2255 2256 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2257 ath9k_wow_add_pattern(sc, wowlan); 2258 2259 spin_lock_bh(&sc->sc_pcu_lock); 2260 /* 2261 * To avoid false wake, we enable beacon miss interrupt only 2262 * when we go to sleep. We save the current interrupt mask 2263 * so we can restore it after the system wakes up 2264 */ 2265 sc->wow_intr_before_sleep = ah->imask; 2266 ah->imask &= ~ATH9K_INT_GLOBAL; 2267 ath9k_hw_disable_interrupts(ah); 2268 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2269 ath9k_hw_set_interrupts(ah); 2270 ath9k_hw_enable_interrupts(ah); 2271 2272 spin_unlock_bh(&sc->sc_pcu_lock); 2273 2274 /* 2275 * we can now sync irq and kill any running tasklets, since we already 2276 * disabled interrupts and not holding a spin lock 2277 */ 2278 synchronize_irq(sc->irq); 2279 tasklet_kill(&sc->intr_tq); 2280 2281 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2282 2283 ath9k_ps_restore(sc); 2284 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2285 atomic_inc(&sc->wow_sleep_proc_intr); 2286 2287 fail_wow: 2288 mutex_unlock(&sc->mutex); 2289 return ret; 2290 } 2291 2292 static int ath9k_resume(struct ieee80211_hw *hw) 2293 { 2294 struct ath_softc *sc = hw->priv; 2295 struct ath_hw *ah = sc->sc_ah; 2296 struct ath_common *common = ath9k_hw_common(ah); 2297 u32 wow_status; 2298 2299 mutex_lock(&sc->mutex); 2300 2301 ath9k_ps_wakeup(sc); 2302 2303 spin_lock_bh(&sc->sc_pcu_lock); 2304 2305 ath9k_hw_disable_interrupts(ah); 2306 ah->imask = sc->wow_intr_before_sleep; 2307 ath9k_hw_set_interrupts(ah); 2308 ath9k_hw_enable_interrupts(ah); 2309 2310 spin_unlock_bh(&sc->sc_pcu_lock); 2311 2312 wow_status = ath9k_hw_wow_wakeup(ah); 2313 2314 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2315 /* 2316 * some devices may not pick beacon miss 2317 * as the reason they woke up so we add 2318 * that here for that shortcoming. 2319 */ 2320 wow_status |= AH_WOW_BEACON_MISS; 2321 atomic_dec(&sc->wow_got_bmiss_intr); 2322 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2323 } 2324 2325 atomic_dec(&sc->wow_sleep_proc_intr); 2326 2327 if (wow_status) { 2328 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2329 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2330 } 2331 2332 ath_restart_work(sc); 2333 ath9k_start_btcoex(sc); 2334 2335 ath9k_ps_restore(sc); 2336 mutex_unlock(&sc->mutex); 2337 2338 return 0; 2339 } 2340 2341 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2342 { 2343 struct ath_softc *sc = hw->priv; 2344 2345 mutex_lock(&sc->mutex); 2346 device_init_wakeup(sc->dev, 1); 2347 device_set_wakeup_enable(sc->dev, enabled); 2348 mutex_unlock(&sc->mutex); 2349 } 2350 2351 #endif 2352 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2353 { 2354 struct ath_softc *sc = hw->priv; 2355 set_bit(SC_OP_SCANNING, &sc->sc_flags); 2356 } 2357 2358 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2359 { 2360 struct ath_softc *sc = hw->priv; 2361 clear_bit(SC_OP_SCANNING, &sc->sc_flags); 2362 } 2363 2364 static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw, 2365 struct ieee80211_vif *vif, 2366 struct cfg80211_chan_def *chandef) 2367 { 2368 struct ath_softc *sc = hw->priv; 2369 2370 /* mac80211 does not support CSA in multi-if cases (yet) */ 2371 if (WARN_ON(sc->csa_vif)) 2372 return; 2373 2374 sc->csa_vif = vif; 2375 } 2376 2377 static void ath9k_tx99_stop(struct ath_softc *sc) 2378 { 2379 struct ath_hw *ah = sc->sc_ah; 2380 struct ath_common *common = ath9k_hw_common(ah); 2381 2382 ath_drain_all_txq(sc); 2383 ath_startrecv(sc); 2384 2385 ath9k_hw_set_interrupts(ah); 2386 ath9k_hw_enable_interrupts(ah); 2387 2388 ieee80211_wake_queues(sc->hw); 2389 2390 kfree_skb(sc->tx99_skb); 2391 sc->tx99_skb = NULL; 2392 sc->tx99_state = false; 2393 2394 ath9k_hw_tx99_stop(sc->sc_ah); 2395 ath_dbg(common, XMIT, "TX99 stopped\n"); 2396 } 2397 2398 static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc) 2399 { 2400 static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24, 2401 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50, 2402 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1, 2403 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18, 2404 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8, 2405 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84, 2406 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3, 2407 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0}; 2408 u32 len = 1200; 2409 struct ieee80211_hw *hw = sc->hw; 2410 struct ieee80211_hdr *hdr; 2411 struct ieee80211_tx_info *tx_info; 2412 struct sk_buff *skb; 2413 2414 skb = alloc_skb(len, GFP_KERNEL); 2415 if (!skb) 2416 return NULL; 2417 2418 skb_put(skb, len); 2419 2420 memset(skb->data, 0, len); 2421 2422 hdr = (struct ieee80211_hdr *)skb->data; 2423 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA); 2424 hdr->duration_id = 0; 2425 2426 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); 2427 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 2428 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 2429 2430 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 2431 2432 tx_info = IEEE80211_SKB_CB(skb); 2433 memset(tx_info, 0, sizeof(*tx_info)); 2434 tx_info->band = hw->conf.chandef.chan->band; 2435 tx_info->flags = IEEE80211_TX_CTL_NO_ACK; 2436 tx_info->control.vif = sc->tx99_vif; 2437 2438 memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data)); 2439 2440 return skb; 2441 } 2442 2443 void ath9k_tx99_deinit(struct ath_softc *sc) 2444 { 2445 ath_reset(sc); 2446 2447 ath9k_ps_wakeup(sc); 2448 ath9k_tx99_stop(sc); 2449 ath9k_ps_restore(sc); 2450 } 2451 2452 int ath9k_tx99_init(struct ath_softc *sc) 2453 { 2454 struct ieee80211_hw *hw = sc->hw; 2455 struct ath_hw *ah = sc->sc_ah; 2456 struct ath_common *common = ath9k_hw_common(ah); 2457 struct ath_tx_control txctl; 2458 int r; 2459 2460 if (sc->sc_flags & SC_OP_INVALID) { 2461 ath_err(common, 2462 "driver is in invalid state unable to use TX99"); 2463 return -EINVAL; 2464 } 2465 2466 sc->tx99_skb = ath9k_build_tx99_skb(sc); 2467 if (!sc->tx99_skb) 2468 return -ENOMEM; 2469 2470 memset(&txctl, 0, sizeof(txctl)); 2471 txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO]; 2472 2473 ath_reset(sc); 2474 2475 ath9k_ps_wakeup(sc); 2476 2477 ath9k_hw_disable_interrupts(ah); 2478 atomic_set(&ah->intr_ref_cnt, -1); 2479 ath_drain_all_txq(sc); 2480 ath_stoprecv(sc); 2481 2482 sc->tx99_state = true; 2483 2484 ieee80211_stop_queues(hw); 2485 2486 if (sc->tx99_power == MAX_RATE_POWER + 1) 2487 sc->tx99_power = MAX_RATE_POWER; 2488 2489 ath9k_hw_tx99_set_txpower(ah, sc->tx99_power); 2490 r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl); 2491 if (r) { 2492 ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n"); 2493 return r; 2494 } 2495 2496 ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n", 2497 sc->tx99_power, 2498 sc->tx99_power / 2); 2499 2500 /* We leave the harware awake as it will be chugging on */ 2501 2502 return 0; 2503 } 2504 2505 struct ieee80211_ops ath9k_ops = { 2506 .tx = ath9k_tx, 2507 .start = ath9k_start, 2508 .stop = ath9k_stop, 2509 .add_interface = ath9k_add_interface, 2510 .change_interface = ath9k_change_interface, 2511 .remove_interface = ath9k_remove_interface, 2512 .config = ath9k_config, 2513 .configure_filter = ath9k_configure_filter, 2514 .sta_add = ath9k_sta_add, 2515 .sta_remove = ath9k_sta_remove, 2516 .sta_notify = ath9k_sta_notify, 2517 .conf_tx = ath9k_conf_tx, 2518 .bss_info_changed = ath9k_bss_info_changed, 2519 .set_key = ath9k_set_key, 2520 .get_tsf = ath9k_get_tsf, 2521 .set_tsf = ath9k_set_tsf, 2522 .reset_tsf = ath9k_reset_tsf, 2523 .ampdu_action = ath9k_ampdu_action, 2524 .get_survey = ath9k_get_survey, 2525 .rfkill_poll = ath9k_rfkill_poll_state, 2526 .set_coverage_class = ath9k_set_coverage_class, 2527 .flush = ath9k_flush, 2528 .tx_frames_pending = ath9k_tx_frames_pending, 2529 .tx_last_beacon = ath9k_tx_last_beacon, 2530 .release_buffered_frames = ath9k_release_buffered_frames, 2531 .get_stats = ath9k_get_stats, 2532 .set_antenna = ath9k_set_antenna, 2533 .get_antenna = ath9k_get_antenna, 2534 2535 #ifdef CONFIG_PM_SLEEP 2536 .suspend = ath9k_suspend, 2537 .resume = ath9k_resume, 2538 .set_wakeup = ath9k_set_wakeup, 2539 #endif 2540 2541 #ifdef CONFIG_ATH9K_DEBUGFS 2542 .get_et_sset_count = ath9k_get_et_sset_count, 2543 .get_et_stats = ath9k_get_et_stats, 2544 .get_et_strings = ath9k_get_et_strings, 2545 #endif 2546 2547 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2548 .sta_add_debugfs = ath9k_sta_add_debugfs, 2549 #endif 2550 .sw_scan_start = ath9k_sw_scan_start, 2551 .sw_scan_complete = ath9k_sw_scan_complete, 2552 .channel_switch_beacon = ath9k_channel_switch_beacon, 2553 }; 2554