1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq, 58 bool sw_pending) 59 { 60 bool pending = false; 61 62 spin_lock_bh(&txq->axq_lock); 63 64 if (txq->axq_depth) { 65 pending = true; 66 goto out; 67 } 68 69 if (!sw_pending) 70 goto out; 71 72 if (txq->mac80211_qnum >= 0) { 73 struct list_head *list; 74 75 list = &sc->cur_chan->acq[txq->mac80211_qnum]; 76 if (!list_empty(list)) 77 pending = true; 78 } 79 out: 80 spin_unlock_bh(&txq->axq_lock); 81 return pending; 82 } 83 84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 85 { 86 unsigned long flags; 87 bool ret; 88 89 spin_lock_irqsave(&sc->sc_pm_lock, flags); 90 ret = ath9k_hw_setpower(sc->sc_ah, mode); 91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 92 93 return ret; 94 } 95 96 void ath_ps_full_sleep(unsigned long data) 97 { 98 struct ath_softc *sc = (struct ath_softc *) data; 99 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 100 bool reset; 101 102 spin_lock(&common->cc_lock); 103 ath_hw_cycle_counters_update(common); 104 spin_unlock(&common->cc_lock); 105 106 ath9k_hw_setrxabort(sc->sc_ah, 1); 107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 108 109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 110 } 111 112 void ath9k_ps_wakeup(struct ath_softc *sc) 113 { 114 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 115 unsigned long flags; 116 enum ath9k_power_mode power_mode; 117 118 spin_lock_irqsave(&sc->sc_pm_lock, flags); 119 if (++sc->ps_usecount != 1) 120 goto unlock; 121 122 del_timer_sync(&sc->sleep_timer); 123 power_mode = sc->sc_ah->power_mode; 124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 125 126 /* 127 * While the hardware is asleep, the cycle counters contain no 128 * useful data. Better clear them now so that they don't mess up 129 * survey data results. 130 */ 131 if (power_mode != ATH9K_PM_AWAKE) { 132 spin_lock(&common->cc_lock); 133 ath_hw_cycle_counters_update(common); 134 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 135 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 136 spin_unlock(&common->cc_lock); 137 } 138 139 unlock: 140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 141 } 142 143 void ath9k_ps_restore(struct ath_softc *sc) 144 { 145 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 146 enum ath9k_power_mode mode; 147 unsigned long flags; 148 149 spin_lock_irqsave(&sc->sc_pm_lock, flags); 150 if (--sc->ps_usecount != 0) 151 goto unlock; 152 153 if (sc->ps_idle) { 154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 155 goto unlock; 156 } 157 158 if (sc->ps_enabled && 159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 160 PS_WAIT_FOR_CAB | 161 PS_WAIT_FOR_PSPOLL_DATA | 162 PS_WAIT_FOR_TX_ACK | 163 PS_WAIT_FOR_ANI))) { 164 mode = ATH9K_PM_NETWORK_SLEEP; 165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 166 ath9k_btcoex_stop_gen_timer(sc); 167 } else { 168 goto unlock; 169 } 170 171 spin_lock(&common->cc_lock); 172 ath_hw_cycle_counters_update(common); 173 spin_unlock(&common->cc_lock); 174 175 ath9k_hw_setpower(sc->sc_ah, mode); 176 177 unlock: 178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 179 } 180 181 static void __ath_cancel_work(struct ath_softc *sc) 182 { 183 cancel_work_sync(&sc->paprd_work); 184 cancel_delayed_work_sync(&sc->tx_complete_work); 185 cancel_delayed_work_sync(&sc->hw_pll_work); 186 187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 188 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 189 cancel_work_sync(&sc->mci_work); 190 #endif 191 } 192 193 void ath_cancel_work(struct ath_softc *sc) 194 { 195 __ath_cancel_work(sc); 196 cancel_work_sync(&sc->hw_reset_work); 197 } 198 199 void ath_restart_work(struct ath_softc *sc) 200 { 201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 202 203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 206 207 ath_start_ani(sc); 208 } 209 210 static bool ath_prepare_reset(struct ath_softc *sc) 211 { 212 struct ath_hw *ah = sc->sc_ah; 213 bool ret = true; 214 215 ieee80211_stop_queues(sc->hw); 216 ath_stop_ani(sc); 217 ath9k_hw_disable_interrupts(ah); 218 219 if (!ath_drain_all_txq(sc)) 220 ret = false; 221 222 if (!ath_stoprecv(sc)) 223 ret = false; 224 225 return ret; 226 } 227 228 static bool ath_complete_reset(struct ath_softc *sc, bool start) 229 { 230 struct ath_hw *ah = sc->sc_ah; 231 struct ath_common *common = ath9k_hw_common(ah); 232 unsigned long flags; 233 234 ath9k_calculate_summary_state(sc, sc->cur_chan); 235 ath_startrecv(sc); 236 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 237 sc->cur_chan->txpower, 238 &sc->cur_chan->cur_txpower); 239 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 240 241 if (!sc->cur_chan->offchannel && start) { 242 /* restore per chanctx TSF timer */ 243 if (sc->cur_chan->tsf_val) { 244 u32 offset; 245 246 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 247 NULL); 248 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 249 } 250 251 252 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 253 goto work; 254 255 if (ah->opmode == NL80211_IFTYPE_STATION && 256 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 257 spin_lock_irqsave(&sc->sc_pm_lock, flags); 258 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 259 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 260 } else { 261 ath9k_set_beacon(sc); 262 } 263 work: 264 ath_restart_work(sc); 265 ath_txq_schedule_all(sc); 266 } 267 268 sc->gtt_cnt = 0; 269 270 ath9k_hw_set_interrupts(ah); 271 ath9k_hw_enable_interrupts(ah); 272 ieee80211_wake_queues(sc->hw); 273 ath9k_p2p_ps_timer(sc); 274 275 return true; 276 } 277 278 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 279 { 280 struct ath_hw *ah = sc->sc_ah; 281 struct ath_common *common = ath9k_hw_common(ah); 282 struct ath9k_hw_cal_data *caldata = NULL; 283 bool fastcc = true; 284 int r; 285 286 __ath_cancel_work(sc); 287 288 disable_irq(sc->irq); 289 tasklet_disable(&sc->intr_tq); 290 tasklet_disable(&sc->bcon_tasklet); 291 spin_lock_bh(&sc->sc_pcu_lock); 292 293 if (!sc->cur_chan->offchannel) { 294 fastcc = false; 295 caldata = &sc->cur_chan->caldata; 296 } 297 298 if (!hchan) { 299 fastcc = false; 300 hchan = ah->curchan; 301 } 302 303 if (!ath_prepare_reset(sc)) 304 fastcc = false; 305 306 if (ath9k_is_chanctx_enabled()) 307 fastcc = false; 308 309 spin_lock_bh(&sc->chan_lock); 310 sc->cur_chandef = sc->cur_chan->chandef; 311 spin_unlock_bh(&sc->chan_lock); 312 313 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 314 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 315 316 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 317 if (r) { 318 ath_err(common, 319 "Unable to reset channel, reset status %d\n", r); 320 321 ath9k_hw_enable_interrupts(ah); 322 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 323 324 goto out; 325 } 326 327 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 328 sc->cur_chan->offchannel) 329 ath9k_mci_set_txpower(sc, true, false); 330 331 if (!ath_complete_reset(sc, true)) 332 r = -EIO; 333 334 out: 335 enable_irq(sc->irq); 336 spin_unlock_bh(&sc->sc_pcu_lock); 337 tasklet_enable(&sc->bcon_tasklet); 338 tasklet_enable(&sc->intr_tq); 339 340 return r; 341 } 342 343 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 344 struct ieee80211_vif *vif) 345 { 346 struct ath_node *an; 347 an = (struct ath_node *)sta->drv_priv; 348 349 an->sc = sc; 350 an->sta = sta; 351 an->vif = vif; 352 memset(&an->key_idx, 0, sizeof(an->key_idx)); 353 354 ath_tx_node_init(sc, an); 355 356 ath_dynack_node_init(sc->sc_ah, an); 357 } 358 359 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 360 { 361 struct ath_node *an = (struct ath_node *)sta->drv_priv; 362 ath_tx_node_cleanup(sc, an); 363 364 ath_dynack_node_deinit(sc->sc_ah, an); 365 } 366 367 void ath9k_tasklet(unsigned long data) 368 { 369 struct ath_softc *sc = (struct ath_softc *)data; 370 struct ath_hw *ah = sc->sc_ah; 371 struct ath_common *common = ath9k_hw_common(ah); 372 enum ath_reset_type type; 373 unsigned long flags; 374 u32 status = sc->intrstatus; 375 u32 rxmask; 376 377 ath9k_ps_wakeup(sc); 378 spin_lock(&sc->sc_pcu_lock); 379 380 if (status & ATH9K_INT_FATAL) { 381 type = RESET_TYPE_FATAL_INT; 382 ath9k_queue_reset(sc, type); 383 384 /* 385 * Increment the ref. counter here so that 386 * interrupts are enabled in the reset routine. 387 */ 388 atomic_inc(&ah->intr_ref_cnt); 389 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 390 goto out; 391 } 392 393 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 394 (status & ATH9K_INT_BB_WATCHDOG)) { 395 spin_lock(&common->cc_lock); 396 ath_hw_cycle_counters_update(common); 397 ar9003_hw_bb_watchdog_dbg_info(ah); 398 spin_unlock(&common->cc_lock); 399 400 if (ar9003_hw_bb_watchdog_check(ah)) { 401 type = RESET_TYPE_BB_WATCHDOG; 402 ath9k_queue_reset(sc, type); 403 404 /* 405 * Increment the ref. counter here so that 406 * interrupts are enabled in the reset routine. 407 */ 408 atomic_inc(&ah->intr_ref_cnt); 409 ath_dbg(common, RESET, 410 "BB_WATCHDOG: Skipping interrupts\n"); 411 goto out; 412 } 413 } 414 415 if (status & ATH9K_INT_GTT) { 416 sc->gtt_cnt++; 417 418 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 419 type = RESET_TYPE_TX_GTT; 420 ath9k_queue_reset(sc, type); 421 atomic_inc(&ah->intr_ref_cnt); 422 ath_dbg(common, RESET, 423 "GTT: Skipping interrupts\n"); 424 goto out; 425 } 426 } 427 428 spin_lock_irqsave(&sc->sc_pm_lock, flags); 429 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 430 /* 431 * TSF sync does not look correct; remain awake to sync with 432 * the next Beacon. 433 */ 434 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 435 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 436 } 437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 438 439 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 440 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 441 ATH9K_INT_RXORN); 442 else 443 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 444 445 if (status & rxmask) { 446 /* Check for high priority Rx first */ 447 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 448 (status & ATH9K_INT_RXHP)) 449 ath_rx_tasklet(sc, 0, true); 450 451 ath_rx_tasklet(sc, 0, false); 452 } 453 454 if (status & ATH9K_INT_TX) { 455 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 456 /* 457 * For EDMA chips, TX completion is enabled for the 458 * beacon queue, so if a beacon has been transmitted 459 * successfully after a GTT interrupt, the GTT counter 460 * gets reset to zero here. 461 */ 462 sc->gtt_cnt = 0; 463 464 ath_tx_edma_tasklet(sc); 465 } else { 466 ath_tx_tasklet(sc); 467 } 468 469 wake_up(&sc->tx_wait); 470 } 471 472 if (status & ATH9K_INT_GENTIMER) 473 ath_gen_timer_isr(sc->sc_ah); 474 475 ath9k_btcoex_handle_interrupt(sc, status); 476 477 /* re-enable hardware interrupt */ 478 ath9k_hw_enable_interrupts(ah); 479 out: 480 spin_unlock(&sc->sc_pcu_lock); 481 ath9k_ps_restore(sc); 482 } 483 484 irqreturn_t ath_isr(int irq, void *dev) 485 { 486 #define SCHED_INTR ( \ 487 ATH9K_INT_FATAL | \ 488 ATH9K_INT_BB_WATCHDOG | \ 489 ATH9K_INT_RXORN | \ 490 ATH9K_INT_RXEOL | \ 491 ATH9K_INT_RX | \ 492 ATH9K_INT_RXLP | \ 493 ATH9K_INT_RXHP | \ 494 ATH9K_INT_TX | \ 495 ATH9K_INT_BMISS | \ 496 ATH9K_INT_CST | \ 497 ATH9K_INT_GTT | \ 498 ATH9K_INT_TSFOOR | \ 499 ATH9K_INT_GENTIMER | \ 500 ATH9K_INT_MCI) 501 502 struct ath_softc *sc = dev; 503 struct ath_hw *ah = sc->sc_ah; 504 struct ath_common *common = ath9k_hw_common(ah); 505 enum ath9k_int status; 506 u32 sync_cause = 0; 507 bool sched = false; 508 509 /* 510 * The hardware is not ready/present, don't 511 * touch anything. Note this can happen early 512 * on if the IRQ is shared. 513 */ 514 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 515 return IRQ_NONE; 516 517 /* shared irq, not for us */ 518 if (!ath9k_hw_intrpend(ah)) 519 return IRQ_NONE; 520 521 /* 522 * Figure out the reason(s) for the interrupt. Note 523 * that the hal returns a pseudo-ISR that may include 524 * bits we haven't explicitly enabled so we mask the 525 * value to insure we only process bits we requested. 526 */ 527 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 528 ath9k_debug_sync_cause(sc, sync_cause); 529 status &= ah->imask; /* discard unasked-for bits */ 530 531 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 532 return IRQ_HANDLED; 533 534 /* 535 * If there are no status bits set, then this interrupt was not 536 * for me (should have been caught above). 537 */ 538 if (!status) 539 return IRQ_NONE; 540 541 /* Cache the status */ 542 sc->intrstatus = status; 543 544 if (status & SCHED_INTR) 545 sched = true; 546 547 /* 548 * If a FATAL interrupt is received, we have to reset the chip 549 * immediately. 550 */ 551 if (status & ATH9K_INT_FATAL) 552 goto chip_reset; 553 554 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 555 (status & ATH9K_INT_BB_WATCHDOG)) 556 goto chip_reset; 557 558 #ifdef CONFIG_ATH9K_WOW 559 if (status & ATH9K_INT_BMISS) { 560 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 561 atomic_inc(&sc->wow_got_bmiss_intr); 562 atomic_dec(&sc->wow_sleep_proc_intr); 563 } 564 } 565 #endif 566 567 if (status & ATH9K_INT_SWBA) 568 tasklet_schedule(&sc->bcon_tasklet); 569 570 if (status & ATH9K_INT_TXURN) 571 ath9k_hw_updatetxtriglevel(ah, true); 572 573 if (status & ATH9K_INT_RXEOL) { 574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 575 ath9k_hw_set_interrupts(ah); 576 } 577 578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 579 if (status & ATH9K_INT_TIM_TIMER) { 580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 581 goto chip_reset; 582 /* Clear RxAbort bit so that we can 583 * receive frames */ 584 ath9k_setpower(sc, ATH9K_PM_AWAKE); 585 spin_lock(&sc->sc_pm_lock); 586 ath9k_hw_setrxabort(sc->sc_ah, 0); 587 sc->ps_flags |= PS_WAIT_FOR_BEACON; 588 spin_unlock(&sc->sc_pm_lock); 589 } 590 591 chip_reset: 592 593 ath_debug_stat_interrupt(sc, status); 594 595 if (sched) { 596 /* turn off every interrupt */ 597 ath9k_hw_disable_interrupts(ah); 598 tasklet_schedule(&sc->intr_tq); 599 } 600 601 return IRQ_HANDLED; 602 603 #undef SCHED_INTR 604 } 605 606 /* 607 * This function is called when a HW reset cannot be deferred 608 * and has to be immediate. 609 */ 610 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan) 611 { 612 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 613 int r; 614 615 ath9k_hw_kill_interrupts(sc->sc_ah); 616 set_bit(ATH_OP_HW_RESET, &common->op_flags); 617 618 ath9k_ps_wakeup(sc); 619 r = ath_reset_internal(sc, hchan); 620 ath9k_ps_restore(sc); 621 622 return r; 623 } 624 625 /* 626 * When a HW reset can be deferred, it is added to the 627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before 628 * queueing. 629 */ 630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 631 { 632 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 633 #ifdef CONFIG_ATH9K_DEBUGFS 634 RESET_STAT_INC(sc, type); 635 #endif 636 ath9k_hw_kill_interrupts(sc->sc_ah); 637 set_bit(ATH_OP_HW_RESET, &common->op_flags); 638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 639 } 640 641 void ath_reset_work(struct work_struct *work) 642 { 643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 644 645 ath9k_ps_wakeup(sc); 646 ath_reset_internal(sc, NULL); 647 ath9k_ps_restore(sc); 648 } 649 650 /**********************/ 651 /* mac80211 callbacks */ 652 /**********************/ 653 654 static int ath9k_start(struct ieee80211_hw *hw) 655 { 656 struct ath_softc *sc = hw->priv; 657 struct ath_hw *ah = sc->sc_ah; 658 struct ath_common *common = ath9k_hw_common(ah); 659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 660 struct ath_chanctx *ctx = sc->cur_chan; 661 struct ath9k_channel *init_channel; 662 int r; 663 664 ath_dbg(common, CONFIG, 665 "Starting driver with initial channel: %d MHz\n", 666 curchan->center_freq); 667 668 ath9k_ps_wakeup(sc); 669 mutex_lock(&sc->mutex); 670 671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 672 sc->cur_chandef = hw->conf.chandef; 673 674 /* Reset SERDES registers */ 675 ath9k_hw_configpcipowersave(ah, false); 676 677 /* 678 * The basic interface to setting the hardware in a good 679 * state is ``reset''. On return the hardware is known to 680 * be powered up and with interrupts disabled. This must 681 * be followed by initialization of the appropriate bits 682 * and then setup of the interrupt mask. 683 */ 684 spin_lock_bh(&sc->sc_pcu_lock); 685 686 atomic_set(&ah->intr_ref_cnt, -1); 687 688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 689 if (r) { 690 ath_err(common, 691 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 692 r, curchan->center_freq); 693 ah->reset_power_on = false; 694 } 695 696 /* Setup our intr mask. */ 697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 698 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 699 ATH9K_INT_GLOBAL; 700 701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 702 ah->imask |= ATH9K_INT_RXHP | 703 ATH9K_INT_RXLP; 704 else 705 ah->imask |= ATH9K_INT_RX; 706 707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 708 ah->imask |= ATH9K_INT_BB_WATCHDOG; 709 710 /* 711 * Enable GTT interrupts only for AR9003/AR9004 chips 712 * for now. 713 */ 714 if (AR_SREV_9300_20_OR_LATER(ah)) 715 ah->imask |= ATH9K_INT_GTT; 716 717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 718 ah->imask |= ATH9K_INT_CST; 719 720 ath_mci_enable(sc); 721 722 clear_bit(ATH_OP_INVALID, &common->op_flags); 723 sc->sc_ah->is_monitoring = false; 724 725 if (!ath_complete_reset(sc, false)) 726 ah->reset_power_on = false; 727 728 if (ah->led_pin >= 0) { 729 ath9k_hw_cfg_output(ah, ah->led_pin, 730 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 731 ath9k_hw_set_gpio(ah, ah->led_pin, 732 (ah->config.led_active_high) ? 1 : 0); 733 } 734 735 /* 736 * Reset key cache to sane defaults (all entries cleared) instead of 737 * semi-random values after suspend/resume. 738 */ 739 ath9k_cmn_init_crypto(sc->sc_ah); 740 741 ath9k_hw_reset_tsf(ah); 742 743 spin_unlock_bh(&sc->sc_pcu_lock); 744 745 mutex_unlock(&sc->mutex); 746 747 ath9k_ps_restore(sc); 748 749 return 0; 750 } 751 752 static void ath9k_tx(struct ieee80211_hw *hw, 753 struct ieee80211_tx_control *control, 754 struct sk_buff *skb) 755 { 756 struct ath_softc *sc = hw->priv; 757 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 758 struct ath_tx_control txctl; 759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 760 unsigned long flags; 761 762 if (sc->ps_enabled) { 763 /* 764 * mac80211 does not set PM field for normal data frames, so we 765 * need to update that based on the current PS mode. 766 */ 767 if (ieee80211_is_data(hdr->frame_control) && 768 !ieee80211_is_nullfunc(hdr->frame_control) && 769 !ieee80211_has_pm(hdr->frame_control)) { 770 ath_dbg(common, PS, 771 "Add PM=1 for a TX frame while in PS mode\n"); 772 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 773 } 774 } 775 776 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 777 /* 778 * We are using PS-Poll and mac80211 can request TX while in 779 * power save mode. Need to wake up hardware for the TX to be 780 * completed and if needed, also for RX of buffered frames. 781 */ 782 ath9k_ps_wakeup(sc); 783 spin_lock_irqsave(&sc->sc_pm_lock, flags); 784 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 785 ath9k_hw_setrxabort(sc->sc_ah, 0); 786 if (ieee80211_is_pspoll(hdr->frame_control)) { 787 ath_dbg(common, PS, 788 "Sending PS-Poll to pick a buffered frame\n"); 789 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 790 } else { 791 ath_dbg(common, PS, "Wake up to complete TX\n"); 792 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 793 } 794 /* 795 * The actual restore operation will happen only after 796 * the ps_flags bit is cleared. We are just dropping 797 * the ps_usecount here. 798 */ 799 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 800 ath9k_ps_restore(sc); 801 } 802 803 /* 804 * Cannot tx while the hardware is in full sleep, it first needs a full 805 * chip reset to recover from that 806 */ 807 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 808 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 809 goto exit; 810 } 811 812 memset(&txctl, 0, sizeof(struct ath_tx_control)); 813 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 814 txctl.sta = control->sta; 815 816 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 817 818 if (ath_tx_start(hw, skb, &txctl) != 0) { 819 ath_dbg(common, XMIT, "TX failed\n"); 820 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 821 goto exit; 822 } 823 824 return; 825 exit: 826 ieee80211_free_txskb(hw, skb); 827 } 828 829 static void ath9k_stop(struct ieee80211_hw *hw) 830 { 831 struct ath_softc *sc = hw->priv; 832 struct ath_hw *ah = sc->sc_ah; 833 struct ath_common *common = ath9k_hw_common(ah); 834 bool prev_idle; 835 836 ath9k_deinit_channel_context(sc); 837 838 mutex_lock(&sc->mutex); 839 840 ath_cancel_work(sc); 841 842 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 843 ath_dbg(common, ANY, "Device not present\n"); 844 mutex_unlock(&sc->mutex); 845 return; 846 } 847 848 /* Ensure HW is awake when we try to shut it down. */ 849 ath9k_ps_wakeup(sc); 850 851 spin_lock_bh(&sc->sc_pcu_lock); 852 853 /* prevent tasklets to enable interrupts once we disable them */ 854 ah->imask &= ~ATH9K_INT_GLOBAL; 855 856 /* make sure h/w will not generate any interrupt 857 * before setting the invalid flag. */ 858 ath9k_hw_disable_interrupts(ah); 859 860 spin_unlock_bh(&sc->sc_pcu_lock); 861 862 /* we can now sync irq and kill any running tasklets, since we already 863 * disabled interrupts and not holding a spin lock */ 864 synchronize_irq(sc->irq); 865 tasklet_kill(&sc->intr_tq); 866 tasklet_kill(&sc->bcon_tasklet); 867 868 prev_idle = sc->ps_idle; 869 sc->ps_idle = true; 870 871 spin_lock_bh(&sc->sc_pcu_lock); 872 873 if (ah->led_pin >= 0) { 874 ath9k_hw_set_gpio(ah, ah->led_pin, 875 (ah->config.led_active_high) ? 0 : 1); 876 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 877 } 878 879 ath_prepare_reset(sc); 880 881 if (sc->rx.frag) { 882 dev_kfree_skb_any(sc->rx.frag); 883 sc->rx.frag = NULL; 884 } 885 886 if (!ah->curchan) 887 ah->curchan = ath9k_cmn_get_channel(hw, ah, 888 &sc->cur_chan->chandef); 889 890 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 891 892 set_bit(ATH_OP_INVALID, &common->op_flags); 893 894 ath9k_hw_phy_disable(ah); 895 896 ath9k_hw_configpcipowersave(ah, true); 897 898 spin_unlock_bh(&sc->sc_pcu_lock); 899 900 ath9k_ps_restore(sc); 901 902 sc->ps_idle = prev_idle; 903 904 mutex_unlock(&sc->mutex); 905 906 ath_dbg(common, CONFIG, "Driver halt\n"); 907 } 908 909 static bool ath9k_uses_beacons(int type) 910 { 911 switch (type) { 912 case NL80211_IFTYPE_AP: 913 case NL80211_IFTYPE_ADHOC: 914 case NL80211_IFTYPE_MESH_POINT: 915 return true; 916 default: 917 return false; 918 } 919 } 920 921 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 922 u8 *mac, struct ieee80211_vif *vif) 923 { 924 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 925 int i; 926 927 if (iter_data->has_hw_macaddr) { 928 for (i = 0; i < ETH_ALEN; i++) 929 iter_data->mask[i] &= 930 ~(iter_data->hw_macaddr[i] ^ mac[i]); 931 } else { 932 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 933 iter_data->has_hw_macaddr = true; 934 } 935 936 if (!vif->bss_conf.use_short_slot) 937 iter_data->slottime = ATH9K_SLOT_TIME_20; 938 939 switch (vif->type) { 940 case NL80211_IFTYPE_AP: 941 iter_data->naps++; 942 break; 943 case NL80211_IFTYPE_STATION: 944 iter_data->nstations++; 945 if (avp->assoc && !iter_data->primary_sta) 946 iter_data->primary_sta = vif; 947 break; 948 case NL80211_IFTYPE_ADHOC: 949 iter_data->nadhocs++; 950 if (vif->bss_conf.enable_beacon) 951 iter_data->beacons = true; 952 break; 953 case NL80211_IFTYPE_MESH_POINT: 954 iter_data->nmeshes++; 955 if (vif->bss_conf.enable_beacon) 956 iter_data->beacons = true; 957 break; 958 case NL80211_IFTYPE_WDS: 959 iter_data->nwds++; 960 break; 961 default: 962 break; 963 } 964 } 965 966 static void ath9k_update_bssid_mask(struct ath_softc *sc, 967 struct ath_chanctx *ctx, 968 struct ath9k_vif_iter_data *iter_data) 969 { 970 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 971 struct ath_vif *avp; 972 int i; 973 974 if (!ath9k_is_chanctx_enabled()) 975 return; 976 977 list_for_each_entry(avp, &ctx->vifs, list) { 978 if (ctx->nvifs_assigned != 1) 979 continue; 980 981 if (!avp->vif->p2p || !iter_data->has_hw_macaddr) 982 continue; 983 984 ether_addr_copy(common->curbssid, avp->bssid); 985 986 /* perm_addr will be used as the p2p device address. */ 987 for (i = 0; i < ETH_ALEN; i++) 988 iter_data->mask[i] &= 989 ~(iter_data->hw_macaddr[i] ^ 990 sc->hw->wiphy->perm_addr[i]); 991 } 992 } 993 994 /* Called with sc->mutex held. */ 995 void ath9k_calculate_iter_data(struct ath_softc *sc, 996 struct ath_chanctx *ctx, 997 struct ath9k_vif_iter_data *iter_data) 998 { 999 struct ath_vif *avp; 1000 1001 /* 1002 * The hardware will use primary station addr together with the 1003 * BSSID mask when matching addresses. 1004 */ 1005 memset(iter_data, 0, sizeof(*iter_data)); 1006 memset(&iter_data->mask, 0xff, ETH_ALEN); 1007 iter_data->slottime = ATH9K_SLOT_TIME_9; 1008 1009 list_for_each_entry(avp, &ctx->vifs, list) 1010 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 1011 1012 ath9k_update_bssid_mask(sc, ctx, iter_data); 1013 } 1014 1015 static void ath9k_set_assoc_state(struct ath_softc *sc, 1016 struct ieee80211_vif *vif, bool changed) 1017 { 1018 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1019 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 1020 unsigned long flags; 1021 1022 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1023 1024 ether_addr_copy(common->curbssid, avp->bssid); 1025 common->curaid = avp->aid; 1026 ath9k_hw_write_associd(sc->sc_ah); 1027 1028 if (changed) { 1029 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1030 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1031 1032 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1033 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1034 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1035 } 1036 1037 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1038 ath9k_mci_update_wlan_channels(sc, false); 1039 1040 ath_dbg(common, CONFIG, 1041 "Primary Station interface: %pM, BSSID: %pM\n", 1042 vif->addr, common->curbssid); 1043 } 1044 1045 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1046 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1047 { 1048 struct ath_hw *ah = sc->sc_ah; 1049 struct ath_common *common = ath9k_hw_common(ah); 1050 struct ieee80211_vif *vif = NULL; 1051 1052 ath9k_ps_wakeup(sc); 1053 1054 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1055 vif = sc->offchannel.scan_vif; 1056 else 1057 vif = sc->offchannel.roc_vif; 1058 1059 if (WARN_ON(!vif)) 1060 goto exit; 1061 1062 eth_zero_addr(common->curbssid); 1063 eth_broadcast_addr(common->bssidmask); 1064 memcpy(common->macaddr, vif->addr, ETH_ALEN); 1065 common->curaid = 0; 1066 ah->opmode = vif->type; 1067 ah->imask &= ~ATH9K_INT_SWBA; 1068 ah->imask &= ~ATH9K_INT_TSFOOR; 1069 ah->slottime = ATH9K_SLOT_TIME_9; 1070 1071 ath_hw_setbssidmask(common); 1072 ath9k_hw_setopmode(ah); 1073 ath9k_hw_write_associd(sc->sc_ah); 1074 ath9k_hw_set_interrupts(ah); 1075 ath9k_hw_init_global_settings(ah); 1076 1077 exit: 1078 ath9k_ps_restore(sc); 1079 } 1080 #endif 1081 1082 /* Called with sc->mutex held. */ 1083 void ath9k_calculate_summary_state(struct ath_softc *sc, 1084 struct ath_chanctx *ctx) 1085 { 1086 struct ath_hw *ah = sc->sc_ah; 1087 struct ath_common *common = ath9k_hw_common(ah); 1088 struct ath9k_vif_iter_data iter_data; 1089 struct ath_beacon_config *cur_conf; 1090 1091 ath_chanctx_check_active(sc, ctx); 1092 1093 if (ctx != sc->cur_chan) 1094 return; 1095 1096 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1097 if (ctx == &sc->offchannel.chan) 1098 return ath9k_set_offchannel_state(sc); 1099 #endif 1100 1101 ath9k_ps_wakeup(sc); 1102 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1103 1104 if (iter_data.has_hw_macaddr) 1105 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN); 1106 1107 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1108 ath_hw_setbssidmask(common); 1109 1110 if (iter_data.naps > 0) { 1111 cur_conf = &ctx->beacon; 1112 ath9k_hw_set_tsfadjust(ah, true); 1113 ah->opmode = NL80211_IFTYPE_AP; 1114 if (cur_conf->enable_beacon) 1115 iter_data.beacons = true; 1116 } else { 1117 ath9k_hw_set_tsfadjust(ah, false); 1118 1119 if (iter_data.nmeshes) 1120 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1121 else if (iter_data.nwds) 1122 ah->opmode = NL80211_IFTYPE_AP; 1123 else if (iter_data.nadhocs) 1124 ah->opmode = NL80211_IFTYPE_ADHOC; 1125 else 1126 ah->opmode = NL80211_IFTYPE_STATION; 1127 } 1128 1129 ath9k_hw_setopmode(ah); 1130 1131 ctx->switch_after_beacon = false; 1132 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1133 ah->imask |= ATH9K_INT_TSFOOR; 1134 else { 1135 ah->imask &= ~ATH9K_INT_TSFOOR; 1136 if (iter_data.naps == 1 && iter_data.beacons) 1137 ctx->switch_after_beacon = true; 1138 } 1139 1140 ah->imask &= ~ATH9K_INT_SWBA; 1141 if (ah->opmode == NL80211_IFTYPE_STATION) { 1142 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1143 1144 if (iter_data.primary_sta) { 1145 iter_data.beacons = true; 1146 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1147 changed); 1148 ctx->primary_sta = iter_data.primary_sta; 1149 } else { 1150 ctx->primary_sta = NULL; 1151 memset(common->curbssid, 0, ETH_ALEN); 1152 common->curaid = 0; 1153 ath9k_hw_write_associd(sc->sc_ah); 1154 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1155 ath9k_mci_update_wlan_channels(sc, true); 1156 } 1157 } else if (iter_data.beacons) { 1158 ah->imask |= ATH9K_INT_SWBA; 1159 } 1160 ath9k_hw_set_interrupts(ah); 1161 1162 if (iter_data.beacons) 1163 set_bit(ATH_OP_BEACONS, &common->op_flags); 1164 else 1165 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1166 1167 if (ah->slottime != iter_data.slottime) { 1168 ah->slottime = iter_data.slottime; 1169 ath9k_hw_init_global_settings(ah); 1170 } 1171 1172 if (iter_data.primary_sta) 1173 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1174 else 1175 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1176 1177 ath_dbg(common, CONFIG, 1178 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1179 common->macaddr, common->curbssid, common->bssidmask); 1180 1181 ath9k_ps_restore(sc); 1182 } 1183 1184 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1185 struct ieee80211_vif *vif) 1186 { 1187 int i; 1188 1189 if (!ath9k_is_chanctx_enabled()) 1190 return; 1191 1192 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1193 vif->hw_queue[i] = i; 1194 1195 if (vif->type == NL80211_IFTYPE_AP || 1196 vif->type == NL80211_IFTYPE_MESH_POINT) 1197 vif->cab_queue = hw->queues - 2; 1198 else 1199 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1200 } 1201 1202 static int ath9k_add_interface(struct ieee80211_hw *hw, 1203 struct ieee80211_vif *vif) 1204 { 1205 struct ath_softc *sc = hw->priv; 1206 struct ath_hw *ah = sc->sc_ah; 1207 struct ath_common *common = ath9k_hw_common(ah); 1208 struct ath_vif *avp = (void *)vif->drv_priv; 1209 struct ath_node *an = &avp->mcast_node; 1210 1211 mutex_lock(&sc->mutex); 1212 1213 if (config_enabled(CONFIG_ATH9K_TX99)) { 1214 if (sc->cur_chan->nvifs >= 1) { 1215 mutex_unlock(&sc->mutex); 1216 return -EOPNOTSUPP; 1217 } 1218 sc->tx99_vif = vif; 1219 } 1220 1221 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1222 sc->cur_chan->nvifs++; 1223 1224 if (ath9k_uses_beacons(vif->type)) 1225 ath9k_beacon_assign_slot(sc, vif); 1226 1227 avp->vif = vif; 1228 if (!ath9k_is_chanctx_enabled()) { 1229 avp->chanctx = sc->cur_chan; 1230 list_add_tail(&avp->list, &avp->chanctx->vifs); 1231 } 1232 1233 ath9k_calculate_summary_state(sc, avp->chanctx); 1234 1235 ath9k_assign_hw_queues(hw, vif); 1236 1237 an->sc = sc; 1238 an->sta = NULL; 1239 an->vif = vif; 1240 an->no_ps_filter = true; 1241 ath_tx_node_init(sc, an); 1242 1243 mutex_unlock(&sc->mutex); 1244 return 0; 1245 } 1246 1247 static int ath9k_change_interface(struct ieee80211_hw *hw, 1248 struct ieee80211_vif *vif, 1249 enum nl80211_iftype new_type, 1250 bool p2p) 1251 { 1252 struct ath_softc *sc = hw->priv; 1253 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1254 struct ath_vif *avp = (void *)vif->drv_priv; 1255 1256 mutex_lock(&sc->mutex); 1257 1258 if (config_enabled(CONFIG_ATH9K_TX99)) { 1259 mutex_unlock(&sc->mutex); 1260 return -EOPNOTSUPP; 1261 } 1262 1263 ath_dbg(common, CONFIG, "Change Interface\n"); 1264 1265 if (ath9k_uses_beacons(vif->type)) 1266 ath9k_beacon_remove_slot(sc, vif); 1267 1268 vif->type = new_type; 1269 vif->p2p = p2p; 1270 1271 if (ath9k_uses_beacons(vif->type)) 1272 ath9k_beacon_assign_slot(sc, vif); 1273 1274 ath9k_assign_hw_queues(hw, vif); 1275 ath9k_calculate_summary_state(sc, avp->chanctx); 1276 1277 mutex_unlock(&sc->mutex); 1278 return 0; 1279 } 1280 1281 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1282 struct ieee80211_vif *vif) 1283 { 1284 struct ath_softc *sc = hw->priv; 1285 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1286 struct ath_vif *avp = (void *)vif->drv_priv; 1287 1288 ath_dbg(common, CONFIG, "Detach Interface\n"); 1289 1290 mutex_lock(&sc->mutex); 1291 1292 ath9k_p2p_remove_vif(sc, vif); 1293 1294 sc->cur_chan->nvifs--; 1295 sc->tx99_vif = NULL; 1296 if (!ath9k_is_chanctx_enabled()) 1297 list_del(&avp->list); 1298 1299 if (ath9k_uses_beacons(vif->type)) 1300 ath9k_beacon_remove_slot(sc, vif); 1301 1302 ath_tx_node_cleanup(sc, &avp->mcast_node); 1303 1304 ath9k_calculate_summary_state(sc, avp->chanctx); 1305 1306 mutex_unlock(&sc->mutex); 1307 } 1308 1309 static void ath9k_enable_ps(struct ath_softc *sc) 1310 { 1311 struct ath_hw *ah = sc->sc_ah; 1312 struct ath_common *common = ath9k_hw_common(ah); 1313 1314 if (config_enabled(CONFIG_ATH9K_TX99)) 1315 return; 1316 1317 sc->ps_enabled = true; 1318 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1319 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1320 ah->imask |= ATH9K_INT_TIM_TIMER; 1321 ath9k_hw_set_interrupts(ah); 1322 } 1323 ath9k_hw_setrxabort(ah, 1); 1324 } 1325 ath_dbg(common, PS, "PowerSave enabled\n"); 1326 } 1327 1328 static void ath9k_disable_ps(struct ath_softc *sc) 1329 { 1330 struct ath_hw *ah = sc->sc_ah; 1331 struct ath_common *common = ath9k_hw_common(ah); 1332 1333 if (config_enabled(CONFIG_ATH9K_TX99)) 1334 return; 1335 1336 sc->ps_enabled = false; 1337 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1338 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1339 ath9k_hw_setrxabort(ah, 0); 1340 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1341 PS_WAIT_FOR_CAB | 1342 PS_WAIT_FOR_PSPOLL_DATA | 1343 PS_WAIT_FOR_TX_ACK); 1344 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1345 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1346 ath9k_hw_set_interrupts(ah); 1347 } 1348 } 1349 ath_dbg(common, PS, "PowerSave disabled\n"); 1350 } 1351 1352 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1353 { 1354 struct ath_softc *sc = hw->priv; 1355 struct ath_hw *ah = sc->sc_ah; 1356 struct ath_common *common = ath9k_hw_common(ah); 1357 struct ieee80211_conf *conf = &hw->conf; 1358 struct ath_chanctx *ctx = sc->cur_chan; 1359 1360 ath9k_ps_wakeup(sc); 1361 mutex_lock(&sc->mutex); 1362 1363 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1364 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1365 if (sc->ps_idle) { 1366 ath_cancel_work(sc); 1367 ath9k_stop_btcoex(sc); 1368 } else { 1369 ath9k_start_btcoex(sc); 1370 /* 1371 * The chip needs a reset to properly wake up from 1372 * full sleep 1373 */ 1374 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1375 } 1376 } 1377 1378 /* 1379 * We just prepare to enable PS. We have to wait until our AP has 1380 * ACK'd our null data frame to disable RX otherwise we'll ignore 1381 * those ACKs and end up retransmitting the same null data frames. 1382 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1383 */ 1384 if (changed & IEEE80211_CONF_CHANGE_PS) { 1385 unsigned long flags; 1386 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1387 if (conf->flags & IEEE80211_CONF_PS) 1388 ath9k_enable_ps(sc); 1389 else 1390 ath9k_disable_ps(sc); 1391 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1392 } 1393 1394 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1395 if (conf->flags & IEEE80211_CONF_MONITOR) { 1396 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1397 sc->sc_ah->is_monitoring = true; 1398 } else { 1399 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1400 sc->sc_ah->is_monitoring = false; 1401 } 1402 } 1403 1404 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1405 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1406 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1407 } 1408 1409 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1410 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1411 sc->cur_chan->txpower = 2 * conf->power_level; 1412 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 1413 sc->cur_chan->txpower, 1414 &sc->cur_chan->cur_txpower); 1415 } 1416 1417 mutex_unlock(&sc->mutex); 1418 ath9k_ps_restore(sc); 1419 1420 return 0; 1421 } 1422 1423 #define SUPPORTED_FILTERS \ 1424 (FIF_PROMISC_IN_BSS | \ 1425 FIF_ALLMULTI | \ 1426 FIF_CONTROL | \ 1427 FIF_PSPOLL | \ 1428 FIF_OTHER_BSS | \ 1429 FIF_BCN_PRBRESP_PROMISC | \ 1430 FIF_PROBE_REQ | \ 1431 FIF_FCSFAIL) 1432 1433 /* FIXME: sc->sc_full_reset ? */ 1434 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1435 unsigned int changed_flags, 1436 unsigned int *total_flags, 1437 u64 multicast) 1438 { 1439 struct ath_softc *sc = hw->priv; 1440 u32 rfilt; 1441 1442 changed_flags &= SUPPORTED_FILTERS; 1443 *total_flags &= SUPPORTED_FILTERS; 1444 1445 spin_lock_bh(&sc->chan_lock); 1446 sc->cur_chan->rxfilter = *total_flags; 1447 spin_unlock_bh(&sc->chan_lock); 1448 1449 ath9k_ps_wakeup(sc); 1450 rfilt = ath_calcrxfilter(sc); 1451 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1452 ath9k_ps_restore(sc); 1453 1454 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1455 rfilt); 1456 } 1457 1458 static int ath9k_sta_add(struct ieee80211_hw *hw, 1459 struct ieee80211_vif *vif, 1460 struct ieee80211_sta *sta) 1461 { 1462 struct ath_softc *sc = hw->priv; 1463 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1464 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1465 struct ieee80211_key_conf ps_key = { }; 1466 int key; 1467 1468 ath_node_attach(sc, sta, vif); 1469 1470 if (vif->type != NL80211_IFTYPE_AP && 1471 vif->type != NL80211_IFTYPE_AP_VLAN) 1472 return 0; 1473 1474 key = ath_key_config(common, vif, sta, &ps_key); 1475 if (key > 0) { 1476 an->ps_key = key; 1477 an->key_idx[0] = key; 1478 } 1479 1480 return 0; 1481 } 1482 1483 static void ath9k_del_ps_key(struct ath_softc *sc, 1484 struct ieee80211_vif *vif, 1485 struct ieee80211_sta *sta) 1486 { 1487 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1488 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1489 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1490 1491 if (!an->ps_key) 1492 return; 1493 1494 ath_key_delete(common, &ps_key); 1495 an->ps_key = 0; 1496 an->key_idx[0] = 0; 1497 } 1498 1499 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1500 struct ieee80211_vif *vif, 1501 struct ieee80211_sta *sta) 1502 { 1503 struct ath_softc *sc = hw->priv; 1504 1505 ath9k_del_ps_key(sc, vif, sta); 1506 ath_node_detach(sc, sta); 1507 1508 return 0; 1509 } 1510 1511 static int ath9k_sta_state(struct ieee80211_hw *hw, 1512 struct ieee80211_vif *vif, 1513 struct ieee80211_sta *sta, 1514 enum ieee80211_sta_state old_state, 1515 enum ieee80211_sta_state new_state) 1516 { 1517 struct ath_softc *sc = hw->priv; 1518 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1519 int ret = 0; 1520 1521 if (old_state == IEEE80211_STA_AUTH && 1522 new_state == IEEE80211_STA_ASSOC) { 1523 ret = ath9k_sta_add(hw, vif, sta); 1524 ath_dbg(common, CONFIG, 1525 "Add station: %pM\n", sta->addr); 1526 } else if (old_state == IEEE80211_STA_ASSOC && 1527 new_state == IEEE80211_STA_AUTH) { 1528 ret = ath9k_sta_remove(hw, vif, sta); 1529 ath_dbg(common, CONFIG, 1530 "Remove station: %pM\n", sta->addr); 1531 } 1532 1533 if (ath9k_is_chanctx_enabled()) { 1534 if (vif->type == NL80211_IFTYPE_STATION) { 1535 if (old_state == IEEE80211_STA_ASSOC && 1536 new_state == IEEE80211_STA_AUTHORIZED) 1537 ath_chanctx_event(sc, vif, 1538 ATH_CHANCTX_EVENT_AUTHORIZED); 1539 } 1540 } 1541 1542 return ret; 1543 } 1544 1545 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1546 struct ath_node *an, 1547 bool set) 1548 { 1549 int i; 1550 1551 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1552 if (!an->key_idx[i]) 1553 continue; 1554 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1555 } 1556 } 1557 1558 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1559 struct ieee80211_vif *vif, 1560 enum sta_notify_cmd cmd, 1561 struct ieee80211_sta *sta) 1562 { 1563 struct ath_softc *sc = hw->priv; 1564 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1565 1566 switch (cmd) { 1567 case STA_NOTIFY_SLEEP: 1568 an->sleeping = true; 1569 ath_tx_aggr_sleep(sta, sc, an); 1570 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1571 break; 1572 case STA_NOTIFY_AWAKE: 1573 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1574 an->sleeping = false; 1575 ath_tx_aggr_wakeup(sc, an); 1576 break; 1577 } 1578 } 1579 1580 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1581 struct ieee80211_vif *vif, u16 queue, 1582 const struct ieee80211_tx_queue_params *params) 1583 { 1584 struct ath_softc *sc = hw->priv; 1585 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1586 struct ath_txq *txq; 1587 struct ath9k_tx_queue_info qi; 1588 int ret = 0; 1589 1590 if (queue >= IEEE80211_NUM_ACS) 1591 return 0; 1592 1593 txq = sc->tx.txq_map[queue]; 1594 1595 ath9k_ps_wakeup(sc); 1596 mutex_lock(&sc->mutex); 1597 1598 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1599 1600 qi.tqi_aifs = params->aifs; 1601 qi.tqi_cwmin = params->cw_min; 1602 qi.tqi_cwmax = params->cw_max; 1603 qi.tqi_burstTime = params->txop * 32; 1604 1605 ath_dbg(common, CONFIG, 1606 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1607 queue, txq->axq_qnum, params->aifs, params->cw_min, 1608 params->cw_max, params->txop); 1609 1610 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1611 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1612 if (ret) 1613 ath_err(common, "TXQ Update failed\n"); 1614 1615 mutex_unlock(&sc->mutex); 1616 ath9k_ps_restore(sc); 1617 1618 return ret; 1619 } 1620 1621 static int ath9k_set_key(struct ieee80211_hw *hw, 1622 enum set_key_cmd cmd, 1623 struct ieee80211_vif *vif, 1624 struct ieee80211_sta *sta, 1625 struct ieee80211_key_conf *key) 1626 { 1627 struct ath_softc *sc = hw->priv; 1628 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1629 struct ath_node *an = NULL; 1630 int ret = 0, i; 1631 1632 if (ath9k_modparam_nohwcrypt) 1633 return -ENOSPC; 1634 1635 if ((vif->type == NL80211_IFTYPE_ADHOC || 1636 vif->type == NL80211_IFTYPE_MESH_POINT) && 1637 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1638 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1639 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1640 /* 1641 * For now, disable hw crypto for the RSN IBSS group keys. This 1642 * could be optimized in the future to use a modified key cache 1643 * design to support per-STA RX GTK, but until that gets 1644 * implemented, use of software crypto for group addressed 1645 * frames is a acceptable to allow RSN IBSS to be used. 1646 */ 1647 return -EOPNOTSUPP; 1648 } 1649 1650 mutex_lock(&sc->mutex); 1651 ath9k_ps_wakeup(sc); 1652 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1653 if (sta) 1654 an = (struct ath_node *)sta->drv_priv; 1655 1656 switch (cmd) { 1657 case SET_KEY: 1658 if (sta) 1659 ath9k_del_ps_key(sc, vif, sta); 1660 1661 key->hw_key_idx = 0; 1662 ret = ath_key_config(common, vif, sta, key); 1663 if (ret >= 0) { 1664 key->hw_key_idx = ret; 1665 /* push IV and Michael MIC generation to stack */ 1666 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1667 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1668 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1669 if (sc->sc_ah->sw_mgmt_crypto_tx && 1670 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1671 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1672 ret = 0; 1673 } 1674 if (an && key->hw_key_idx) { 1675 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1676 if (an->key_idx[i]) 1677 continue; 1678 an->key_idx[i] = key->hw_key_idx; 1679 break; 1680 } 1681 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1682 } 1683 break; 1684 case DISABLE_KEY: 1685 ath_key_delete(common, key); 1686 if (an) { 1687 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1688 if (an->key_idx[i] != key->hw_key_idx) 1689 continue; 1690 an->key_idx[i] = 0; 1691 break; 1692 } 1693 } 1694 key->hw_key_idx = 0; 1695 break; 1696 default: 1697 ret = -EINVAL; 1698 } 1699 1700 ath9k_ps_restore(sc); 1701 mutex_unlock(&sc->mutex); 1702 1703 return ret; 1704 } 1705 1706 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1707 struct ieee80211_vif *vif, 1708 struct ieee80211_bss_conf *bss_conf, 1709 u32 changed) 1710 { 1711 #define CHECK_ANI \ 1712 (BSS_CHANGED_ASSOC | \ 1713 BSS_CHANGED_IBSS | \ 1714 BSS_CHANGED_BEACON_ENABLED) 1715 1716 struct ath_softc *sc = hw->priv; 1717 struct ath_hw *ah = sc->sc_ah; 1718 struct ath_common *common = ath9k_hw_common(ah); 1719 struct ath_vif *avp = (void *)vif->drv_priv; 1720 int slottime; 1721 1722 ath9k_ps_wakeup(sc); 1723 mutex_lock(&sc->mutex); 1724 1725 if (changed & BSS_CHANGED_ASSOC) { 1726 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1727 bss_conf->bssid, bss_conf->assoc); 1728 1729 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1730 avp->aid = bss_conf->aid; 1731 avp->assoc = bss_conf->assoc; 1732 1733 ath9k_calculate_summary_state(sc, avp->chanctx); 1734 } 1735 1736 if (changed & BSS_CHANGED_IBSS) { 1737 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1738 common->curaid = bss_conf->aid; 1739 ath9k_hw_write_associd(sc->sc_ah); 1740 } 1741 1742 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1743 (changed & BSS_CHANGED_BEACON_INT) || 1744 (changed & BSS_CHANGED_BEACON_INFO)) { 1745 ath9k_beacon_config(sc, vif, changed); 1746 if (changed & BSS_CHANGED_BEACON_ENABLED) 1747 ath9k_calculate_summary_state(sc, avp->chanctx); 1748 } 1749 1750 if ((avp->chanctx == sc->cur_chan) && 1751 (changed & BSS_CHANGED_ERP_SLOT)) { 1752 if (bss_conf->use_short_slot) 1753 slottime = 9; 1754 else 1755 slottime = 20; 1756 if (vif->type == NL80211_IFTYPE_AP) { 1757 /* 1758 * Defer update, so that connected stations can adjust 1759 * their settings at the same time. 1760 * See beacon.c for more details 1761 */ 1762 sc->beacon.slottime = slottime; 1763 sc->beacon.updateslot = UPDATE; 1764 } else { 1765 ah->slottime = slottime; 1766 ath9k_hw_init_global_settings(ah); 1767 } 1768 } 1769 1770 if (changed & BSS_CHANGED_P2P_PS) 1771 ath9k_p2p_bss_info_changed(sc, vif); 1772 1773 if (changed & CHECK_ANI) 1774 ath_check_ani(sc); 1775 1776 mutex_unlock(&sc->mutex); 1777 ath9k_ps_restore(sc); 1778 1779 #undef CHECK_ANI 1780 } 1781 1782 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1783 { 1784 struct ath_softc *sc = hw->priv; 1785 u64 tsf; 1786 1787 mutex_lock(&sc->mutex); 1788 ath9k_ps_wakeup(sc); 1789 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1790 ath9k_ps_restore(sc); 1791 mutex_unlock(&sc->mutex); 1792 1793 return tsf; 1794 } 1795 1796 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1797 struct ieee80211_vif *vif, 1798 u64 tsf) 1799 { 1800 struct ath_softc *sc = hw->priv; 1801 1802 mutex_lock(&sc->mutex); 1803 ath9k_ps_wakeup(sc); 1804 ath9k_hw_settsf64(sc->sc_ah, tsf); 1805 ath9k_ps_restore(sc); 1806 mutex_unlock(&sc->mutex); 1807 } 1808 1809 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1810 { 1811 struct ath_softc *sc = hw->priv; 1812 1813 mutex_lock(&sc->mutex); 1814 1815 ath9k_ps_wakeup(sc); 1816 ath9k_hw_reset_tsf(sc->sc_ah); 1817 ath9k_ps_restore(sc); 1818 1819 mutex_unlock(&sc->mutex); 1820 } 1821 1822 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1823 struct ieee80211_vif *vif, 1824 enum ieee80211_ampdu_mlme_action action, 1825 struct ieee80211_sta *sta, 1826 u16 tid, u16 *ssn, u8 buf_size) 1827 { 1828 struct ath_softc *sc = hw->priv; 1829 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1830 bool flush = false; 1831 int ret = 0; 1832 1833 mutex_lock(&sc->mutex); 1834 1835 switch (action) { 1836 case IEEE80211_AMPDU_RX_START: 1837 break; 1838 case IEEE80211_AMPDU_RX_STOP: 1839 break; 1840 case IEEE80211_AMPDU_TX_START: 1841 if (ath9k_is_chanctx_enabled()) { 1842 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 1843 ret = -EBUSY; 1844 break; 1845 } 1846 } 1847 ath9k_ps_wakeup(sc); 1848 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1849 if (!ret) 1850 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1851 ath9k_ps_restore(sc); 1852 break; 1853 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1854 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1855 flush = true; 1856 case IEEE80211_AMPDU_TX_STOP_CONT: 1857 ath9k_ps_wakeup(sc); 1858 ath_tx_aggr_stop(sc, sta, tid); 1859 if (!flush) 1860 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1861 ath9k_ps_restore(sc); 1862 break; 1863 case IEEE80211_AMPDU_TX_OPERATIONAL: 1864 ath9k_ps_wakeup(sc); 1865 ath_tx_aggr_resume(sc, sta, tid); 1866 ath9k_ps_restore(sc); 1867 break; 1868 default: 1869 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1870 } 1871 1872 mutex_unlock(&sc->mutex); 1873 1874 return ret; 1875 } 1876 1877 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1878 struct survey_info *survey) 1879 { 1880 struct ath_softc *sc = hw->priv; 1881 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1882 struct ieee80211_supported_band *sband; 1883 struct ieee80211_channel *chan; 1884 int pos; 1885 1886 if (config_enabled(CONFIG_ATH9K_TX99)) 1887 return -EOPNOTSUPP; 1888 1889 spin_lock_bh(&common->cc_lock); 1890 if (idx == 0) 1891 ath_update_survey_stats(sc); 1892 1893 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1894 if (sband && idx >= sband->n_channels) { 1895 idx -= sband->n_channels; 1896 sband = NULL; 1897 } 1898 1899 if (!sband) 1900 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1901 1902 if (!sband || idx >= sband->n_channels) { 1903 spin_unlock_bh(&common->cc_lock); 1904 return -ENOENT; 1905 } 1906 1907 chan = &sband->channels[idx]; 1908 pos = chan->hw_value; 1909 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1910 survey->channel = chan; 1911 spin_unlock_bh(&common->cc_lock); 1912 1913 return 0; 1914 } 1915 1916 static void ath9k_enable_dynack(struct ath_softc *sc) 1917 { 1918 #ifdef CONFIG_ATH9K_DYNACK 1919 u32 rfilt; 1920 struct ath_hw *ah = sc->sc_ah; 1921 1922 ath_dynack_reset(ah); 1923 1924 ah->dynack.enabled = true; 1925 rfilt = ath_calcrxfilter(sc); 1926 ath9k_hw_setrxfilter(ah, rfilt); 1927 #endif 1928 } 1929 1930 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 1931 s16 coverage_class) 1932 { 1933 struct ath_softc *sc = hw->priv; 1934 struct ath_hw *ah = sc->sc_ah; 1935 1936 if (config_enabled(CONFIG_ATH9K_TX99)) 1937 return; 1938 1939 mutex_lock(&sc->mutex); 1940 1941 if (coverage_class >= 0) { 1942 ah->coverage_class = coverage_class; 1943 if (ah->dynack.enabled) { 1944 u32 rfilt; 1945 1946 ah->dynack.enabled = false; 1947 rfilt = ath_calcrxfilter(sc); 1948 ath9k_hw_setrxfilter(ah, rfilt); 1949 } 1950 ath9k_ps_wakeup(sc); 1951 ath9k_hw_init_global_settings(ah); 1952 ath9k_ps_restore(sc); 1953 } else if (!ah->dynack.enabled) { 1954 ath9k_enable_dynack(sc); 1955 } 1956 1957 mutex_unlock(&sc->mutex); 1958 } 1959 1960 static bool ath9k_has_tx_pending(struct ath_softc *sc, 1961 bool sw_pending) 1962 { 1963 int i, npend = 0; 1964 1965 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1966 if (!ATH_TXQ_SETUP(sc, i)) 1967 continue; 1968 1969 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i], 1970 sw_pending); 1971 if (npend) 1972 break; 1973 } 1974 1975 return !!npend; 1976 } 1977 1978 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1979 u32 queues, bool drop) 1980 { 1981 struct ath_softc *sc = hw->priv; 1982 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1983 1984 if (ath9k_is_chanctx_enabled()) { 1985 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 1986 goto flush; 1987 1988 /* 1989 * If MCC is active, extend the flush timeout 1990 * and wait for the HW/SW queues to become 1991 * empty. This needs to be done outside the 1992 * sc->mutex lock to allow the channel scheduler 1993 * to switch channel contexts. 1994 * 1995 * The vif queues have been stopped in mac80211, 1996 * so there won't be any incoming frames. 1997 */ 1998 __ath9k_flush(hw, queues, drop, true, true); 1999 return; 2000 } 2001 flush: 2002 mutex_lock(&sc->mutex); 2003 __ath9k_flush(hw, queues, drop, true, false); 2004 mutex_unlock(&sc->mutex); 2005 } 2006 2007 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, 2008 bool sw_pending, bool timeout_override) 2009 { 2010 struct ath_softc *sc = hw->priv; 2011 struct ath_hw *ah = sc->sc_ah; 2012 struct ath_common *common = ath9k_hw_common(ah); 2013 int timeout; 2014 bool drain_txq; 2015 2016 cancel_delayed_work_sync(&sc->tx_complete_work); 2017 2018 if (ah->ah_flags & AH_UNPLUGGED) { 2019 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2020 return; 2021 } 2022 2023 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2024 ath_dbg(common, ANY, "Device not present\n"); 2025 return; 2026 } 2027 2028 spin_lock_bh(&sc->chan_lock); 2029 if (timeout_override) 2030 timeout = HZ / 5; 2031 else 2032 timeout = sc->cur_chan->flush_timeout; 2033 spin_unlock_bh(&sc->chan_lock); 2034 2035 ath_dbg(common, CHAN_CTX, 2036 "Flush timeout: %d\n", jiffies_to_msecs(timeout)); 2037 2038 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending), 2039 timeout) > 0) 2040 drop = false; 2041 2042 if (drop) { 2043 ath9k_ps_wakeup(sc); 2044 spin_lock_bh(&sc->sc_pcu_lock); 2045 drain_txq = ath_drain_all_txq(sc); 2046 spin_unlock_bh(&sc->sc_pcu_lock); 2047 2048 if (!drain_txq) 2049 ath_reset(sc, NULL); 2050 2051 ath9k_ps_restore(sc); 2052 } 2053 2054 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2055 } 2056 2057 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2058 { 2059 struct ath_softc *sc = hw->priv; 2060 2061 return ath9k_has_tx_pending(sc, true); 2062 } 2063 2064 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2065 { 2066 struct ath_softc *sc = hw->priv; 2067 struct ath_hw *ah = sc->sc_ah; 2068 struct ieee80211_vif *vif; 2069 struct ath_vif *avp; 2070 struct ath_buf *bf; 2071 struct ath_tx_status ts; 2072 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2073 int status; 2074 2075 vif = sc->beacon.bslot[0]; 2076 if (!vif) 2077 return 0; 2078 2079 if (!vif->bss_conf.enable_beacon) 2080 return 0; 2081 2082 avp = (void *)vif->drv_priv; 2083 2084 if (!sc->beacon.tx_processed && !edma) { 2085 tasklet_disable(&sc->bcon_tasklet); 2086 2087 bf = avp->av_bcbuf; 2088 if (!bf || !bf->bf_mpdu) 2089 goto skip; 2090 2091 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2092 if (status == -EINPROGRESS) 2093 goto skip; 2094 2095 sc->beacon.tx_processed = true; 2096 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2097 2098 skip: 2099 tasklet_enable(&sc->bcon_tasklet); 2100 } 2101 2102 return sc->beacon.tx_last; 2103 } 2104 2105 static int ath9k_get_stats(struct ieee80211_hw *hw, 2106 struct ieee80211_low_level_stats *stats) 2107 { 2108 struct ath_softc *sc = hw->priv; 2109 struct ath_hw *ah = sc->sc_ah; 2110 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2111 2112 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2113 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2114 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2115 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2116 return 0; 2117 } 2118 2119 static u32 fill_chainmask(u32 cap, u32 new) 2120 { 2121 u32 filled = 0; 2122 int i; 2123 2124 for (i = 0; cap && new; i++, cap >>= 1) { 2125 if (!(cap & BIT(0))) 2126 continue; 2127 2128 if (new & BIT(0)) 2129 filled |= BIT(i); 2130 2131 new >>= 1; 2132 } 2133 2134 return filled; 2135 } 2136 2137 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2138 { 2139 if (AR_SREV_9300_20_OR_LATER(ah)) 2140 return true; 2141 2142 switch (val & 0x7) { 2143 case 0x1: 2144 case 0x3: 2145 case 0x7: 2146 return true; 2147 case 0x2: 2148 return (ah->caps.rx_chainmask == 1); 2149 default: 2150 return false; 2151 } 2152 } 2153 2154 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2155 { 2156 struct ath_softc *sc = hw->priv; 2157 struct ath_hw *ah = sc->sc_ah; 2158 2159 if (ah->caps.rx_chainmask != 1) 2160 rx_ant |= tx_ant; 2161 2162 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2163 return -EINVAL; 2164 2165 sc->ant_rx = rx_ant; 2166 sc->ant_tx = tx_ant; 2167 2168 if (ah->caps.rx_chainmask == 1) 2169 return 0; 2170 2171 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2172 if (AR_SREV_9100(ah)) 2173 ah->rxchainmask = 0x7; 2174 else 2175 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2176 2177 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2178 ath9k_cmn_reload_chainmask(ah); 2179 2180 return 0; 2181 } 2182 2183 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2184 { 2185 struct ath_softc *sc = hw->priv; 2186 2187 *tx_ant = sc->ant_tx; 2188 *rx_ant = sc->ant_rx; 2189 return 0; 2190 } 2191 2192 static void ath9k_sw_scan_start(struct ieee80211_hw *hw, 2193 struct ieee80211_vif *vif, 2194 const u8 *mac_addr) 2195 { 2196 struct ath_softc *sc = hw->priv; 2197 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2198 set_bit(ATH_OP_SCANNING, &common->op_flags); 2199 } 2200 2201 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, 2202 struct ieee80211_vif *vif) 2203 { 2204 struct ath_softc *sc = hw->priv; 2205 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2206 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2207 } 2208 2209 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2210 2211 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc) 2212 { 2213 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2214 2215 if (sc->offchannel.roc_vif) { 2216 ath_dbg(common, CHAN_CTX, 2217 "%s: Aborting RoC\n", __func__); 2218 2219 del_timer_sync(&sc->offchannel.timer); 2220 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2221 ath_roc_complete(sc, true); 2222 } 2223 2224 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 2225 ath_dbg(common, CHAN_CTX, 2226 "%s: Aborting HW scan\n", __func__); 2227 2228 del_timer_sync(&sc->offchannel.timer); 2229 ath_scan_complete(sc, true); 2230 } 2231 } 2232 2233 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2234 struct ieee80211_scan_request *hw_req) 2235 { 2236 struct cfg80211_scan_request *req = &hw_req->req; 2237 struct ath_softc *sc = hw->priv; 2238 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2239 int ret = 0; 2240 2241 mutex_lock(&sc->mutex); 2242 2243 if (WARN_ON(sc->offchannel.scan_req)) { 2244 ret = -EBUSY; 2245 goto out; 2246 } 2247 2248 ath9k_ps_wakeup(sc); 2249 set_bit(ATH_OP_SCANNING, &common->op_flags); 2250 sc->offchannel.scan_vif = vif; 2251 sc->offchannel.scan_req = req; 2252 sc->offchannel.scan_idx = 0; 2253 2254 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2255 vif->addr); 2256 2257 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2258 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2259 ath_offchannel_next(sc); 2260 } 2261 2262 out: 2263 mutex_unlock(&sc->mutex); 2264 2265 return ret; 2266 } 2267 2268 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2269 struct ieee80211_vif *vif) 2270 { 2271 struct ath_softc *sc = hw->priv; 2272 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2273 2274 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2275 2276 mutex_lock(&sc->mutex); 2277 del_timer_sync(&sc->offchannel.timer); 2278 ath_scan_complete(sc, true); 2279 mutex_unlock(&sc->mutex); 2280 } 2281 2282 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2283 struct ieee80211_vif *vif, 2284 struct ieee80211_channel *chan, int duration, 2285 enum ieee80211_roc_type type) 2286 { 2287 struct ath_softc *sc = hw->priv; 2288 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2289 int ret = 0; 2290 2291 mutex_lock(&sc->mutex); 2292 2293 if (WARN_ON(sc->offchannel.roc_vif)) { 2294 ret = -EBUSY; 2295 goto out; 2296 } 2297 2298 ath9k_ps_wakeup(sc); 2299 sc->offchannel.roc_vif = vif; 2300 sc->offchannel.roc_chan = chan; 2301 sc->offchannel.roc_duration = duration; 2302 2303 ath_dbg(common, CHAN_CTX, 2304 "RoC request on vif: %pM, type: %d duration: %d\n", 2305 vif->addr, type, duration); 2306 2307 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2308 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2309 ath_offchannel_next(sc); 2310 } 2311 2312 out: 2313 mutex_unlock(&sc->mutex); 2314 2315 return ret; 2316 } 2317 2318 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) 2319 { 2320 struct ath_softc *sc = hw->priv; 2321 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2322 2323 mutex_lock(&sc->mutex); 2324 2325 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2326 del_timer_sync(&sc->offchannel.timer); 2327 2328 if (sc->offchannel.roc_vif) { 2329 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2330 ath_roc_complete(sc, true); 2331 } 2332 2333 mutex_unlock(&sc->mutex); 2334 2335 return 0; 2336 } 2337 2338 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2339 struct ieee80211_chanctx_conf *conf) 2340 { 2341 struct ath_softc *sc = hw->priv; 2342 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2343 struct ath_chanctx *ctx, **ptr; 2344 int pos; 2345 2346 mutex_lock(&sc->mutex); 2347 2348 ath_for_each_chanctx(sc, ctx) { 2349 if (ctx->assigned) 2350 continue; 2351 2352 ptr = (void *) conf->drv_priv; 2353 *ptr = ctx; 2354 ctx->assigned = true; 2355 pos = ctx - &sc->chanctx[0]; 2356 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2357 2358 ath_dbg(common, CHAN_CTX, 2359 "Add channel context: %d MHz\n", 2360 conf->def.chan->center_freq); 2361 2362 ath_chanctx_set_channel(sc, ctx, &conf->def); 2363 2364 mutex_unlock(&sc->mutex); 2365 return 0; 2366 } 2367 2368 mutex_unlock(&sc->mutex); 2369 return -ENOSPC; 2370 } 2371 2372 2373 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2374 struct ieee80211_chanctx_conf *conf) 2375 { 2376 struct ath_softc *sc = hw->priv; 2377 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2378 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2379 2380 mutex_lock(&sc->mutex); 2381 2382 ath_dbg(common, CHAN_CTX, 2383 "Remove channel context: %d MHz\n", 2384 conf->def.chan->center_freq); 2385 2386 ctx->assigned = false; 2387 ctx->hw_queue_base = 0; 2388 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2389 2390 mutex_unlock(&sc->mutex); 2391 } 2392 2393 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2394 struct ieee80211_chanctx_conf *conf, 2395 u32 changed) 2396 { 2397 struct ath_softc *sc = hw->priv; 2398 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2399 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2400 2401 mutex_lock(&sc->mutex); 2402 ath_dbg(common, CHAN_CTX, 2403 "Change channel context: %d MHz\n", 2404 conf->def.chan->center_freq); 2405 ath_chanctx_set_channel(sc, ctx, &conf->def); 2406 mutex_unlock(&sc->mutex); 2407 } 2408 2409 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2410 struct ieee80211_vif *vif, 2411 struct ieee80211_chanctx_conf *conf) 2412 { 2413 struct ath_softc *sc = hw->priv; 2414 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2415 struct ath_vif *avp = (void *)vif->drv_priv; 2416 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2417 int i; 2418 2419 ath9k_cancel_pending_offchannel(sc); 2420 2421 mutex_lock(&sc->mutex); 2422 2423 ath_dbg(common, CHAN_CTX, 2424 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2425 vif->addr, vif->type, vif->p2p, 2426 conf->def.chan->center_freq); 2427 2428 avp->chanctx = ctx; 2429 ctx->nvifs_assigned++; 2430 list_add_tail(&avp->list, &ctx->vifs); 2431 ath9k_calculate_summary_state(sc, ctx); 2432 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2433 vif->hw_queue[i] = ctx->hw_queue_base + i; 2434 2435 mutex_unlock(&sc->mutex); 2436 2437 return 0; 2438 } 2439 2440 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2441 struct ieee80211_vif *vif, 2442 struct ieee80211_chanctx_conf *conf) 2443 { 2444 struct ath_softc *sc = hw->priv; 2445 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2446 struct ath_vif *avp = (void *)vif->drv_priv; 2447 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2448 int ac; 2449 2450 ath9k_cancel_pending_offchannel(sc); 2451 2452 mutex_lock(&sc->mutex); 2453 2454 ath_dbg(common, CHAN_CTX, 2455 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2456 vif->addr, vif->type, vif->p2p, 2457 conf->def.chan->center_freq); 2458 2459 avp->chanctx = NULL; 2460 ctx->nvifs_assigned--; 2461 list_del(&avp->list); 2462 ath9k_calculate_summary_state(sc, ctx); 2463 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2464 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2465 2466 mutex_unlock(&sc->mutex); 2467 } 2468 2469 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2470 struct ieee80211_vif *vif) 2471 { 2472 struct ath_softc *sc = hw->priv; 2473 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2474 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2475 struct ath_beacon_config *cur_conf; 2476 struct ath_chanctx *go_ctx; 2477 unsigned long timeout; 2478 bool changed = false; 2479 u32 beacon_int; 2480 2481 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2482 return; 2483 2484 if (!avp->chanctx) 2485 return; 2486 2487 mutex_lock(&sc->mutex); 2488 2489 spin_lock_bh(&sc->chan_lock); 2490 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) 2491 changed = true; 2492 spin_unlock_bh(&sc->chan_lock); 2493 2494 if (!changed) 2495 goto out; 2496 2497 ath9k_cancel_pending_offchannel(sc); 2498 2499 go_ctx = ath_is_go_chanctx_present(sc); 2500 2501 if (go_ctx) { 2502 /* 2503 * Wait till the GO interface gets a chance 2504 * to send out an NoA. 2505 */ 2506 spin_lock_bh(&sc->chan_lock); 2507 sc->sched.mgd_prepare_tx = true; 2508 cur_conf = &go_ctx->beacon; 2509 beacon_int = TU_TO_USEC(cur_conf->beacon_interval); 2510 spin_unlock_bh(&sc->chan_lock); 2511 2512 timeout = usecs_to_jiffies(beacon_int * 2); 2513 init_completion(&sc->go_beacon); 2514 2515 mutex_unlock(&sc->mutex); 2516 2517 if (wait_for_completion_timeout(&sc->go_beacon, 2518 timeout) == 0) { 2519 ath_dbg(common, CHAN_CTX, 2520 "Failed to send new NoA\n"); 2521 2522 spin_lock_bh(&sc->chan_lock); 2523 sc->sched.mgd_prepare_tx = false; 2524 spin_unlock_bh(&sc->chan_lock); 2525 } 2526 2527 mutex_lock(&sc->mutex); 2528 } 2529 2530 ath_dbg(common, CHAN_CTX, 2531 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n", 2532 __func__, vif->addr); 2533 2534 spin_lock_bh(&sc->chan_lock); 2535 sc->next_chan = avp->chanctx; 2536 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2537 spin_unlock_bh(&sc->chan_lock); 2538 2539 ath_chanctx_set_next(sc, true); 2540 out: 2541 mutex_unlock(&sc->mutex); 2542 } 2543 2544 void ath9k_fill_chanctx_ops(void) 2545 { 2546 if (!ath9k_is_chanctx_enabled()) 2547 return; 2548 2549 ath9k_ops.hw_scan = ath9k_hw_scan; 2550 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2551 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2552 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2553 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2554 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2555 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2556 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2557 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2558 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2559 } 2560 2561 #endif 2562 2563 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2564 int *dbm) 2565 { 2566 struct ath_softc *sc = hw->priv; 2567 struct ath_vif *avp = (void *)vif->drv_priv; 2568 2569 mutex_lock(&sc->mutex); 2570 if (avp->chanctx) 2571 *dbm = avp->chanctx->cur_txpower; 2572 else 2573 *dbm = sc->cur_chan->cur_txpower; 2574 mutex_unlock(&sc->mutex); 2575 2576 *dbm /= 2; 2577 2578 return 0; 2579 } 2580 2581 struct ieee80211_ops ath9k_ops = { 2582 .tx = ath9k_tx, 2583 .start = ath9k_start, 2584 .stop = ath9k_stop, 2585 .add_interface = ath9k_add_interface, 2586 .change_interface = ath9k_change_interface, 2587 .remove_interface = ath9k_remove_interface, 2588 .config = ath9k_config, 2589 .configure_filter = ath9k_configure_filter, 2590 .sta_state = ath9k_sta_state, 2591 .sta_notify = ath9k_sta_notify, 2592 .conf_tx = ath9k_conf_tx, 2593 .bss_info_changed = ath9k_bss_info_changed, 2594 .set_key = ath9k_set_key, 2595 .get_tsf = ath9k_get_tsf, 2596 .set_tsf = ath9k_set_tsf, 2597 .reset_tsf = ath9k_reset_tsf, 2598 .ampdu_action = ath9k_ampdu_action, 2599 .get_survey = ath9k_get_survey, 2600 .rfkill_poll = ath9k_rfkill_poll_state, 2601 .set_coverage_class = ath9k_set_coverage_class, 2602 .flush = ath9k_flush, 2603 .tx_frames_pending = ath9k_tx_frames_pending, 2604 .tx_last_beacon = ath9k_tx_last_beacon, 2605 .release_buffered_frames = ath9k_release_buffered_frames, 2606 .get_stats = ath9k_get_stats, 2607 .set_antenna = ath9k_set_antenna, 2608 .get_antenna = ath9k_get_antenna, 2609 2610 #ifdef CONFIG_ATH9K_WOW 2611 .suspend = ath9k_suspend, 2612 .resume = ath9k_resume, 2613 .set_wakeup = ath9k_set_wakeup, 2614 #endif 2615 2616 #ifdef CONFIG_ATH9K_DEBUGFS 2617 .get_et_sset_count = ath9k_get_et_sset_count, 2618 .get_et_stats = ath9k_get_et_stats, 2619 .get_et_strings = ath9k_get_et_strings, 2620 #endif 2621 2622 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2623 .sta_add_debugfs = ath9k_sta_add_debugfs, 2624 #endif 2625 .sw_scan_start = ath9k_sw_scan_start, 2626 .sw_scan_complete = ath9k_sw_scan_complete, 2627 .get_txpower = ath9k_get_txpower, 2628 }; 2629