1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth) 64 pending = true; 65 66 if (txq->mac80211_qnum >= 0) { 67 struct list_head *list; 68 69 list = &sc->cur_chan->acq[txq->mac80211_qnum]; 70 if (!list_empty(list)) 71 pending = true; 72 } 73 spin_unlock_bh(&txq->axq_lock); 74 return pending; 75 } 76 77 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 78 { 79 unsigned long flags; 80 bool ret; 81 82 spin_lock_irqsave(&sc->sc_pm_lock, flags); 83 ret = ath9k_hw_setpower(sc->sc_ah, mode); 84 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 85 86 return ret; 87 } 88 89 void ath_ps_full_sleep(unsigned long data) 90 { 91 struct ath_softc *sc = (struct ath_softc *) data; 92 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 93 bool reset; 94 95 spin_lock(&common->cc_lock); 96 ath_hw_cycle_counters_update(common); 97 spin_unlock(&common->cc_lock); 98 99 ath9k_hw_setrxabort(sc->sc_ah, 1); 100 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 101 102 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 103 } 104 105 void ath9k_ps_wakeup(struct ath_softc *sc) 106 { 107 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 108 unsigned long flags; 109 enum ath9k_power_mode power_mode; 110 111 spin_lock_irqsave(&sc->sc_pm_lock, flags); 112 if (++sc->ps_usecount != 1) 113 goto unlock; 114 115 del_timer_sync(&sc->sleep_timer); 116 power_mode = sc->sc_ah->power_mode; 117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 118 119 /* 120 * While the hardware is asleep, the cycle counters contain no 121 * useful data. Better clear them now so that they don't mess up 122 * survey data results. 123 */ 124 if (power_mode != ATH9K_PM_AWAKE) { 125 spin_lock(&common->cc_lock); 126 ath_hw_cycle_counters_update(common); 127 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 128 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 129 spin_unlock(&common->cc_lock); 130 } 131 132 unlock: 133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 134 } 135 136 void ath9k_ps_restore(struct ath_softc *sc) 137 { 138 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 139 enum ath9k_power_mode mode; 140 unsigned long flags; 141 142 spin_lock_irqsave(&sc->sc_pm_lock, flags); 143 if (--sc->ps_usecount != 0) 144 goto unlock; 145 146 if (sc->ps_idle) { 147 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 148 goto unlock; 149 } 150 151 if (sc->ps_enabled && 152 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 153 PS_WAIT_FOR_CAB | 154 PS_WAIT_FOR_PSPOLL_DATA | 155 PS_WAIT_FOR_TX_ACK | 156 PS_WAIT_FOR_ANI))) { 157 mode = ATH9K_PM_NETWORK_SLEEP; 158 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 159 ath9k_btcoex_stop_gen_timer(sc); 160 } else { 161 goto unlock; 162 } 163 164 spin_lock(&common->cc_lock); 165 ath_hw_cycle_counters_update(common); 166 spin_unlock(&common->cc_lock); 167 168 ath9k_hw_setpower(sc->sc_ah, mode); 169 170 unlock: 171 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 172 } 173 174 static void __ath_cancel_work(struct ath_softc *sc) 175 { 176 cancel_work_sync(&sc->paprd_work); 177 cancel_delayed_work_sync(&sc->tx_complete_work); 178 cancel_delayed_work_sync(&sc->hw_pll_work); 179 180 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 181 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 182 cancel_work_sync(&sc->mci_work); 183 #endif 184 } 185 186 void ath_cancel_work(struct ath_softc *sc) 187 { 188 __ath_cancel_work(sc); 189 cancel_work_sync(&sc->hw_reset_work); 190 } 191 192 void ath_restart_work(struct ath_softc *sc) 193 { 194 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 195 196 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 197 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 198 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 199 200 ath_start_ani(sc); 201 } 202 203 static bool ath_prepare_reset(struct ath_softc *sc) 204 { 205 struct ath_hw *ah = sc->sc_ah; 206 bool ret = true; 207 208 ieee80211_stop_queues(sc->hw); 209 ath_stop_ani(sc); 210 ath9k_hw_disable_interrupts(ah); 211 212 if (!ath_drain_all_txq(sc)) 213 ret = false; 214 215 if (!ath_stoprecv(sc)) 216 ret = false; 217 218 return ret; 219 } 220 221 static bool ath_complete_reset(struct ath_softc *sc, bool start) 222 { 223 struct ath_hw *ah = sc->sc_ah; 224 struct ath_common *common = ath9k_hw_common(ah); 225 unsigned long flags; 226 int i; 227 228 if (ath_startrecv(sc) != 0) { 229 ath_err(common, "Unable to restart recv logic\n"); 230 return false; 231 } 232 233 ath9k_cmn_update_txpow(ah, sc->curtxpow, 234 sc->cur_chan->txpower, &sc->curtxpow); 235 236 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 237 ath9k_calculate_summary_state(sc, sc->cur_chan); 238 239 if (!sc->cur_chan->offchannel && start) { 240 /* restore per chanctx TSF timer */ 241 if (sc->cur_chan->tsf_val) { 242 u32 offset; 243 244 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 245 NULL); 246 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 247 } 248 249 250 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 251 goto work; 252 253 if (ah->opmode == NL80211_IFTYPE_STATION && 254 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 255 spin_lock_irqsave(&sc->sc_pm_lock, flags); 256 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 257 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 258 } else { 259 ath9k_set_beacon(sc); 260 } 261 work: 262 ath_restart_work(sc); 263 ath_txq_schedule_all(sc); 264 } 265 266 sc->gtt_cnt = 0; 267 268 ath9k_hw_set_interrupts(ah); 269 ath9k_hw_enable_interrupts(ah); 270 271 if (!ath9k_use_chanctx) 272 ieee80211_wake_queues(sc->hw); 273 else { 274 if (sc->cur_chan == &sc->offchannel.chan) 275 ieee80211_wake_queue(sc->hw, 276 sc->hw->offchannel_tx_hw_queue); 277 else { 278 for (i = 0; i < IEEE80211_NUM_ACS; i++) 279 ieee80211_wake_queue(sc->hw, 280 sc->cur_chan->hw_queue_base + i); 281 } 282 if (ah->opmode == NL80211_IFTYPE_AP) 283 ieee80211_wake_queue(sc->hw, sc->hw->queues - 2); 284 } 285 286 ath9k_p2p_ps_timer(sc); 287 288 return true; 289 } 290 291 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 292 { 293 struct ath_hw *ah = sc->sc_ah; 294 struct ath_common *common = ath9k_hw_common(ah); 295 struct ath9k_hw_cal_data *caldata = NULL; 296 bool fastcc = true; 297 int r; 298 299 __ath_cancel_work(sc); 300 301 tasklet_disable(&sc->intr_tq); 302 spin_lock_bh(&sc->sc_pcu_lock); 303 304 if (!sc->cur_chan->offchannel) { 305 fastcc = false; 306 caldata = &sc->cur_chan->caldata; 307 } 308 309 if (!hchan) { 310 fastcc = false; 311 hchan = ah->curchan; 312 } 313 314 if (!ath_prepare_reset(sc)) 315 fastcc = false; 316 317 spin_lock_bh(&sc->chan_lock); 318 sc->cur_chandef = sc->cur_chan->chandef; 319 spin_unlock_bh(&sc->chan_lock); 320 321 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 322 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 323 324 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 325 if (r) { 326 ath_err(common, 327 "Unable to reset channel, reset status %d\n", r); 328 329 ath9k_hw_enable_interrupts(ah); 330 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 331 332 goto out; 333 } 334 335 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 336 sc->cur_chan->offchannel) 337 ath9k_mci_set_txpower(sc, true, false); 338 339 if (!ath_complete_reset(sc, true)) 340 r = -EIO; 341 342 out: 343 spin_unlock_bh(&sc->sc_pcu_lock); 344 tasklet_enable(&sc->intr_tq); 345 346 return r; 347 } 348 349 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 350 struct ieee80211_vif *vif) 351 { 352 struct ath_node *an; 353 an = (struct ath_node *)sta->drv_priv; 354 355 an->sc = sc; 356 an->sta = sta; 357 an->vif = vif; 358 memset(&an->key_idx, 0, sizeof(an->key_idx)); 359 360 ath_tx_node_init(sc, an); 361 } 362 363 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 364 { 365 struct ath_node *an = (struct ath_node *)sta->drv_priv; 366 ath_tx_node_cleanup(sc, an); 367 } 368 369 void ath9k_tasklet(unsigned long data) 370 { 371 struct ath_softc *sc = (struct ath_softc *)data; 372 struct ath_hw *ah = sc->sc_ah; 373 struct ath_common *common = ath9k_hw_common(ah); 374 enum ath_reset_type type; 375 unsigned long flags; 376 u32 status = sc->intrstatus; 377 u32 rxmask; 378 379 ath9k_ps_wakeup(sc); 380 spin_lock(&sc->sc_pcu_lock); 381 382 if (status & ATH9K_INT_FATAL) { 383 type = RESET_TYPE_FATAL_INT; 384 ath9k_queue_reset(sc, type); 385 386 /* 387 * Increment the ref. counter here so that 388 * interrupts are enabled in the reset routine. 389 */ 390 atomic_inc(&ah->intr_ref_cnt); 391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 392 goto out; 393 } 394 395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 396 (status & ATH9K_INT_BB_WATCHDOG)) { 397 spin_lock(&common->cc_lock); 398 ath_hw_cycle_counters_update(common); 399 ar9003_hw_bb_watchdog_dbg_info(ah); 400 spin_unlock(&common->cc_lock); 401 402 if (ar9003_hw_bb_watchdog_check(ah)) { 403 type = RESET_TYPE_BB_WATCHDOG; 404 ath9k_queue_reset(sc, type); 405 406 /* 407 * Increment the ref. counter here so that 408 * interrupts are enabled in the reset routine. 409 */ 410 atomic_inc(&ah->intr_ref_cnt); 411 ath_dbg(common, RESET, 412 "BB_WATCHDOG: Skipping interrupts\n"); 413 goto out; 414 } 415 } 416 417 if (status & ATH9K_INT_GTT) { 418 sc->gtt_cnt++; 419 420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 421 type = RESET_TYPE_TX_GTT; 422 ath9k_queue_reset(sc, type); 423 atomic_inc(&ah->intr_ref_cnt); 424 ath_dbg(common, RESET, 425 "GTT: Skipping interrupts\n"); 426 goto out; 427 } 428 } 429 430 spin_lock_irqsave(&sc->sc_pm_lock, flags); 431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 432 /* 433 * TSF sync does not look correct; remain awake to sync with 434 * the next Beacon. 435 */ 436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 438 } 439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 440 441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 443 ATH9K_INT_RXORN); 444 else 445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 446 447 if (status & rxmask) { 448 /* Check for high priority Rx first */ 449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 450 (status & ATH9K_INT_RXHP)) 451 ath_rx_tasklet(sc, 0, true); 452 453 ath_rx_tasklet(sc, 0, false); 454 } 455 456 if (status & ATH9K_INT_TX) { 457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 458 /* 459 * For EDMA chips, TX completion is enabled for the 460 * beacon queue, so if a beacon has been transmitted 461 * successfully after a GTT interrupt, the GTT counter 462 * gets reset to zero here. 463 */ 464 sc->gtt_cnt = 0; 465 466 ath_tx_edma_tasklet(sc); 467 } else { 468 ath_tx_tasklet(sc); 469 } 470 471 wake_up(&sc->tx_wait); 472 } 473 474 if (status & ATH9K_INT_GENTIMER) 475 ath_gen_timer_isr(sc->sc_ah); 476 477 ath9k_btcoex_handle_interrupt(sc, status); 478 479 /* re-enable hardware interrupt */ 480 ath9k_hw_enable_interrupts(ah); 481 out: 482 spin_unlock(&sc->sc_pcu_lock); 483 ath9k_ps_restore(sc); 484 } 485 486 irqreturn_t ath_isr(int irq, void *dev) 487 { 488 #define SCHED_INTR ( \ 489 ATH9K_INT_FATAL | \ 490 ATH9K_INT_BB_WATCHDOG | \ 491 ATH9K_INT_RXORN | \ 492 ATH9K_INT_RXEOL | \ 493 ATH9K_INT_RX | \ 494 ATH9K_INT_RXLP | \ 495 ATH9K_INT_RXHP | \ 496 ATH9K_INT_TX | \ 497 ATH9K_INT_BMISS | \ 498 ATH9K_INT_CST | \ 499 ATH9K_INT_GTT | \ 500 ATH9K_INT_TSFOOR | \ 501 ATH9K_INT_GENTIMER | \ 502 ATH9K_INT_MCI) 503 504 struct ath_softc *sc = dev; 505 struct ath_hw *ah = sc->sc_ah; 506 struct ath_common *common = ath9k_hw_common(ah); 507 enum ath9k_int status; 508 u32 sync_cause = 0; 509 bool sched = false; 510 511 /* 512 * The hardware is not ready/present, don't 513 * touch anything. Note this can happen early 514 * on if the IRQ is shared. 515 */ 516 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 517 return IRQ_NONE; 518 519 /* shared irq, not for us */ 520 521 if (!ath9k_hw_intrpend(ah)) 522 return IRQ_NONE; 523 524 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 525 ath9k_hw_kill_interrupts(ah); 526 return IRQ_HANDLED; 527 } 528 529 /* 530 * Figure out the reason(s) for the interrupt. Note 531 * that the hal returns a pseudo-ISR that may include 532 * bits we haven't explicitly enabled so we mask the 533 * value to insure we only process bits we requested. 534 */ 535 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 536 ath9k_debug_sync_cause(sc, sync_cause); 537 status &= ah->imask; /* discard unasked-for bits */ 538 539 /* 540 * If there are no status bits set, then this interrupt was not 541 * for me (should have been caught above). 542 */ 543 if (!status) 544 return IRQ_NONE; 545 546 /* Cache the status */ 547 sc->intrstatus = status; 548 549 if (status & SCHED_INTR) 550 sched = true; 551 552 /* 553 * If a FATAL or RXORN interrupt is received, we have to reset the 554 * chip immediately. 555 */ 556 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 557 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 558 goto chip_reset; 559 560 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 561 (status & ATH9K_INT_BB_WATCHDOG)) 562 goto chip_reset; 563 564 #ifdef CONFIG_ATH9K_WOW 565 if (status & ATH9K_INT_BMISS) { 566 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 567 atomic_inc(&sc->wow_got_bmiss_intr); 568 atomic_dec(&sc->wow_sleep_proc_intr); 569 } 570 } 571 #endif 572 573 if (status & ATH9K_INT_SWBA) 574 tasklet_schedule(&sc->bcon_tasklet); 575 576 if (status & ATH9K_INT_TXURN) 577 ath9k_hw_updatetxtriglevel(ah, true); 578 579 if (status & ATH9K_INT_RXEOL) { 580 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 581 ath9k_hw_set_interrupts(ah); 582 } 583 584 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 585 if (status & ATH9K_INT_TIM_TIMER) { 586 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 587 goto chip_reset; 588 /* Clear RxAbort bit so that we can 589 * receive frames */ 590 ath9k_setpower(sc, ATH9K_PM_AWAKE); 591 spin_lock(&sc->sc_pm_lock); 592 ath9k_hw_setrxabort(sc->sc_ah, 0); 593 sc->ps_flags |= PS_WAIT_FOR_BEACON; 594 spin_unlock(&sc->sc_pm_lock); 595 } 596 597 chip_reset: 598 599 ath_debug_stat_interrupt(sc, status); 600 601 if (sched) { 602 /* turn off every interrupt */ 603 ath9k_hw_disable_interrupts(ah); 604 tasklet_schedule(&sc->intr_tq); 605 } 606 607 return IRQ_HANDLED; 608 609 #undef SCHED_INTR 610 } 611 612 int ath_reset(struct ath_softc *sc) 613 { 614 int r; 615 616 ath9k_ps_wakeup(sc); 617 r = ath_reset_internal(sc, NULL); 618 ath9k_ps_restore(sc); 619 620 return r; 621 } 622 623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 624 { 625 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 626 #ifdef CONFIG_ATH9K_DEBUGFS 627 RESET_STAT_INC(sc, type); 628 #endif 629 set_bit(ATH_OP_HW_RESET, &common->op_flags); 630 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 631 } 632 633 void ath_reset_work(struct work_struct *work) 634 { 635 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 636 637 ath_reset(sc); 638 } 639 640 /**********************/ 641 /* mac80211 callbacks */ 642 /**********************/ 643 644 static int ath9k_start(struct ieee80211_hw *hw) 645 { 646 struct ath_softc *sc = hw->priv; 647 struct ath_hw *ah = sc->sc_ah; 648 struct ath_common *common = ath9k_hw_common(ah); 649 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 650 struct ath_chanctx *ctx = sc->cur_chan; 651 struct ath9k_channel *init_channel; 652 int r; 653 654 ath_dbg(common, CONFIG, 655 "Starting driver with initial channel: %d MHz\n", 656 curchan->center_freq); 657 658 ath9k_ps_wakeup(sc); 659 mutex_lock(&sc->mutex); 660 661 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 662 sc->cur_chandef = hw->conf.chandef; 663 664 /* Reset SERDES registers */ 665 ath9k_hw_configpcipowersave(ah, false); 666 667 /* 668 * The basic interface to setting the hardware in a good 669 * state is ``reset''. On return the hardware is known to 670 * be powered up and with interrupts disabled. This must 671 * be followed by initialization of the appropriate bits 672 * and then setup of the interrupt mask. 673 */ 674 spin_lock_bh(&sc->sc_pcu_lock); 675 676 atomic_set(&ah->intr_ref_cnt, -1); 677 678 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 679 if (r) { 680 ath_err(common, 681 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 682 r, curchan->center_freq); 683 ah->reset_power_on = false; 684 } 685 686 /* Setup our intr mask. */ 687 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 688 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 689 ATH9K_INT_GLOBAL; 690 691 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 692 ah->imask |= ATH9K_INT_RXHP | 693 ATH9K_INT_RXLP; 694 else 695 ah->imask |= ATH9K_INT_RX; 696 697 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 698 ah->imask |= ATH9K_INT_BB_WATCHDOG; 699 700 /* 701 * Enable GTT interrupts only for AR9003/AR9004 chips 702 * for now. 703 */ 704 if (AR_SREV_9300_20_OR_LATER(ah)) 705 ah->imask |= ATH9K_INT_GTT; 706 707 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 708 ah->imask |= ATH9K_INT_CST; 709 710 ath_mci_enable(sc); 711 712 clear_bit(ATH_OP_INVALID, &common->op_flags); 713 sc->sc_ah->is_monitoring = false; 714 715 if (!ath_complete_reset(sc, false)) 716 ah->reset_power_on = false; 717 718 if (ah->led_pin >= 0) { 719 ath9k_hw_cfg_output(ah, ah->led_pin, 720 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 721 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 722 } 723 724 /* 725 * Reset key cache to sane defaults (all entries cleared) instead of 726 * semi-random values after suspend/resume. 727 */ 728 ath9k_cmn_init_crypto(sc->sc_ah); 729 730 ath9k_hw_reset_tsf(ah); 731 732 spin_unlock_bh(&sc->sc_pcu_lock); 733 734 mutex_unlock(&sc->mutex); 735 736 ath9k_ps_restore(sc); 737 738 return 0; 739 } 740 741 static void ath9k_tx(struct ieee80211_hw *hw, 742 struct ieee80211_tx_control *control, 743 struct sk_buff *skb) 744 { 745 struct ath_softc *sc = hw->priv; 746 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 747 struct ath_tx_control txctl; 748 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 749 unsigned long flags; 750 751 if (sc->ps_enabled) { 752 /* 753 * mac80211 does not set PM field for normal data frames, so we 754 * need to update that based on the current PS mode. 755 */ 756 if (ieee80211_is_data(hdr->frame_control) && 757 !ieee80211_is_nullfunc(hdr->frame_control) && 758 !ieee80211_has_pm(hdr->frame_control)) { 759 ath_dbg(common, PS, 760 "Add PM=1 for a TX frame while in PS mode\n"); 761 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 762 } 763 } 764 765 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 766 /* 767 * We are using PS-Poll and mac80211 can request TX while in 768 * power save mode. Need to wake up hardware for the TX to be 769 * completed and if needed, also for RX of buffered frames. 770 */ 771 ath9k_ps_wakeup(sc); 772 spin_lock_irqsave(&sc->sc_pm_lock, flags); 773 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 774 ath9k_hw_setrxabort(sc->sc_ah, 0); 775 if (ieee80211_is_pspoll(hdr->frame_control)) { 776 ath_dbg(common, PS, 777 "Sending PS-Poll to pick a buffered frame\n"); 778 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 779 } else { 780 ath_dbg(common, PS, "Wake up to complete TX\n"); 781 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 782 } 783 /* 784 * The actual restore operation will happen only after 785 * the ps_flags bit is cleared. We are just dropping 786 * the ps_usecount here. 787 */ 788 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 789 ath9k_ps_restore(sc); 790 } 791 792 /* 793 * Cannot tx while the hardware is in full sleep, it first needs a full 794 * chip reset to recover from that 795 */ 796 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 797 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 798 goto exit; 799 } 800 801 memset(&txctl, 0, sizeof(struct ath_tx_control)); 802 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 803 txctl.sta = control->sta; 804 805 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 806 807 if (ath_tx_start(hw, skb, &txctl) != 0) { 808 ath_dbg(common, XMIT, "TX failed\n"); 809 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 810 goto exit; 811 } 812 813 return; 814 exit: 815 ieee80211_free_txskb(hw, skb); 816 } 817 818 static void ath9k_stop(struct ieee80211_hw *hw) 819 { 820 struct ath_softc *sc = hw->priv; 821 struct ath_hw *ah = sc->sc_ah; 822 struct ath_common *common = ath9k_hw_common(ah); 823 bool prev_idle; 824 825 cancel_work_sync(&sc->chanctx_work); 826 mutex_lock(&sc->mutex); 827 828 ath_cancel_work(sc); 829 830 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 831 ath_dbg(common, ANY, "Device not present\n"); 832 mutex_unlock(&sc->mutex); 833 return; 834 } 835 836 /* Ensure HW is awake when we try to shut it down. */ 837 ath9k_ps_wakeup(sc); 838 839 spin_lock_bh(&sc->sc_pcu_lock); 840 841 /* prevent tasklets to enable interrupts once we disable them */ 842 ah->imask &= ~ATH9K_INT_GLOBAL; 843 844 /* make sure h/w will not generate any interrupt 845 * before setting the invalid flag. */ 846 ath9k_hw_disable_interrupts(ah); 847 848 spin_unlock_bh(&sc->sc_pcu_lock); 849 850 /* we can now sync irq and kill any running tasklets, since we already 851 * disabled interrupts and not holding a spin lock */ 852 synchronize_irq(sc->irq); 853 tasklet_kill(&sc->intr_tq); 854 tasklet_kill(&sc->bcon_tasklet); 855 856 prev_idle = sc->ps_idle; 857 sc->ps_idle = true; 858 859 spin_lock_bh(&sc->sc_pcu_lock); 860 861 if (ah->led_pin >= 0) { 862 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 863 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 864 } 865 866 ath_prepare_reset(sc); 867 868 if (sc->rx.frag) { 869 dev_kfree_skb_any(sc->rx.frag); 870 sc->rx.frag = NULL; 871 } 872 873 if (!ah->curchan) 874 ah->curchan = ath9k_cmn_get_channel(hw, ah, 875 &sc->cur_chan->chandef); 876 877 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 878 ath9k_hw_phy_disable(ah); 879 880 ath9k_hw_configpcipowersave(ah, true); 881 882 spin_unlock_bh(&sc->sc_pcu_lock); 883 884 ath9k_ps_restore(sc); 885 886 set_bit(ATH_OP_INVALID, &common->op_flags); 887 sc->ps_idle = prev_idle; 888 889 mutex_unlock(&sc->mutex); 890 891 ath_dbg(common, CONFIG, "Driver halt\n"); 892 } 893 894 static bool ath9k_uses_beacons(int type) 895 { 896 switch (type) { 897 case NL80211_IFTYPE_AP: 898 case NL80211_IFTYPE_ADHOC: 899 case NL80211_IFTYPE_MESH_POINT: 900 return true; 901 default: 902 return false; 903 } 904 } 905 906 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 907 { 908 struct ath9k_vif_iter_data *iter_data = data; 909 int i; 910 911 if (iter_data->has_hw_macaddr) { 912 for (i = 0; i < ETH_ALEN; i++) 913 iter_data->mask[i] &= 914 ~(iter_data->hw_macaddr[i] ^ mac[i]); 915 } else { 916 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 917 iter_data->has_hw_macaddr = true; 918 } 919 920 if (!vif->bss_conf.use_short_slot) 921 iter_data->slottime = ATH9K_SLOT_TIME_20; 922 923 switch (vif->type) { 924 case NL80211_IFTYPE_AP: 925 iter_data->naps++; 926 if (vif->bss_conf.enable_beacon) 927 iter_data->beacons = true; 928 break; 929 case NL80211_IFTYPE_STATION: 930 iter_data->nstations++; 931 if (vif->bss_conf.assoc && !iter_data->primary_sta) 932 iter_data->primary_sta = vif; 933 break; 934 case NL80211_IFTYPE_ADHOC: 935 iter_data->nadhocs++; 936 if (vif->bss_conf.enable_beacon) 937 iter_data->beacons = true; 938 break; 939 case NL80211_IFTYPE_MESH_POINT: 940 iter_data->nmeshes++; 941 if (vif->bss_conf.enable_beacon) 942 iter_data->beacons = true; 943 break; 944 case NL80211_IFTYPE_WDS: 945 iter_data->nwds++; 946 break; 947 default: 948 break; 949 } 950 } 951 952 /* Called with sc->mutex held. */ 953 void ath9k_calculate_iter_data(struct ath_softc *sc, 954 struct ath_chanctx *ctx, 955 struct ath9k_vif_iter_data *iter_data) 956 { 957 struct ath_vif *avp; 958 959 /* 960 * Pick the MAC address of the first interface as the new hardware 961 * MAC address. The hardware will use it together with the BSSID mask 962 * when matching addresses. 963 */ 964 memset(iter_data, 0, sizeof(*iter_data)); 965 memset(&iter_data->mask, 0xff, ETH_ALEN); 966 iter_data->slottime = ATH9K_SLOT_TIME_9; 967 968 list_for_each_entry(avp, &ctx->vifs, list) 969 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 970 971 if (ctx == &sc->offchannel.chan) { 972 struct ieee80211_vif *vif; 973 974 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 975 vif = sc->offchannel.scan_vif; 976 else 977 vif = sc->offchannel.roc_vif; 978 979 if (vif) 980 ath9k_vif_iter(iter_data, vif->addr, vif); 981 iter_data->beacons = false; 982 } 983 } 984 985 static void ath9k_set_assoc_state(struct ath_softc *sc, 986 struct ieee80211_vif *vif, bool changed) 987 { 988 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 989 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 990 unsigned long flags; 991 992 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 993 /* Set the AID, BSSID and do beacon-sync only when 994 * the HW opmode is STATION. 995 * 996 * But the primary bit is set above in any case. 997 */ 998 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 999 return; 1000 1001 ether_addr_copy(common->curbssid, bss_conf->bssid); 1002 common->curaid = bss_conf->aid; 1003 ath9k_hw_write_associd(sc->sc_ah); 1004 1005 if (changed) { 1006 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1007 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1008 1009 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1010 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1011 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1012 } 1013 1014 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1015 ath9k_mci_update_wlan_channels(sc, false); 1016 1017 ath_dbg(common, CONFIG, 1018 "Primary Station interface: %pM, BSSID: %pM\n", 1019 vif->addr, common->curbssid); 1020 } 1021 1022 /* Called with sc->mutex held. */ 1023 void ath9k_calculate_summary_state(struct ath_softc *sc, 1024 struct ath_chanctx *ctx) 1025 { 1026 struct ath_hw *ah = sc->sc_ah; 1027 struct ath_common *common = ath9k_hw_common(ah); 1028 struct ath9k_vif_iter_data iter_data; 1029 1030 ath_chanctx_check_active(sc, ctx); 1031 1032 if (ctx != sc->cur_chan) 1033 return; 1034 1035 ath9k_ps_wakeup(sc); 1036 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1037 1038 if (iter_data.has_hw_macaddr) 1039 ether_addr_copy(common->macaddr, iter_data.hw_macaddr); 1040 1041 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1042 ath_hw_setbssidmask(common); 1043 1044 if (iter_data.naps > 0) { 1045 ath9k_hw_set_tsfadjust(ah, true); 1046 ah->opmode = NL80211_IFTYPE_AP; 1047 } else { 1048 ath9k_hw_set_tsfadjust(ah, false); 1049 1050 if (iter_data.nmeshes) 1051 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1052 else if (iter_data.nwds) 1053 ah->opmode = NL80211_IFTYPE_AP; 1054 else if (iter_data.nadhocs) 1055 ah->opmode = NL80211_IFTYPE_ADHOC; 1056 else 1057 ah->opmode = NL80211_IFTYPE_STATION; 1058 } 1059 1060 ath9k_hw_setopmode(ah); 1061 1062 ctx->switch_after_beacon = false; 1063 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1064 ah->imask |= ATH9K_INT_TSFOOR; 1065 else { 1066 ah->imask &= ~ATH9K_INT_TSFOOR; 1067 if (iter_data.naps == 1 && iter_data.beacons) 1068 ctx->switch_after_beacon = true; 1069 } 1070 1071 ah->imask &= ~ATH9K_INT_SWBA; 1072 if (ah->opmode == NL80211_IFTYPE_STATION) { 1073 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1074 1075 iter_data.beacons = true; 1076 if (iter_data.primary_sta) { 1077 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1078 changed); 1079 if (!ctx->primary_sta || 1080 !ctx->primary_sta->bss_conf.assoc) 1081 ctx->primary_sta = iter_data.primary_sta; 1082 } else { 1083 ctx->primary_sta = NULL; 1084 memset(common->curbssid, 0, ETH_ALEN); 1085 common->curaid = 0; 1086 ath9k_hw_write_associd(sc->sc_ah); 1087 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1088 ath9k_mci_update_wlan_channels(sc, true); 1089 } 1090 } else if (iter_data.beacons) { 1091 ah->imask |= ATH9K_INT_SWBA; 1092 } 1093 ath9k_hw_set_interrupts(ah); 1094 1095 if (iter_data.beacons) 1096 set_bit(ATH_OP_BEACONS, &common->op_flags); 1097 else 1098 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1099 1100 if (ah->slottime != iter_data.slottime) { 1101 ah->slottime = iter_data.slottime; 1102 ath9k_hw_init_global_settings(ah); 1103 } 1104 1105 if (iter_data.primary_sta) 1106 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1107 else 1108 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1109 1110 ctx->primary_sta = iter_data.primary_sta; 1111 1112 ath9k_ps_restore(sc); 1113 } 1114 1115 static int ath9k_add_interface(struct ieee80211_hw *hw, 1116 struct ieee80211_vif *vif) 1117 { 1118 struct ath_softc *sc = hw->priv; 1119 struct ath_hw *ah = sc->sc_ah; 1120 struct ath_common *common = ath9k_hw_common(ah); 1121 struct ath_vif *avp = (void *)vif->drv_priv; 1122 struct ath_node *an = &avp->mcast_node; 1123 int i; 1124 1125 mutex_lock(&sc->mutex); 1126 1127 if (config_enabled(CONFIG_ATH9K_TX99)) { 1128 if (sc->nvifs >= 1) { 1129 mutex_unlock(&sc->mutex); 1130 return -EOPNOTSUPP; 1131 } 1132 sc->tx99_vif = vif; 1133 } 1134 1135 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1136 sc->nvifs++; 1137 1138 if (ath9k_uses_beacons(vif->type)) 1139 ath9k_beacon_assign_slot(sc, vif); 1140 1141 avp->vif = vif; 1142 if (!ath9k_use_chanctx) { 1143 avp->chanctx = sc->cur_chan; 1144 list_add_tail(&avp->list, &avp->chanctx->vifs); 1145 } 1146 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1147 vif->hw_queue[i] = i; 1148 if (vif->type == NL80211_IFTYPE_AP) 1149 vif->cab_queue = hw->queues - 2; 1150 else 1151 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1152 1153 an->sc = sc; 1154 an->sta = NULL; 1155 an->vif = vif; 1156 an->no_ps_filter = true; 1157 ath_tx_node_init(sc, an); 1158 1159 mutex_unlock(&sc->mutex); 1160 return 0; 1161 } 1162 1163 static int ath9k_change_interface(struct ieee80211_hw *hw, 1164 struct ieee80211_vif *vif, 1165 enum nl80211_iftype new_type, 1166 bool p2p) 1167 { 1168 struct ath_softc *sc = hw->priv; 1169 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1170 struct ath_vif *avp = (void *)vif->drv_priv; 1171 int i; 1172 1173 mutex_lock(&sc->mutex); 1174 1175 if (config_enabled(CONFIG_ATH9K_TX99)) { 1176 mutex_unlock(&sc->mutex); 1177 return -EOPNOTSUPP; 1178 } 1179 1180 ath_dbg(common, CONFIG, "Change Interface\n"); 1181 1182 if (ath9k_uses_beacons(vif->type)) 1183 ath9k_beacon_remove_slot(sc, vif); 1184 1185 vif->type = new_type; 1186 vif->p2p = p2p; 1187 1188 if (ath9k_uses_beacons(vif->type)) 1189 ath9k_beacon_assign_slot(sc, vif); 1190 1191 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1192 vif->hw_queue[i] = i; 1193 1194 if (vif->type == NL80211_IFTYPE_AP) 1195 vif->cab_queue = hw->queues - 2; 1196 else 1197 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1198 1199 ath9k_calculate_summary_state(sc, avp->chanctx); 1200 1201 mutex_unlock(&sc->mutex); 1202 return 0; 1203 } 1204 1205 static void 1206 ath9k_update_p2p_ps_timer(struct ath_softc *sc, struct ath_vif *avp) 1207 { 1208 struct ath_hw *ah = sc->sc_ah; 1209 s32 tsf, target_tsf; 1210 1211 if (!avp || !avp->noa.has_next_tsf) 1212 return; 1213 1214 ath9k_hw_gen_timer_stop(ah, sc->p2p_ps_timer); 1215 1216 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1217 1218 target_tsf = avp->noa.next_tsf; 1219 if (!avp->noa.absent) 1220 target_tsf -= ATH_P2P_PS_STOP_TIME; 1221 1222 if (target_tsf - tsf < ATH_P2P_PS_STOP_TIME) 1223 target_tsf = tsf + ATH_P2P_PS_STOP_TIME; 1224 1225 ath9k_hw_gen_timer_start(ah, sc->p2p_ps_timer, (u32) target_tsf, 1000000); 1226 } 1227 1228 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1229 struct ieee80211_vif *vif) 1230 { 1231 struct ath_softc *sc = hw->priv; 1232 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1233 struct ath_vif *avp = (void *)vif->drv_priv; 1234 1235 ath_dbg(common, CONFIG, "Detach Interface\n"); 1236 1237 mutex_lock(&sc->mutex); 1238 1239 spin_lock_bh(&sc->sc_pcu_lock); 1240 if (avp == sc->p2p_ps_vif) { 1241 sc->p2p_ps_vif = NULL; 1242 ath9k_update_p2p_ps_timer(sc, NULL); 1243 } 1244 spin_unlock_bh(&sc->sc_pcu_lock); 1245 1246 sc->nvifs--; 1247 sc->tx99_vif = NULL; 1248 if (!ath9k_use_chanctx) 1249 list_del(&avp->list); 1250 1251 if (ath9k_uses_beacons(vif->type)) 1252 ath9k_beacon_remove_slot(sc, vif); 1253 1254 ath_tx_node_cleanup(sc, &avp->mcast_node); 1255 1256 mutex_unlock(&sc->mutex); 1257 } 1258 1259 static void ath9k_enable_ps(struct ath_softc *sc) 1260 { 1261 struct ath_hw *ah = sc->sc_ah; 1262 struct ath_common *common = ath9k_hw_common(ah); 1263 1264 if (config_enabled(CONFIG_ATH9K_TX99)) 1265 return; 1266 1267 sc->ps_enabled = true; 1268 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1269 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1270 ah->imask |= ATH9K_INT_TIM_TIMER; 1271 ath9k_hw_set_interrupts(ah); 1272 } 1273 ath9k_hw_setrxabort(ah, 1); 1274 } 1275 ath_dbg(common, PS, "PowerSave enabled\n"); 1276 } 1277 1278 static void ath9k_disable_ps(struct ath_softc *sc) 1279 { 1280 struct ath_hw *ah = sc->sc_ah; 1281 struct ath_common *common = ath9k_hw_common(ah); 1282 1283 if (config_enabled(CONFIG_ATH9K_TX99)) 1284 return; 1285 1286 sc->ps_enabled = false; 1287 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1288 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1289 ath9k_hw_setrxabort(ah, 0); 1290 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1291 PS_WAIT_FOR_CAB | 1292 PS_WAIT_FOR_PSPOLL_DATA | 1293 PS_WAIT_FOR_TX_ACK); 1294 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1295 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1296 ath9k_hw_set_interrupts(ah); 1297 } 1298 } 1299 ath_dbg(common, PS, "PowerSave disabled\n"); 1300 } 1301 1302 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1303 { 1304 struct ath_softc *sc = hw->priv; 1305 struct ath_hw *ah = sc->sc_ah; 1306 struct ath_common *common = ath9k_hw_common(ah); 1307 u32 rxfilter; 1308 1309 if (config_enabled(CONFIG_ATH9K_TX99)) 1310 return; 1311 1312 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1313 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1314 return; 1315 } 1316 1317 ath9k_ps_wakeup(sc); 1318 rxfilter = ath9k_hw_getrxfilter(ah); 1319 ath9k_hw_setrxfilter(ah, rxfilter | 1320 ATH9K_RX_FILTER_PHYRADAR | 1321 ATH9K_RX_FILTER_PHYERR); 1322 1323 /* TODO: usually this should not be neccesary, but for some reason 1324 * (or in some mode?) the trigger must be called after the 1325 * configuration, otherwise the register will have its values reset 1326 * (on my ar9220 to value 0x01002310) 1327 */ 1328 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1329 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1330 ath9k_ps_restore(sc); 1331 } 1332 1333 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1334 enum spectral_mode spectral_mode) 1335 { 1336 struct ath_softc *sc = hw->priv; 1337 struct ath_hw *ah = sc->sc_ah; 1338 struct ath_common *common = ath9k_hw_common(ah); 1339 1340 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1341 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1342 return -1; 1343 } 1344 1345 switch (spectral_mode) { 1346 case SPECTRAL_DISABLED: 1347 sc->spec_config.enabled = 0; 1348 break; 1349 case SPECTRAL_BACKGROUND: 1350 /* send endless samples. 1351 * TODO: is this really useful for "background"? 1352 */ 1353 sc->spec_config.endless = 1; 1354 sc->spec_config.enabled = 1; 1355 break; 1356 case SPECTRAL_CHANSCAN: 1357 case SPECTRAL_MANUAL: 1358 sc->spec_config.endless = 0; 1359 sc->spec_config.enabled = 1; 1360 break; 1361 default: 1362 return -1; 1363 } 1364 1365 ath9k_ps_wakeup(sc); 1366 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1367 ath9k_ps_restore(sc); 1368 1369 sc->spectral_mode = spectral_mode; 1370 1371 return 0; 1372 } 1373 1374 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1375 { 1376 struct ath_softc *sc = hw->priv; 1377 struct ath_hw *ah = sc->sc_ah; 1378 struct ath_common *common = ath9k_hw_common(ah); 1379 struct ieee80211_conf *conf = &hw->conf; 1380 struct ath_chanctx *ctx = sc->cur_chan; 1381 1382 ath9k_ps_wakeup(sc); 1383 mutex_lock(&sc->mutex); 1384 1385 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1386 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1387 if (sc->ps_idle) { 1388 ath_cancel_work(sc); 1389 ath9k_stop_btcoex(sc); 1390 } else { 1391 ath9k_start_btcoex(sc); 1392 /* 1393 * The chip needs a reset to properly wake up from 1394 * full sleep 1395 */ 1396 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1397 } 1398 } 1399 1400 /* 1401 * We just prepare to enable PS. We have to wait until our AP has 1402 * ACK'd our null data frame to disable RX otherwise we'll ignore 1403 * those ACKs and end up retransmitting the same null data frames. 1404 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1405 */ 1406 if (changed & IEEE80211_CONF_CHANGE_PS) { 1407 unsigned long flags; 1408 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1409 if (conf->flags & IEEE80211_CONF_PS) 1410 ath9k_enable_ps(sc); 1411 else 1412 ath9k_disable_ps(sc); 1413 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1414 } 1415 1416 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1417 if (conf->flags & IEEE80211_CONF_MONITOR) { 1418 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1419 sc->sc_ah->is_monitoring = true; 1420 } else { 1421 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1422 sc->sc_ah->is_monitoring = false; 1423 } 1424 } 1425 1426 if (!ath9k_use_chanctx && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1427 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1428 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1429 } 1430 1431 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1432 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1433 sc->cur_chan->txpower = 2 * conf->power_level; 1434 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1435 sc->cur_chan->txpower, &sc->curtxpow); 1436 } 1437 1438 mutex_unlock(&sc->mutex); 1439 ath9k_ps_restore(sc); 1440 1441 return 0; 1442 } 1443 1444 #define SUPPORTED_FILTERS \ 1445 (FIF_PROMISC_IN_BSS | \ 1446 FIF_ALLMULTI | \ 1447 FIF_CONTROL | \ 1448 FIF_PSPOLL | \ 1449 FIF_OTHER_BSS | \ 1450 FIF_BCN_PRBRESP_PROMISC | \ 1451 FIF_PROBE_REQ | \ 1452 FIF_FCSFAIL) 1453 1454 /* FIXME: sc->sc_full_reset ? */ 1455 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1456 unsigned int changed_flags, 1457 unsigned int *total_flags, 1458 u64 multicast) 1459 { 1460 struct ath_softc *sc = hw->priv; 1461 u32 rfilt; 1462 1463 changed_flags &= SUPPORTED_FILTERS; 1464 *total_flags &= SUPPORTED_FILTERS; 1465 1466 sc->rx.rxfilter = *total_flags; 1467 ath9k_ps_wakeup(sc); 1468 rfilt = ath_calcrxfilter(sc); 1469 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1470 ath9k_ps_restore(sc); 1471 1472 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1473 rfilt); 1474 } 1475 1476 static int ath9k_sta_add(struct ieee80211_hw *hw, 1477 struct ieee80211_vif *vif, 1478 struct ieee80211_sta *sta) 1479 { 1480 struct ath_softc *sc = hw->priv; 1481 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1482 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1483 struct ieee80211_key_conf ps_key = { }; 1484 int key; 1485 1486 ath_node_attach(sc, sta, vif); 1487 1488 if (vif->type != NL80211_IFTYPE_AP && 1489 vif->type != NL80211_IFTYPE_AP_VLAN) 1490 return 0; 1491 1492 key = ath_key_config(common, vif, sta, &ps_key); 1493 if (key > 0) { 1494 an->ps_key = key; 1495 an->key_idx[0] = key; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void ath9k_del_ps_key(struct ath_softc *sc, 1502 struct ieee80211_vif *vif, 1503 struct ieee80211_sta *sta) 1504 { 1505 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1506 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1507 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1508 1509 if (!an->ps_key) 1510 return; 1511 1512 ath_key_delete(common, &ps_key); 1513 an->ps_key = 0; 1514 an->key_idx[0] = 0; 1515 } 1516 1517 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1518 struct ieee80211_vif *vif, 1519 struct ieee80211_sta *sta) 1520 { 1521 struct ath_softc *sc = hw->priv; 1522 1523 ath9k_del_ps_key(sc, vif, sta); 1524 ath_node_detach(sc, sta); 1525 1526 return 0; 1527 } 1528 1529 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1530 struct ath_node *an, 1531 bool set) 1532 { 1533 int i; 1534 1535 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1536 if (!an->key_idx[i]) 1537 continue; 1538 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1539 } 1540 } 1541 1542 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1543 struct ieee80211_vif *vif, 1544 enum sta_notify_cmd cmd, 1545 struct ieee80211_sta *sta) 1546 { 1547 struct ath_softc *sc = hw->priv; 1548 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1549 1550 switch (cmd) { 1551 case STA_NOTIFY_SLEEP: 1552 an->sleeping = true; 1553 ath_tx_aggr_sleep(sta, sc, an); 1554 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1555 break; 1556 case STA_NOTIFY_AWAKE: 1557 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1558 an->sleeping = false; 1559 ath_tx_aggr_wakeup(sc, an); 1560 break; 1561 } 1562 } 1563 1564 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1565 struct ieee80211_vif *vif, u16 queue, 1566 const struct ieee80211_tx_queue_params *params) 1567 { 1568 struct ath_softc *sc = hw->priv; 1569 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1570 struct ath_txq *txq; 1571 struct ath9k_tx_queue_info qi; 1572 int ret = 0; 1573 1574 if (queue >= IEEE80211_NUM_ACS) 1575 return 0; 1576 1577 txq = sc->tx.txq_map[queue]; 1578 1579 ath9k_ps_wakeup(sc); 1580 mutex_lock(&sc->mutex); 1581 1582 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1583 1584 qi.tqi_aifs = params->aifs; 1585 qi.tqi_cwmin = params->cw_min; 1586 qi.tqi_cwmax = params->cw_max; 1587 qi.tqi_burstTime = params->txop * 32; 1588 1589 ath_dbg(common, CONFIG, 1590 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1591 queue, txq->axq_qnum, params->aifs, params->cw_min, 1592 params->cw_max, params->txop); 1593 1594 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1595 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1596 if (ret) 1597 ath_err(common, "TXQ Update failed\n"); 1598 1599 mutex_unlock(&sc->mutex); 1600 ath9k_ps_restore(sc); 1601 1602 return ret; 1603 } 1604 1605 static int ath9k_set_key(struct ieee80211_hw *hw, 1606 enum set_key_cmd cmd, 1607 struct ieee80211_vif *vif, 1608 struct ieee80211_sta *sta, 1609 struct ieee80211_key_conf *key) 1610 { 1611 struct ath_softc *sc = hw->priv; 1612 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1613 struct ath_node *an = NULL; 1614 int ret = 0, i; 1615 1616 if (ath9k_modparam_nohwcrypt) 1617 return -ENOSPC; 1618 1619 if ((vif->type == NL80211_IFTYPE_ADHOC || 1620 vif->type == NL80211_IFTYPE_MESH_POINT) && 1621 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1622 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1623 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1624 /* 1625 * For now, disable hw crypto for the RSN IBSS group keys. This 1626 * could be optimized in the future to use a modified key cache 1627 * design to support per-STA RX GTK, but until that gets 1628 * implemented, use of software crypto for group addressed 1629 * frames is a acceptable to allow RSN IBSS to be used. 1630 */ 1631 return -EOPNOTSUPP; 1632 } 1633 1634 mutex_lock(&sc->mutex); 1635 ath9k_ps_wakeup(sc); 1636 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1637 if (sta) 1638 an = (struct ath_node *)sta->drv_priv; 1639 1640 switch (cmd) { 1641 case SET_KEY: 1642 if (sta) 1643 ath9k_del_ps_key(sc, vif, sta); 1644 1645 key->hw_key_idx = 0; 1646 ret = ath_key_config(common, vif, sta, key); 1647 if (ret >= 0) { 1648 key->hw_key_idx = ret; 1649 /* push IV and Michael MIC generation to stack */ 1650 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1651 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1652 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1653 if (sc->sc_ah->sw_mgmt_crypto && 1654 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1655 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1656 ret = 0; 1657 } 1658 if (an && key->hw_key_idx) { 1659 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1660 if (an->key_idx[i]) 1661 continue; 1662 an->key_idx[i] = key->hw_key_idx; 1663 break; 1664 } 1665 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1666 } 1667 break; 1668 case DISABLE_KEY: 1669 ath_key_delete(common, key); 1670 if (an) { 1671 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1672 if (an->key_idx[i] != key->hw_key_idx) 1673 continue; 1674 an->key_idx[i] = 0; 1675 break; 1676 } 1677 } 1678 key->hw_key_idx = 0; 1679 break; 1680 default: 1681 ret = -EINVAL; 1682 } 1683 1684 ath9k_ps_restore(sc); 1685 mutex_unlock(&sc->mutex); 1686 1687 return ret; 1688 } 1689 1690 void ath9k_p2p_ps_timer(void *priv) 1691 { 1692 struct ath_softc *sc = priv; 1693 struct ath_vif *avp = sc->p2p_ps_vif; 1694 struct ieee80211_vif *vif; 1695 struct ieee80211_sta *sta; 1696 struct ath_node *an; 1697 u32 tsf; 1698 1699 del_timer_sync(&sc->sched.timer); 1700 ath9k_hw_gen_timer_stop(sc->sc_ah, sc->p2p_ps_timer); 1701 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_TSF_TIMER); 1702 1703 if (!avp || avp->chanctx != sc->cur_chan) 1704 return; 1705 1706 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1707 if (!avp->noa.absent) 1708 tsf += ATH_P2P_PS_STOP_TIME; 1709 1710 if (!avp->noa.has_next_tsf || 1711 avp->noa.next_tsf - tsf > BIT(31)) 1712 ieee80211_update_p2p_noa(&avp->noa, tsf); 1713 1714 ath9k_update_p2p_ps_timer(sc, avp); 1715 1716 rcu_read_lock(); 1717 1718 vif = avp->vif; 1719 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 1720 if (!sta) 1721 goto out; 1722 1723 an = (void *) sta->drv_priv; 1724 if (an->sleeping == !!avp->noa.absent) 1725 goto out; 1726 1727 an->sleeping = avp->noa.absent; 1728 if (an->sleeping) 1729 ath_tx_aggr_sleep(sta, sc, an); 1730 else 1731 ath_tx_aggr_wakeup(sc, an); 1732 1733 out: 1734 rcu_read_unlock(); 1735 } 1736 1737 void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif) 1738 { 1739 struct ath_vif *avp = (void *)vif->drv_priv; 1740 u32 tsf; 1741 1742 if (!sc->p2p_ps_timer) 1743 return; 1744 1745 if (vif->type != NL80211_IFTYPE_STATION || !vif->p2p) 1746 return; 1747 1748 sc->p2p_ps_vif = avp; 1749 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1750 ieee80211_parse_p2p_noa(&vif->bss_conf.p2p_noa_attr, &avp->noa, tsf); 1751 ath9k_update_p2p_ps_timer(sc, avp); 1752 } 1753 1754 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1755 struct ieee80211_vif *vif, 1756 struct ieee80211_bss_conf *bss_conf, 1757 u32 changed) 1758 { 1759 #define CHECK_ANI \ 1760 (BSS_CHANGED_ASSOC | \ 1761 BSS_CHANGED_IBSS | \ 1762 BSS_CHANGED_BEACON_ENABLED) 1763 1764 struct ath_softc *sc = hw->priv; 1765 struct ath_hw *ah = sc->sc_ah; 1766 struct ath_common *common = ath9k_hw_common(ah); 1767 struct ath_vif *avp = (void *)vif->drv_priv; 1768 unsigned long flags; 1769 int slottime; 1770 1771 ath9k_ps_wakeup(sc); 1772 mutex_lock(&sc->mutex); 1773 1774 if (changed & BSS_CHANGED_ASSOC) { 1775 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1776 bss_conf->bssid, bss_conf->assoc); 1777 1778 ath9k_calculate_summary_state(sc, avp->chanctx); 1779 if (bss_conf->assoc) 1780 ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_ASSOC); 1781 } 1782 1783 if (changed & BSS_CHANGED_IBSS) { 1784 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1785 common->curaid = bss_conf->aid; 1786 ath9k_hw_write_associd(sc->sc_ah); 1787 } 1788 1789 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1790 (changed & BSS_CHANGED_BEACON_INT) || 1791 (changed & BSS_CHANGED_BEACON_INFO)) { 1792 if (changed & BSS_CHANGED_BEACON_ENABLED) 1793 ath9k_calculate_summary_state(sc, avp->chanctx); 1794 ath9k_beacon_config(sc, vif, changed); 1795 } 1796 1797 if ((avp->chanctx == sc->cur_chan) && 1798 (changed & BSS_CHANGED_ERP_SLOT)) { 1799 if (bss_conf->use_short_slot) 1800 slottime = 9; 1801 else 1802 slottime = 20; 1803 if (vif->type == NL80211_IFTYPE_AP) { 1804 /* 1805 * Defer update, so that connected stations can adjust 1806 * their settings at the same time. 1807 * See beacon.c for more details 1808 */ 1809 sc->beacon.slottime = slottime; 1810 sc->beacon.updateslot = UPDATE; 1811 } else { 1812 ah->slottime = slottime; 1813 ath9k_hw_init_global_settings(ah); 1814 } 1815 } 1816 1817 if (changed & BSS_CHANGED_P2P_PS) { 1818 spin_lock_bh(&sc->sc_pcu_lock); 1819 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1820 if (!(sc->ps_flags & PS_BEACON_SYNC)) 1821 ath9k_update_p2p_ps(sc, vif); 1822 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1823 spin_unlock_bh(&sc->sc_pcu_lock); 1824 } 1825 1826 if (changed & CHECK_ANI) 1827 ath_check_ani(sc); 1828 1829 mutex_unlock(&sc->mutex); 1830 ath9k_ps_restore(sc); 1831 1832 #undef CHECK_ANI 1833 } 1834 1835 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1836 { 1837 struct ath_softc *sc = hw->priv; 1838 u64 tsf; 1839 1840 mutex_lock(&sc->mutex); 1841 ath9k_ps_wakeup(sc); 1842 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1843 ath9k_ps_restore(sc); 1844 mutex_unlock(&sc->mutex); 1845 1846 return tsf; 1847 } 1848 1849 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1850 struct ieee80211_vif *vif, 1851 u64 tsf) 1852 { 1853 struct ath_softc *sc = hw->priv; 1854 1855 mutex_lock(&sc->mutex); 1856 ath9k_ps_wakeup(sc); 1857 ath9k_hw_settsf64(sc->sc_ah, tsf); 1858 ath9k_ps_restore(sc); 1859 mutex_unlock(&sc->mutex); 1860 } 1861 1862 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1863 { 1864 struct ath_softc *sc = hw->priv; 1865 1866 mutex_lock(&sc->mutex); 1867 1868 ath9k_ps_wakeup(sc); 1869 ath9k_hw_reset_tsf(sc->sc_ah); 1870 ath9k_ps_restore(sc); 1871 1872 mutex_unlock(&sc->mutex); 1873 } 1874 1875 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1876 struct ieee80211_vif *vif, 1877 enum ieee80211_ampdu_mlme_action action, 1878 struct ieee80211_sta *sta, 1879 u16 tid, u16 *ssn, u8 buf_size) 1880 { 1881 struct ath_softc *sc = hw->priv; 1882 bool flush = false; 1883 int ret = 0; 1884 1885 mutex_lock(&sc->mutex); 1886 1887 switch (action) { 1888 case IEEE80211_AMPDU_RX_START: 1889 break; 1890 case IEEE80211_AMPDU_RX_STOP: 1891 break; 1892 case IEEE80211_AMPDU_TX_START: 1893 ath9k_ps_wakeup(sc); 1894 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1895 if (!ret) 1896 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1897 ath9k_ps_restore(sc); 1898 break; 1899 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1900 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1901 flush = true; 1902 case IEEE80211_AMPDU_TX_STOP_CONT: 1903 ath9k_ps_wakeup(sc); 1904 ath_tx_aggr_stop(sc, sta, tid); 1905 if (!flush) 1906 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1907 ath9k_ps_restore(sc); 1908 break; 1909 case IEEE80211_AMPDU_TX_OPERATIONAL: 1910 ath9k_ps_wakeup(sc); 1911 ath_tx_aggr_resume(sc, sta, tid); 1912 ath9k_ps_restore(sc); 1913 break; 1914 default: 1915 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1916 } 1917 1918 mutex_unlock(&sc->mutex); 1919 1920 return ret; 1921 } 1922 1923 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1924 struct survey_info *survey) 1925 { 1926 struct ath_softc *sc = hw->priv; 1927 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1928 struct ieee80211_supported_band *sband; 1929 struct ieee80211_channel *chan; 1930 int pos; 1931 1932 if (config_enabled(CONFIG_ATH9K_TX99)) 1933 return -EOPNOTSUPP; 1934 1935 spin_lock_bh(&common->cc_lock); 1936 if (idx == 0) 1937 ath_update_survey_stats(sc); 1938 1939 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1940 if (sband && idx >= sband->n_channels) { 1941 idx -= sband->n_channels; 1942 sband = NULL; 1943 } 1944 1945 if (!sband) 1946 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1947 1948 if (!sband || idx >= sband->n_channels) { 1949 spin_unlock_bh(&common->cc_lock); 1950 return -ENOENT; 1951 } 1952 1953 chan = &sband->channels[idx]; 1954 pos = chan->hw_value; 1955 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1956 survey->channel = chan; 1957 spin_unlock_bh(&common->cc_lock); 1958 1959 return 0; 1960 } 1961 1962 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1963 { 1964 struct ath_softc *sc = hw->priv; 1965 struct ath_hw *ah = sc->sc_ah; 1966 1967 if (config_enabled(CONFIG_ATH9K_TX99)) 1968 return; 1969 1970 mutex_lock(&sc->mutex); 1971 ah->coverage_class = coverage_class; 1972 1973 ath9k_ps_wakeup(sc); 1974 ath9k_hw_init_global_settings(ah); 1975 ath9k_ps_restore(sc); 1976 1977 mutex_unlock(&sc->mutex); 1978 } 1979 1980 static bool ath9k_has_tx_pending(struct ath_softc *sc) 1981 { 1982 int i, npend = 0; 1983 1984 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1985 if (!ATH_TXQ_SETUP(sc, i)) 1986 continue; 1987 1988 if (!sc->tx.txq[i].axq_depth) 1989 continue; 1990 1991 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1992 if (npend) 1993 break; 1994 } 1995 1996 return !!npend; 1997 } 1998 1999 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2000 u32 queues, bool drop) 2001 { 2002 struct ath_softc *sc = hw->priv; 2003 2004 mutex_lock(&sc->mutex); 2005 __ath9k_flush(hw, queues, drop); 2006 mutex_unlock(&sc->mutex); 2007 } 2008 2009 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 2010 { 2011 struct ath_softc *sc = hw->priv; 2012 struct ath_hw *ah = sc->sc_ah; 2013 struct ath_common *common = ath9k_hw_common(ah); 2014 int timeout = HZ / 5; /* 200 ms */ 2015 bool drain_txq; 2016 int i; 2017 2018 cancel_delayed_work_sync(&sc->tx_complete_work); 2019 2020 if (ah->ah_flags & AH_UNPLUGGED) { 2021 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2022 return; 2023 } 2024 2025 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2026 ath_dbg(common, ANY, "Device not present\n"); 2027 return; 2028 } 2029 2030 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 2031 timeout) > 0) 2032 drop = false; 2033 2034 if (drop) { 2035 ath9k_ps_wakeup(sc); 2036 spin_lock_bh(&sc->sc_pcu_lock); 2037 drain_txq = ath_drain_all_txq(sc); 2038 spin_unlock_bh(&sc->sc_pcu_lock); 2039 2040 if (!drain_txq) 2041 ath_reset(sc); 2042 2043 ath9k_ps_restore(sc); 2044 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2045 ieee80211_wake_queue(sc->hw, 2046 sc->cur_chan->hw_queue_base + i); 2047 } 2048 } 2049 2050 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2051 } 2052 2053 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2054 { 2055 struct ath_softc *sc = hw->priv; 2056 int i; 2057 2058 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2059 if (!ATH_TXQ_SETUP(sc, i)) 2060 continue; 2061 2062 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 2063 return true; 2064 } 2065 return false; 2066 } 2067 2068 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2069 { 2070 struct ath_softc *sc = hw->priv; 2071 struct ath_hw *ah = sc->sc_ah; 2072 struct ieee80211_vif *vif; 2073 struct ath_vif *avp; 2074 struct ath_buf *bf; 2075 struct ath_tx_status ts; 2076 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2077 int status; 2078 2079 vif = sc->beacon.bslot[0]; 2080 if (!vif) 2081 return 0; 2082 2083 if (!vif->bss_conf.enable_beacon) 2084 return 0; 2085 2086 avp = (void *)vif->drv_priv; 2087 2088 if (!sc->beacon.tx_processed && !edma) { 2089 tasklet_disable(&sc->bcon_tasklet); 2090 2091 bf = avp->av_bcbuf; 2092 if (!bf || !bf->bf_mpdu) 2093 goto skip; 2094 2095 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2096 if (status == -EINPROGRESS) 2097 goto skip; 2098 2099 sc->beacon.tx_processed = true; 2100 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2101 2102 skip: 2103 tasklet_enable(&sc->bcon_tasklet); 2104 } 2105 2106 return sc->beacon.tx_last; 2107 } 2108 2109 static int ath9k_get_stats(struct ieee80211_hw *hw, 2110 struct ieee80211_low_level_stats *stats) 2111 { 2112 struct ath_softc *sc = hw->priv; 2113 struct ath_hw *ah = sc->sc_ah; 2114 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2115 2116 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2117 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2118 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2119 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2120 return 0; 2121 } 2122 2123 static u32 fill_chainmask(u32 cap, u32 new) 2124 { 2125 u32 filled = 0; 2126 int i; 2127 2128 for (i = 0; cap && new; i++, cap >>= 1) { 2129 if (!(cap & BIT(0))) 2130 continue; 2131 2132 if (new & BIT(0)) 2133 filled |= BIT(i); 2134 2135 new >>= 1; 2136 } 2137 2138 return filled; 2139 } 2140 2141 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2142 { 2143 if (AR_SREV_9300_20_OR_LATER(ah)) 2144 return true; 2145 2146 switch (val & 0x7) { 2147 case 0x1: 2148 case 0x3: 2149 case 0x7: 2150 return true; 2151 case 0x2: 2152 return (ah->caps.rx_chainmask == 1); 2153 default: 2154 return false; 2155 } 2156 } 2157 2158 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2159 { 2160 struct ath_softc *sc = hw->priv; 2161 struct ath_hw *ah = sc->sc_ah; 2162 2163 if (ah->caps.rx_chainmask != 1) 2164 rx_ant |= tx_ant; 2165 2166 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2167 return -EINVAL; 2168 2169 sc->ant_rx = rx_ant; 2170 sc->ant_tx = tx_ant; 2171 2172 if (ah->caps.rx_chainmask == 1) 2173 return 0; 2174 2175 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2176 if (AR_SREV_9100(ah)) 2177 ah->rxchainmask = 0x7; 2178 else 2179 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2180 2181 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2182 ath9k_cmn_reload_chainmask(ah); 2183 2184 return 0; 2185 } 2186 2187 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2188 { 2189 struct ath_softc *sc = hw->priv; 2190 2191 *tx_ant = sc->ant_tx; 2192 *rx_ant = sc->ant_rx; 2193 return 0; 2194 } 2195 2196 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2197 { 2198 struct ath_softc *sc = hw->priv; 2199 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2200 set_bit(ATH_OP_SCANNING, &common->op_flags); 2201 } 2202 2203 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2204 { 2205 struct ath_softc *sc = hw->priv; 2206 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2207 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2208 } 2209 2210 static int ath_scan_channel_duration(struct ath_softc *sc, 2211 struct ieee80211_channel *chan) 2212 { 2213 struct cfg80211_scan_request *req = sc->offchannel.scan_req; 2214 2215 if (!req->n_ssids || (chan->flags & IEEE80211_CHAN_NO_IR)) 2216 return (HZ / 9); /* ~110 ms */ 2217 2218 return (HZ / 16); /* ~60 ms */ 2219 } 2220 2221 static void 2222 ath_scan_next_channel(struct ath_softc *sc) 2223 { 2224 struct cfg80211_scan_request *req = sc->offchannel.scan_req; 2225 struct ieee80211_channel *chan; 2226 2227 if (sc->offchannel.scan_idx >= req->n_channels) { 2228 sc->offchannel.state = ATH_OFFCHANNEL_IDLE; 2229 ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc, false), 2230 NULL); 2231 return; 2232 } 2233 2234 chan = req->channels[sc->offchannel.scan_idx++]; 2235 sc->offchannel.duration = ath_scan_channel_duration(sc, chan); 2236 sc->offchannel.state = ATH_OFFCHANNEL_PROBE_SEND; 2237 ath_chanctx_offchan_switch(sc, chan); 2238 } 2239 2240 static void ath_offchannel_next(struct ath_softc *sc) 2241 { 2242 struct ieee80211_vif *vif; 2243 2244 if (sc->offchannel.scan_req) { 2245 vif = sc->offchannel.scan_vif; 2246 sc->offchannel.chan.txpower = vif->bss_conf.txpower; 2247 ath_scan_next_channel(sc); 2248 } else if (sc->offchannel.roc_vif) { 2249 vif = sc->offchannel.roc_vif; 2250 sc->offchannel.chan.txpower = vif->bss_conf.txpower; 2251 sc->offchannel.duration = sc->offchannel.roc_duration; 2252 sc->offchannel.state = ATH_OFFCHANNEL_ROC_START; 2253 ath_chanctx_offchan_switch(sc, sc->offchannel.roc_chan); 2254 } else { 2255 ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc, false), 2256 NULL); 2257 sc->offchannel.state = ATH_OFFCHANNEL_IDLE; 2258 if (sc->ps_idle) 2259 ath_cancel_work(sc); 2260 } 2261 } 2262 2263 static void ath_roc_complete(struct ath_softc *sc, bool abort) 2264 { 2265 sc->offchannel.roc_vif = NULL; 2266 sc->offchannel.roc_chan = NULL; 2267 if (!abort) 2268 ieee80211_remain_on_channel_expired(sc->hw); 2269 ath_offchannel_next(sc); 2270 ath9k_ps_restore(sc); 2271 } 2272 2273 static void ath_scan_complete(struct ath_softc *sc, bool abort) 2274 { 2275 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2276 2277 sc->offchannel.scan_req = NULL; 2278 sc->offchannel.scan_vif = NULL; 2279 sc->offchannel.state = ATH_OFFCHANNEL_IDLE; 2280 ieee80211_scan_completed(sc->hw, abort); 2281 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2282 ath_offchannel_next(sc); 2283 ath9k_ps_restore(sc); 2284 } 2285 2286 static void ath_scan_send_probe(struct ath_softc *sc, 2287 struct cfg80211_ssid *ssid) 2288 { 2289 struct cfg80211_scan_request *req = sc->offchannel.scan_req; 2290 struct ieee80211_vif *vif = sc->offchannel.scan_vif; 2291 struct ath_tx_control txctl = {}; 2292 struct sk_buff *skb; 2293 struct ieee80211_tx_info *info; 2294 int band = sc->offchannel.chan.chandef.chan->band; 2295 2296 skb = ieee80211_probereq_get(sc->hw, vif, 2297 ssid->ssid, ssid->ssid_len, req->ie_len); 2298 if (!skb) 2299 return; 2300 2301 info = IEEE80211_SKB_CB(skb); 2302 if (req->no_cck) 2303 info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE; 2304 2305 if (req->ie_len) 2306 memcpy(skb_put(skb, req->ie_len), req->ie, req->ie_len); 2307 2308 skb_set_queue_mapping(skb, IEEE80211_AC_VO); 2309 2310 if (!ieee80211_tx_prepare_skb(sc->hw, vif, skb, band, NULL)) 2311 goto error; 2312 2313 txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO]; 2314 txctl.force_channel = true; 2315 if (ath_tx_start(sc->hw, skb, &txctl)) 2316 goto error; 2317 2318 return; 2319 2320 error: 2321 ieee80211_free_txskb(sc->hw, skb); 2322 } 2323 2324 static void ath_scan_channel_start(struct ath_softc *sc) 2325 { 2326 struct cfg80211_scan_request *req = sc->offchannel.scan_req; 2327 int i; 2328 2329 if (!(sc->cur_chan->chandef.chan->flags & IEEE80211_CHAN_NO_IR) && 2330 req->n_ssids) { 2331 for (i = 0; i < req->n_ssids; i++) 2332 ath_scan_send_probe(sc, &req->ssids[i]); 2333 2334 } 2335 2336 sc->offchannel.state = ATH_OFFCHANNEL_PROBE_WAIT; 2337 mod_timer(&sc->offchannel.timer, jiffies + sc->offchannel.duration); 2338 } 2339 2340 void ath_offchannel_channel_change(struct ath_softc *sc) 2341 { 2342 switch (sc->offchannel.state) { 2343 case ATH_OFFCHANNEL_PROBE_SEND: 2344 if (!sc->offchannel.scan_req) 2345 return; 2346 2347 if (sc->cur_chan->chandef.chan != 2348 sc->offchannel.chan.chandef.chan) 2349 return; 2350 2351 ath_scan_channel_start(sc); 2352 break; 2353 case ATH_OFFCHANNEL_IDLE: 2354 if (!sc->offchannel.scan_req) 2355 return; 2356 2357 ath_scan_complete(sc, false); 2358 break; 2359 case ATH_OFFCHANNEL_ROC_START: 2360 if (sc->cur_chan != &sc->offchannel.chan) 2361 break; 2362 2363 sc->offchannel.state = ATH_OFFCHANNEL_ROC_WAIT; 2364 mod_timer(&sc->offchannel.timer, jiffies + 2365 msecs_to_jiffies(sc->offchannel.duration)); 2366 ieee80211_ready_on_channel(sc->hw); 2367 break; 2368 case ATH_OFFCHANNEL_ROC_DONE: 2369 ath_roc_complete(sc, false); 2370 break; 2371 default: 2372 break; 2373 } 2374 } 2375 2376 void ath_offchannel_timer(unsigned long data) 2377 { 2378 struct ath_softc *sc = (struct ath_softc *)data; 2379 struct ath_chanctx *ctx; 2380 2381 switch (sc->offchannel.state) { 2382 case ATH_OFFCHANNEL_PROBE_WAIT: 2383 if (!sc->offchannel.scan_req) 2384 return; 2385 2386 /* get first active channel context */ 2387 ctx = ath_chanctx_get_oper_chan(sc, true); 2388 if (ctx->active) { 2389 sc->offchannel.state = ATH_OFFCHANNEL_SUSPEND; 2390 ath_chanctx_switch(sc, ctx, NULL); 2391 mod_timer(&sc->offchannel.timer, jiffies + HZ / 10); 2392 break; 2393 } 2394 /* fall through */ 2395 case ATH_OFFCHANNEL_SUSPEND: 2396 if (!sc->offchannel.scan_req) 2397 return; 2398 2399 ath_scan_next_channel(sc); 2400 break; 2401 case ATH_OFFCHANNEL_ROC_START: 2402 case ATH_OFFCHANNEL_ROC_WAIT: 2403 ctx = ath_chanctx_get_oper_chan(sc, false); 2404 sc->offchannel.state = ATH_OFFCHANNEL_ROC_DONE; 2405 ath_chanctx_switch(sc, ctx, NULL); 2406 break; 2407 default: 2408 break; 2409 } 2410 } 2411 2412 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2413 struct ieee80211_scan_request *hw_req) 2414 { 2415 struct cfg80211_scan_request *req = &hw_req->req; 2416 struct ath_softc *sc = hw->priv; 2417 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2418 int ret = 0; 2419 2420 mutex_lock(&sc->mutex); 2421 2422 if (WARN_ON(sc->offchannel.scan_req)) { 2423 ret = -EBUSY; 2424 goto out; 2425 } 2426 2427 ath9k_ps_wakeup(sc); 2428 set_bit(ATH_OP_SCANNING, &common->op_flags); 2429 sc->offchannel.scan_vif = vif; 2430 sc->offchannel.scan_req = req; 2431 sc->offchannel.scan_idx = 0; 2432 2433 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) 2434 ath_offchannel_next(sc); 2435 2436 out: 2437 mutex_unlock(&sc->mutex); 2438 2439 return ret; 2440 } 2441 2442 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2443 struct ieee80211_vif *vif) 2444 { 2445 struct ath_softc *sc = hw->priv; 2446 2447 mutex_lock(&sc->mutex); 2448 del_timer_sync(&sc->offchannel.timer); 2449 ath_scan_complete(sc, true); 2450 mutex_unlock(&sc->mutex); 2451 } 2452 2453 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2454 struct ieee80211_vif *vif, 2455 struct ieee80211_channel *chan, int duration, 2456 enum ieee80211_roc_type type) 2457 { 2458 struct ath_softc *sc = hw->priv; 2459 int ret = 0; 2460 2461 mutex_lock(&sc->mutex); 2462 2463 if (WARN_ON(sc->offchannel.roc_vif)) { 2464 ret = -EBUSY; 2465 goto out; 2466 } 2467 2468 ath9k_ps_wakeup(sc); 2469 sc->offchannel.roc_vif = vif; 2470 sc->offchannel.roc_chan = chan; 2471 sc->offchannel.roc_duration = duration; 2472 2473 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) 2474 ath_offchannel_next(sc); 2475 2476 out: 2477 mutex_unlock(&sc->mutex); 2478 2479 return ret; 2480 } 2481 2482 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) 2483 { 2484 struct ath_softc *sc = hw->priv; 2485 2486 mutex_lock(&sc->mutex); 2487 2488 del_timer_sync(&sc->offchannel.timer); 2489 2490 if (sc->offchannel.roc_vif) { 2491 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2492 ath_roc_complete(sc, true); 2493 } 2494 2495 mutex_unlock(&sc->mutex); 2496 2497 return 0; 2498 } 2499 2500 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2501 struct ieee80211_chanctx_conf *conf) 2502 { 2503 struct ath_softc *sc = hw->priv; 2504 struct ath_chanctx *ctx, **ptr; 2505 int pos; 2506 2507 mutex_lock(&sc->mutex); 2508 2509 ath_for_each_chanctx(sc, ctx) { 2510 if (ctx->assigned) 2511 continue; 2512 2513 ptr = (void *) conf->drv_priv; 2514 *ptr = ctx; 2515 ctx->assigned = true; 2516 pos = ctx - &sc->chanctx[0]; 2517 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2518 ath_chanctx_set_channel(sc, ctx, &conf->def); 2519 mutex_unlock(&sc->mutex); 2520 return 0; 2521 } 2522 mutex_unlock(&sc->mutex); 2523 return -ENOSPC; 2524 } 2525 2526 2527 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2528 struct ieee80211_chanctx_conf *conf) 2529 { 2530 struct ath_softc *sc = hw->priv; 2531 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2532 2533 mutex_lock(&sc->mutex); 2534 ctx->assigned = false; 2535 ctx->hw_queue_base = -1; 2536 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2537 mutex_unlock(&sc->mutex); 2538 } 2539 2540 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2541 struct ieee80211_chanctx_conf *conf, 2542 u32 changed) 2543 { 2544 struct ath_softc *sc = hw->priv; 2545 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2546 2547 mutex_lock(&sc->mutex); 2548 ath_chanctx_set_channel(sc, ctx, &conf->def); 2549 mutex_unlock(&sc->mutex); 2550 } 2551 2552 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2553 struct ieee80211_vif *vif, 2554 struct ieee80211_chanctx_conf *conf) 2555 { 2556 struct ath_softc *sc = hw->priv; 2557 struct ath_vif *avp = (void *)vif->drv_priv; 2558 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2559 int i; 2560 2561 mutex_lock(&sc->mutex); 2562 avp->chanctx = ctx; 2563 list_add_tail(&avp->list, &ctx->vifs); 2564 ath9k_calculate_summary_state(sc, ctx); 2565 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2566 vif->hw_queue[i] = ctx->hw_queue_base + i; 2567 mutex_unlock(&sc->mutex); 2568 2569 return 0; 2570 } 2571 2572 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2573 struct ieee80211_vif *vif, 2574 struct ieee80211_chanctx_conf *conf) 2575 { 2576 struct ath_softc *sc = hw->priv; 2577 struct ath_vif *avp = (void *)vif->drv_priv; 2578 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2579 int ac; 2580 2581 mutex_lock(&sc->mutex); 2582 avp->chanctx = NULL; 2583 list_del(&avp->list); 2584 ath9k_calculate_summary_state(sc, ctx); 2585 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2586 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2587 mutex_unlock(&sc->mutex); 2588 } 2589 2590 void ath9k_fill_chanctx_ops(void) 2591 { 2592 if (!ath9k_use_chanctx) 2593 return; 2594 2595 ath9k_ops.hw_scan = ath9k_hw_scan; 2596 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2597 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2598 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2599 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2600 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2601 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2602 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2603 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2604 ath9k_ops.mgd_prepare_tx = ath9k_chanctx_force_active; 2605 } 2606 2607 struct ieee80211_ops ath9k_ops = { 2608 .tx = ath9k_tx, 2609 .start = ath9k_start, 2610 .stop = ath9k_stop, 2611 .add_interface = ath9k_add_interface, 2612 .change_interface = ath9k_change_interface, 2613 .remove_interface = ath9k_remove_interface, 2614 .config = ath9k_config, 2615 .configure_filter = ath9k_configure_filter, 2616 .sta_add = ath9k_sta_add, 2617 .sta_remove = ath9k_sta_remove, 2618 .sta_notify = ath9k_sta_notify, 2619 .conf_tx = ath9k_conf_tx, 2620 .bss_info_changed = ath9k_bss_info_changed, 2621 .set_key = ath9k_set_key, 2622 .get_tsf = ath9k_get_tsf, 2623 .set_tsf = ath9k_set_tsf, 2624 .reset_tsf = ath9k_reset_tsf, 2625 .ampdu_action = ath9k_ampdu_action, 2626 .get_survey = ath9k_get_survey, 2627 .rfkill_poll = ath9k_rfkill_poll_state, 2628 .set_coverage_class = ath9k_set_coverage_class, 2629 .flush = ath9k_flush, 2630 .tx_frames_pending = ath9k_tx_frames_pending, 2631 .tx_last_beacon = ath9k_tx_last_beacon, 2632 .release_buffered_frames = ath9k_release_buffered_frames, 2633 .get_stats = ath9k_get_stats, 2634 .set_antenna = ath9k_set_antenna, 2635 .get_antenna = ath9k_get_antenna, 2636 2637 #ifdef CONFIG_ATH9K_WOW 2638 .suspend = ath9k_suspend, 2639 .resume = ath9k_resume, 2640 .set_wakeup = ath9k_set_wakeup, 2641 #endif 2642 2643 #ifdef CONFIG_ATH9K_DEBUGFS 2644 .get_et_sset_count = ath9k_get_et_sset_count, 2645 .get_et_stats = ath9k_get_et_stats, 2646 .get_et_strings = ath9k_get_et_strings, 2647 #endif 2648 2649 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2650 .sta_add_debugfs = ath9k_sta_add_debugfs, 2651 #endif 2652 .sw_scan_start = ath9k_sw_scan_start, 2653 .sw_scan_complete = ath9k_sw_scan_complete, 2654 }; 2655