1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static u8 parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 64 pending = true; 65 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 66 pending = !list_empty(&txq->txq_fifo_pending); 67 68 spin_unlock_bh(&txq->axq_lock); 69 return pending; 70 } 71 72 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 73 { 74 unsigned long flags; 75 bool ret; 76 77 spin_lock_irqsave(&sc->sc_pm_lock, flags); 78 ret = ath9k_hw_setpower(sc->sc_ah, mode); 79 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 80 81 return ret; 82 } 83 84 void ath9k_ps_wakeup(struct ath_softc *sc) 85 { 86 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 87 unsigned long flags; 88 enum ath9k_power_mode power_mode; 89 90 spin_lock_irqsave(&sc->sc_pm_lock, flags); 91 if (++sc->ps_usecount != 1) 92 goto unlock; 93 94 power_mode = sc->sc_ah->power_mode; 95 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 96 97 /* 98 * While the hardware is asleep, the cycle counters contain no 99 * useful data. Better clear them now so that they don't mess up 100 * survey data results. 101 */ 102 if (power_mode != ATH9K_PM_AWAKE) { 103 spin_lock(&common->cc_lock); 104 ath_hw_cycle_counters_update(common); 105 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 106 spin_unlock(&common->cc_lock); 107 } 108 109 unlock: 110 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 111 } 112 113 void ath9k_ps_restore(struct ath_softc *sc) 114 { 115 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 116 unsigned long flags; 117 118 spin_lock_irqsave(&sc->sc_pm_lock, flags); 119 if (--sc->ps_usecount != 0) 120 goto unlock; 121 122 spin_lock(&common->cc_lock); 123 ath_hw_cycle_counters_update(common); 124 spin_unlock(&common->cc_lock); 125 126 if (sc->ps_idle) 127 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 128 else if (sc->ps_enabled && 129 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 130 PS_WAIT_FOR_CAB | 131 PS_WAIT_FOR_PSPOLL_DATA | 132 PS_WAIT_FOR_TX_ACK))) 133 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); 134 135 unlock: 136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 137 } 138 139 static void ath_start_ani(struct ath_common *common) 140 { 141 struct ath_hw *ah = common->ah; 142 unsigned long timestamp = jiffies_to_msecs(jiffies); 143 struct ath_softc *sc = (struct ath_softc *) common->priv; 144 145 if (!(sc->sc_flags & SC_OP_ANI_RUN)) 146 return; 147 148 if (sc->sc_flags & SC_OP_OFFCHANNEL) 149 return; 150 151 common->ani.longcal_timer = timestamp; 152 common->ani.shortcal_timer = timestamp; 153 common->ani.checkani_timer = timestamp; 154 155 mod_timer(&common->ani.timer, 156 jiffies + 157 msecs_to_jiffies((u32)ah->config.ani_poll_interval)); 158 } 159 160 static void ath_update_survey_nf(struct ath_softc *sc, int channel) 161 { 162 struct ath_hw *ah = sc->sc_ah; 163 struct ath9k_channel *chan = &ah->channels[channel]; 164 struct survey_info *survey = &sc->survey[channel]; 165 166 if (chan->noisefloor) { 167 survey->filled |= SURVEY_INFO_NOISE_DBM; 168 survey->noise = chan->noisefloor; 169 } 170 } 171 172 /* 173 * Updates the survey statistics and returns the busy time since last 174 * update in %, if the measurement duration was long enough for the 175 * result to be useful, -1 otherwise. 176 */ 177 static int ath_update_survey_stats(struct ath_softc *sc) 178 { 179 struct ath_hw *ah = sc->sc_ah; 180 struct ath_common *common = ath9k_hw_common(ah); 181 int pos = ah->curchan - &ah->channels[0]; 182 struct survey_info *survey = &sc->survey[pos]; 183 struct ath_cycle_counters *cc = &common->cc_survey; 184 unsigned int div = common->clockrate * 1000; 185 int ret = 0; 186 187 if (!ah->curchan) 188 return -1; 189 190 if (ah->power_mode == ATH9K_PM_AWAKE) 191 ath_hw_cycle_counters_update(common); 192 193 if (cc->cycles > 0) { 194 survey->filled |= SURVEY_INFO_CHANNEL_TIME | 195 SURVEY_INFO_CHANNEL_TIME_BUSY | 196 SURVEY_INFO_CHANNEL_TIME_RX | 197 SURVEY_INFO_CHANNEL_TIME_TX; 198 survey->channel_time += cc->cycles / div; 199 survey->channel_time_busy += cc->rx_busy / div; 200 survey->channel_time_rx += cc->rx_frame / div; 201 survey->channel_time_tx += cc->tx_frame / div; 202 } 203 204 if (cc->cycles < div) 205 return -1; 206 207 if (cc->cycles > 0) 208 ret = cc->rx_busy * 100 / cc->cycles; 209 210 memset(cc, 0, sizeof(*cc)); 211 212 ath_update_survey_nf(sc, pos); 213 214 return ret; 215 } 216 217 /* 218 * Set/change channels. If the channel is really being changed, it's done 219 * by reseting the chip. To accomplish this we must first cleanup any pending 220 * DMA, then restart stuff. 221 */ 222 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 223 struct ath9k_channel *hchan) 224 { 225 struct ath_hw *ah = sc->sc_ah; 226 struct ath_common *common = ath9k_hw_common(ah); 227 struct ieee80211_conf *conf = &common->hw->conf; 228 bool fastcc = true, stopped; 229 struct ieee80211_channel *channel = hw->conf.channel; 230 struct ath9k_hw_cal_data *caldata = NULL; 231 int r; 232 233 if (sc->sc_flags & SC_OP_INVALID) 234 return -EIO; 235 236 sc->hw_busy_count = 0; 237 238 del_timer_sync(&common->ani.timer); 239 cancel_work_sync(&sc->paprd_work); 240 cancel_work_sync(&sc->hw_check_work); 241 cancel_delayed_work_sync(&sc->tx_complete_work); 242 cancel_delayed_work_sync(&sc->hw_pll_work); 243 244 ath9k_ps_wakeup(sc); 245 246 spin_lock_bh(&sc->sc_pcu_lock); 247 248 /* 249 * This is only performed if the channel settings have 250 * actually changed. 251 * 252 * To switch channels clear any pending DMA operations; 253 * wait long enough for the RX fifo to drain, reset the 254 * hardware at the new frequency, and then re-enable 255 * the relevant bits of the h/w. 256 */ 257 ath9k_hw_disable_interrupts(ah); 258 stopped = ath_drain_all_txq(sc, false); 259 260 if (!ath_stoprecv(sc)) 261 stopped = false; 262 263 if (!ath9k_hw_check_alive(ah)) 264 stopped = false; 265 266 /* XXX: do not flush receive queue here. We don't want 267 * to flush data frames already in queue because of 268 * changing channel. */ 269 270 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) 271 fastcc = false; 272 273 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) 274 caldata = &sc->caldata; 275 276 ath_dbg(common, ATH_DBG_CONFIG, 277 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", 278 sc->sc_ah->curchan->channel, 279 channel->center_freq, conf_is_ht40(conf), 280 fastcc); 281 282 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 283 if (r) { 284 ath_err(common, 285 "Unable to reset channel (%u MHz), reset status %d\n", 286 channel->center_freq, r); 287 goto ps_restore; 288 } 289 290 if (ath_startrecv(sc) != 0) { 291 ath_err(common, "Unable to restart recv logic\n"); 292 r = -EIO; 293 goto ps_restore; 294 } 295 296 ath9k_cmn_update_txpow(ah, sc->curtxpow, 297 sc->config.txpowlimit, &sc->curtxpow); 298 ath9k_hw_set_interrupts(ah, ah->imask); 299 300 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { 301 if (sc->sc_flags & SC_OP_BEACONS) 302 ath_beacon_config(sc, NULL); 303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); 305 ath_start_ani(common); 306 } 307 308 ps_restore: 309 ieee80211_wake_queues(hw); 310 311 spin_unlock_bh(&sc->sc_pcu_lock); 312 313 ath9k_ps_restore(sc); 314 return r; 315 } 316 317 static void ath_paprd_activate(struct ath_softc *sc) 318 { 319 struct ath_hw *ah = sc->sc_ah; 320 struct ath9k_hw_cal_data *caldata = ah->caldata; 321 struct ath_common *common = ath9k_hw_common(ah); 322 int chain; 323 324 if (!caldata || !caldata->paprd_done) 325 return; 326 327 ath9k_ps_wakeup(sc); 328 ar9003_paprd_enable(ah, false); 329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 330 if (!(common->tx_chainmask & BIT(chain))) 331 continue; 332 333 ar9003_paprd_populate_single_table(ah, caldata, chain); 334 } 335 336 ar9003_paprd_enable(ah, true); 337 ath9k_ps_restore(sc); 338 } 339 340 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) 341 { 342 struct ieee80211_hw *hw = sc->hw; 343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 344 struct ath_hw *ah = sc->sc_ah; 345 struct ath_common *common = ath9k_hw_common(ah); 346 struct ath_tx_control txctl; 347 int time_left; 348 349 memset(&txctl, 0, sizeof(txctl)); 350 txctl.txq = sc->tx.txq_map[WME_AC_BE]; 351 352 memset(tx_info, 0, sizeof(*tx_info)); 353 tx_info->band = hw->conf.channel->band; 354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; 355 tx_info->control.rates[0].idx = 0; 356 tx_info->control.rates[0].count = 1; 357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; 358 tx_info->control.rates[1].idx = -1; 359 360 init_completion(&sc->paprd_complete); 361 txctl.paprd = BIT(chain); 362 363 if (ath_tx_start(hw, skb, &txctl) != 0) { 364 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n"); 365 dev_kfree_skb_any(skb); 366 return false; 367 } 368 369 time_left = wait_for_completion_timeout(&sc->paprd_complete, 370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 371 372 if (!time_left) 373 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, 374 "Timeout waiting for paprd training on TX chain %d\n", 375 chain); 376 377 return !!time_left; 378 } 379 380 void ath_paprd_calibrate(struct work_struct *work) 381 { 382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); 383 struct ieee80211_hw *hw = sc->hw; 384 struct ath_hw *ah = sc->sc_ah; 385 struct ieee80211_hdr *hdr; 386 struct sk_buff *skb = NULL; 387 struct ath9k_hw_cal_data *caldata = ah->caldata; 388 struct ath_common *common = ath9k_hw_common(ah); 389 int ftype; 390 int chain_ok = 0; 391 int chain; 392 int len = 1800; 393 394 if (!caldata) 395 return; 396 397 if (ar9003_paprd_init_table(ah) < 0) 398 return; 399 400 skb = alloc_skb(len, GFP_KERNEL); 401 if (!skb) 402 return; 403 404 skb_put(skb, len); 405 memset(skb->data, 0, len); 406 hdr = (struct ieee80211_hdr *)skb->data; 407 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; 408 hdr->frame_control = cpu_to_le16(ftype); 409 hdr->duration_id = cpu_to_le16(10); 410 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); 411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 413 414 ath9k_ps_wakeup(sc); 415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 416 if (!(common->tx_chainmask & BIT(chain))) 417 continue; 418 419 chain_ok = 0; 420 421 ath_dbg(common, ATH_DBG_CALIBRATE, 422 "Sending PAPRD frame for thermal measurement " 423 "on chain %d\n", chain); 424 if (!ath_paprd_send_frame(sc, skb, chain)) 425 goto fail_paprd; 426 427 ar9003_paprd_setup_gain_table(ah, chain); 428 429 ath_dbg(common, ATH_DBG_CALIBRATE, 430 "Sending PAPRD training frame on chain %d\n", chain); 431 if (!ath_paprd_send_frame(sc, skb, chain)) 432 goto fail_paprd; 433 434 if (!ar9003_paprd_is_done(ah)) 435 break; 436 437 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) 438 break; 439 440 chain_ok = 1; 441 } 442 kfree_skb(skb); 443 444 if (chain_ok) { 445 caldata->paprd_done = true; 446 ath_paprd_activate(sc); 447 } 448 449 fail_paprd: 450 ath9k_ps_restore(sc); 451 } 452 453 /* 454 * This routine performs the periodic noise floor calibration function 455 * that is used to adjust and optimize the chip performance. This 456 * takes environmental changes (location, temperature) into account. 457 * When the task is complete, it reschedules itself depending on the 458 * appropriate interval that was calculated. 459 */ 460 void ath_ani_calibrate(unsigned long data) 461 { 462 struct ath_softc *sc = (struct ath_softc *)data; 463 struct ath_hw *ah = sc->sc_ah; 464 struct ath_common *common = ath9k_hw_common(ah); 465 bool longcal = false; 466 bool shortcal = false; 467 bool aniflag = false; 468 unsigned int timestamp = jiffies_to_msecs(jiffies); 469 u32 cal_interval, short_cal_interval, long_cal_interval; 470 unsigned long flags; 471 472 if (ah->caldata && ah->caldata->nfcal_interference) 473 long_cal_interval = ATH_LONG_CALINTERVAL_INT; 474 else 475 long_cal_interval = ATH_LONG_CALINTERVAL; 476 477 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? 478 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; 479 480 /* Only calibrate if awake */ 481 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) 482 goto set_timer; 483 484 ath9k_ps_wakeup(sc); 485 486 /* Long calibration runs independently of short calibration. */ 487 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { 488 longcal = true; 489 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 490 common->ani.longcal_timer = timestamp; 491 } 492 493 /* Short calibration applies only while caldone is false */ 494 if (!common->ani.caldone) { 495 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { 496 shortcal = true; 497 ath_dbg(common, ATH_DBG_ANI, 498 "shortcal @%lu\n", jiffies); 499 common->ani.shortcal_timer = timestamp; 500 common->ani.resetcal_timer = timestamp; 501 } 502 } else { 503 if ((timestamp - common->ani.resetcal_timer) >= 504 ATH_RESTART_CALINTERVAL) { 505 common->ani.caldone = ath9k_hw_reset_calvalid(ah); 506 if (common->ani.caldone) 507 common->ani.resetcal_timer = timestamp; 508 } 509 } 510 511 /* Verify whether we must check ANI */ 512 if ((timestamp - common->ani.checkani_timer) >= 513 ah->config.ani_poll_interval) { 514 aniflag = true; 515 common->ani.checkani_timer = timestamp; 516 } 517 518 /* Skip all processing if there's nothing to do. */ 519 if (longcal || shortcal || aniflag) { 520 /* Call ANI routine if necessary */ 521 if (aniflag) { 522 spin_lock_irqsave(&common->cc_lock, flags); 523 ath9k_hw_ani_monitor(ah, ah->curchan); 524 ath_update_survey_stats(sc); 525 spin_unlock_irqrestore(&common->cc_lock, flags); 526 } 527 528 /* Perform calibration if necessary */ 529 if (longcal || shortcal) { 530 common->ani.caldone = 531 ath9k_hw_calibrate(ah, 532 ah->curchan, 533 common->rx_chainmask, 534 longcal); 535 } 536 } 537 538 ath9k_ps_restore(sc); 539 540 set_timer: 541 /* 542 * Set timer interval based on previous results. 543 * The interval must be the shortest necessary to satisfy ANI, 544 * short calibration and long calibration. 545 */ 546 cal_interval = ATH_LONG_CALINTERVAL; 547 if (sc->sc_ah->config.enable_ani) 548 cal_interval = min(cal_interval, 549 (u32)ah->config.ani_poll_interval); 550 if (!common->ani.caldone) 551 cal_interval = min(cal_interval, (u32)short_cal_interval); 552 553 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 554 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { 555 if (!ah->caldata->paprd_done) 556 ieee80211_queue_work(sc->hw, &sc->paprd_work); 557 else if (!ah->paprd_table_write_done) 558 ath_paprd_activate(sc); 559 } 560 } 561 562 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 563 { 564 struct ath_node *an; 565 struct ath_hw *ah = sc->sc_ah; 566 an = (struct ath_node *)sta->drv_priv; 567 568 #ifdef CONFIG_ATH9K_DEBUGFS 569 spin_lock(&sc->nodes_lock); 570 list_add(&an->list, &sc->nodes); 571 spin_unlock(&sc->nodes_lock); 572 an->sta = sta; 573 #endif 574 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM) 575 sc->sc_flags |= SC_OP_ENABLE_APM; 576 577 if (sc->sc_flags & SC_OP_TXAGGR) { 578 ath_tx_node_init(sc, an); 579 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 580 sta->ht_cap.ampdu_factor); 581 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 582 } 583 } 584 585 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 586 { 587 struct ath_node *an = (struct ath_node *)sta->drv_priv; 588 589 #ifdef CONFIG_ATH9K_DEBUGFS 590 spin_lock(&sc->nodes_lock); 591 list_del(&an->list); 592 spin_unlock(&sc->nodes_lock); 593 an->sta = NULL; 594 #endif 595 596 if (sc->sc_flags & SC_OP_TXAGGR) 597 ath_tx_node_cleanup(sc, an); 598 } 599 600 void ath_hw_check(struct work_struct *work) 601 { 602 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); 603 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 604 unsigned long flags; 605 int busy; 606 607 ath9k_ps_wakeup(sc); 608 if (ath9k_hw_check_alive(sc->sc_ah)) 609 goto out; 610 611 spin_lock_irqsave(&common->cc_lock, flags); 612 busy = ath_update_survey_stats(sc); 613 spin_unlock_irqrestore(&common->cc_lock, flags); 614 615 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " 616 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); 617 if (busy >= 99) { 618 if (++sc->hw_busy_count >= 3) 619 ath_reset(sc, true); 620 } else if (busy >= 0) 621 sc->hw_busy_count = 0; 622 623 out: 624 ath9k_ps_restore(sc); 625 } 626 627 void ath9k_tasklet(unsigned long data) 628 { 629 struct ath_softc *sc = (struct ath_softc *)data; 630 struct ath_hw *ah = sc->sc_ah; 631 struct ath_common *common = ath9k_hw_common(ah); 632 633 u32 status = sc->intrstatus; 634 u32 rxmask; 635 636 if (status & ATH9K_INT_FATAL) { 637 ath_reset(sc, true); 638 return; 639 } 640 641 ath9k_ps_wakeup(sc); 642 spin_lock(&sc->sc_pcu_lock); 643 644 /* 645 * Only run the baseband hang check if beacons stop working in AP or 646 * IBSS mode, because it has a high false positive rate. For station 647 * mode it should not be necessary, since the upper layers will detect 648 * this through a beacon miss automatically and the following channel 649 * change will trigger a hardware reset anyway 650 */ 651 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && 652 !ath9k_hw_check_alive(ah)) 653 ieee80211_queue_work(sc->hw, &sc->hw_check_work); 654 655 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 656 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 657 ATH9K_INT_RXORN); 658 else 659 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 660 661 if (status & rxmask) { 662 /* Check for high priority Rx first */ 663 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 664 (status & ATH9K_INT_RXHP)) 665 ath_rx_tasklet(sc, 0, true); 666 667 ath_rx_tasklet(sc, 0, false); 668 } 669 670 if (status & ATH9K_INT_TX) { 671 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 672 ath_tx_edma_tasklet(sc); 673 else 674 ath_tx_tasklet(sc); 675 } 676 677 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 678 /* 679 * TSF sync does not look correct; remain awake to sync with 680 * the next Beacon. 681 */ 682 ath_dbg(common, ATH_DBG_PS, 683 "TSFOOR - Sync with next Beacon\n"); 684 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 685 } 686 687 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 688 if (status & ATH9K_INT_GENTIMER) 689 ath_gen_timer_isr(sc->sc_ah); 690 691 /* re-enable hardware interrupt */ 692 ath9k_hw_enable_interrupts(ah); 693 694 spin_unlock(&sc->sc_pcu_lock); 695 ath9k_ps_restore(sc); 696 } 697 698 irqreturn_t ath_isr(int irq, void *dev) 699 { 700 #define SCHED_INTR ( \ 701 ATH9K_INT_FATAL | \ 702 ATH9K_INT_RXORN | \ 703 ATH9K_INT_RXEOL | \ 704 ATH9K_INT_RX | \ 705 ATH9K_INT_RXLP | \ 706 ATH9K_INT_RXHP | \ 707 ATH9K_INT_TX | \ 708 ATH9K_INT_BMISS | \ 709 ATH9K_INT_CST | \ 710 ATH9K_INT_TSFOOR | \ 711 ATH9K_INT_GENTIMER) 712 713 struct ath_softc *sc = dev; 714 struct ath_hw *ah = sc->sc_ah; 715 struct ath_common *common = ath9k_hw_common(ah); 716 enum ath9k_int status; 717 bool sched = false; 718 719 /* 720 * The hardware is not ready/present, don't 721 * touch anything. Note this can happen early 722 * on if the IRQ is shared. 723 */ 724 if (sc->sc_flags & SC_OP_INVALID) 725 return IRQ_NONE; 726 727 728 /* shared irq, not for us */ 729 730 if (!ath9k_hw_intrpend(ah)) 731 return IRQ_NONE; 732 733 /* 734 * Figure out the reason(s) for the interrupt. Note 735 * that the hal returns a pseudo-ISR that may include 736 * bits we haven't explicitly enabled so we mask the 737 * value to insure we only process bits we requested. 738 */ 739 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 740 status &= ah->imask; /* discard unasked-for bits */ 741 742 /* 743 * If there are no status bits set, then this interrupt was not 744 * for me (should have been caught above). 745 */ 746 if (!status) 747 return IRQ_NONE; 748 749 /* Cache the status */ 750 sc->intrstatus = status; 751 752 if (status & SCHED_INTR) 753 sched = true; 754 755 /* 756 * If a FATAL or RXORN interrupt is received, we have to reset the 757 * chip immediately. 758 */ 759 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 760 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 761 goto chip_reset; 762 763 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 764 (status & ATH9K_INT_BB_WATCHDOG)) { 765 766 spin_lock(&common->cc_lock); 767 ath_hw_cycle_counters_update(common); 768 ar9003_hw_bb_watchdog_dbg_info(ah); 769 spin_unlock(&common->cc_lock); 770 771 goto chip_reset; 772 } 773 774 if (status & ATH9K_INT_SWBA) 775 tasklet_schedule(&sc->bcon_tasklet); 776 777 if (status & ATH9K_INT_TXURN) 778 ath9k_hw_updatetxtriglevel(ah, true); 779 780 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 781 if (status & ATH9K_INT_RXEOL) { 782 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 783 ath9k_hw_set_interrupts(ah, ah->imask); 784 } 785 } 786 787 if (status & ATH9K_INT_MIB) { 788 /* 789 * Disable interrupts until we service the MIB 790 * interrupt; otherwise it will continue to 791 * fire. 792 */ 793 ath9k_hw_disable_interrupts(ah); 794 /* 795 * Let the hal handle the event. We assume 796 * it will clear whatever condition caused 797 * the interrupt. 798 */ 799 spin_lock(&common->cc_lock); 800 ath9k_hw_proc_mib_event(ah); 801 spin_unlock(&common->cc_lock); 802 ath9k_hw_enable_interrupts(ah); 803 } 804 805 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 806 if (status & ATH9K_INT_TIM_TIMER) { 807 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 808 goto chip_reset; 809 /* Clear RxAbort bit so that we can 810 * receive frames */ 811 ath9k_setpower(sc, ATH9K_PM_AWAKE); 812 ath9k_hw_setrxabort(sc->sc_ah, 0); 813 sc->ps_flags |= PS_WAIT_FOR_BEACON; 814 } 815 816 chip_reset: 817 818 ath_debug_stat_interrupt(sc, status); 819 820 if (sched) { 821 /* turn off every interrupt */ 822 ath9k_hw_disable_interrupts(ah); 823 tasklet_schedule(&sc->intr_tq); 824 } 825 826 return IRQ_HANDLED; 827 828 #undef SCHED_INTR 829 } 830 831 static void ath9k_bss_assoc_info(struct ath_softc *sc, 832 struct ieee80211_hw *hw, 833 struct ieee80211_vif *vif, 834 struct ieee80211_bss_conf *bss_conf) 835 { 836 struct ath_hw *ah = sc->sc_ah; 837 struct ath_common *common = ath9k_hw_common(ah); 838 839 if (bss_conf->assoc) { 840 ath_dbg(common, ATH_DBG_CONFIG, 841 "Bss Info ASSOC %d, bssid: %pM\n", 842 bss_conf->aid, common->curbssid); 843 844 /* New association, store aid */ 845 common->curaid = bss_conf->aid; 846 ath9k_hw_write_associd(ah); 847 848 /* 849 * Request a re-configuration of Beacon related timers 850 * on the receipt of the first Beacon frame (i.e., 851 * after time sync with the AP). 852 */ 853 sc->ps_flags |= PS_BEACON_SYNC; 854 855 /* Configure the beacon */ 856 ath_beacon_config(sc, vif); 857 858 /* Reset rssi stats */ 859 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 860 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 861 862 sc->sc_flags |= SC_OP_ANI_RUN; 863 ath_start_ani(common); 864 } else { 865 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 866 common->curaid = 0; 867 /* Stop ANI */ 868 sc->sc_flags &= ~SC_OP_ANI_RUN; 869 del_timer_sync(&common->ani.timer); 870 } 871 } 872 873 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) 874 { 875 struct ath_hw *ah = sc->sc_ah; 876 struct ath_common *common = ath9k_hw_common(ah); 877 struct ieee80211_channel *channel = hw->conf.channel; 878 int r; 879 880 ath9k_ps_wakeup(sc); 881 spin_lock_bh(&sc->sc_pcu_lock); 882 883 ath9k_hw_configpcipowersave(ah, 0, 0); 884 885 if (!ah->curchan) 886 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); 887 888 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 889 if (r) { 890 ath_err(common, 891 "Unable to reset channel (%u MHz), reset status %d\n", 892 channel->center_freq, r); 893 } 894 895 ath9k_cmn_update_txpow(ah, sc->curtxpow, 896 sc->config.txpowlimit, &sc->curtxpow); 897 if (ath_startrecv(sc) != 0) { 898 ath_err(common, "Unable to restart recv logic\n"); 899 goto out; 900 } 901 if (sc->sc_flags & SC_OP_BEACONS) 902 ath_beacon_config(sc, NULL); /* restart beacons */ 903 904 /* Re-Enable interrupts */ 905 ath9k_hw_set_interrupts(ah, ah->imask); 906 907 /* Enable LED */ 908 ath9k_hw_cfg_output(ah, ah->led_pin, 909 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 910 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 911 912 ieee80211_wake_queues(hw); 913 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2); 914 915 out: 916 spin_unlock_bh(&sc->sc_pcu_lock); 917 918 ath9k_ps_restore(sc); 919 } 920 921 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) 922 { 923 struct ath_hw *ah = sc->sc_ah; 924 struct ieee80211_channel *channel = hw->conf.channel; 925 int r; 926 927 ath9k_ps_wakeup(sc); 928 cancel_delayed_work_sync(&sc->hw_pll_work); 929 930 spin_lock_bh(&sc->sc_pcu_lock); 931 932 ieee80211_stop_queues(hw); 933 934 /* 935 * Keep the LED on when the radio is disabled 936 * during idle unassociated state. 937 */ 938 if (!sc->ps_idle) { 939 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 940 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 941 } 942 943 /* Disable interrupts */ 944 ath9k_hw_disable_interrupts(ah); 945 946 ath_drain_all_txq(sc, false); /* clear pending tx frames */ 947 948 ath_stoprecv(sc); /* turn off frame recv */ 949 ath_flushrecv(sc); /* flush recv queue */ 950 951 if (!ah->curchan) 952 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 953 954 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 955 if (r) { 956 ath_err(ath9k_hw_common(sc->sc_ah), 957 "Unable to reset channel (%u MHz), reset status %d\n", 958 channel->center_freq, r); 959 } 960 961 ath9k_hw_phy_disable(ah); 962 963 ath9k_hw_configpcipowersave(ah, 1, 1); 964 965 spin_unlock_bh(&sc->sc_pcu_lock); 966 ath9k_ps_restore(sc); 967 } 968 969 int ath_reset(struct ath_softc *sc, bool retry_tx) 970 { 971 struct ath_hw *ah = sc->sc_ah; 972 struct ath_common *common = ath9k_hw_common(ah); 973 struct ieee80211_hw *hw = sc->hw; 974 int r; 975 976 sc->hw_busy_count = 0; 977 978 /* Stop ANI */ 979 del_timer_sync(&common->ani.timer); 980 981 ath9k_ps_wakeup(sc); 982 spin_lock_bh(&sc->sc_pcu_lock); 983 984 ieee80211_stop_queues(hw); 985 986 ath9k_hw_disable_interrupts(ah); 987 ath_drain_all_txq(sc, retry_tx); 988 989 ath_stoprecv(sc); 990 ath_flushrecv(sc); 991 992 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); 993 if (r) 994 ath_err(common, 995 "Unable to reset hardware; reset status %d\n", r); 996 997 if (ath_startrecv(sc) != 0) 998 ath_err(common, "Unable to start recv logic\n"); 999 1000 /* 1001 * We may be doing a reset in response to a request 1002 * that changes the channel so update any state that 1003 * might change as a result. 1004 */ 1005 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1006 sc->config.txpowlimit, &sc->curtxpow); 1007 1008 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) 1009 ath_beacon_config(sc, NULL); /* restart beacons */ 1010 1011 ath9k_hw_set_interrupts(ah, ah->imask); 1012 1013 if (retry_tx) { 1014 int i; 1015 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1016 if (ATH_TXQ_SETUP(sc, i)) { 1017 spin_lock_bh(&sc->tx.txq[i].axq_lock); 1018 ath_txq_schedule(sc, &sc->tx.txq[i]); 1019 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 1020 } 1021 } 1022 } 1023 1024 ieee80211_wake_queues(hw); 1025 spin_unlock_bh(&sc->sc_pcu_lock); 1026 1027 /* Start ANI */ 1028 ath_start_ani(common); 1029 ath9k_ps_restore(sc); 1030 1031 return r; 1032 } 1033 1034 /**********************/ 1035 /* mac80211 callbacks */ 1036 /**********************/ 1037 1038 static int ath9k_start(struct ieee80211_hw *hw) 1039 { 1040 struct ath_softc *sc = hw->priv; 1041 struct ath_hw *ah = sc->sc_ah; 1042 struct ath_common *common = ath9k_hw_common(ah); 1043 struct ieee80211_channel *curchan = hw->conf.channel; 1044 struct ath9k_channel *init_channel; 1045 int r; 1046 1047 ath_dbg(common, ATH_DBG_CONFIG, 1048 "Starting driver with initial channel: %d MHz\n", 1049 curchan->center_freq); 1050 1051 mutex_lock(&sc->mutex); 1052 1053 /* setup initial channel */ 1054 sc->chan_idx = curchan->hw_value; 1055 1056 init_channel = ath9k_cmn_get_curchannel(hw, ah); 1057 1058 /* Reset SERDES registers */ 1059 ath9k_hw_configpcipowersave(ah, 0, 0); 1060 1061 /* 1062 * The basic interface to setting the hardware in a good 1063 * state is ``reset''. On return the hardware is known to 1064 * be powered up and with interrupts disabled. This must 1065 * be followed by initialization of the appropriate bits 1066 * and then setup of the interrupt mask. 1067 */ 1068 spin_lock_bh(&sc->sc_pcu_lock); 1069 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1070 if (r) { 1071 ath_err(common, 1072 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 1073 r, curchan->center_freq); 1074 spin_unlock_bh(&sc->sc_pcu_lock); 1075 goto mutex_unlock; 1076 } 1077 1078 /* 1079 * This is needed only to setup initial state 1080 * but it's best done after a reset. 1081 */ 1082 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1083 sc->config.txpowlimit, &sc->curtxpow); 1084 1085 /* 1086 * Setup the hardware after reset: 1087 * The receive engine is set going. 1088 * Frame transmit is handled entirely 1089 * in the frame output path; there's nothing to do 1090 * here except setup the interrupt mask. 1091 */ 1092 if (ath_startrecv(sc) != 0) { 1093 ath_err(common, "Unable to start recv logic\n"); 1094 r = -EIO; 1095 spin_unlock_bh(&sc->sc_pcu_lock); 1096 goto mutex_unlock; 1097 } 1098 spin_unlock_bh(&sc->sc_pcu_lock); 1099 1100 /* Setup our intr mask. */ 1101 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 1102 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 1103 ATH9K_INT_GLOBAL; 1104 1105 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 1106 ah->imask |= ATH9K_INT_RXHP | 1107 ATH9K_INT_RXLP | 1108 ATH9K_INT_BB_WATCHDOG; 1109 else 1110 ah->imask |= ATH9K_INT_RX; 1111 1112 ah->imask |= ATH9K_INT_GTT; 1113 1114 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 1115 ah->imask |= ATH9K_INT_CST; 1116 1117 sc->sc_flags &= ~SC_OP_INVALID; 1118 sc->sc_ah->is_monitoring = false; 1119 1120 /* Disable BMISS interrupt when we're not associated */ 1121 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1122 ath9k_hw_set_interrupts(ah, ah->imask); 1123 1124 ieee80211_wake_queues(hw); 1125 1126 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 1127 1128 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && 1129 !ah->btcoex_hw.enabled) { 1130 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 1131 AR_STOMP_LOW_WLAN_WGHT); 1132 ath9k_hw_btcoex_enable(ah); 1133 1134 if (common->bus_ops->bt_coex_prep) 1135 common->bus_ops->bt_coex_prep(common); 1136 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1137 ath9k_btcoex_timer_resume(sc); 1138 } 1139 1140 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) 1141 common->bus_ops->extn_synch_en(common); 1142 1143 mutex_unlock: 1144 mutex_unlock(&sc->mutex); 1145 1146 return r; 1147 } 1148 1149 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 1150 { 1151 struct ath_softc *sc = hw->priv; 1152 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1153 struct ath_tx_control txctl; 1154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1155 1156 if (sc->ps_enabled) { 1157 /* 1158 * mac80211 does not set PM field for normal data frames, so we 1159 * need to update that based on the current PS mode. 1160 */ 1161 if (ieee80211_is_data(hdr->frame_control) && 1162 !ieee80211_is_nullfunc(hdr->frame_control) && 1163 !ieee80211_has_pm(hdr->frame_control)) { 1164 ath_dbg(common, ATH_DBG_PS, 1165 "Add PM=1 for a TX frame while in PS mode\n"); 1166 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1167 } 1168 } 1169 1170 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { 1171 /* 1172 * We are using PS-Poll and mac80211 can request TX while in 1173 * power save mode. Need to wake up hardware for the TX to be 1174 * completed and if needed, also for RX of buffered frames. 1175 */ 1176 ath9k_ps_wakeup(sc); 1177 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 1178 ath9k_hw_setrxabort(sc->sc_ah, 0); 1179 if (ieee80211_is_pspoll(hdr->frame_control)) { 1180 ath_dbg(common, ATH_DBG_PS, 1181 "Sending PS-Poll to pick a buffered frame\n"); 1182 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 1183 } else { 1184 ath_dbg(common, ATH_DBG_PS, 1185 "Wake up to complete TX\n"); 1186 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 1187 } 1188 /* 1189 * The actual restore operation will happen only after 1190 * the sc_flags bit is cleared. We are just dropping 1191 * the ps_usecount here. 1192 */ 1193 ath9k_ps_restore(sc); 1194 } 1195 1196 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1197 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 1198 1199 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1200 1201 if (ath_tx_start(hw, skb, &txctl) != 0) { 1202 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); 1203 goto exit; 1204 } 1205 1206 return; 1207 exit: 1208 dev_kfree_skb_any(skb); 1209 } 1210 1211 static void ath9k_stop(struct ieee80211_hw *hw) 1212 { 1213 struct ath_softc *sc = hw->priv; 1214 struct ath_hw *ah = sc->sc_ah; 1215 struct ath_common *common = ath9k_hw_common(ah); 1216 1217 mutex_lock(&sc->mutex); 1218 1219 cancel_delayed_work_sync(&sc->tx_complete_work); 1220 cancel_delayed_work_sync(&sc->hw_pll_work); 1221 cancel_work_sync(&sc->paprd_work); 1222 cancel_work_sync(&sc->hw_check_work); 1223 1224 if (sc->sc_flags & SC_OP_INVALID) { 1225 ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); 1226 mutex_unlock(&sc->mutex); 1227 return; 1228 } 1229 1230 /* Ensure HW is awake when we try to shut it down. */ 1231 ath9k_ps_wakeup(sc); 1232 1233 if (ah->btcoex_hw.enabled) { 1234 ath9k_hw_btcoex_disable(ah); 1235 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1236 ath9k_btcoex_timer_pause(sc); 1237 } 1238 1239 spin_lock_bh(&sc->sc_pcu_lock); 1240 1241 /* prevent tasklets to enable interrupts once we disable them */ 1242 ah->imask &= ~ATH9K_INT_GLOBAL; 1243 1244 /* make sure h/w will not generate any interrupt 1245 * before setting the invalid flag. */ 1246 ath9k_hw_disable_interrupts(ah); 1247 1248 if (!(sc->sc_flags & SC_OP_INVALID)) { 1249 ath_drain_all_txq(sc, false); 1250 ath_stoprecv(sc); 1251 ath9k_hw_phy_disable(ah); 1252 } else 1253 sc->rx.rxlink = NULL; 1254 1255 if (sc->rx.frag) { 1256 dev_kfree_skb_any(sc->rx.frag); 1257 sc->rx.frag = NULL; 1258 } 1259 1260 /* disable HAL and put h/w to sleep */ 1261 ath9k_hw_disable(ah); 1262 ath9k_hw_configpcipowersave(ah, 1, 1); 1263 1264 spin_unlock_bh(&sc->sc_pcu_lock); 1265 1266 /* we can now sync irq and kill any running tasklets, since we already 1267 * disabled interrupts and not holding a spin lock */ 1268 synchronize_irq(sc->irq); 1269 tasklet_kill(&sc->intr_tq); 1270 tasklet_kill(&sc->bcon_tasklet); 1271 1272 ath9k_ps_restore(sc); 1273 1274 sc->ps_idle = true; 1275 ath_radio_disable(sc, hw); 1276 1277 sc->sc_flags |= SC_OP_INVALID; 1278 1279 mutex_unlock(&sc->mutex); 1280 1281 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); 1282 } 1283 1284 bool ath9k_uses_beacons(int type) 1285 { 1286 switch (type) { 1287 case NL80211_IFTYPE_AP: 1288 case NL80211_IFTYPE_ADHOC: 1289 case NL80211_IFTYPE_MESH_POINT: 1290 return true; 1291 default: 1292 return false; 1293 } 1294 } 1295 1296 static void ath9k_reclaim_beacon(struct ath_softc *sc, 1297 struct ieee80211_vif *vif) 1298 { 1299 struct ath_vif *avp = (void *)vif->drv_priv; 1300 1301 ath9k_set_beaconing_status(sc, false); 1302 ath_beacon_return(sc, avp); 1303 ath9k_set_beaconing_status(sc, true); 1304 sc->sc_flags &= ~SC_OP_BEACONS; 1305 } 1306 1307 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1308 { 1309 struct ath9k_vif_iter_data *iter_data = data; 1310 int i; 1311 1312 if (iter_data->hw_macaddr) 1313 for (i = 0; i < ETH_ALEN; i++) 1314 iter_data->mask[i] &= 1315 ~(iter_data->hw_macaddr[i] ^ mac[i]); 1316 1317 switch (vif->type) { 1318 case NL80211_IFTYPE_AP: 1319 iter_data->naps++; 1320 break; 1321 case NL80211_IFTYPE_STATION: 1322 iter_data->nstations++; 1323 break; 1324 case NL80211_IFTYPE_ADHOC: 1325 iter_data->nadhocs++; 1326 break; 1327 case NL80211_IFTYPE_MESH_POINT: 1328 iter_data->nmeshes++; 1329 break; 1330 case NL80211_IFTYPE_WDS: 1331 iter_data->nwds++; 1332 break; 1333 default: 1334 iter_data->nothers++; 1335 break; 1336 } 1337 } 1338 1339 /* Called with sc->mutex held. */ 1340 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 1341 struct ieee80211_vif *vif, 1342 struct ath9k_vif_iter_data *iter_data) 1343 { 1344 struct ath_softc *sc = hw->priv; 1345 struct ath_hw *ah = sc->sc_ah; 1346 struct ath_common *common = ath9k_hw_common(ah); 1347 1348 /* 1349 * Use the hardware MAC address as reference, the hardware uses it 1350 * together with the BSSID mask when matching addresses. 1351 */ 1352 memset(iter_data, 0, sizeof(*iter_data)); 1353 iter_data->hw_macaddr = common->macaddr; 1354 memset(&iter_data->mask, 0xff, ETH_ALEN); 1355 1356 if (vif) 1357 ath9k_vif_iter(iter_data, vif->addr, vif); 1358 1359 /* Get list of all active MAC addresses */ 1360 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, 1361 iter_data); 1362 } 1363 1364 /* Called with sc->mutex held. */ 1365 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 1366 struct ieee80211_vif *vif) 1367 { 1368 struct ath_softc *sc = hw->priv; 1369 struct ath_hw *ah = sc->sc_ah; 1370 struct ath_common *common = ath9k_hw_common(ah); 1371 struct ath9k_vif_iter_data iter_data; 1372 1373 ath9k_calculate_iter_data(hw, vif, &iter_data); 1374 1375 ath9k_ps_wakeup(sc); 1376 /* Set BSSID mask. */ 1377 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1378 ath_hw_setbssidmask(common); 1379 1380 /* Set op-mode & TSF */ 1381 if (iter_data.naps > 0) { 1382 ath9k_hw_set_tsfadjust(ah, 1); 1383 sc->sc_flags |= SC_OP_TSF_RESET; 1384 ah->opmode = NL80211_IFTYPE_AP; 1385 } else { 1386 ath9k_hw_set_tsfadjust(ah, 0); 1387 sc->sc_flags &= ~SC_OP_TSF_RESET; 1388 1389 if (iter_data.nwds + iter_data.nmeshes) 1390 ah->opmode = NL80211_IFTYPE_AP; 1391 else if (iter_data.nadhocs) 1392 ah->opmode = NL80211_IFTYPE_ADHOC; 1393 else 1394 ah->opmode = NL80211_IFTYPE_STATION; 1395 } 1396 1397 /* 1398 * Enable MIB interrupts when there are hardware phy counters. 1399 */ 1400 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { 1401 if (ah->config.enable_ani) 1402 ah->imask |= ATH9K_INT_MIB; 1403 ah->imask |= ATH9K_INT_TSFOOR; 1404 } else { 1405 ah->imask &= ~ATH9K_INT_MIB; 1406 ah->imask &= ~ATH9K_INT_TSFOOR; 1407 } 1408 1409 ath9k_hw_set_interrupts(ah, ah->imask); 1410 ath9k_ps_restore(sc); 1411 1412 /* Set up ANI */ 1413 if ((iter_data.naps + iter_data.nadhocs) > 0) { 1414 sc->sc_flags |= SC_OP_ANI_RUN; 1415 ath_start_ani(common); 1416 } else { 1417 sc->sc_flags &= ~SC_OP_ANI_RUN; 1418 del_timer_sync(&common->ani.timer); 1419 } 1420 } 1421 1422 /* Called with sc->mutex held, vif counts set up properly. */ 1423 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, 1424 struct ieee80211_vif *vif) 1425 { 1426 struct ath_softc *sc = hw->priv; 1427 1428 ath9k_calculate_summary_state(hw, vif); 1429 1430 if (ath9k_uses_beacons(vif->type)) { 1431 int error; 1432 /* This may fail because upper levels do not have beacons 1433 * properly configured yet. That's OK, we assume it 1434 * will be properly configured and then we will be notified 1435 * in the info_changed method and set up beacons properly 1436 * there. 1437 */ 1438 ath9k_set_beaconing_status(sc, false); 1439 error = ath_beacon_alloc(sc, vif); 1440 if (!error) 1441 ath_beacon_config(sc, vif); 1442 ath9k_set_beaconing_status(sc, true); 1443 } 1444 } 1445 1446 1447 static int ath9k_add_interface(struct ieee80211_hw *hw, 1448 struct ieee80211_vif *vif) 1449 { 1450 struct ath_softc *sc = hw->priv; 1451 struct ath_hw *ah = sc->sc_ah; 1452 struct ath_common *common = ath9k_hw_common(ah); 1453 struct ath_vif *avp = (void *)vif->drv_priv; 1454 int ret = 0; 1455 1456 mutex_lock(&sc->mutex); 1457 1458 switch (vif->type) { 1459 case NL80211_IFTYPE_STATION: 1460 case NL80211_IFTYPE_WDS: 1461 case NL80211_IFTYPE_ADHOC: 1462 case NL80211_IFTYPE_AP: 1463 case NL80211_IFTYPE_MESH_POINT: 1464 break; 1465 default: 1466 ath_err(common, "Interface type %d not yet supported\n", 1467 vif->type); 1468 ret = -EOPNOTSUPP; 1469 goto out; 1470 } 1471 1472 if (ath9k_uses_beacons(vif->type)) { 1473 if (sc->nbcnvifs >= ATH_BCBUF) { 1474 ath_err(common, "Not enough beacon buffers when adding" 1475 " new interface of type: %i\n", 1476 vif->type); 1477 ret = -ENOBUFS; 1478 goto out; 1479 } 1480 } 1481 1482 if ((vif->type == NL80211_IFTYPE_ADHOC) && 1483 sc->nvifs > 0) { 1484 ath_err(common, "Cannot create ADHOC interface when other" 1485 " interfaces already exist.\n"); 1486 ret = -EINVAL; 1487 goto out; 1488 } 1489 1490 ath_dbg(common, ATH_DBG_CONFIG, 1491 "Attach a VIF of type: %d\n", vif->type); 1492 1493 /* Set the VIF opmode */ 1494 avp->av_opmode = vif->type; 1495 avp->av_bslot = -1; 1496 1497 sc->nvifs++; 1498 1499 ath9k_do_vif_add_setup(hw, vif); 1500 out: 1501 mutex_unlock(&sc->mutex); 1502 return ret; 1503 } 1504 1505 static int ath9k_change_interface(struct ieee80211_hw *hw, 1506 struct ieee80211_vif *vif, 1507 enum nl80211_iftype new_type, 1508 bool p2p) 1509 { 1510 struct ath_softc *sc = hw->priv; 1511 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1512 int ret = 0; 1513 1514 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); 1515 mutex_lock(&sc->mutex); 1516 1517 /* See if new interface type is valid. */ 1518 if ((new_type == NL80211_IFTYPE_ADHOC) && 1519 (sc->nvifs > 1)) { 1520 ath_err(common, "When using ADHOC, it must be the only" 1521 " interface.\n"); 1522 ret = -EINVAL; 1523 goto out; 1524 } 1525 1526 if (ath9k_uses_beacons(new_type) && 1527 !ath9k_uses_beacons(vif->type)) { 1528 if (sc->nbcnvifs >= ATH_BCBUF) { 1529 ath_err(common, "No beacon slot available\n"); 1530 ret = -ENOBUFS; 1531 goto out; 1532 } 1533 } 1534 1535 /* Clean up old vif stuff */ 1536 if (ath9k_uses_beacons(vif->type)) 1537 ath9k_reclaim_beacon(sc, vif); 1538 1539 /* Add new settings */ 1540 vif->type = new_type; 1541 vif->p2p = p2p; 1542 1543 ath9k_do_vif_add_setup(hw, vif); 1544 out: 1545 mutex_unlock(&sc->mutex); 1546 return ret; 1547 } 1548 1549 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1550 struct ieee80211_vif *vif) 1551 { 1552 struct ath_softc *sc = hw->priv; 1553 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1554 1555 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1556 1557 mutex_lock(&sc->mutex); 1558 1559 sc->nvifs--; 1560 1561 /* Reclaim beacon resources */ 1562 if (ath9k_uses_beacons(vif->type)) 1563 ath9k_reclaim_beacon(sc, vif); 1564 1565 ath9k_calculate_summary_state(hw, NULL); 1566 1567 mutex_unlock(&sc->mutex); 1568 } 1569 1570 static void ath9k_enable_ps(struct ath_softc *sc) 1571 { 1572 struct ath_hw *ah = sc->sc_ah; 1573 1574 sc->ps_enabled = true; 1575 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1576 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1577 ah->imask |= ATH9K_INT_TIM_TIMER; 1578 ath9k_hw_set_interrupts(ah, ah->imask); 1579 } 1580 ath9k_hw_setrxabort(ah, 1); 1581 } 1582 } 1583 1584 static void ath9k_disable_ps(struct ath_softc *sc) 1585 { 1586 struct ath_hw *ah = sc->sc_ah; 1587 1588 sc->ps_enabled = false; 1589 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1590 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1591 ath9k_hw_setrxabort(ah, 0); 1592 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1593 PS_WAIT_FOR_CAB | 1594 PS_WAIT_FOR_PSPOLL_DATA | 1595 PS_WAIT_FOR_TX_ACK); 1596 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1597 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1598 ath9k_hw_set_interrupts(ah, ah->imask); 1599 } 1600 } 1601 1602 } 1603 1604 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1605 { 1606 struct ath_softc *sc = hw->priv; 1607 struct ath_hw *ah = sc->sc_ah; 1608 struct ath_common *common = ath9k_hw_common(ah); 1609 struct ieee80211_conf *conf = &hw->conf; 1610 bool disable_radio = false; 1611 1612 mutex_lock(&sc->mutex); 1613 1614 /* 1615 * Leave this as the first check because we need to turn on the 1616 * radio if it was disabled before prior to processing the rest 1617 * of the changes. Likewise we must only disable the radio towards 1618 * the end. 1619 */ 1620 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1621 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1622 if (!sc->ps_idle) { 1623 ath_radio_enable(sc, hw); 1624 ath_dbg(common, ATH_DBG_CONFIG, 1625 "not-idle: enabling radio\n"); 1626 } else { 1627 disable_radio = true; 1628 } 1629 } 1630 1631 /* 1632 * We just prepare to enable PS. We have to wait until our AP has 1633 * ACK'd our null data frame to disable RX otherwise we'll ignore 1634 * those ACKs and end up retransmitting the same null data frames. 1635 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1636 */ 1637 if (changed & IEEE80211_CONF_CHANGE_PS) { 1638 unsigned long flags; 1639 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1640 if (conf->flags & IEEE80211_CONF_PS) 1641 ath9k_enable_ps(sc); 1642 else 1643 ath9k_disable_ps(sc); 1644 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1645 } 1646 1647 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1648 if (conf->flags & IEEE80211_CONF_MONITOR) { 1649 ath_dbg(common, ATH_DBG_CONFIG, 1650 "Monitor mode is enabled\n"); 1651 sc->sc_ah->is_monitoring = true; 1652 } else { 1653 ath_dbg(common, ATH_DBG_CONFIG, 1654 "Monitor mode is disabled\n"); 1655 sc->sc_ah->is_monitoring = false; 1656 } 1657 } 1658 1659 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1660 struct ieee80211_channel *curchan = hw->conf.channel; 1661 int pos = curchan->hw_value; 1662 int old_pos = -1; 1663 unsigned long flags; 1664 1665 if (ah->curchan) 1666 old_pos = ah->curchan - &ah->channels[0]; 1667 1668 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 1669 sc->sc_flags |= SC_OP_OFFCHANNEL; 1670 else 1671 sc->sc_flags &= ~SC_OP_OFFCHANNEL; 1672 1673 ath_dbg(common, ATH_DBG_CONFIG, 1674 "Set channel: %d MHz type: %d\n", 1675 curchan->center_freq, conf->channel_type); 1676 1677 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1678 curchan, conf->channel_type); 1679 1680 /* update survey stats for the old channel before switching */ 1681 spin_lock_irqsave(&common->cc_lock, flags); 1682 ath_update_survey_stats(sc); 1683 spin_unlock_irqrestore(&common->cc_lock, flags); 1684 1685 /* 1686 * If the operating channel changes, change the survey in-use flags 1687 * along with it. 1688 * Reset the survey data for the new channel, unless we're switching 1689 * back to the operating channel from an off-channel operation. 1690 */ 1691 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1692 sc->cur_survey != &sc->survey[pos]) { 1693 1694 if (sc->cur_survey) 1695 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1696 1697 sc->cur_survey = &sc->survey[pos]; 1698 1699 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1700 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1701 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1702 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1703 } 1704 1705 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1706 ath_err(common, "Unable to set channel\n"); 1707 mutex_unlock(&sc->mutex); 1708 return -EINVAL; 1709 } 1710 1711 /* 1712 * The most recent snapshot of channel->noisefloor for the old 1713 * channel is only available after the hardware reset. Copy it to 1714 * the survey stats now. 1715 */ 1716 if (old_pos >= 0) 1717 ath_update_survey_nf(sc, old_pos); 1718 } 1719 1720 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1721 ath_dbg(common, ATH_DBG_CONFIG, 1722 "Set power: %d\n", conf->power_level); 1723 sc->config.txpowlimit = 2 * conf->power_level; 1724 ath9k_ps_wakeup(sc); 1725 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1726 sc->config.txpowlimit, &sc->curtxpow); 1727 ath9k_ps_restore(sc); 1728 } 1729 1730 if (disable_radio) { 1731 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); 1732 ath_radio_disable(sc, hw); 1733 } 1734 1735 mutex_unlock(&sc->mutex); 1736 1737 return 0; 1738 } 1739 1740 #define SUPPORTED_FILTERS \ 1741 (FIF_PROMISC_IN_BSS | \ 1742 FIF_ALLMULTI | \ 1743 FIF_CONTROL | \ 1744 FIF_PSPOLL | \ 1745 FIF_OTHER_BSS | \ 1746 FIF_BCN_PRBRESP_PROMISC | \ 1747 FIF_PROBE_REQ | \ 1748 FIF_FCSFAIL) 1749 1750 /* FIXME: sc->sc_full_reset ? */ 1751 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1752 unsigned int changed_flags, 1753 unsigned int *total_flags, 1754 u64 multicast) 1755 { 1756 struct ath_softc *sc = hw->priv; 1757 u32 rfilt; 1758 1759 changed_flags &= SUPPORTED_FILTERS; 1760 *total_flags &= SUPPORTED_FILTERS; 1761 1762 sc->rx.rxfilter = *total_flags; 1763 ath9k_ps_wakeup(sc); 1764 rfilt = ath_calcrxfilter(sc); 1765 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1766 ath9k_ps_restore(sc); 1767 1768 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 1769 "Set HW RX filter: 0x%x\n", rfilt); 1770 } 1771 1772 static int ath9k_sta_add(struct ieee80211_hw *hw, 1773 struct ieee80211_vif *vif, 1774 struct ieee80211_sta *sta) 1775 { 1776 struct ath_softc *sc = hw->priv; 1777 1778 ath_node_attach(sc, sta); 1779 1780 return 0; 1781 } 1782 1783 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1784 struct ieee80211_vif *vif, 1785 struct ieee80211_sta *sta) 1786 { 1787 struct ath_softc *sc = hw->priv; 1788 1789 ath_node_detach(sc, sta); 1790 1791 return 0; 1792 } 1793 1794 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, 1795 const struct ieee80211_tx_queue_params *params) 1796 { 1797 struct ath_softc *sc = hw->priv; 1798 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1799 struct ath_txq *txq; 1800 struct ath9k_tx_queue_info qi; 1801 int ret = 0; 1802 1803 if (queue >= WME_NUM_AC) 1804 return 0; 1805 1806 txq = sc->tx.txq_map[queue]; 1807 1808 mutex_lock(&sc->mutex); 1809 1810 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1811 1812 qi.tqi_aifs = params->aifs; 1813 qi.tqi_cwmin = params->cw_min; 1814 qi.tqi_cwmax = params->cw_max; 1815 qi.tqi_burstTime = params->txop; 1816 1817 ath_dbg(common, ATH_DBG_CONFIG, 1818 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1819 queue, txq->axq_qnum, params->aifs, params->cw_min, 1820 params->cw_max, params->txop); 1821 1822 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1823 if (ret) 1824 ath_err(common, "TXQ Update failed\n"); 1825 1826 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) 1827 if (queue == WME_AC_BE && !ret) 1828 ath_beaconq_config(sc); 1829 1830 mutex_unlock(&sc->mutex); 1831 1832 return ret; 1833 } 1834 1835 static int ath9k_set_key(struct ieee80211_hw *hw, 1836 enum set_key_cmd cmd, 1837 struct ieee80211_vif *vif, 1838 struct ieee80211_sta *sta, 1839 struct ieee80211_key_conf *key) 1840 { 1841 struct ath_softc *sc = hw->priv; 1842 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1843 int ret = 0; 1844 1845 if (ath9k_modparam_nohwcrypt) 1846 return -ENOSPC; 1847 1848 mutex_lock(&sc->mutex); 1849 ath9k_ps_wakeup(sc); 1850 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1851 1852 switch (cmd) { 1853 case SET_KEY: 1854 ret = ath_key_config(common, vif, sta, key); 1855 if (ret >= 0) { 1856 key->hw_key_idx = ret; 1857 /* push IV and Michael MIC generation to stack */ 1858 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1859 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1860 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1861 if (sc->sc_ah->sw_mgmt_crypto && 1862 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1863 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1864 ret = 0; 1865 } 1866 break; 1867 case DISABLE_KEY: 1868 ath_key_delete(common, key); 1869 break; 1870 default: 1871 ret = -EINVAL; 1872 } 1873 1874 ath9k_ps_restore(sc); 1875 mutex_unlock(&sc->mutex); 1876 1877 return ret; 1878 } 1879 1880 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1881 struct ieee80211_vif *vif, 1882 struct ieee80211_bss_conf *bss_conf, 1883 u32 changed) 1884 { 1885 struct ath_softc *sc = hw->priv; 1886 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 1887 struct ath_hw *ah = sc->sc_ah; 1888 struct ath_common *common = ath9k_hw_common(ah); 1889 struct ath_vif *avp = (void *)vif->drv_priv; 1890 int slottime; 1891 int error; 1892 1893 mutex_lock(&sc->mutex); 1894 1895 if (changed & BSS_CHANGED_BSSID) { 1896 /* Set BSSID */ 1897 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1898 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1899 common->curaid = 0; 1900 ath9k_hw_write_associd(ah); 1901 1902 /* Set aggregation protection mode parameters */ 1903 sc->config.ath_aggr_prot = 0; 1904 1905 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", 1906 common->curbssid, common->curaid); 1907 1908 /* need to reconfigure the beacon */ 1909 sc->sc_flags &= ~SC_OP_BEACONS ; 1910 } 1911 1912 /* Enable transmission of beacons (AP, IBSS, MESH) */ 1913 if ((changed & BSS_CHANGED_BEACON) || 1914 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { 1915 ath9k_set_beaconing_status(sc, false); 1916 error = ath_beacon_alloc(sc, vif); 1917 if (!error) 1918 ath_beacon_config(sc, vif); 1919 ath9k_set_beaconing_status(sc, true); 1920 } 1921 1922 if (changed & BSS_CHANGED_ERP_SLOT) { 1923 if (bss_conf->use_short_slot) 1924 slottime = 9; 1925 else 1926 slottime = 20; 1927 if (vif->type == NL80211_IFTYPE_AP) { 1928 /* 1929 * Defer update, so that connected stations can adjust 1930 * their settings at the same time. 1931 * See beacon.c for more details 1932 */ 1933 sc->beacon.slottime = slottime; 1934 sc->beacon.updateslot = UPDATE; 1935 } else { 1936 ah->slottime = slottime; 1937 ath9k_hw_init_global_settings(ah); 1938 } 1939 } 1940 1941 /* Disable transmission of beacons */ 1942 if ((changed & BSS_CHANGED_BEACON_ENABLED) && 1943 !bss_conf->enable_beacon) { 1944 ath9k_set_beaconing_status(sc, false); 1945 avp->is_bslot_active = false; 1946 ath9k_set_beaconing_status(sc, true); 1947 } 1948 1949 if (changed & BSS_CHANGED_BEACON_INT) { 1950 cur_conf->beacon_interval = bss_conf->beacon_int; 1951 /* 1952 * In case of AP mode, the HW TSF has to be reset 1953 * when the beacon interval changes. 1954 */ 1955 if (vif->type == NL80211_IFTYPE_AP) { 1956 sc->sc_flags |= SC_OP_TSF_RESET; 1957 ath9k_set_beaconing_status(sc, false); 1958 error = ath_beacon_alloc(sc, vif); 1959 if (!error) 1960 ath_beacon_config(sc, vif); 1961 ath9k_set_beaconing_status(sc, true); 1962 } else { 1963 ath_beacon_config(sc, vif); 1964 } 1965 } 1966 1967 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1968 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1969 bss_conf->use_short_preamble); 1970 if (bss_conf->use_short_preamble) 1971 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 1972 else 1973 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; 1974 } 1975 1976 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1977 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1978 bss_conf->use_cts_prot); 1979 if (bss_conf->use_cts_prot && 1980 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1981 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 1982 else 1983 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; 1984 } 1985 1986 if (changed & BSS_CHANGED_ASSOC) { 1987 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1988 bss_conf->assoc); 1989 ath9k_bss_assoc_info(sc, hw, vif, bss_conf); 1990 } 1991 1992 mutex_unlock(&sc->mutex); 1993 } 1994 1995 static u64 ath9k_get_tsf(struct ieee80211_hw *hw) 1996 { 1997 struct ath_softc *sc = hw->priv; 1998 u64 tsf; 1999 2000 mutex_lock(&sc->mutex); 2001 ath9k_ps_wakeup(sc); 2002 tsf = ath9k_hw_gettsf64(sc->sc_ah); 2003 ath9k_ps_restore(sc); 2004 mutex_unlock(&sc->mutex); 2005 2006 return tsf; 2007 } 2008 2009 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 2010 { 2011 struct ath_softc *sc = hw->priv; 2012 2013 mutex_lock(&sc->mutex); 2014 ath9k_ps_wakeup(sc); 2015 ath9k_hw_settsf64(sc->sc_ah, tsf); 2016 ath9k_ps_restore(sc); 2017 mutex_unlock(&sc->mutex); 2018 } 2019 2020 static void ath9k_reset_tsf(struct ieee80211_hw *hw) 2021 { 2022 struct ath_softc *sc = hw->priv; 2023 2024 mutex_lock(&sc->mutex); 2025 2026 ath9k_ps_wakeup(sc); 2027 ath9k_hw_reset_tsf(sc->sc_ah); 2028 ath9k_ps_restore(sc); 2029 2030 mutex_unlock(&sc->mutex); 2031 } 2032 2033 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 2034 struct ieee80211_vif *vif, 2035 enum ieee80211_ampdu_mlme_action action, 2036 struct ieee80211_sta *sta, 2037 u16 tid, u16 *ssn, u8 buf_size) 2038 { 2039 struct ath_softc *sc = hw->priv; 2040 int ret = 0; 2041 2042 local_bh_disable(); 2043 2044 switch (action) { 2045 case IEEE80211_AMPDU_RX_START: 2046 if (!(sc->sc_flags & SC_OP_RXAGGR)) 2047 ret = -ENOTSUPP; 2048 break; 2049 case IEEE80211_AMPDU_RX_STOP: 2050 break; 2051 case IEEE80211_AMPDU_TX_START: 2052 if (!(sc->sc_flags & SC_OP_TXAGGR)) 2053 return -EOPNOTSUPP; 2054 2055 ath9k_ps_wakeup(sc); 2056 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 2057 if (!ret) 2058 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2059 ath9k_ps_restore(sc); 2060 break; 2061 case IEEE80211_AMPDU_TX_STOP: 2062 ath9k_ps_wakeup(sc); 2063 ath_tx_aggr_stop(sc, sta, tid); 2064 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2065 ath9k_ps_restore(sc); 2066 break; 2067 case IEEE80211_AMPDU_TX_OPERATIONAL: 2068 ath9k_ps_wakeup(sc); 2069 ath_tx_aggr_resume(sc, sta, tid); 2070 ath9k_ps_restore(sc); 2071 break; 2072 default: 2073 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 2074 } 2075 2076 local_bh_enable(); 2077 2078 return ret; 2079 } 2080 2081 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 2082 struct survey_info *survey) 2083 { 2084 struct ath_softc *sc = hw->priv; 2085 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2086 struct ieee80211_supported_band *sband; 2087 struct ieee80211_channel *chan; 2088 unsigned long flags; 2089 int pos; 2090 2091 spin_lock_irqsave(&common->cc_lock, flags); 2092 if (idx == 0) 2093 ath_update_survey_stats(sc); 2094 2095 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 2096 if (sband && idx >= sband->n_channels) { 2097 idx -= sband->n_channels; 2098 sband = NULL; 2099 } 2100 2101 if (!sband) 2102 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 2103 2104 if (!sband || idx >= sband->n_channels) { 2105 spin_unlock_irqrestore(&common->cc_lock, flags); 2106 return -ENOENT; 2107 } 2108 2109 chan = &sband->channels[idx]; 2110 pos = chan->hw_value; 2111 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 2112 survey->channel = chan; 2113 spin_unlock_irqrestore(&common->cc_lock, flags); 2114 2115 return 0; 2116 } 2117 2118 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 2119 { 2120 struct ath_softc *sc = hw->priv; 2121 struct ath_hw *ah = sc->sc_ah; 2122 2123 mutex_lock(&sc->mutex); 2124 ah->coverage_class = coverage_class; 2125 ath9k_hw_init_global_settings(ah); 2126 mutex_unlock(&sc->mutex); 2127 } 2128 2129 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 2130 { 2131 struct ath_softc *sc = hw->priv; 2132 int timeout = 200; /* ms */ 2133 int i, j; 2134 2135 ath9k_ps_wakeup(sc); 2136 mutex_lock(&sc->mutex); 2137 2138 cancel_delayed_work_sync(&sc->tx_complete_work); 2139 2140 if (drop) 2141 timeout = 1; 2142 2143 for (j = 0; j < timeout; j++) { 2144 int npend = 0; 2145 2146 if (j) 2147 usleep_range(1000, 2000); 2148 2149 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2150 if (!ATH_TXQ_SETUP(sc, i)) 2151 continue; 2152 2153 npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 2154 } 2155 2156 if (!npend) 2157 goto out; 2158 } 2159 2160 if (!ath_drain_all_txq(sc, false)) 2161 ath_reset(sc, false); 2162 2163 out: 2164 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2165 mutex_unlock(&sc->mutex); 2166 ath9k_ps_restore(sc); 2167 } 2168 2169 struct ieee80211_ops ath9k_ops = { 2170 .tx = ath9k_tx, 2171 .start = ath9k_start, 2172 .stop = ath9k_stop, 2173 .add_interface = ath9k_add_interface, 2174 .change_interface = ath9k_change_interface, 2175 .remove_interface = ath9k_remove_interface, 2176 .config = ath9k_config, 2177 .configure_filter = ath9k_configure_filter, 2178 .sta_add = ath9k_sta_add, 2179 .sta_remove = ath9k_sta_remove, 2180 .conf_tx = ath9k_conf_tx, 2181 .bss_info_changed = ath9k_bss_info_changed, 2182 .set_key = ath9k_set_key, 2183 .get_tsf = ath9k_get_tsf, 2184 .set_tsf = ath9k_set_tsf, 2185 .reset_tsf = ath9k_reset_tsf, 2186 .ampdu_action = ath9k_ampdu_action, 2187 .get_survey = ath9k_get_survey, 2188 .rfkill_poll = ath9k_rfkill_poll_state, 2189 .set_coverage_class = ath9k_set_coverage_class, 2190 .flush = ath9k_flush, 2191 }; 2192