1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 23 u32 queues, bool drop); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq, 61 bool sw_pending) 62 { 63 bool pending = false; 64 65 spin_lock_bh(&txq->axq_lock); 66 67 if (txq->axq_depth) { 68 pending = true; 69 goto out; 70 } 71 72 if (!sw_pending) 73 goto out; 74 75 if (txq->mac80211_qnum >= 0) { 76 struct ath_acq *acq; 77 78 acq = &sc->cur_chan->acq[txq->mac80211_qnum]; 79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old)) 80 pending = true; 81 } 82 out: 83 spin_unlock_bh(&txq->axq_lock); 84 return pending; 85 } 86 87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 88 { 89 unsigned long flags; 90 bool ret; 91 92 spin_lock_irqsave(&sc->sc_pm_lock, flags); 93 ret = ath9k_hw_setpower(sc->sc_ah, mode); 94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 95 96 return ret; 97 } 98 99 void ath_ps_full_sleep(struct timer_list *t) 100 { 101 struct ath_softc *sc = from_timer(sc, t, sleep_timer); 102 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 103 unsigned long flags; 104 bool reset; 105 106 spin_lock_irqsave(&common->cc_lock, flags); 107 ath_hw_cycle_counters_update(common); 108 spin_unlock_irqrestore(&common->cc_lock, flags); 109 110 ath9k_hw_setrxabort(sc->sc_ah, 1); 111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 112 113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 114 } 115 116 void ath9k_ps_wakeup(struct ath_softc *sc) 117 { 118 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 119 unsigned long flags; 120 enum ath9k_power_mode power_mode; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (++sc->ps_usecount != 1) 124 goto unlock; 125 126 del_timer_sync(&sc->sleep_timer); 127 power_mode = sc->sc_ah->power_mode; 128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 129 130 /* 131 * While the hardware is asleep, the cycle counters contain no 132 * useful data. Better clear them now so that they don't mess up 133 * survey data results. 134 */ 135 if (power_mode != ATH9K_PM_AWAKE) { 136 spin_lock(&common->cc_lock); 137 ath_hw_cycle_counters_update(common); 138 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 139 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 140 spin_unlock(&common->cc_lock); 141 } 142 143 unlock: 144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 145 } 146 147 void ath9k_ps_restore(struct ath_softc *sc) 148 { 149 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 150 enum ath9k_power_mode mode; 151 unsigned long flags; 152 153 spin_lock_irqsave(&sc->sc_pm_lock, flags); 154 if (--sc->ps_usecount != 0) 155 goto unlock; 156 157 if (sc->ps_idle) { 158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 159 goto unlock; 160 } 161 162 if (sc->ps_enabled && 163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 164 PS_WAIT_FOR_CAB | 165 PS_WAIT_FOR_PSPOLL_DATA | 166 PS_WAIT_FOR_TX_ACK | 167 PS_WAIT_FOR_ANI))) { 168 mode = ATH9K_PM_NETWORK_SLEEP; 169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 170 ath9k_btcoex_stop_gen_timer(sc); 171 } else { 172 goto unlock; 173 } 174 175 spin_lock(&common->cc_lock); 176 ath_hw_cycle_counters_update(common); 177 spin_unlock(&common->cc_lock); 178 179 ath9k_hw_setpower(sc->sc_ah, mode); 180 181 unlock: 182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 183 } 184 185 static void __ath_cancel_work(struct ath_softc *sc) 186 { 187 cancel_work_sync(&sc->paprd_work); 188 cancel_delayed_work_sync(&sc->hw_check_work); 189 cancel_delayed_work_sync(&sc->hw_pll_work); 190 191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 192 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 193 cancel_work_sync(&sc->mci_work); 194 #endif 195 } 196 197 void ath_cancel_work(struct ath_softc *sc) 198 { 199 __ath_cancel_work(sc); 200 cancel_work_sync(&sc->hw_reset_work); 201 } 202 203 void ath_restart_work(struct ath_softc *sc) 204 { 205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, 206 ATH_HW_CHECK_POLL_INT); 207 208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 211 212 ath_start_ani(sc); 213 } 214 215 static bool ath_prepare_reset(struct ath_softc *sc) 216 { 217 struct ath_hw *ah = sc->sc_ah; 218 bool ret = true; 219 220 ieee80211_stop_queues(sc->hw); 221 ath_stop_ani(sc); 222 ath9k_hw_disable_interrupts(ah); 223 224 if (AR_SREV_9300_20_OR_LATER(ah)) { 225 ret &= ath_stoprecv(sc); 226 ret &= ath_drain_all_txq(sc); 227 } else { 228 ret &= ath_drain_all_txq(sc); 229 ret &= ath_stoprecv(sc); 230 } 231 232 return ret; 233 } 234 235 static bool ath_complete_reset(struct ath_softc *sc, bool start) 236 { 237 struct ath_hw *ah = sc->sc_ah; 238 struct ath_common *common = ath9k_hw_common(ah); 239 unsigned long flags; 240 241 ath9k_calculate_summary_state(sc, sc->cur_chan); 242 ath_startrecv(sc); 243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 244 sc->cur_chan->txpower, 245 &sc->cur_chan->cur_txpower); 246 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 247 248 if (!sc->cur_chan->offchannel && start) { 249 /* restore per chanctx TSF timer */ 250 if (sc->cur_chan->tsf_val) { 251 u32 offset; 252 253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 254 NULL); 255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 256 } 257 258 259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 260 goto work; 261 262 if (ah->opmode == NL80211_IFTYPE_STATION && 263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 264 spin_lock_irqsave(&sc->sc_pm_lock, flags); 265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 267 } else { 268 ath9k_set_beacon(sc); 269 } 270 work: 271 ath_restart_work(sc); 272 ath_txq_schedule_all(sc); 273 } 274 275 sc->gtt_cnt = 0; 276 277 ath9k_hw_set_interrupts(ah); 278 ath9k_hw_enable_interrupts(ah); 279 ieee80211_wake_queues(sc->hw); 280 ath9k_p2p_ps_timer(sc); 281 282 return true; 283 } 284 285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 286 { 287 struct ath_hw *ah = sc->sc_ah; 288 struct ath_common *common = ath9k_hw_common(ah); 289 struct ath9k_hw_cal_data *caldata = NULL; 290 bool fastcc = true; 291 int r; 292 293 __ath_cancel_work(sc); 294 295 disable_irq(sc->irq); 296 tasklet_disable(&sc->intr_tq); 297 tasklet_disable(&sc->bcon_tasklet); 298 spin_lock_bh(&sc->sc_pcu_lock); 299 300 if (!sc->cur_chan->offchannel) { 301 fastcc = false; 302 caldata = &sc->cur_chan->caldata; 303 } 304 305 if (!hchan) { 306 fastcc = false; 307 hchan = ah->curchan; 308 } 309 310 if (!ath_prepare_reset(sc)) 311 fastcc = false; 312 313 if (ath9k_is_chanctx_enabled()) 314 fastcc = false; 315 316 spin_lock_bh(&sc->chan_lock); 317 sc->cur_chandef = sc->cur_chan->chandef; 318 spin_unlock_bh(&sc->chan_lock); 319 320 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 321 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 322 323 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 324 if (r) { 325 ath_err(common, 326 "Unable to reset channel, reset status %d\n", r); 327 328 ath9k_hw_enable_interrupts(ah); 329 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 330 331 goto out; 332 } 333 334 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 335 sc->cur_chan->offchannel) 336 ath9k_mci_set_txpower(sc, true, false); 337 338 if (!ath_complete_reset(sc, true)) 339 r = -EIO; 340 341 out: 342 enable_irq(sc->irq); 343 spin_unlock_bh(&sc->sc_pcu_lock); 344 tasklet_enable(&sc->bcon_tasklet); 345 tasklet_enable(&sc->intr_tq); 346 347 return r; 348 } 349 350 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 351 struct ieee80211_vif *vif) 352 { 353 struct ath_node *an; 354 an = (struct ath_node *)sta->drv_priv; 355 356 an->sc = sc; 357 an->sta = sta; 358 an->vif = vif; 359 memset(&an->key_idx, 0, sizeof(an->key_idx)); 360 361 ath_tx_node_init(sc, an); 362 363 ath_dynack_node_init(sc->sc_ah, an); 364 } 365 366 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 367 { 368 struct ath_node *an = (struct ath_node *)sta->drv_priv; 369 ath_tx_node_cleanup(sc, an); 370 371 ath_dynack_node_deinit(sc->sc_ah, an); 372 } 373 374 void ath9k_tasklet(struct tasklet_struct *t) 375 { 376 struct ath_softc *sc = from_tasklet(sc, t, intr_tq); 377 struct ath_hw *ah = sc->sc_ah; 378 struct ath_common *common = ath9k_hw_common(ah); 379 enum ath_reset_type type; 380 unsigned long flags; 381 u32 status; 382 u32 rxmask; 383 384 spin_lock_irqsave(&sc->intr_lock, flags); 385 status = sc->intrstatus; 386 sc->intrstatus = 0; 387 spin_unlock_irqrestore(&sc->intr_lock, flags); 388 389 ath9k_ps_wakeup(sc); 390 spin_lock(&sc->sc_pcu_lock); 391 392 if (status & ATH9K_INT_FATAL) { 393 type = RESET_TYPE_FATAL_INT; 394 ath9k_queue_reset(sc, type); 395 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 396 goto out; 397 } 398 399 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 400 (status & ATH9K_INT_BB_WATCHDOG)) { 401 spin_lock_irqsave(&common->cc_lock, flags); 402 ath_hw_cycle_counters_update(common); 403 ar9003_hw_bb_watchdog_dbg_info(ah); 404 spin_unlock_irqrestore(&common->cc_lock, flags); 405 406 if (ar9003_hw_bb_watchdog_check(ah)) { 407 type = RESET_TYPE_BB_WATCHDOG; 408 ath9k_queue_reset(sc, type); 409 410 ath_dbg(common, RESET, 411 "BB_WATCHDOG: Skipping interrupts\n"); 412 goto out; 413 } 414 } 415 416 if (status & ATH9K_INT_GTT) { 417 sc->gtt_cnt++; 418 419 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 420 type = RESET_TYPE_TX_GTT; 421 ath9k_queue_reset(sc, type); 422 ath_dbg(common, RESET, 423 "GTT: Skipping interrupts\n"); 424 goto out; 425 } 426 } 427 428 spin_lock_irqsave(&sc->sc_pm_lock, flags); 429 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 430 /* 431 * TSF sync does not look correct; remain awake to sync with 432 * the next Beacon. 433 */ 434 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 435 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 436 } 437 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 438 439 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 440 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 441 ATH9K_INT_RXORN); 442 else 443 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 444 445 if (status & rxmask) { 446 /* Check for high priority Rx first */ 447 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 448 (status & ATH9K_INT_RXHP)) 449 ath_rx_tasklet(sc, 0, true); 450 451 ath_rx_tasklet(sc, 0, false); 452 } 453 454 if (status & ATH9K_INT_TX) { 455 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 456 /* 457 * For EDMA chips, TX completion is enabled for the 458 * beacon queue, so if a beacon has been transmitted 459 * successfully after a GTT interrupt, the GTT counter 460 * gets reset to zero here. 461 */ 462 sc->gtt_cnt = 0; 463 464 ath_tx_edma_tasklet(sc); 465 } else { 466 ath_tx_tasklet(sc); 467 } 468 469 wake_up(&sc->tx_wait); 470 } 471 472 if (status & ATH9K_INT_GENTIMER) 473 ath_gen_timer_isr(sc->sc_ah); 474 475 ath9k_btcoex_handle_interrupt(sc, status); 476 477 /* re-enable hardware interrupt */ 478 ath9k_hw_resume_interrupts(ah); 479 out: 480 spin_unlock(&sc->sc_pcu_lock); 481 ath9k_ps_restore(sc); 482 } 483 484 irqreturn_t ath_isr(int irq, void *dev) 485 { 486 #define SCHED_INTR ( \ 487 ATH9K_INT_FATAL | \ 488 ATH9K_INT_BB_WATCHDOG | \ 489 ATH9K_INT_RXORN | \ 490 ATH9K_INT_RXEOL | \ 491 ATH9K_INT_RX | \ 492 ATH9K_INT_RXLP | \ 493 ATH9K_INT_RXHP | \ 494 ATH9K_INT_TX | \ 495 ATH9K_INT_BMISS | \ 496 ATH9K_INT_CST | \ 497 ATH9K_INT_GTT | \ 498 ATH9K_INT_TSFOOR | \ 499 ATH9K_INT_GENTIMER | \ 500 ATH9K_INT_MCI) 501 502 struct ath_softc *sc = dev; 503 struct ath_hw *ah = sc->sc_ah; 504 struct ath_common *common = ath9k_hw_common(ah); 505 enum ath9k_int status; 506 u32 sync_cause = 0; 507 bool sched = false; 508 509 /* 510 * The hardware is not ready/present, don't 511 * touch anything. Note this can happen early 512 * on if the IRQ is shared. 513 */ 514 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 515 return IRQ_NONE; 516 517 /* shared irq, not for us */ 518 if (!ath9k_hw_intrpend(ah)) 519 return IRQ_NONE; 520 521 /* 522 * Figure out the reason(s) for the interrupt. Note 523 * that the hal returns a pseudo-ISR that may include 524 * bits we haven't explicitly enabled so we mask the 525 * value to insure we only process bits we requested. 526 */ 527 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 528 ath9k_debug_sync_cause(sc, sync_cause); 529 status &= ah->imask; /* discard unasked-for bits */ 530 531 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 532 return IRQ_HANDLED; 533 534 /* 535 * If there are no status bits set, then this interrupt was not 536 * for me (should have been caught above). 537 */ 538 if (!status) 539 return IRQ_NONE; 540 541 /* Cache the status */ 542 spin_lock(&sc->intr_lock); 543 sc->intrstatus |= status; 544 spin_unlock(&sc->intr_lock); 545 546 if (status & SCHED_INTR) 547 sched = true; 548 549 /* 550 * If a FATAL interrupt is received, we have to reset the chip 551 * immediately. 552 */ 553 if (status & ATH9K_INT_FATAL) 554 goto chip_reset; 555 556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 557 (status & ATH9K_INT_BB_WATCHDOG)) 558 goto chip_reset; 559 560 if (status & ATH9K_INT_SWBA) 561 tasklet_schedule(&sc->bcon_tasklet); 562 563 if (status & ATH9K_INT_TXURN) 564 ath9k_hw_updatetxtriglevel(ah, true); 565 566 if (status & ATH9K_INT_RXEOL) { 567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 568 ath9k_hw_set_interrupts(ah); 569 } 570 571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 572 if (status & ATH9K_INT_TIM_TIMER) { 573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 574 goto chip_reset; 575 /* Clear RxAbort bit so that we can 576 * receive frames */ 577 ath9k_setpower(sc, ATH9K_PM_AWAKE); 578 spin_lock(&sc->sc_pm_lock); 579 ath9k_hw_setrxabort(sc->sc_ah, 0); 580 sc->ps_flags |= PS_WAIT_FOR_BEACON; 581 spin_unlock(&sc->sc_pm_lock); 582 } 583 584 chip_reset: 585 586 ath_debug_stat_interrupt(sc, status); 587 588 if (sched) { 589 /* turn off every interrupt */ 590 ath9k_hw_kill_interrupts(ah); 591 tasklet_schedule(&sc->intr_tq); 592 } 593 594 return IRQ_HANDLED; 595 596 #undef SCHED_INTR 597 } 598 599 /* 600 * This function is called when a HW reset cannot be deferred 601 * and has to be immediate. 602 */ 603 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan) 604 { 605 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 606 int r; 607 608 ath9k_hw_kill_interrupts(sc->sc_ah); 609 set_bit(ATH_OP_HW_RESET, &common->op_flags); 610 611 ath9k_ps_wakeup(sc); 612 r = ath_reset_internal(sc, hchan); 613 ath9k_ps_restore(sc); 614 615 return r; 616 } 617 618 /* 619 * When a HW reset can be deferred, it is added to the 620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before 621 * queueing. 622 */ 623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 624 { 625 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 626 #ifdef CONFIG_ATH9K_DEBUGFS 627 RESET_STAT_INC(sc, type); 628 #endif 629 ath9k_hw_kill_interrupts(sc->sc_ah); 630 set_bit(ATH_OP_HW_RESET, &common->op_flags); 631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 632 } 633 634 void ath_reset_work(struct work_struct *work) 635 { 636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 637 638 ath9k_ps_wakeup(sc); 639 ath_reset_internal(sc, NULL); 640 ath9k_ps_restore(sc); 641 } 642 643 /**********************/ 644 /* mac80211 callbacks */ 645 /**********************/ 646 647 static int ath9k_start(struct ieee80211_hw *hw) 648 { 649 struct ath_softc *sc = hw->priv; 650 struct ath_hw *ah = sc->sc_ah; 651 struct ath_common *common = ath9k_hw_common(ah); 652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 653 struct ath_chanctx *ctx = sc->cur_chan; 654 struct ath9k_channel *init_channel; 655 int r; 656 657 ath_dbg(common, CONFIG, 658 "Starting driver with initial channel: %d MHz\n", 659 curchan->center_freq); 660 661 ath9k_ps_wakeup(sc); 662 mutex_lock(&sc->mutex); 663 664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 665 sc->cur_chandef = hw->conf.chandef; 666 667 /* Reset SERDES registers */ 668 ath9k_hw_configpcipowersave(ah, false); 669 670 /* 671 * The basic interface to setting the hardware in a good 672 * state is ``reset''. On return the hardware is known to 673 * be powered up and with interrupts disabled. This must 674 * be followed by initialization of the appropriate bits 675 * and then setup of the interrupt mask. 676 */ 677 spin_lock_bh(&sc->sc_pcu_lock); 678 679 atomic_set(&ah->intr_ref_cnt, -1); 680 681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 682 if (r) { 683 ath_err(common, 684 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 685 r, curchan->center_freq); 686 ah->reset_power_on = false; 687 } 688 689 /* Setup our intr mask. */ 690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 691 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 692 ATH9K_INT_GLOBAL; 693 694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 695 ah->imask |= ATH9K_INT_RXHP | 696 ATH9K_INT_RXLP; 697 else 698 ah->imask |= ATH9K_INT_RX; 699 700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 701 ah->imask |= ATH9K_INT_BB_WATCHDOG; 702 703 /* 704 * Enable GTT interrupts only for AR9003/AR9004 chips 705 * for now. 706 */ 707 if (AR_SREV_9300_20_OR_LATER(ah)) 708 ah->imask |= ATH9K_INT_GTT; 709 710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 711 ah->imask |= ATH9K_INT_CST; 712 713 ath_mci_enable(sc); 714 715 clear_bit(ATH_OP_INVALID, &common->op_flags); 716 sc->sc_ah->is_monitoring = false; 717 718 if (!ath_complete_reset(sc, false)) 719 ah->reset_power_on = false; 720 721 if (ah->led_pin >= 0) { 722 ath9k_hw_set_gpio(ah, ah->led_pin, 723 (ah->config.led_active_high) ? 1 : 0); 724 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL, 725 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 726 } 727 728 /* 729 * Reset key cache to sane defaults (all entries cleared) instead of 730 * semi-random values after suspend/resume. 731 */ 732 ath9k_cmn_init_crypto(sc->sc_ah); 733 734 ath9k_hw_reset_tsf(ah); 735 736 spin_unlock_bh(&sc->sc_pcu_lock); 737 738 ath9k_rng_start(sc); 739 740 mutex_unlock(&sc->mutex); 741 742 ath9k_ps_restore(sc); 743 744 return 0; 745 } 746 747 static void ath9k_tx(struct ieee80211_hw *hw, 748 struct ieee80211_tx_control *control, 749 struct sk_buff *skb) 750 { 751 struct ath_softc *sc = hw->priv; 752 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 753 struct ath_tx_control txctl; 754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 755 unsigned long flags; 756 757 if (sc->ps_enabled) { 758 /* 759 * mac80211 does not set PM field for normal data frames, so we 760 * need to update that based on the current PS mode. 761 */ 762 if (ieee80211_is_data(hdr->frame_control) && 763 !ieee80211_is_nullfunc(hdr->frame_control) && 764 !ieee80211_has_pm(hdr->frame_control)) { 765 ath_dbg(common, PS, 766 "Add PM=1 for a TX frame while in PS mode\n"); 767 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 768 } 769 } 770 771 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 772 /* 773 * We are using PS-Poll and mac80211 can request TX while in 774 * power save mode. Need to wake up hardware for the TX to be 775 * completed and if needed, also for RX of buffered frames. 776 */ 777 ath9k_ps_wakeup(sc); 778 spin_lock_irqsave(&sc->sc_pm_lock, flags); 779 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 780 ath9k_hw_setrxabort(sc->sc_ah, 0); 781 if (ieee80211_is_pspoll(hdr->frame_control)) { 782 ath_dbg(common, PS, 783 "Sending PS-Poll to pick a buffered frame\n"); 784 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 785 } else { 786 ath_dbg(common, PS, "Wake up to complete TX\n"); 787 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 788 } 789 /* 790 * The actual restore operation will happen only after 791 * the ps_flags bit is cleared. We are just dropping 792 * the ps_usecount here. 793 */ 794 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 795 ath9k_ps_restore(sc); 796 } 797 798 /* 799 * Cannot tx while the hardware is in full sleep, it first needs a full 800 * chip reset to recover from that 801 */ 802 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 803 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 804 goto exit; 805 } 806 807 memset(&txctl, 0, sizeof(struct ath_tx_control)); 808 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 809 txctl.sta = control->sta; 810 811 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 812 813 if (ath_tx_start(hw, skb, &txctl) != 0) { 814 ath_dbg(common, XMIT, "TX failed\n"); 815 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed); 816 goto exit; 817 } 818 819 return; 820 exit: 821 ieee80211_free_txskb(hw, skb); 822 } 823 824 static void ath9k_stop(struct ieee80211_hw *hw) 825 { 826 struct ath_softc *sc = hw->priv; 827 struct ath_hw *ah = sc->sc_ah; 828 struct ath_common *common = ath9k_hw_common(ah); 829 bool prev_idle; 830 831 ath9k_deinit_channel_context(sc); 832 833 mutex_lock(&sc->mutex); 834 835 ath9k_rng_stop(sc); 836 837 ath_cancel_work(sc); 838 839 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 840 ath_dbg(common, ANY, "Device not present\n"); 841 mutex_unlock(&sc->mutex); 842 return; 843 } 844 845 /* Ensure HW is awake when we try to shut it down. */ 846 ath9k_ps_wakeup(sc); 847 848 spin_lock_bh(&sc->sc_pcu_lock); 849 850 /* prevent tasklets to enable interrupts once we disable them */ 851 ah->imask &= ~ATH9K_INT_GLOBAL; 852 853 /* make sure h/w will not generate any interrupt 854 * before setting the invalid flag. */ 855 ath9k_hw_disable_interrupts(ah); 856 857 spin_unlock_bh(&sc->sc_pcu_lock); 858 859 /* we can now sync irq and kill any running tasklets, since we already 860 * disabled interrupts and not holding a spin lock */ 861 synchronize_irq(sc->irq); 862 tasklet_kill(&sc->intr_tq); 863 tasklet_kill(&sc->bcon_tasklet); 864 865 prev_idle = sc->ps_idle; 866 sc->ps_idle = true; 867 868 spin_lock_bh(&sc->sc_pcu_lock); 869 870 if (ah->led_pin >= 0) { 871 ath9k_hw_set_gpio(ah, ah->led_pin, 872 (ah->config.led_active_high) ? 0 : 1); 873 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL); 874 } 875 876 ath_prepare_reset(sc); 877 878 if (sc->rx.frag) { 879 dev_kfree_skb_any(sc->rx.frag); 880 sc->rx.frag = NULL; 881 } 882 883 if (!ah->curchan) 884 ah->curchan = ath9k_cmn_get_channel(hw, ah, 885 &sc->cur_chan->chandef); 886 887 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 888 889 set_bit(ATH_OP_INVALID, &common->op_flags); 890 891 ath9k_hw_phy_disable(ah); 892 893 ath9k_hw_configpcipowersave(ah, true); 894 895 spin_unlock_bh(&sc->sc_pcu_lock); 896 897 ath9k_ps_restore(sc); 898 899 sc->ps_idle = prev_idle; 900 901 mutex_unlock(&sc->mutex); 902 903 ath_dbg(common, CONFIG, "Driver halt\n"); 904 } 905 906 static bool ath9k_uses_beacons(int type) 907 { 908 switch (type) { 909 case NL80211_IFTYPE_AP: 910 case NL80211_IFTYPE_ADHOC: 911 case NL80211_IFTYPE_MESH_POINT: 912 return true; 913 default: 914 return false; 915 } 916 } 917 918 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data, 919 struct ieee80211_vif *vif) 920 { 921 /* Use the first (configured) interface, but prefering AP interfaces. */ 922 if (!iter_data->primary_beacon_vif) { 923 iter_data->primary_beacon_vif = vif; 924 } else { 925 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP && 926 vif->type == NL80211_IFTYPE_AP) 927 iter_data->primary_beacon_vif = vif; 928 } 929 930 iter_data->beacons = true; 931 iter_data->nbcnvifs += 1; 932 } 933 934 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 935 u8 *mac, struct ieee80211_vif *vif) 936 { 937 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 938 int i; 939 940 if (iter_data->has_hw_macaddr) { 941 for (i = 0; i < ETH_ALEN; i++) 942 iter_data->mask[i] &= 943 ~(iter_data->hw_macaddr[i] ^ mac[i]); 944 } else { 945 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 946 iter_data->has_hw_macaddr = true; 947 } 948 949 if (!vif->bss_conf.use_short_slot) 950 iter_data->slottime = 20; 951 952 switch (vif->type) { 953 case NL80211_IFTYPE_AP: 954 iter_data->naps++; 955 if (vif->bss_conf.enable_beacon) 956 ath9k_vif_iter_set_beacon(iter_data, vif); 957 break; 958 case NL80211_IFTYPE_STATION: 959 iter_data->nstations++; 960 if (avp->assoc && !iter_data->primary_sta) 961 iter_data->primary_sta = vif; 962 break; 963 case NL80211_IFTYPE_OCB: 964 iter_data->nocbs++; 965 break; 966 case NL80211_IFTYPE_ADHOC: 967 iter_data->nadhocs++; 968 if (vif->bss_conf.enable_beacon) 969 ath9k_vif_iter_set_beacon(iter_data, vif); 970 break; 971 case NL80211_IFTYPE_MESH_POINT: 972 iter_data->nmeshes++; 973 if (vif->bss_conf.enable_beacon) 974 ath9k_vif_iter_set_beacon(iter_data, vif); 975 break; 976 default: 977 break; 978 } 979 } 980 981 static void ath9k_update_bssid_mask(struct ath_softc *sc, 982 struct ath_chanctx *ctx, 983 struct ath9k_vif_iter_data *iter_data) 984 { 985 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 986 struct ath_vif *avp; 987 int i; 988 989 if (!ath9k_is_chanctx_enabled()) 990 return; 991 992 list_for_each_entry(avp, &ctx->vifs, list) { 993 if (ctx->nvifs_assigned != 1) 994 continue; 995 996 if (!iter_data->has_hw_macaddr) 997 continue; 998 999 ether_addr_copy(common->curbssid, avp->bssid); 1000 1001 /* perm_addr will be used as the p2p device address. */ 1002 for (i = 0; i < ETH_ALEN; i++) 1003 iter_data->mask[i] &= 1004 ~(iter_data->hw_macaddr[i] ^ 1005 sc->hw->wiphy->perm_addr[i]); 1006 } 1007 } 1008 1009 /* Called with sc->mutex held. */ 1010 void ath9k_calculate_iter_data(struct ath_softc *sc, 1011 struct ath_chanctx *ctx, 1012 struct ath9k_vif_iter_data *iter_data) 1013 { 1014 struct ath_vif *avp; 1015 1016 /* 1017 * The hardware will use primary station addr together with the 1018 * BSSID mask when matching addresses. 1019 */ 1020 memset(iter_data, 0, sizeof(*iter_data)); 1021 eth_broadcast_addr(iter_data->mask); 1022 iter_data->slottime = 9; 1023 1024 list_for_each_entry(avp, &ctx->vifs, list) 1025 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 1026 1027 ath9k_update_bssid_mask(sc, ctx, iter_data); 1028 } 1029 1030 static void ath9k_set_assoc_state(struct ath_softc *sc, 1031 struct ieee80211_vif *vif, bool changed) 1032 { 1033 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1034 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 1035 unsigned long flags; 1036 1037 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1038 1039 ether_addr_copy(common->curbssid, avp->bssid); 1040 common->curaid = avp->aid; 1041 ath9k_hw_write_associd(sc->sc_ah); 1042 1043 if (changed) { 1044 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1045 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1046 1047 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1048 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1049 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1050 } 1051 1052 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1053 ath9k_mci_update_wlan_channels(sc, false); 1054 1055 ath_dbg(common, CONFIG, 1056 "Primary Station interface: %pM, BSSID: %pM\n", 1057 vif->addr, common->curbssid); 1058 } 1059 1060 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1061 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1062 { 1063 struct ath_hw *ah = sc->sc_ah; 1064 struct ath_common *common = ath9k_hw_common(ah); 1065 struct ieee80211_vif *vif = NULL; 1066 1067 ath9k_ps_wakeup(sc); 1068 1069 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1070 vif = sc->offchannel.scan_vif; 1071 else 1072 vif = sc->offchannel.roc_vif; 1073 1074 if (WARN_ON(!vif)) 1075 goto exit; 1076 1077 eth_zero_addr(common->curbssid); 1078 eth_broadcast_addr(common->bssidmask); 1079 memcpy(common->macaddr, vif->addr, ETH_ALEN); 1080 common->curaid = 0; 1081 ah->opmode = vif->type; 1082 ah->imask &= ~ATH9K_INT_SWBA; 1083 ah->imask &= ~ATH9K_INT_TSFOOR; 1084 ah->slottime = 9; 1085 1086 ath_hw_setbssidmask(common); 1087 ath9k_hw_setopmode(ah); 1088 ath9k_hw_write_associd(sc->sc_ah); 1089 ath9k_hw_set_interrupts(ah); 1090 ath9k_hw_init_global_settings(ah); 1091 1092 exit: 1093 ath9k_ps_restore(sc); 1094 } 1095 #endif 1096 1097 /* Called with sc->mutex held. */ 1098 void ath9k_calculate_summary_state(struct ath_softc *sc, 1099 struct ath_chanctx *ctx) 1100 { 1101 struct ath_hw *ah = sc->sc_ah; 1102 struct ath_common *common = ath9k_hw_common(ah); 1103 struct ath9k_vif_iter_data iter_data; 1104 1105 ath_chanctx_check_active(sc, ctx); 1106 1107 if (ctx != sc->cur_chan) 1108 return; 1109 1110 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1111 if (ctx == &sc->offchannel.chan) 1112 return ath9k_set_offchannel_state(sc); 1113 #endif 1114 1115 ath9k_ps_wakeup(sc); 1116 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1117 1118 if (iter_data.has_hw_macaddr) 1119 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN); 1120 1121 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1122 ath_hw_setbssidmask(common); 1123 1124 if (iter_data.naps > 0) { 1125 ath9k_hw_set_tsfadjust(ah, true); 1126 ah->opmode = NL80211_IFTYPE_AP; 1127 } else { 1128 ath9k_hw_set_tsfadjust(ah, false); 1129 if (iter_data.beacons) 1130 ath9k_beacon_ensure_primary_slot(sc); 1131 1132 if (iter_data.nmeshes) 1133 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1134 else if (iter_data.nocbs) 1135 ah->opmode = NL80211_IFTYPE_OCB; 1136 else if (iter_data.nadhocs) 1137 ah->opmode = NL80211_IFTYPE_ADHOC; 1138 else 1139 ah->opmode = NL80211_IFTYPE_STATION; 1140 } 1141 1142 ath9k_hw_setopmode(ah); 1143 1144 ctx->switch_after_beacon = false; 1145 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1146 ah->imask |= ATH9K_INT_TSFOOR; 1147 else { 1148 ah->imask &= ~ATH9K_INT_TSFOOR; 1149 if (iter_data.naps == 1 && iter_data.beacons) 1150 ctx->switch_after_beacon = true; 1151 } 1152 1153 if (ah->opmode == NL80211_IFTYPE_STATION) { 1154 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1155 1156 if (iter_data.primary_sta) { 1157 iter_data.primary_beacon_vif = iter_data.primary_sta; 1158 iter_data.beacons = true; 1159 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1160 changed); 1161 ctx->primary_sta = iter_data.primary_sta; 1162 } else { 1163 ctx->primary_sta = NULL; 1164 eth_zero_addr(common->curbssid); 1165 common->curaid = 0; 1166 ath9k_hw_write_associd(sc->sc_ah); 1167 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1168 ath9k_mci_update_wlan_channels(sc, true); 1169 } 1170 } 1171 sc->nbcnvifs = iter_data.nbcnvifs; 1172 ath9k_beacon_config(sc, iter_data.primary_beacon_vif, 1173 iter_data.beacons); 1174 ath9k_hw_set_interrupts(ah); 1175 1176 if (ah->slottime != iter_data.slottime) { 1177 ah->slottime = iter_data.slottime; 1178 ath9k_hw_init_global_settings(ah); 1179 } 1180 1181 if (iter_data.primary_sta) 1182 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1183 else 1184 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1185 1186 ath_dbg(common, CONFIG, 1187 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1188 common->macaddr, common->curbssid, common->bssidmask); 1189 1190 ath9k_ps_restore(sc); 1191 } 1192 1193 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1194 { 1195 int *power = data; 1196 1197 if (vif->bss_conf.txpower == INT_MIN) 1198 return; 1199 1200 if (*power < vif->bss_conf.txpower) 1201 *power = vif->bss_conf.txpower; 1202 } 1203 1204 /* Called with sc->mutex held. */ 1205 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif) 1206 { 1207 int power; 1208 struct ath_hw *ah = sc->sc_ah; 1209 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 1210 1211 ath9k_ps_wakeup(sc); 1212 if (ah->tpc_enabled) { 1213 power = (vif) ? vif->bss_conf.txpower : -1; 1214 ieee80211_iterate_active_interfaces_atomic( 1215 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1216 ath9k_tpc_vif_iter, &power); 1217 if (power == -1) 1218 power = sc->hw->conf.power_level; 1219 } else { 1220 power = sc->hw->conf.power_level; 1221 } 1222 sc->cur_chan->txpower = 2 * power; 1223 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 1224 sc->cur_chan->cur_txpower = reg->max_power_level; 1225 ath9k_ps_restore(sc); 1226 } 1227 1228 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1229 struct ieee80211_vif *vif) 1230 { 1231 int i; 1232 1233 if (!ath9k_is_chanctx_enabled()) 1234 return; 1235 1236 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1237 vif->hw_queue[i] = i; 1238 1239 if (vif->type == NL80211_IFTYPE_AP || 1240 vif->type == NL80211_IFTYPE_MESH_POINT) 1241 vif->cab_queue = hw->queues - 2; 1242 else 1243 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1244 } 1245 1246 static int ath9k_add_interface(struct ieee80211_hw *hw, 1247 struct ieee80211_vif *vif) 1248 { 1249 struct ath_softc *sc = hw->priv; 1250 struct ath_hw *ah = sc->sc_ah; 1251 struct ath_common *common = ath9k_hw_common(ah); 1252 struct ath_vif *avp = (void *)vif->drv_priv; 1253 struct ath_node *an = &avp->mcast_node; 1254 1255 mutex_lock(&sc->mutex); 1256 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1257 if (sc->cur_chan->nvifs >= 1) { 1258 mutex_unlock(&sc->mutex); 1259 return -EOPNOTSUPP; 1260 } 1261 sc->tx99_vif = vif; 1262 } 1263 1264 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1265 sc->cur_chan->nvifs++; 1266 1267 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled()) 1268 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE; 1269 1270 if (ath9k_uses_beacons(vif->type)) 1271 ath9k_beacon_assign_slot(sc, vif); 1272 1273 avp->vif = vif; 1274 if (!ath9k_is_chanctx_enabled()) { 1275 avp->chanctx = sc->cur_chan; 1276 list_add_tail(&avp->list, &avp->chanctx->vifs); 1277 } 1278 1279 ath9k_calculate_summary_state(sc, avp->chanctx); 1280 1281 ath9k_assign_hw_queues(hw, vif); 1282 1283 ath9k_set_txpower(sc, vif); 1284 1285 an->sc = sc; 1286 an->sta = NULL; 1287 an->vif = vif; 1288 an->no_ps_filter = true; 1289 ath_tx_node_init(sc, an); 1290 1291 mutex_unlock(&sc->mutex); 1292 return 0; 1293 } 1294 1295 static int ath9k_change_interface(struct ieee80211_hw *hw, 1296 struct ieee80211_vif *vif, 1297 enum nl80211_iftype new_type, 1298 bool p2p) 1299 { 1300 struct ath_softc *sc = hw->priv; 1301 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1302 struct ath_vif *avp = (void *)vif->drv_priv; 1303 1304 mutex_lock(&sc->mutex); 1305 1306 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1307 mutex_unlock(&sc->mutex); 1308 return -EOPNOTSUPP; 1309 } 1310 1311 ath_dbg(common, CONFIG, "Change Interface\n"); 1312 1313 if (ath9k_uses_beacons(vif->type)) 1314 ath9k_beacon_remove_slot(sc, vif); 1315 1316 vif->type = new_type; 1317 vif->p2p = p2p; 1318 1319 if (ath9k_uses_beacons(vif->type)) 1320 ath9k_beacon_assign_slot(sc, vif); 1321 1322 ath9k_assign_hw_queues(hw, vif); 1323 ath9k_calculate_summary_state(sc, avp->chanctx); 1324 1325 ath9k_set_txpower(sc, vif); 1326 1327 mutex_unlock(&sc->mutex); 1328 return 0; 1329 } 1330 1331 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1332 struct ieee80211_vif *vif) 1333 { 1334 struct ath_softc *sc = hw->priv; 1335 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1336 struct ath_vif *avp = (void *)vif->drv_priv; 1337 1338 ath_dbg(common, CONFIG, "Detach Interface\n"); 1339 1340 mutex_lock(&sc->mutex); 1341 1342 ath9k_p2p_remove_vif(sc, vif); 1343 1344 sc->cur_chan->nvifs--; 1345 sc->tx99_vif = NULL; 1346 if (!ath9k_is_chanctx_enabled()) 1347 list_del(&avp->list); 1348 1349 if (ath9k_uses_beacons(vif->type)) 1350 ath9k_beacon_remove_slot(sc, vif); 1351 1352 ath_tx_node_cleanup(sc, &avp->mcast_node); 1353 1354 ath9k_calculate_summary_state(sc, avp->chanctx); 1355 1356 ath9k_set_txpower(sc, NULL); 1357 1358 mutex_unlock(&sc->mutex); 1359 } 1360 1361 static void ath9k_enable_ps(struct ath_softc *sc) 1362 { 1363 struct ath_hw *ah = sc->sc_ah; 1364 struct ath_common *common = ath9k_hw_common(ah); 1365 1366 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1367 return; 1368 1369 sc->ps_enabled = true; 1370 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1371 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1372 ah->imask |= ATH9K_INT_TIM_TIMER; 1373 ath9k_hw_set_interrupts(ah); 1374 } 1375 ath9k_hw_setrxabort(ah, 1); 1376 } 1377 ath_dbg(common, PS, "PowerSave enabled\n"); 1378 } 1379 1380 static void ath9k_disable_ps(struct ath_softc *sc) 1381 { 1382 struct ath_hw *ah = sc->sc_ah; 1383 struct ath_common *common = ath9k_hw_common(ah); 1384 1385 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1386 return; 1387 1388 sc->ps_enabled = false; 1389 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1390 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1391 ath9k_hw_setrxabort(ah, 0); 1392 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1393 PS_WAIT_FOR_CAB | 1394 PS_WAIT_FOR_PSPOLL_DATA | 1395 PS_WAIT_FOR_TX_ACK); 1396 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1397 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1398 ath9k_hw_set_interrupts(ah); 1399 } 1400 } 1401 ath_dbg(common, PS, "PowerSave disabled\n"); 1402 } 1403 1404 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1405 { 1406 struct ath_softc *sc = hw->priv; 1407 struct ath_hw *ah = sc->sc_ah; 1408 struct ath_common *common = ath9k_hw_common(ah); 1409 struct ieee80211_conf *conf = &hw->conf; 1410 struct ath_chanctx *ctx = sc->cur_chan; 1411 1412 ath9k_ps_wakeup(sc); 1413 mutex_lock(&sc->mutex); 1414 1415 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1416 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1417 if (sc->ps_idle) { 1418 ath_cancel_work(sc); 1419 ath9k_stop_btcoex(sc); 1420 } else { 1421 ath9k_start_btcoex(sc); 1422 /* 1423 * The chip needs a reset to properly wake up from 1424 * full sleep 1425 */ 1426 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1427 } 1428 } 1429 1430 /* 1431 * We just prepare to enable PS. We have to wait until our AP has 1432 * ACK'd our null data frame to disable RX otherwise we'll ignore 1433 * those ACKs and end up retransmitting the same null data frames. 1434 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1435 */ 1436 if (changed & IEEE80211_CONF_CHANGE_PS) { 1437 unsigned long flags; 1438 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1439 if (conf->flags & IEEE80211_CONF_PS) 1440 ath9k_enable_ps(sc); 1441 else 1442 ath9k_disable_ps(sc); 1443 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1444 } 1445 1446 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1447 if (conf->flags & IEEE80211_CONF_MONITOR) { 1448 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1449 sc->sc_ah->is_monitoring = true; 1450 } else { 1451 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1452 sc->sc_ah->is_monitoring = false; 1453 } 1454 } 1455 1456 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1457 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1458 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1459 } 1460 1461 if (changed & IEEE80211_CONF_CHANGE_POWER) 1462 ath9k_set_txpower(sc, NULL); 1463 1464 mutex_unlock(&sc->mutex); 1465 ath9k_ps_restore(sc); 1466 1467 return 0; 1468 } 1469 1470 #define SUPPORTED_FILTERS \ 1471 (FIF_ALLMULTI | \ 1472 FIF_CONTROL | \ 1473 FIF_PSPOLL | \ 1474 FIF_OTHER_BSS | \ 1475 FIF_BCN_PRBRESP_PROMISC | \ 1476 FIF_PROBE_REQ | \ 1477 FIF_MCAST_ACTION | \ 1478 FIF_FCSFAIL) 1479 1480 /* FIXME: sc->sc_full_reset ? */ 1481 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1482 unsigned int changed_flags, 1483 unsigned int *total_flags, 1484 u64 multicast) 1485 { 1486 struct ath_softc *sc = hw->priv; 1487 struct ath_chanctx *ctx; 1488 u32 rfilt; 1489 1490 changed_flags &= SUPPORTED_FILTERS; 1491 *total_flags &= SUPPORTED_FILTERS; 1492 1493 spin_lock_bh(&sc->chan_lock); 1494 ath_for_each_chanctx(sc, ctx) 1495 ctx->rxfilter = *total_flags; 1496 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1497 sc->offchannel.chan.rxfilter = *total_flags; 1498 #endif 1499 spin_unlock_bh(&sc->chan_lock); 1500 1501 ath9k_ps_wakeup(sc); 1502 rfilt = ath_calcrxfilter(sc); 1503 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1504 ath9k_ps_restore(sc); 1505 1506 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1507 rfilt); 1508 } 1509 1510 static int ath9k_sta_add(struct ieee80211_hw *hw, 1511 struct ieee80211_vif *vif, 1512 struct ieee80211_sta *sta) 1513 { 1514 struct ath_softc *sc = hw->priv; 1515 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1516 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1517 struct ieee80211_key_conf ps_key = { }; 1518 int key; 1519 1520 ath_node_attach(sc, sta, vif); 1521 1522 if (vif->type != NL80211_IFTYPE_AP && 1523 vif->type != NL80211_IFTYPE_AP_VLAN) 1524 return 0; 1525 1526 key = ath_key_config(common, vif, sta, &ps_key); 1527 if (key > 0) { 1528 an->ps_key = key; 1529 an->key_idx[0] = key; 1530 } 1531 1532 return 0; 1533 } 1534 1535 static void ath9k_del_ps_key(struct ath_softc *sc, 1536 struct ieee80211_vif *vif, 1537 struct ieee80211_sta *sta) 1538 { 1539 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1540 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1541 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1542 1543 if (!an->ps_key) 1544 return; 1545 1546 ath_key_delete(common, &ps_key); 1547 an->ps_key = 0; 1548 an->key_idx[0] = 0; 1549 } 1550 1551 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1552 struct ieee80211_vif *vif, 1553 struct ieee80211_sta *sta) 1554 { 1555 struct ath_softc *sc = hw->priv; 1556 1557 ath9k_del_ps_key(sc, vif, sta); 1558 ath_node_detach(sc, sta); 1559 1560 return 0; 1561 } 1562 1563 static int ath9k_sta_state(struct ieee80211_hw *hw, 1564 struct ieee80211_vif *vif, 1565 struct ieee80211_sta *sta, 1566 enum ieee80211_sta_state old_state, 1567 enum ieee80211_sta_state new_state) 1568 { 1569 struct ath_softc *sc = hw->priv; 1570 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1571 int ret = 0; 1572 1573 if (old_state == IEEE80211_STA_NOTEXIST && 1574 new_state == IEEE80211_STA_NONE) { 1575 ret = ath9k_sta_add(hw, vif, sta); 1576 ath_dbg(common, CONFIG, 1577 "Add station: %pM\n", sta->addr); 1578 } else if (old_state == IEEE80211_STA_NONE && 1579 new_state == IEEE80211_STA_NOTEXIST) { 1580 ret = ath9k_sta_remove(hw, vif, sta); 1581 ath_dbg(common, CONFIG, 1582 "Remove station: %pM\n", sta->addr); 1583 } 1584 1585 if (ath9k_is_chanctx_enabled()) { 1586 if (vif->type == NL80211_IFTYPE_STATION) { 1587 if (old_state == IEEE80211_STA_ASSOC && 1588 new_state == IEEE80211_STA_AUTHORIZED) 1589 ath_chanctx_event(sc, vif, 1590 ATH_CHANCTX_EVENT_AUTHORIZED); 1591 } 1592 } 1593 1594 return ret; 1595 } 1596 1597 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1598 struct ath_node *an, 1599 bool set) 1600 { 1601 int i; 1602 1603 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1604 if (!an->key_idx[i]) 1605 continue; 1606 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1607 } 1608 } 1609 1610 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1611 struct ieee80211_vif *vif, 1612 enum sta_notify_cmd cmd, 1613 struct ieee80211_sta *sta) 1614 { 1615 struct ath_softc *sc = hw->priv; 1616 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1617 1618 switch (cmd) { 1619 case STA_NOTIFY_SLEEP: 1620 an->sleeping = true; 1621 ath_tx_aggr_sleep(sta, sc, an); 1622 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1623 break; 1624 case STA_NOTIFY_AWAKE: 1625 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1626 an->sleeping = false; 1627 ath_tx_aggr_wakeup(sc, an); 1628 break; 1629 } 1630 } 1631 1632 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1633 struct ieee80211_vif *vif, u16 queue, 1634 const struct ieee80211_tx_queue_params *params) 1635 { 1636 struct ath_softc *sc = hw->priv; 1637 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1638 struct ath_txq *txq; 1639 struct ath9k_tx_queue_info qi; 1640 int ret = 0; 1641 1642 if (queue >= IEEE80211_NUM_ACS) 1643 return 0; 1644 1645 txq = sc->tx.txq_map[queue]; 1646 1647 ath9k_ps_wakeup(sc); 1648 mutex_lock(&sc->mutex); 1649 1650 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1651 1652 qi.tqi_aifs = params->aifs; 1653 qi.tqi_cwmin = params->cw_min; 1654 qi.tqi_cwmax = params->cw_max; 1655 qi.tqi_burstTime = params->txop * 32; 1656 1657 ath_dbg(common, CONFIG, 1658 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1659 queue, txq->axq_qnum, params->aifs, params->cw_min, 1660 params->cw_max, params->txop); 1661 1662 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1663 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1664 if (ret) 1665 ath_err(common, "TXQ Update failed\n"); 1666 1667 mutex_unlock(&sc->mutex); 1668 ath9k_ps_restore(sc); 1669 1670 return ret; 1671 } 1672 1673 static int ath9k_set_key(struct ieee80211_hw *hw, 1674 enum set_key_cmd cmd, 1675 struct ieee80211_vif *vif, 1676 struct ieee80211_sta *sta, 1677 struct ieee80211_key_conf *key) 1678 { 1679 struct ath_softc *sc = hw->priv; 1680 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1681 struct ath_node *an = NULL; 1682 int ret = 0, i; 1683 1684 if (ath9k_modparam_nohwcrypt) 1685 return -ENOSPC; 1686 1687 if ((vif->type == NL80211_IFTYPE_ADHOC || 1688 vif->type == NL80211_IFTYPE_MESH_POINT) && 1689 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1690 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1691 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1692 /* 1693 * For now, disable hw crypto for the RSN IBSS group keys. This 1694 * could be optimized in the future to use a modified key cache 1695 * design to support per-STA RX GTK, but until that gets 1696 * implemented, use of software crypto for group addressed 1697 * frames is a acceptable to allow RSN IBSS to be used. 1698 */ 1699 return -EOPNOTSUPP; 1700 } 1701 1702 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to 1703 * make sure these are not send unencrypted or with a wrong (new) key 1704 */ 1705 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 1706 ieee80211_stop_queues(hw); 1707 ath9k_flush(hw, vif, 0, true); 1708 ieee80211_wake_queues(hw); 1709 } 1710 1711 mutex_lock(&sc->mutex); 1712 ath9k_ps_wakeup(sc); 1713 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1714 if (sta) 1715 an = (struct ath_node *)sta->drv_priv; 1716 1717 switch (cmd) { 1718 case SET_KEY: 1719 if (sta) 1720 ath9k_del_ps_key(sc, vif, sta); 1721 1722 key->hw_key_idx = 0; 1723 ret = ath_key_config(common, vif, sta, key); 1724 if (ret >= 0) { 1725 key->hw_key_idx = ret; 1726 /* push IV and Michael MIC generation to stack */ 1727 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1728 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1729 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1730 if (sc->sc_ah->sw_mgmt_crypto_tx && 1731 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1732 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1733 ret = 0; 1734 } 1735 if (an && key->hw_key_idx) { 1736 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1737 if (an->key_idx[i]) 1738 continue; 1739 an->key_idx[i] = key->hw_key_idx; 1740 break; 1741 } 1742 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1743 } 1744 break; 1745 case DISABLE_KEY: 1746 ath_key_delete(common, key); 1747 if (an) { 1748 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1749 if (an->key_idx[i] != key->hw_key_idx) 1750 continue; 1751 an->key_idx[i] = 0; 1752 break; 1753 } 1754 } 1755 key->hw_key_idx = 0; 1756 break; 1757 default: 1758 ret = -EINVAL; 1759 } 1760 1761 ath9k_ps_restore(sc); 1762 mutex_unlock(&sc->mutex); 1763 1764 return ret; 1765 } 1766 1767 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1768 struct ieee80211_vif *vif, 1769 struct ieee80211_bss_conf *bss_conf, 1770 u32 changed) 1771 { 1772 #define CHECK_ANI \ 1773 (BSS_CHANGED_ASSOC | \ 1774 BSS_CHANGED_IBSS | \ 1775 BSS_CHANGED_BEACON_ENABLED) 1776 1777 struct ath_softc *sc = hw->priv; 1778 struct ath_hw *ah = sc->sc_ah; 1779 struct ath_common *common = ath9k_hw_common(ah); 1780 struct ath_vif *avp = (void *)vif->drv_priv; 1781 int slottime; 1782 1783 ath9k_ps_wakeup(sc); 1784 mutex_lock(&sc->mutex); 1785 1786 if (changed & BSS_CHANGED_ASSOC) { 1787 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1788 bss_conf->bssid, bss_conf->assoc); 1789 1790 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1791 avp->aid = bss_conf->aid; 1792 avp->assoc = bss_conf->assoc; 1793 1794 ath9k_calculate_summary_state(sc, avp->chanctx); 1795 } 1796 1797 if ((changed & BSS_CHANGED_IBSS) || 1798 (changed & BSS_CHANGED_OCB)) { 1799 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1800 common->curaid = bss_conf->aid; 1801 ath9k_hw_write_associd(sc->sc_ah); 1802 } 1803 1804 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1805 (changed & BSS_CHANGED_BEACON_INT) || 1806 (changed & BSS_CHANGED_BEACON_INFO)) { 1807 ath9k_calculate_summary_state(sc, avp->chanctx); 1808 } 1809 1810 if ((avp->chanctx == sc->cur_chan) && 1811 (changed & BSS_CHANGED_ERP_SLOT)) { 1812 if (bss_conf->use_short_slot) 1813 slottime = 9; 1814 else 1815 slottime = 20; 1816 1817 if (vif->type == NL80211_IFTYPE_AP) { 1818 /* 1819 * Defer update, so that connected stations can adjust 1820 * their settings at the same time. 1821 * See beacon.c for more details 1822 */ 1823 sc->beacon.slottime = slottime; 1824 sc->beacon.updateslot = UPDATE; 1825 } else { 1826 ah->slottime = slottime; 1827 ath9k_hw_init_global_settings(ah); 1828 } 1829 } 1830 1831 if (changed & BSS_CHANGED_P2P_PS) 1832 ath9k_p2p_bss_info_changed(sc, vif); 1833 1834 if (changed & CHECK_ANI) 1835 ath_check_ani(sc); 1836 1837 if (changed & BSS_CHANGED_TXPOWER) { 1838 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n", 1839 vif->addr, bss_conf->txpower, bss_conf->txpower_type); 1840 ath9k_set_txpower(sc, vif); 1841 } 1842 1843 mutex_unlock(&sc->mutex); 1844 ath9k_ps_restore(sc); 1845 1846 #undef CHECK_ANI 1847 } 1848 1849 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1850 { 1851 struct ath_softc *sc = hw->priv; 1852 struct ath_vif *avp = (void *)vif->drv_priv; 1853 u64 tsf; 1854 1855 mutex_lock(&sc->mutex); 1856 ath9k_ps_wakeup(sc); 1857 /* Get current TSF either from HW or kernel time. */ 1858 if (sc->cur_chan == avp->chanctx) { 1859 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1860 } else { 1861 tsf = sc->cur_chan->tsf_val + 1862 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL); 1863 } 1864 tsf += le64_to_cpu(avp->tsf_adjust); 1865 ath9k_ps_restore(sc); 1866 mutex_unlock(&sc->mutex); 1867 1868 return tsf; 1869 } 1870 1871 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1872 struct ieee80211_vif *vif, 1873 u64 tsf) 1874 { 1875 struct ath_softc *sc = hw->priv; 1876 struct ath_vif *avp = (void *)vif->drv_priv; 1877 1878 mutex_lock(&sc->mutex); 1879 ath9k_ps_wakeup(sc); 1880 tsf -= le64_to_cpu(avp->tsf_adjust); 1881 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1882 if (sc->cur_chan == avp->chanctx) 1883 ath9k_hw_settsf64(sc->sc_ah, tsf); 1884 avp->chanctx->tsf_val = tsf; 1885 ath9k_ps_restore(sc); 1886 mutex_unlock(&sc->mutex); 1887 } 1888 1889 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1890 { 1891 struct ath_softc *sc = hw->priv; 1892 struct ath_vif *avp = (void *)vif->drv_priv; 1893 1894 mutex_lock(&sc->mutex); 1895 1896 ath9k_ps_wakeup(sc); 1897 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1898 if (sc->cur_chan == avp->chanctx) 1899 ath9k_hw_reset_tsf(sc->sc_ah); 1900 avp->chanctx->tsf_val = 0; 1901 ath9k_ps_restore(sc); 1902 1903 mutex_unlock(&sc->mutex); 1904 } 1905 1906 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1907 struct ieee80211_vif *vif, 1908 struct ieee80211_ampdu_params *params) 1909 { 1910 struct ath_softc *sc = hw->priv; 1911 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1912 bool flush = false; 1913 int ret = 0; 1914 struct ieee80211_sta *sta = params->sta; 1915 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1916 enum ieee80211_ampdu_mlme_action action = params->action; 1917 u16 tid = params->tid; 1918 u16 *ssn = ¶ms->ssn; 1919 struct ath_atx_tid *atid; 1920 1921 mutex_lock(&sc->mutex); 1922 1923 switch (action) { 1924 case IEEE80211_AMPDU_RX_START: 1925 break; 1926 case IEEE80211_AMPDU_RX_STOP: 1927 break; 1928 case IEEE80211_AMPDU_TX_START: 1929 if (ath9k_is_chanctx_enabled()) { 1930 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 1931 ret = -EBUSY; 1932 break; 1933 } 1934 } 1935 ath9k_ps_wakeup(sc); 1936 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1937 if (!ret) 1938 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1939 ath9k_ps_restore(sc); 1940 break; 1941 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1942 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1943 flush = true; 1944 fallthrough; 1945 case IEEE80211_AMPDU_TX_STOP_CONT: 1946 ath9k_ps_wakeup(sc); 1947 ath_tx_aggr_stop(sc, sta, tid); 1948 if (!flush) 1949 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1950 ath9k_ps_restore(sc); 1951 break; 1952 case IEEE80211_AMPDU_TX_OPERATIONAL: 1953 atid = ath_node_to_tid(an, tid); 1954 atid->baw_size = IEEE80211_MIN_AMPDU_BUF << 1955 sta->ht_cap.ampdu_factor; 1956 break; 1957 default: 1958 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1959 } 1960 1961 mutex_unlock(&sc->mutex); 1962 1963 return ret; 1964 } 1965 1966 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1967 struct survey_info *survey) 1968 { 1969 struct ath_softc *sc = hw->priv; 1970 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1971 struct ieee80211_supported_band *sband; 1972 struct ieee80211_channel *chan; 1973 unsigned long flags; 1974 int pos; 1975 1976 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1977 return -EOPNOTSUPP; 1978 1979 spin_lock_irqsave(&common->cc_lock, flags); 1980 if (idx == 0) 1981 ath_update_survey_stats(sc); 1982 1983 sband = hw->wiphy->bands[NL80211_BAND_2GHZ]; 1984 if (sband && idx >= sband->n_channels) { 1985 idx -= sband->n_channels; 1986 sband = NULL; 1987 } 1988 1989 if (!sband) 1990 sband = hw->wiphy->bands[NL80211_BAND_5GHZ]; 1991 1992 if (!sband || idx >= sband->n_channels) { 1993 spin_unlock_irqrestore(&common->cc_lock, flags); 1994 return -ENOENT; 1995 } 1996 1997 chan = &sband->channels[idx]; 1998 pos = chan->hw_value; 1999 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 2000 survey->channel = chan; 2001 spin_unlock_irqrestore(&common->cc_lock, flags); 2002 2003 return 0; 2004 } 2005 2006 static void ath9k_enable_dynack(struct ath_softc *sc) 2007 { 2008 #ifdef CONFIG_ATH9K_DYNACK 2009 u32 rfilt; 2010 struct ath_hw *ah = sc->sc_ah; 2011 2012 ath_dynack_reset(ah); 2013 2014 ah->dynack.enabled = true; 2015 rfilt = ath_calcrxfilter(sc); 2016 ath9k_hw_setrxfilter(ah, rfilt); 2017 #endif 2018 } 2019 2020 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 2021 s16 coverage_class) 2022 { 2023 struct ath_softc *sc = hw->priv; 2024 struct ath_hw *ah = sc->sc_ah; 2025 2026 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 2027 return; 2028 2029 mutex_lock(&sc->mutex); 2030 2031 if (coverage_class >= 0) { 2032 ah->coverage_class = coverage_class; 2033 if (ah->dynack.enabled) { 2034 u32 rfilt; 2035 2036 ah->dynack.enabled = false; 2037 rfilt = ath_calcrxfilter(sc); 2038 ath9k_hw_setrxfilter(ah, rfilt); 2039 } 2040 ath9k_ps_wakeup(sc); 2041 ath9k_hw_init_global_settings(ah); 2042 ath9k_ps_restore(sc); 2043 } else if (!ah->dynack.enabled) { 2044 ath9k_enable_dynack(sc); 2045 } 2046 2047 mutex_unlock(&sc->mutex); 2048 } 2049 2050 static bool ath9k_has_tx_pending(struct ath_softc *sc, 2051 bool sw_pending) 2052 { 2053 int i, npend = 0; 2054 2055 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2056 if (!ATH_TXQ_SETUP(sc, i)) 2057 continue; 2058 2059 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i], 2060 sw_pending); 2061 if (npend) 2062 break; 2063 } 2064 2065 return !!npend; 2066 } 2067 2068 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2069 u32 queues, bool drop) 2070 { 2071 struct ath_softc *sc = hw->priv; 2072 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2073 2074 if (ath9k_is_chanctx_enabled()) { 2075 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2076 goto flush; 2077 2078 /* 2079 * If MCC is active, extend the flush timeout 2080 * and wait for the HW/SW queues to become 2081 * empty. This needs to be done outside the 2082 * sc->mutex lock to allow the channel scheduler 2083 * to switch channel contexts. 2084 * 2085 * The vif queues have been stopped in mac80211, 2086 * so there won't be any incoming frames. 2087 */ 2088 __ath9k_flush(hw, queues, drop, true, true); 2089 return; 2090 } 2091 flush: 2092 mutex_lock(&sc->mutex); 2093 __ath9k_flush(hw, queues, drop, true, false); 2094 mutex_unlock(&sc->mutex); 2095 } 2096 2097 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, 2098 bool sw_pending, bool timeout_override) 2099 { 2100 struct ath_softc *sc = hw->priv; 2101 struct ath_hw *ah = sc->sc_ah; 2102 struct ath_common *common = ath9k_hw_common(ah); 2103 int timeout; 2104 bool drain_txq; 2105 2106 cancel_delayed_work_sync(&sc->hw_check_work); 2107 2108 if (ah->ah_flags & AH_UNPLUGGED) { 2109 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2110 return; 2111 } 2112 2113 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2114 ath_dbg(common, ANY, "Device not present\n"); 2115 return; 2116 } 2117 2118 spin_lock_bh(&sc->chan_lock); 2119 if (timeout_override) 2120 timeout = HZ / 5; 2121 else 2122 timeout = sc->cur_chan->flush_timeout; 2123 spin_unlock_bh(&sc->chan_lock); 2124 2125 ath_dbg(common, CHAN_CTX, 2126 "Flush timeout: %d\n", jiffies_to_msecs(timeout)); 2127 2128 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending), 2129 timeout) > 0) 2130 drop = false; 2131 2132 if (drop) { 2133 ath9k_ps_wakeup(sc); 2134 spin_lock_bh(&sc->sc_pcu_lock); 2135 drain_txq = ath_drain_all_txq(sc); 2136 spin_unlock_bh(&sc->sc_pcu_lock); 2137 2138 if (!drain_txq) 2139 ath_reset(sc, NULL); 2140 2141 ath9k_ps_restore(sc); 2142 } 2143 2144 ieee80211_queue_delayed_work(hw, &sc->hw_check_work, 2145 ATH_HW_CHECK_POLL_INT); 2146 } 2147 2148 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2149 { 2150 struct ath_softc *sc = hw->priv; 2151 2152 return ath9k_has_tx_pending(sc, true); 2153 } 2154 2155 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2156 { 2157 struct ath_softc *sc = hw->priv; 2158 struct ath_hw *ah = sc->sc_ah; 2159 struct ieee80211_vif *vif; 2160 struct ath_vif *avp; 2161 struct ath_buf *bf; 2162 struct ath_tx_status ts; 2163 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2164 int status; 2165 2166 vif = sc->beacon.bslot[0]; 2167 if (!vif) 2168 return 0; 2169 2170 if (!vif->bss_conf.enable_beacon) 2171 return 0; 2172 2173 avp = (void *)vif->drv_priv; 2174 2175 if (!sc->beacon.tx_processed && !edma) { 2176 tasklet_disable(&sc->bcon_tasklet); 2177 2178 bf = avp->av_bcbuf; 2179 if (!bf || !bf->bf_mpdu) 2180 goto skip; 2181 2182 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2183 if (status == -EINPROGRESS) 2184 goto skip; 2185 2186 sc->beacon.tx_processed = true; 2187 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2188 2189 skip: 2190 tasklet_enable(&sc->bcon_tasklet); 2191 } 2192 2193 return sc->beacon.tx_last; 2194 } 2195 2196 static int ath9k_get_stats(struct ieee80211_hw *hw, 2197 struct ieee80211_low_level_stats *stats) 2198 { 2199 struct ath_softc *sc = hw->priv; 2200 struct ath_hw *ah = sc->sc_ah; 2201 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2202 2203 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2204 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2205 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2206 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2207 return 0; 2208 } 2209 2210 static u32 fill_chainmask(u32 cap, u32 new) 2211 { 2212 u32 filled = 0; 2213 int i; 2214 2215 for (i = 0; cap && new; i++, cap >>= 1) { 2216 if (!(cap & BIT(0))) 2217 continue; 2218 2219 if (new & BIT(0)) 2220 filled |= BIT(i); 2221 2222 new >>= 1; 2223 } 2224 2225 return filled; 2226 } 2227 2228 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2229 { 2230 if (AR_SREV_9300_20_OR_LATER(ah)) 2231 return true; 2232 2233 switch (val & 0x7) { 2234 case 0x1: 2235 case 0x3: 2236 case 0x7: 2237 return true; 2238 case 0x2: 2239 return (ah->caps.rx_chainmask == 1); 2240 default: 2241 return false; 2242 } 2243 } 2244 2245 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2246 { 2247 struct ath_softc *sc = hw->priv; 2248 struct ath_hw *ah = sc->sc_ah; 2249 2250 if (ah->caps.rx_chainmask != 1) 2251 rx_ant |= tx_ant; 2252 2253 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2254 return -EINVAL; 2255 2256 sc->ant_rx = rx_ant; 2257 sc->ant_tx = tx_ant; 2258 2259 if (ah->caps.rx_chainmask == 1) 2260 return 0; 2261 2262 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2263 if (AR_SREV_9100(ah)) 2264 ah->rxchainmask = 0x7; 2265 else 2266 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2267 2268 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2269 ath9k_cmn_reload_chainmask(ah); 2270 2271 return 0; 2272 } 2273 2274 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2275 { 2276 struct ath_softc *sc = hw->priv; 2277 2278 *tx_ant = sc->ant_tx; 2279 *rx_ant = sc->ant_rx; 2280 return 0; 2281 } 2282 2283 static void ath9k_sw_scan_start(struct ieee80211_hw *hw, 2284 struct ieee80211_vif *vif, 2285 const u8 *mac_addr) 2286 { 2287 struct ath_softc *sc = hw->priv; 2288 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2289 set_bit(ATH_OP_SCANNING, &common->op_flags); 2290 } 2291 2292 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, 2293 struct ieee80211_vif *vif) 2294 { 2295 struct ath_softc *sc = hw->priv; 2296 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2297 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2298 } 2299 2300 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2301 2302 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc) 2303 { 2304 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2305 2306 if (sc->offchannel.roc_vif) { 2307 ath_dbg(common, CHAN_CTX, 2308 "%s: Aborting RoC\n", __func__); 2309 2310 del_timer_sync(&sc->offchannel.timer); 2311 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2312 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT); 2313 } 2314 2315 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 2316 ath_dbg(common, CHAN_CTX, 2317 "%s: Aborting HW scan\n", __func__); 2318 2319 del_timer_sync(&sc->offchannel.timer); 2320 ath_scan_complete(sc, true); 2321 } 2322 } 2323 2324 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2325 struct ieee80211_scan_request *hw_req) 2326 { 2327 struct cfg80211_scan_request *req = &hw_req->req; 2328 struct ath_softc *sc = hw->priv; 2329 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2330 int ret = 0; 2331 2332 mutex_lock(&sc->mutex); 2333 2334 if (WARN_ON(sc->offchannel.scan_req)) { 2335 ret = -EBUSY; 2336 goto out; 2337 } 2338 2339 ath9k_ps_wakeup(sc); 2340 set_bit(ATH_OP_SCANNING, &common->op_flags); 2341 sc->offchannel.scan_vif = vif; 2342 sc->offchannel.scan_req = req; 2343 sc->offchannel.scan_idx = 0; 2344 2345 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2346 vif->addr); 2347 2348 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2349 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2350 ath_offchannel_next(sc); 2351 } 2352 2353 out: 2354 mutex_unlock(&sc->mutex); 2355 2356 return ret; 2357 } 2358 2359 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2360 struct ieee80211_vif *vif) 2361 { 2362 struct ath_softc *sc = hw->priv; 2363 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2364 2365 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2366 2367 mutex_lock(&sc->mutex); 2368 del_timer_sync(&sc->offchannel.timer); 2369 ath_scan_complete(sc, true); 2370 mutex_unlock(&sc->mutex); 2371 } 2372 2373 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2374 struct ieee80211_vif *vif, 2375 struct ieee80211_channel *chan, int duration, 2376 enum ieee80211_roc_type type) 2377 { 2378 struct ath_softc *sc = hw->priv; 2379 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2380 int ret = 0; 2381 2382 mutex_lock(&sc->mutex); 2383 2384 if (WARN_ON(sc->offchannel.roc_vif)) { 2385 ret = -EBUSY; 2386 goto out; 2387 } 2388 2389 ath9k_ps_wakeup(sc); 2390 sc->offchannel.roc_vif = vif; 2391 sc->offchannel.roc_chan = chan; 2392 sc->offchannel.roc_duration = duration; 2393 2394 ath_dbg(common, CHAN_CTX, 2395 "RoC request on vif: %pM, type: %d duration: %d\n", 2396 vif->addr, type, duration); 2397 2398 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2399 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2400 ath_offchannel_next(sc); 2401 } 2402 2403 out: 2404 mutex_unlock(&sc->mutex); 2405 2406 return ret; 2407 } 2408 2409 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw, 2410 struct ieee80211_vif *vif) 2411 { 2412 struct ath_softc *sc = hw->priv; 2413 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2414 2415 mutex_lock(&sc->mutex); 2416 2417 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2418 del_timer_sync(&sc->offchannel.timer); 2419 2420 if (sc->offchannel.roc_vif) { 2421 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2422 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL); 2423 } 2424 2425 mutex_unlock(&sc->mutex); 2426 2427 return 0; 2428 } 2429 2430 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2431 struct ieee80211_chanctx_conf *conf) 2432 { 2433 struct ath_softc *sc = hw->priv; 2434 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2435 struct ath_chanctx *ctx, **ptr; 2436 int pos; 2437 2438 mutex_lock(&sc->mutex); 2439 2440 ath_for_each_chanctx(sc, ctx) { 2441 if (ctx->assigned) 2442 continue; 2443 2444 ptr = (void *) conf->drv_priv; 2445 *ptr = ctx; 2446 ctx->assigned = true; 2447 pos = ctx - &sc->chanctx[0]; 2448 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2449 2450 ath_dbg(common, CHAN_CTX, 2451 "Add channel context: %d MHz\n", 2452 conf->def.chan->center_freq); 2453 2454 ath_chanctx_set_channel(sc, ctx, &conf->def); 2455 2456 mutex_unlock(&sc->mutex); 2457 return 0; 2458 } 2459 2460 mutex_unlock(&sc->mutex); 2461 return -ENOSPC; 2462 } 2463 2464 2465 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2466 struct ieee80211_chanctx_conf *conf) 2467 { 2468 struct ath_softc *sc = hw->priv; 2469 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2470 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2471 2472 mutex_lock(&sc->mutex); 2473 2474 ath_dbg(common, CHAN_CTX, 2475 "Remove channel context: %d MHz\n", 2476 conf->def.chan->center_freq); 2477 2478 ctx->assigned = false; 2479 ctx->hw_queue_base = 0; 2480 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2481 2482 mutex_unlock(&sc->mutex); 2483 } 2484 2485 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2486 struct ieee80211_chanctx_conf *conf, 2487 u32 changed) 2488 { 2489 struct ath_softc *sc = hw->priv; 2490 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2491 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2492 2493 mutex_lock(&sc->mutex); 2494 ath_dbg(common, CHAN_CTX, 2495 "Change channel context: %d MHz\n", 2496 conf->def.chan->center_freq); 2497 ath_chanctx_set_channel(sc, ctx, &conf->def); 2498 mutex_unlock(&sc->mutex); 2499 } 2500 2501 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2502 struct ieee80211_vif *vif, 2503 struct ieee80211_chanctx_conf *conf) 2504 { 2505 struct ath_softc *sc = hw->priv; 2506 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2507 struct ath_vif *avp = (void *)vif->drv_priv; 2508 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2509 int i; 2510 2511 ath9k_cancel_pending_offchannel(sc); 2512 2513 mutex_lock(&sc->mutex); 2514 2515 ath_dbg(common, CHAN_CTX, 2516 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2517 vif->addr, vif->type, vif->p2p, 2518 conf->def.chan->center_freq); 2519 2520 avp->chanctx = ctx; 2521 ctx->nvifs_assigned++; 2522 list_add_tail(&avp->list, &ctx->vifs); 2523 ath9k_calculate_summary_state(sc, ctx); 2524 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2525 vif->hw_queue[i] = ctx->hw_queue_base + i; 2526 2527 mutex_unlock(&sc->mutex); 2528 2529 return 0; 2530 } 2531 2532 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2533 struct ieee80211_vif *vif, 2534 struct ieee80211_chanctx_conf *conf) 2535 { 2536 struct ath_softc *sc = hw->priv; 2537 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2538 struct ath_vif *avp = (void *)vif->drv_priv; 2539 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2540 int ac; 2541 2542 ath9k_cancel_pending_offchannel(sc); 2543 2544 mutex_lock(&sc->mutex); 2545 2546 ath_dbg(common, CHAN_CTX, 2547 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2548 vif->addr, vif->type, vif->p2p, 2549 conf->def.chan->center_freq); 2550 2551 avp->chanctx = NULL; 2552 ctx->nvifs_assigned--; 2553 list_del(&avp->list); 2554 ath9k_calculate_summary_state(sc, ctx); 2555 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2556 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2557 2558 mutex_unlock(&sc->mutex); 2559 } 2560 2561 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2562 struct ieee80211_vif *vif, 2563 u16 duration) 2564 { 2565 struct ath_softc *sc = hw->priv; 2566 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2567 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2568 struct ath_beacon_config *cur_conf; 2569 struct ath_chanctx *go_ctx; 2570 unsigned long timeout; 2571 bool changed = false; 2572 u32 beacon_int; 2573 2574 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2575 return; 2576 2577 if (!avp->chanctx) 2578 return; 2579 2580 mutex_lock(&sc->mutex); 2581 2582 spin_lock_bh(&sc->chan_lock); 2583 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) 2584 changed = true; 2585 spin_unlock_bh(&sc->chan_lock); 2586 2587 if (!changed) 2588 goto out; 2589 2590 ath9k_cancel_pending_offchannel(sc); 2591 2592 go_ctx = ath_is_go_chanctx_present(sc); 2593 2594 if (go_ctx) { 2595 /* 2596 * Wait till the GO interface gets a chance 2597 * to send out an NoA. 2598 */ 2599 spin_lock_bh(&sc->chan_lock); 2600 sc->sched.mgd_prepare_tx = true; 2601 cur_conf = &go_ctx->beacon; 2602 beacon_int = TU_TO_USEC(cur_conf->beacon_interval); 2603 spin_unlock_bh(&sc->chan_lock); 2604 2605 timeout = usecs_to_jiffies(beacon_int * 2); 2606 init_completion(&sc->go_beacon); 2607 2608 mutex_unlock(&sc->mutex); 2609 2610 if (wait_for_completion_timeout(&sc->go_beacon, 2611 timeout) == 0) { 2612 ath_dbg(common, CHAN_CTX, 2613 "Failed to send new NoA\n"); 2614 2615 spin_lock_bh(&sc->chan_lock); 2616 sc->sched.mgd_prepare_tx = false; 2617 spin_unlock_bh(&sc->chan_lock); 2618 } 2619 2620 mutex_lock(&sc->mutex); 2621 } 2622 2623 ath_dbg(common, CHAN_CTX, 2624 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n", 2625 __func__, vif->addr); 2626 2627 spin_lock_bh(&sc->chan_lock); 2628 sc->next_chan = avp->chanctx; 2629 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2630 spin_unlock_bh(&sc->chan_lock); 2631 2632 ath_chanctx_set_next(sc, true); 2633 out: 2634 mutex_unlock(&sc->mutex); 2635 } 2636 2637 void ath9k_fill_chanctx_ops(void) 2638 { 2639 if (!ath9k_is_chanctx_enabled()) 2640 return; 2641 2642 ath9k_ops.hw_scan = ath9k_hw_scan; 2643 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2644 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2645 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2646 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2647 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2648 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2649 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2650 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2651 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2652 } 2653 2654 #endif 2655 2656 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2657 int *dbm) 2658 { 2659 struct ath_softc *sc = hw->priv; 2660 struct ath_vif *avp = (void *)vif->drv_priv; 2661 2662 mutex_lock(&sc->mutex); 2663 if (avp->chanctx) 2664 *dbm = avp->chanctx->cur_txpower; 2665 else 2666 *dbm = sc->cur_chan->cur_txpower; 2667 mutex_unlock(&sc->mutex); 2668 2669 *dbm /= 2; 2670 2671 return 0; 2672 } 2673 2674 struct ieee80211_ops ath9k_ops = { 2675 .tx = ath9k_tx, 2676 .start = ath9k_start, 2677 .stop = ath9k_stop, 2678 .add_interface = ath9k_add_interface, 2679 .change_interface = ath9k_change_interface, 2680 .remove_interface = ath9k_remove_interface, 2681 .config = ath9k_config, 2682 .configure_filter = ath9k_configure_filter, 2683 .sta_state = ath9k_sta_state, 2684 .sta_notify = ath9k_sta_notify, 2685 .conf_tx = ath9k_conf_tx, 2686 .bss_info_changed = ath9k_bss_info_changed, 2687 .set_key = ath9k_set_key, 2688 .get_tsf = ath9k_get_tsf, 2689 .set_tsf = ath9k_set_tsf, 2690 .reset_tsf = ath9k_reset_tsf, 2691 .ampdu_action = ath9k_ampdu_action, 2692 .get_survey = ath9k_get_survey, 2693 .rfkill_poll = ath9k_rfkill_poll_state, 2694 .set_coverage_class = ath9k_set_coverage_class, 2695 .flush = ath9k_flush, 2696 .tx_frames_pending = ath9k_tx_frames_pending, 2697 .tx_last_beacon = ath9k_tx_last_beacon, 2698 .release_buffered_frames = ath9k_release_buffered_frames, 2699 .get_stats = ath9k_get_stats, 2700 .set_antenna = ath9k_set_antenna, 2701 .get_antenna = ath9k_get_antenna, 2702 2703 #ifdef CONFIG_ATH9K_WOW 2704 .suspend = ath9k_suspend, 2705 .resume = ath9k_resume, 2706 .set_wakeup = ath9k_set_wakeup, 2707 #endif 2708 2709 #ifdef CONFIG_ATH9K_DEBUGFS 2710 .get_et_sset_count = ath9k_get_et_sset_count, 2711 .get_et_stats = ath9k_get_et_stats, 2712 .get_et_strings = ath9k_get_et_strings, 2713 #endif 2714 2715 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2716 .sta_add_debugfs = ath9k_sta_add_debugfs, 2717 #endif 2718 .sw_scan_start = ath9k_sw_scan_start, 2719 .sw_scan_complete = ath9k_sw_scan_complete, 2720 .get_txpower = ath9k_get_txpower, 2721 .wake_tx_queue = ath9k_wake_tx_queue, 2722 }; 2723