xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/main.c (revision 208012f0)
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21 
22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 			u32 queues, bool drop);
24 
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 	/*
28 	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 	 *   0 for no restriction
30 	 *   1 for 1/4 us
31 	 *   2 for 1/2 us
32 	 *   3 for 1 us
33 	 *   4 for 2 us
34 	 *   5 for 4 us
35 	 *   6 for 8 us
36 	 *   7 for 16 us
37 	 */
38 	switch (mpdudensity) {
39 	case 0:
40 		return 0;
41 	case 1:
42 	case 2:
43 	case 3:
44 		/* Our lower layer calculations limit our precision to
45 		   1 microsecond */
46 		return 1;
47 	case 4:
48 		return 2;
49 	case 5:
50 		return 4;
51 	case 6:
52 		return 8;
53 	case 7:
54 		return 16;
55 	default:
56 		return 0;
57 	}
58 }
59 
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 				     bool sw_pending)
62 {
63 	bool pending = false;
64 
65 	spin_lock_bh(&txq->axq_lock);
66 
67 	if (txq->axq_depth) {
68 		pending = true;
69 		goto out;
70 	}
71 
72 	if (!sw_pending)
73 		goto out;
74 
75 	if (txq->mac80211_qnum >= 0) {
76 		struct ath_acq *acq;
77 
78 		acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 		if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 			pending = true;
81 	}
82 out:
83 	spin_unlock_bh(&txq->axq_lock);
84 	return pending;
85 }
86 
87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88 {
89 	unsigned long flags;
90 	bool ret;
91 
92 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 	ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95 
96 	return ret;
97 }
98 
99 void ath_ps_full_sleep(struct timer_list *t)
100 {
101 	struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 	unsigned long flags;
104 	bool reset;
105 
106 	spin_lock_irqsave(&common->cc_lock, flags);
107 	ath_hw_cycle_counters_update(common);
108 	spin_unlock_irqrestore(&common->cc_lock, flags);
109 
110 	ath9k_hw_setrxabort(sc->sc_ah, 1);
111 	ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112 
113 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114 }
115 
116 void ath9k_ps_wakeup(struct ath_softc *sc)
117 {
118 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 	unsigned long flags;
120 	enum ath9k_power_mode power_mode;
121 
122 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 	if (++sc->ps_usecount != 1)
124 		goto unlock;
125 
126 	del_timer_sync(&sc->sleep_timer);
127 	power_mode = sc->sc_ah->power_mode;
128 	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129 
130 	/*
131 	 * While the hardware is asleep, the cycle counters contain no
132 	 * useful data. Better clear them now so that they don't mess up
133 	 * survey data results.
134 	 */
135 	if (power_mode != ATH9K_PM_AWAKE) {
136 		spin_lock(&common->cc_lock);
137 		ath_hw_cycle_counters_update(common);
138 		memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 		memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 		spin_unlock(&common->cc_lock);
141 	}
142 
143  unlock:
144 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146 
147 void ath9k_ps_restore(struct ath_softc *sc)
148 {
149 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 	enum ath9k_power_mode mode;
151 	unsigned long flags;
152 
153 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 	if (--sc->ps_usecount != 0)
155 		goto unlock;
156 
157 	if (sc->ps_idle) {
158 		mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 		goto unlock;
160 	}
161 
162 	if (sc->ps_enabled &&
163 		   !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 				     PS_WAIT_FOR_CAB |
165 				     PS_WAIT_FOR_PSPOLL_DATA |
166 				     PS_WAIT_FOR_TX_ACK |
167 				     PS_WAIT_FOR_ANI))) {
168 		mode = ATH9K_PM_NETWORK_SLEEP;
169 		if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 			ath9k_btcoex_stop_gen_timer(sc);
171 	} else {
172 		goto unlock;
173 	}
174 
175 	spin_lock(&common->cc_lock);
176 	ath_hw_cycle_counters_update(common);
177 	spin_unlock(&common->cc_lock);
178 
179 	ath9k_hw_setpower(sc->sc_ah, mode);
180 
181  unlock:
182 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183 }
184 
185 static void __ath_cancel_work(struct ath_softc *sc)
186 {
187 	cancel_work_sync(&sc->paprd_work);
188 	cancel_delayed_work_sync(&sc->hw_check_work);
189 	cancel_delayed_work_sync(&sc->hw_pll_work);
190 
191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 		cancel_work_sync(&sc->mci_work);
194 #endif
195 }
196 
197 void ath_cancel_work(struct ath_softc *sc)
198 {
199 	__ath_cancel_work(sc);
200 	cancel_work_sync(&sc->hw_reset_work);
201 }
202 
203 void ath_restart_work(struct ath_softc *sc)
204 {
205 	ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 				     ATH_HW_CHECK_POLL_INT);
207 
208 	if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211 
212 	ath_start_ani(sc);
213 }
214 
215 static bool ath_prepare_reset(struct ath_softc *sc)
216 {
217 	struct ath_hw *ah = sc->sc_ah;
218 	bool ret = true;
219 
220 	ieee80211_stop_queues(sc->hw);
221 	ath_stop_ani(sc);
222 	ath9k_hw_disable_interrupts(ah);
223 
224 	if (AR_SREV_9300_20_OR_LATER(ah)) {
225 		ret &= ath_stoprecv(sc);
226 		ret &= ath_drain_all_txq(sc);
227 	} else {
228 		ret &= ath_drain_all_txq(sc);
229 		ret &= ath_stoprecv(sc);
230 	}
231 
232 	return ret;
233 }
234 
235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 {
237 	struct ath_hw *ah = sc->sc_ah;
238 	struct ath_common *common = ath9k_hw_common(ah);
239 	unsigned long flags;
240 
241 	ath9k_calculate_summary_state(sc, sc->cur_chan);
242 	ath_startrecv(sc);
243 	ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 			       sc->cur_chan->txpower,
245 			       &sc->cur_chan->cur_txpower);
246 	clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247 
248 	if (!sc->cur_chan->offchannel && start) {
249 		/* restore per chanctx TSF timer */
250 		if (sc->cur_chan->tsf_val) {
251 			u32 offset;
252 
253 			offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 							 NULL);
255 			ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 		}
257 
258 
259 		if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 			goto work;
261 
262 		if (ah->opmode == NL80211_IFTYPE_STATION &&
263 		    test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 			spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 			sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 			spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 		} else {
268 			ath9k_set_beacon(sc);
269 		}
270 	work:
271 		ath_restart_work(sc);
272 		ath_txq_schedule_all(sc);
273 	}
274 
275 	sc->gtt_cnt = 0;
276 
277 	ath9k_hw_set_interrupts(ah);
278 	ath9k_hw_enable_interrupts(ah);
279 	ieee80211_wake_queues(sc->hw);
280 	ath9k_p2p_ps_timer(sc);
281 
282 	return true;
283 }
284 
285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286 {
287 	struct ath_hw *ah = sc->sc_ah;
288 	struct ath_common *common = ath9k_hw_common(ah);
289 	struct ath9k_hw_cal_data *caldata = NULL;
290 	bool fastcc = true;
291 	int r;
292 
293 	__ath_cancel_work(sc);
294 
295 	disable_irq(sc->irq);
296 	tasklet_disable(&sc->intr_tq);
297 	tasklet_disable(&sc->bcon_tasklet);
298 	spin_lock_bh(&sc->sc_pcu_lock);
299 
300 	if (!sc->cur_chan->offchannel) {
301 		fastcc = false;
302 		caldata = &sc->cur_chan->caldata;
303 	}
304 
305 	if (!hchan) {
306 		fastcc = false;
307 		hchan = ah->curchan;
308 	}
309 
310 	if (!ath_prepare_reset(sc))
311 		fastcc = false;
312 
313 	if (ath9k_is_chanctx_enabled())
314 		fastcc = false;
315 
316 	spin_lock_bh(&sc->chan_lock);
317 	sc->cur_chandef = sc->cur_chan->chandef;
318 	spin_unlock_bh(&sc->chan_lock);
319 
320 	ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
321 		hchan->channel, IS_CHAN_HT40(hchan), fastcc);
322 
323 	r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
324 	if (r) {
325 		ath_err(common,
326 			"Unable to reset channel, reset status %d\n", r);
327 
328 		ath9k_hw_enable_interrupts(ah);
329 		ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
330 
331 		goto out;
332 	}
333 
334 	if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
335 	    sc->cur_chan->offchannel)
336 		ath9k_mci_set_txpower(sc, true, false);
337 
338 	if (!ath_complete_reset(sc, true))
339 		r = -EIO;
340 
341 out:
342 	enable_irq(sc->irq);
343 	spin_unlock_bh(&sc->sc_pcu_lock);
344 	tasklet_enable(&sc->bcon_tasklet);
345 	tasklet_enable(&sc->intr_tq);
346 
347 	return r;
348 }
349 
350 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
351 			    struct ieee80211_vif *vif)
352 {
353 	struct ath_node *an;
354 	an = (struct ath_node *)sta->drv_priv;
355 
356 	an->sc = sc;
357 	an->sta = sta;
358 	an->vif = vif;
359 	memset(&an->key_idx, 0, sizeof(an->key_idx));
360 
361 	ath_tx_node_init(sc, an);
362 
363 	ath_dynack_node_init(sc->sc_ah, an);
364 }
365 
366 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
367 {
368 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
369 	ath_tx_node_cleanup(sc, an);
370 
371 	ath_dynack_node_deinit(sc->sc_ah, an);
372 }
373 
374 void ath9k_tasklet(struct tasklet_struct *t)
375 {
376 	struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
377 	struct ath_hw *ah = sc->sc_ah;
378 	struct ath_common *common = ath9k_hw_common(ah);
379 	enum ath_reset_type type;
380 	unsigned long flags;
381 	u32 status;
382 	u32 rxmask;
383 
384 	spin_lock_irqsave(&sc->intr_lock, flags);
385 	status = sc->intrstatus;
386 	sc->intrstatus = 0;
387 	spin_unlock_irqrestore(&sc->intr_lock, flags);
388 
389 	ath9k_ps_wakeup(sc);
390 	spin_lock(&sc->sc_pcu_lock);
391 
392 	if (status & ATH9K_INT_FATAL) {
393 		type = RESET_TYPE_FATAL_INT;
394 		ath9k_queue_reset(sc, type);
395 		ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
396 		goto out;
397 	}
398 
399 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
400 	    (status & ATH9K_INT_BB_WATCHDOG)) {
401 		spin_lock_irqsave(&common->cc_lock, flags);
402 		ath_hw_cycle_counters_update(common);
403 		ar9003_hw_bb_watchdog_dbg_info(ah);
404 		spin_unlock_irqrestore(&common->cc_lock, flags);
405 
406 		if (ar9003_hw_bb_watchdog_check(ah)) {
407 			type = RESET_TYPE_BB_WATCHDOG;
408 			ath9k_queue_reset(sc, type);
409 
410 			ath_dbg(common, RESET,
411 				"BB_WATCHDOG: Skipping interrupts\n");
412 			goto out;
413 		}
414 	}
415 
416 	if (status & ATH9K_INT_GTT) {
417 		sc->gtt_cnt++;
418 
419 		if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
420 			type = RESET_TYPE_TX_GTT;
421 			ath9k_queue_reset(sc, type);
422 			ath_dbg(common, RESET,
423 				"GTT: Skipping interrupts\n");
424 			goto out;
425 		}
426 	}
427 
428 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
429 	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
430 		/*
431 		 * TSF sync does not look correct; remain awake to sync with
432 		 * the next Beacon.
433 		 */
434 		ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
435 		sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
436 	}
437 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
438 
439 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
440 		rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
441 			  ATH9K_INT_RXORN);
442 	else
443 		rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
444 
445 	if (status & rxmask) {
446 		/* Check for high priority Rx first */
447 		if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
448 		    (status & ATH9K_INT_RXHP))
449 			ath_rx_tasklet(sc, 0, true);
450 
451 		ath_rx_tasklet(sc, 0, false);
452 	}
453 
454 	if (status & ATH9K_INT_TX) {
455 		if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
456 			/*
457 			 * For EDMA chips, TX completion is enabled for the
458 			 * beacon queue, so if a beacon has been transmitted
459 			 * successfully after a GTT interrupt, the GTT counter
460 			 * gets reset to zero here.
461 			 */
462 			sc->gtt_cnt = 0;
463 
464 			ath_tx_edma_tasklet(sc);
465 		} else {
466 			ath_tx_tasklet(sc);
467 		}
468 
469 		wake_up(&sc->tx_wait);
470 	}
471 
472 	if (status & ATH9K_INT_GENTIMER)
473 		ath_gen_timer_isr(sc->sc_ah);
474 
475 	ath9k_btcoex_handle_interrupt(sc, status);
476 
477 	/* re-enable hardware interrupt */
478 	ath9k_hw_resume_interrupts(ah);
479 out:
480 	spin_unlock(&sc->sc_pcu_lock);
481 	ath9k_ps_restore(sc);
482 }
483 
484 irqreturn_t ath_isr(int irq, void *dev)
485 {
486 #define SCHED_INTR (				\
487 		ATH9K_INT_FATAL |		\
488 		ATH9K_INT_BB_WATCHDOG |		\
489 		ATH9K_INT_RXORN |		\
490 		ATH9K_INT_RXEOL |		\
491 		ATH9K_INT_RX |			\
492 		ATH9K_INT_RXLP |		\
493 		ATH9K_INT_RXHP |		\
494 		ATH9K_INT_TX |			\
495 		ATH9K_INT_BMISS |		\
496 		ATH9K_INT_CST |			\
497 		ATH9K_INT_GTT |			\
498 		ATH9K_INT_TSFOOR |		\
499 		ATH9K_INT_GENTIMER |		\
500 		ATH9K_INT_MCI)
501 
502 	struct ath_softc *sc = dev;
503 	struct ath_hw *ah = sc->sc_ah;
504 	struct ath_common *common = ath9k_hw_common(ah);
505 	enum ath9k_int status;
506 	u32 sync_cause = 0;
507 	bool sched = false;
508 
509 	/*
510 	 * The hardware is not ready/present, don't
511 	 * touch anything. Note this can happen early
512 	 * on if the IRQ is shared.
513 	 */
514 	if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
515 		return IRQ_NONE;
516 
517 	/* shared irq, not for us */
518 	if (!ath9k_hw_intrpend(ah))
519 		return IRQ_NONE;
520 
521 	/*
522 	 * Figure out the reason(s) for the interrupt.  Note
523 	 * that the hal returns a pseudo-ISR that may include
524 	 * bits we haven't explicitly enabled so we mask the
525 	 * value to insure we only process bits we requested.
526 	 */
527 	ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
528 	ath9k_debug_sync_cause(sc, sync_cause);
529 	status &= ah->imask;	/* discard unasked-for bits */
530 
531 	if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
532 		return IRQ_HANDLED;
533 
534 	/*
535 	 * If there are no status bits set, then this interrupt was not
536 	 * for me (should have been caught above).
537 	 */
538 	if (!status)
539 		return IRQ_NONE;
540 
541 	/* Cache the status */
542 	spin_lock(&sc->intr_lock);
543 	sc->intrstatus |= status;
544 	spin_unlock(&sc->intr_lock);
545 
546 	if (status & SCHED_INTR)
547 		sched = true;
548 
549 	/*
550 	 * If a FATAL interrupt is received, we have to reset the chip
551 	 * immediately.
552 	 */
553 	if (status & ATH9K_INT_FATAL)
554 		goto chip_reset;
555 
556 	if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
557 	    (status & ATH9K_INT_BB_WATCHDOG))
558 		goto chip_reset;
559 
560 	if (status & ATH9K_INT_SWBA)
561 		tasklet_schedule(&sc->bcon_tasklet);
562 
563 	if (status & ATH9K_INT_TXURN)
564 		ath9k_hw_updatetxtriglevel(ah, true);
565 
566 	if (status & ATH9K_INT_RXEOL) {
567 		ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
568 		ath9k_hw_set_interrupts(ah);
569 	}
570 
571 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 		if (status & ATH9K_INT_TIM_TIMER) {
573 			if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 				goto chip_reset;
575 			/* Clear RxAbort bit so that we can
576 			 * receive frames */
577 			ath9k_setpower(sc, ATH9K_PM_AWAKE);
578 			spin_lock(&sc->sc_pm_lock);
579 			ath9k_hw_setrxabort(sc->sc_ah, 0);
580 			sc->ps_flags |= PS_WAIT_FOR_BEACON;
581 			spin_unlock(&sc->sc_pm_lock);
582 		}
583 
584 chip_reset:
585 
586 	ath_debug_stat_interrupt(sc, status);
587 
588 	if (sched) {
589 		/* turn off every interrupt */
590 		ath9k_hw_kill_interrupts(ah);
591 		tasklet_schedule(&sc->intr_tq);
592 	}
593 
594 	return IRQ_HANDLED;
595 
596 #undef SCHED_INTR
597 }
598 
599 /*
600  * This function is called when a HW reset cannot be deferred
601  * and has to be immediate.
602  */
603 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
604 {
605 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 	int r;
607 
608 	ath9k_hw_kill_interrupts(sc->sc_ah);
609 	set_bit(ATH_OP_HW_RESET, &common->op_flags);
610 
611 	ath9k_ps_wakeup(sc);
612 	r = ath_reset_internal(sc, hchan);
613 	ath9k_ps_restore(sc);
614 
615 	return r;
616 }
617 
618 /*
619  * When a HW reset can be deferred, it is added to the
620  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621  * queueing.
622  */
623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624 {
625 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 	RESET_STAT_INC(sc, type);
628 #endif
629 	ath9k_hw_kill_interrupts(sc->sc_ah);
630 	set_bit(ATH_OP_HW_RESET, &common->op_flags);
631 	ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632 }
633 
634 void ath_reset_work(struct work_struct *work)
635 {
636 	struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637 
638 	ath9k_ps_wakeup(sc);
639 	ath_reset_internal(sc, NULL);
640 	ath9k_ps_restore(sc);
641 }
642 
643 /**********************/
644 /* mac80211 callbacks */
645 /**********************/
646 
647 static int ath9k_start(struct ieee80211_hw *hw)
648 {
649 	struct ath_softc *sc = hw->priv;
650 	struct ath_hw *ah = sc->sc_ah;
651 	struct ath_common *common = ath9k_hw_common(ah);
652 	struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
653 	struct ath_chanctx *ctx = sc->cur_chan;
654 	struct ath9k_channel *init_channel;
655 	int r;
656 
657 	ath_dbg(common, CONFIG,
658 		"Starting driver with initial channel: %d MHz\n",
659 		curchan->center_freq);
660 
661 	ath9k_ps_wakeup(sc);
662 	mutex_lock(&sc->mutex);
663 
664 	init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
665 	sc->cur_chandef = hw->conf.chandef;
666 
667 	/* Reset SERDES registers */
668 	ath9k_hw_configpcipowersave(ah, false);
669 
670 	/*
671 	 * The basic interface to setting the hardware in a good
672 	 * state is ``reset''.  On return the hardware is known to
673 	 * be powered up and with interrupts disabled.  This must
674 	 * be followed by initialization of the appropriate bits
675 	 * and then setup of the interrupt mask.
676 	 */
677 	spin_lock_bh(&sc->sc_pcu_lock);
678 
679 	atomic_set(&ah->intr_ref_cnt, -1);
680 
681 	r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
682 	if (r) {
683 		ath_err(common,
684 			"Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 			r, curchan->center_freq);
686 		ah->reset_power_on = false;
687 	}
688 
689 	/* Setup our intr mask. */
690 	ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 		    ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 		    ATH9K_INT_GLOBAL;
693 
694 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
695 		ah->imask |= ATH9K_INT_RXHP |
696 			     ATH9K_INT_RXLP;
697 	else
698 		ah->imask |= ATH9K_INT_RX;
699 
700 	if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 		ah->imask |= ATH9K_INT_BB_WATCHDOG;
702 
703 	/*
704 	 * Enable GTT interrupts only for AR9003/AR9004 chips
705 	 * for now.
706 	 */
707 	if (AR_SREV_9300_20_OR_LATER(ah))
708 		ah->imask |= ATH9K_INT_GTT;
709 
710 	if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
711 		ah->imask |= ATH9K_INT_CST;
712 
713 	ath_mci_enable(sc);
714 
715 	clear_bit(ATH_OP_INVALID, &common->op_flags);
716 	sc->sc_ah->is_monitoring = false;
717 
718 	if (!ath_complete_reset(sc, false))
719 		ah->reset_power_on = false;
720 
721 	if (ah->led_pin >= 0) {
722 		ath9k_hw_set_gpio(ah, ah->led_pin,
723 				  (ah->config.led_active_high) ? 1 : 0);
724 		ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
725 					  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
726 	}
727 
728 	/*
729 	 * Reset key cache to sane defaults (all entries cleared) instead of
730 	 * semi-random values after suspend/resume.
731 	 */
732 	ath9k_cmn_init_crypto(sc->sc_ah);
733 
734 	ath9k_hw_reset_tsf(ah);
735 
736 	spin_unlock_bh(&sc->sc_pcu_lock);
737 
738 	ath9k_rng_start(sc);
739 
740 	mutex_unlock(&sc->mutex);
741 
742 	ath9k_ps_restore(sc);
743 
744 	return 0;
745 }
746 
747 static void ath9k_tx(struct ieee80211_hw *hw,
748 		     struct ieee80211_tx_control *control,
749 		     struct sk_buff *skb)
750 {
751 	struct ath_softc *sc = hw->priv;
752 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
753 	struct ath_tx_control txctl;
754 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
755 	unsigned long flags;
756 
757 	if (sc->ps_enabled) {
758 		/*
759 		 * mac80211 does not set PM field for normal data frames, so we
760 		 * need to update that based on the current PS mode.
761 		 */
762 		if (ieee80211_is_data(hdr->frame_control) &&
763 		    !ieee80211_is_nullfunc(hdr->frame_control) &&
764 		    !ieee80211_has_pm(hdr->frame_control)) {
765 			ath_dbg(common, PS,
766 				"Add PM=1 for a TX frame while in PS mode\n");
767 			hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
768 		}
769 	}
770 
771 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
772 		/*
773 		 * We are using PS-Poll and mac80211 can request TX while in
774 		 * power save mode. Need to wake up hardware for the TX to be
775 		 * completed and if needed, also for RX of buffered frames.
776 		 */
777 		ath9k_ps_wakeup(sc);
778 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
779 		if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 			ath9k_hw_setrxabort(sc->sc_ah, 0);
781 		if (ieee80211_is_pspoll(hdr->frame_control)) {
782 			ath_dbg(common, PS,
783 				"Sending PS-Poll to pick a buffered frame\n");
784 			sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
785 		} else {
786 			ath_dbg(common, PS, "Wake up to complete TX\n");
787 			sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
788 		}
789 		/*
790 		 * The actual restore operation will happen only after
791 		 * the ps_flags bit is cleared. We are just dropping
792 		 * the ps_usecount here.
793 		 */
794 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
795 		ath9k_ps_restore(sc);
796 	}
797 
798 	/*
799 	 * Cannot tx while the hardware is in full sleep, it first needs a full
800 	 * chip reset to recover from that
801 	 */
802 	if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
803 		ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
804 		goto exit;
805 	}
806 
807 	memset(&txctl, 0, sizeof(struct ath_tx_control));
808 	txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
809 	txctl.sta = control->sta;
810 
811 	ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
812 
813 	if (ath_tx_start(hw, skb, &txctl) != 0) {
814 		ath_dbg(common, XMIT, "TX failed\n");
815 		TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
816 		goto exit;
817 	}
818 
819 	return;
820 exit:
821 	ieee80211_free_txskb(hw, skb);
822 }
823 
824 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
825 {
826 	struct ath_buf *bf;
827 	struct ieee80211_tx_info *txinfo;
828 	struct ath_frame_info *fi;
829 
830 	list_for_each_entry(bf, txq_list, list) {
831 		if (bf->bf_state.stale || !bf->bf_mpdu)
832 			continue;
833 
834 		txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
835 		fi = (struct ath_frame_info *)&txinfo->rate_driver_data[0];
836 		if (fi->keyix == keyix)
837 			return true;
838 	}
839 
840 	return false;
841 }
842 
843 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
844 {
845 	struct ath_hw *ah = sc->sc_ah;
846 	int i;
847 	struct ath_txq *txq;
848 	bool key_in_use = false;
849 
850 	for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
851 		if (!ATH_TXQ_SETUP(sc, i))
852 			continue;
853 		txq = &sc->tx.txq[i];
854 		if (!txq->axq_depth)
855 			continue;
856 		if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
857 			continue;
858 
859 		ath_txq_lock(sc, txq);
860 		key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
861 		if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
862 			int idx = txq->txq_tailidx;
863 
864 			while (!key_in_use &&
865 			       !list_empty(&txq->txq_fifo[idx])) {
866 				key_in_use = ath9k_txq_list_has_key(
867 					&txq->txq_fifo[idx], keyix);
868 				INCR(idx, ATH_TXFIFO_DEPTH);
869 			}
870 		}
871 		ath_txq_unlock(sc, txq);
872 	}
873 
874 	return key_in_use;
875 }
876 
877 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
878 {
879 	struct ath_hw *ah = sc->sc_ah;
880 	struct ath_common *common = ath9k_hw_common(ah);
881 
882 	if (!test_bit(keyix, ah->pending_del_keymap) ||
883 	    ath9k_txq_has_key(sc, keyix))
884 		return;
885 
886 	/* No more TXQ frames point to this key cache entry, so delete it. */
887 	clear_bit(keyix, ah->pending_del_keymap);
888 	ath_key_delete(common, keyix);
889 }
890 
891 static void ath9k_stop(struct ieee80211_hw *hw)
892 {
893 	struct ath_softc *sc = hw->priv;
894 	struct ath_hw *ah = sc->sc_ah;
895 	struct ath_common *common = ath9k_hw_common(ah);
896 	bool prev_idle;
897 	int i;
898 
899 	ath9k_deinit_channel_context(sc);
900 
901 	mutex_lock(&sc->mutex);
902 
903 	ath9k_rng_stop(sc);
904 
905 	ath_cancel_work(sc);
906 
907 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
908 		ath_dbg(common, ANY, "Device not present\n");
909 		mutex_unlock(&sc->mutex);
910 		return;
911 	}
912 
913 	/* Ensure HW is awake when we try to shut it down. */
914 	ath9k_ps_wakeup(sc);
915 
916 	spin_lock_bh(&sc->sc_pcu_lock);
917 
918 	/* prevent tasklets to enable interrupts once we disable them */
919 	ah->imask &= ~ATH9K_INT_GLOBAL;
920 
921 	/* make sure h/w will not generate any interrupt
922 	 * before setting the invalid flag. */
923 	ath9k_hw_disable_interrupts(ah);
924 
925 	spin_unlock_bh(&sc->sc_pcu_lock);
926 
927 	/* we can now sync irq and kill any running tasklets, since we already
928 	 * disabled interrupts and not holding a spin lock */
929 	synchronize_irq(sc->irq);
930 	tasklet_kill(&sc->intr_tq);
931 	tasklet_kill(&sc->bcon_tasklet);
932 
933 	prev_idle = sc->ps_idle;
934 	sc->ps_idle = true;
935 
936 	spin_lock_bh(&sc->sc_pcu_lock);
937 
938 	if (ah->led_pin >= 0) {
939 		ath9k_hw_set_gpio(ah, ah->led_pin,
940 				  (ah->config.led_active_high) ? 0 : 1);
941 		ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
942 	}
943 
944 	ath_prepare_reset(sc);
945 
946 	if (sc->rx.frag) {
947 		dev_kfree_skb_any(sc->rx.frag);
948 		sc->rx.frag = NULL;
949 	}
950 
951 	if (!ah->curchan)
952 		ah->curchan = ath9k_cmn_get_channel(hw, ah,
953 						    &sc->cur_chan->chandef);
954 
955 	ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
956 
957 	set_bit(ATH_OP_INVALID, &common->op_flags);
958 
959 	ath9k_hw_phy_disable(ah);
960 
961 	ath9k_hw_configpcipowersave(ah, true);
962 
963 	spin_unlock_bh(&sc->sc_pcu_lock);
964 
965 	for (i = 0; i < ATH_KEYMAX; i++)
966 		ath9k_pending_key_del(sc, i);
967 
968 	/* Clear key cache entries explicitly to get rid of any potentially
969 	 * remaining keys.
970 	 */
971 	ath9k_cmn_init_crypto(sc->sc_ah);
972 
973 	ath9k_ps_restore(sc);
974 
975 	sc->ps_idle = prev_idle;
976 
977 	mutex_unlock(&sc->mutex);
978 
979 	ath_dbg(common, CONFIG, "Driver halt\n");
980 }
981 
982 static bool ath9k_uses_beacons(int type)
983 {
984 	switch (type) {
985 	case NL80211_IFTYPE_AP:
986 	case NL80211_IFTYPE_ADHOC:
987 	case NL80211_IFTYPE_MESH_POINT:
988 		return true;
989 	default:
990 		return false;
991 	}
992 }
993 
994 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
995 				      struct ieee80211_vif *vif)
996 {
997 	/* Use the first (configured) interface, but prefering AP interfaces. */
998 	if (!iter_data->primary_beacon_vif) {
999 		iter_data->primary_beacon_vif = vif;
1000 	} else {
1001 		if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1002 		    vif->type == NL80211_IFTYPE_AP)
1003 			iter_data->primary_beacon_vif = vif;
1004 	}
1005 
1006 	iter_data->beacons = true;
1007 	iter_data->nbcnvifs += 1;
1008 }
1009 
1010 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1011 			   u8 *mac, struct ieee80211_vif *vif)
1012 {
1013 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1014 	int i;
1015 
1016 	if (iter_data->has_hw_macaddr) {
1017 		for (i = 0; i < ETH_ALEN; i++)
1018 			iter_data->mask[i] &=
1019 				~(iter_data->hw_macaddr[i] ^ mac[i]);
1020 	} else {
1021 		memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1022 		iter_data->has_hw_macaddr = true;
1023 	}
1024 
1025 	if (!vif->bss_conf.use_short_slot)
1026 		iter_data->slottime = 20;
1027 
1028 	switch (vif->type) {
1029 	case NL80211_IFTYPE_AP:
1030 		iter_data->naps++;
1031 		if (vif->bss_conf.enable_beacon)
1032 			ath9k_vif_iter_set_beacon(iter_data, vif);
1033 		break;
1034 	case NL80211_IFTYPE_STATION:
1035 		iter_data->nstations++;
1036 		if (avp->assoc && !iter_data->primary_sta)
1037 			iter_data->primary_sta = vif;
1038 		break;
1039 	case NL80211_IFTYPE_OCB:
1040 		iter_data->nocbs++;
1041 		break;
1042 	case NL80211_IFTYPE_ADHOC:
1043 		iter_data->nadhocs++;
1044 		if (vif->bss_conf.enable_beacon)
1045 			ath9k_vif_iter_set_beacon(iter_data, vif);
1046 		break;
1047 	case NL80211_IFTYPE_MESH_POINT:
1048 		iter_data->nmeshes++;
1049 		if (vif->bss_conf.enable_beacon)
1050 			ath9k_vif_iter_set_beacon(iter_data, vif);
1051 		break;
1052 	default:
1053 		break;
1054 	}
1055 }
1056 
1057 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1058 				    struct ath_chanctx *ctx,
1059 				    struct ath9k_vif_iter_data *iter_data)
1060 {
1061 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1062 	struct ath_vif *avp;
1063 	int i;
1064 
1065 	if (!ath9k_is_chanctx_enabled())
1066 		return;
1067 
1068 	list_for_each_entry(avp, &ctx->vifs, list) {
1069 		if (ctx->nvifs_assigned != 1)
1070 			continue;
1071 
1072 		if (!iter_data->has_hw_macaddr)
1073 			continue;
1074 
1075 		ether_addr_copy(common->curbssid, avp->bssid);
1076 
1077 		/* perm_addr will be used as the p2p device address. */
1078 		for (i = 0; i < ETH_ALEN; i++)
1079 			iter_data->mask[i] &=
1080 				~(iter_data->hw_macaddr[i] ^
1081 				  sc->hw->wiphy->perm_addr[i]);
1082 	}
1083 }
1084 
1085 /* Called with sc->mutex held. */
1086 void ath9k_calculate_iter_data(struct ath_softc *sc,
1087 			       struct ath_chanctx *ctx,
1088 			       struct ath9k_vif_iter_data *iter_data)
1089 {
1090 	struct ath_vif *avp;
1091 
1092 	/*
1093 	 * The hardware will use primary station addr together with the
1094 	 * BSSID mask when matching addresses.
1095 	 */
1096 	memset(iter_data, 0, sizeof(*iter_data));
1097 	eth_broadcast_addr(iter_data->mask);
1098 	iter_data->slottime = 9;
1099 
1100 	list_for_each_entry(avp, &ctx->vifs, list)
1101 		ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1102 
1103 	ath9k_update_bssid_mask(sc, ctx, iter_data);
1104 }
1105 
1106 static void ath9k_set_assoc_state(struct ath_softc *sc,
1107 				  struct ieee80211_vif *vif, bool changed)
1108 {
1109 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1110 	struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1111 	unsigned long flags;
1112 
1113 	set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1114 
1115 	ether_addr_copy(common->curbssid, avp->bssid);
1116 	common->curaid = avp->aid;
1117 	ath9k_hw_write_associd(sc->sc_ah);
1118 
1119 	if (changed) {
1120 		common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1121 		sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1122 
1123 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
1124 		sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1125 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1126 	}
1127 
1128 	if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1129 		ath9k_mci_update_wlan_channels(sc, false);
1130 
1131 	ath_dbg(common, CONFIG,
1132 		"Primary Station interface: %pM, BSSID: %pM\n",
1133 		vif->addr, common->curbssid);
1134 }
1135 
1136 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1137 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1138 {
1139 	struct ath_hw *ah = sc->sc_ah;
1140 	struct ath_common *common = ath9k_hw_common(ah);
1141 	struct ieee80211_vif *vif = NULL;
1142 
1143 	ath9k_ps_wakeup(sc);
1144 
1145 	if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1146 		vif = sc->offchannel.scan_vif;
1147 	else
1148 		vif = sc->offchannel.roc_vif;
1149 
1150 	if (WARN_ON(!vif))
1151 		goto exit;
1152 
1153 	eth_zero_addr(common->curbssid);
1154 	eth_broadcast_addr(common->bssidmask);
1155 	memcpy(common->macaddr, vif->addr, ETH_ALEN);
1156 	common->curaid = 0;
1157 	ah->opmode = vif->type;
1158 	ah->imask &= ~ATH9K_INT_SWBA;
1159 	ah->imask &= ~ATH9K_INT_TSFOOR;
1160 	ah->slottime = 9;
1161 
1162 	ath_hw_setbssidmask(common);
1163 	ath9k_hw_setopmode(ah);
1164 	ath9k_hw_write_associd(sc->sc_ah);
1165 	ath9k_hw_set_interrupts(ah);
1166 	ath9k_hw_init_global_settings(ah);
1167 
1168 exit:
1169 	ath9k_ps_restore(sc);
1170 }
1171 #endif
1172 
1173 /* Called with sc->mutex held. */
1174 void ath9k_calculate_summary_state(struct ath_softc *sc,
1175 				   struct ath_chanctx *ctx)
1176 {
1177 	struct ath_hw *ah = sc->sc_ah;
1178 	struct ath_common *common = ath9k_hw_common(ah);
1179 	struct ath9k_vif_iter_data iter_data;
1180 
1181 	ath_chanctx_check_active(sc, ctx);
1182 
1183 	if (ctx != sc->cur_chan)
1184 		return;
1185 
1186 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1187 	if (ctx == &sc->offchannel.chan)
1188 		return ath9k_set_offchannel_state(sc);
1189 #endif
1190 
1191 	ath9k_ps_wakeup(sc);
1192 	ath9k_calculate_iter_data(sc, ctx, &iter_data);
1193 
1194 	if (iter_data.has_hw_macaddr)
1195 		memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1196 
1197 	memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1198 	ath_hw_setbssidmask(common);
1199 
1200 	if (iter_data.naps > 0) {
1201 		ath9k_hw_set_tsfadjust(ah, true);
1202 		ah->opmode = NL80211_IFTYPE_AP;
1203 	} else {
1204 		ath9k_hw_set_tsfadjust(ah, false);
1205 		if (iter_data.beacons)
1206 			ath9k_beacon_ensure_primary_slot(sc);
1207 
1208 		if (iter_data.nmeshes)
1209 			ah->opmode = NL80211_IFTYPE_MESH_POINT;
1210 		else if (iter_data.nocbs)
1211 			ah->opmode = NL80211_IFTYPE_OCB;
1212 		else if (iter_data.nadhocs)
1213 			ah->opmode = NL80211_IFTYPE_ADHOC;
1214 		else
1215 			ah->opmode = NL80211_IFTYPE_STATION;
1216 	}
1217 
1218 	ath9k_hw_setopmode(ah);
1219 
1220 	ctx->switch_after_beacon = false;
1221 	if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1222 		ah->imask |= ATH9K_INT_TSFOOR;
1223 	else {
1224 		ah->imask &= ~ATH9K_INT_TSFOOR;
1225 		if (iter_data.naps == 1 && iter_data.beacons)
1226 			ctx->switch_after_beacon = true;
1227 	}
1228 
1229 	if (ah->opmode == NL80211_IFTYPE_STATION) {
1230 		bool changed = (iter_data.primary_sta != ctx->primary_sta);
1231 
1232 		if (iter_data.primary_sta) {
1233 			iter_data.primary_beacon_vif = iter_data.primary_sta;
1234 			iter_data.beacons = true;
1235 			ath9k_set_assoc_state(sc, iter_data.primary_sta,
1236 					      changed);
1237 			ctx->primary_sta = iter_data.primary_sta;
1238 		} else {
1239 			ctx->primary_sta = NULL;
1240 			eth_zero_addr(common->curbssid);
1241 			common->curaid = 0;
1242 			ath9k_hw_write_associd(sc->sc_ah);
1243 			if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1244 				ath9k_mci_update_wlan_channels(sc, true);
1245 		}
1246 	}
1247 	sc->nbcnvifs = iter_data.nbcnvifs;
1248 	ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1249 			    iter_data.beacons);
1250 	ath9k_hw_set_interrupts(ah);
1251 
1252 	if (ah->slottime != iter_data.slottime) {
1253 		ah->slottime = iter_data.slottime;
1254 		ath9k_hw_init_global_settings(ah);
1255 	}
1256 
1257 	if (iter_data.primary_sta)
1258 		set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1259 	else
1260 		clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1261 
1262 	ath_dbg(common, CONFIG,
1263 		"macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1264 		common->macaddr, common->curbssid, common->bssidmask);
1265 
1266 	ath9k_ps_restore(sc);
1267 }
1268 
1269 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1270 {
1271 	int *power = data;
1272 
1273 	if (vif->bss_conf.txpower == INT_MIN)
1274 		return;
1275 
1276 	if (*power < vif->bss_conf.txpower)
1277 		*power = vif->bss_conf.txpower;
1278 }
1279 
1280 /* Called with sc->mutex held. */
1281 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1282 {
1283 	int power;
1284 	struct ath_hw *ah = sc->sc_ah;
1285 	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1286 
1287 	ath9k_ps_wakeup(sc);
1288 	if (ah->tpc_enabled) {
1289 		power = (vif) ? vif->bss_conf.txpower : -1;
1290 		ieee80211_iterate_active_interfaces_atomic(
1291 				sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1292 				ath9k_tpc_vif_iter, &power);
1293 		if (power == -1)
1294 			power = sc->hw->conf.power_level;
1295 	} else {
1296 		power = sc->hw->conf.power_level;
1297 	}
1298 	sc->cur_chan->txpower = 2 * power;
1299 	ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1300 	sc->cur_chan->cur_txpower = reg->max_power_level;
1301 	ath9k_ps_restore(sc);
1302 }
1303 
1304 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1305 				   struct ieee80211_vif *vif)
1306 {
1307 	int i;
1308 
1309 	if (!ath9k_is_chanctx_enabled())
1310 		return;
1311 
1312 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
1313 		vif->hw_queue[i] = i;
1314 
1315 	if (vif->type == NL80211_IFTYPE_AP ||
1316 	    vif->type == NL80211_IFTYPE_MESH_POINT)
1317 		vif->cab_queue = hw->queues - 2;
1318 	else
1319 		vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1320 }
1321 
1322 static int ath9k_add_interface(struct ieee80211_hw *hw,
1323 			       struct ieee80211_vif *vif)
1324 {
1325 	struct ath_softc *sc = hw->priv;
1326 	struct ath_hw *ah = sc->sc_ah;
1327 	struct ath_common *common = ath9k_hw_common(ah);
1328 	struct ath_vif *avp = (void *)vif->drv_priv;
1329 	struct ath_node *an = &avp->mcast_node;
1330 
1331 	mutex_lock(&sc->mutex);
1332 	if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1333 		if (sc->cur_chan->nvifs >= 1) {
1334 			mutex_unlock(&sc->mutex);
1335 			return -EOPNOTSUPP;
1336 		}
1337 		sc->tx99_vif = vif;
1338 	}
1339 
1340 	ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1341 	sc->cur_chan->nvifs++;
1342 
1343 	if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1344 		vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1345 
1346 	if (ath9k_uses_beacons(vif->type))
1347 		ath9k_beacon_assign_slot(sc, vif);
1348 
1349 	avp->vif = vif;
1350 	if (!ath9k_is_chanctx_enabled()) {
1351 		avp->chanctx = sc->cur_chan;
1352 		list_add_tail(&avp->list, &avp->chanctx->vifs);
1353 	}
1354 
1355 	ath9k_calculate_summary_state(sc, avp->chanctx);
1356 
1357 	ath9k_assign_hw_queues(hw, vif);
1358 
1359 	ath9k_set_txpower(sc, vif);
1360 
1361 	an->sc = sc;
1362 	an->sta = NULL;
1363 	an->vif = vif;
1364 	an->no_ps_filter = true;
1365 	ath_tx_node_init(sc, an);
1366 
1367 	mutex_unlock(&sc->mutex);
1368 	return 0;
1369 }
1370 
1371 static int ath9k_change_interface(struct ieee80211_hw *hw,
1372 				  struct ieee80211_vif *vif,
1373 				  enum nl80211_iftype new_type,
1374 				  bool p2p)
1375 {
1376 	struct ath_softc *sc = hw->priv;
1377 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1378 	struct ath_vif *avp = (void *)vif->drv_priv;
1379 
1380 	mutex_lock(&sc->mutex);
1381 
1382 	if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1383 		mutex_unlock(&sc->mutex);
1384 		return -EOPNOTSUPP;
1385 	}
1386 
1387 	ath_dbg(common, CONFIG, "Change Interface\n");
1388 
1389 	if (ath9k_uses_beacons(vif->type))
1390 		ath9k_beacon_remove_slot(sc, vif);
1391 
1392 	vif->type = new_type;
1393 	vif->p2p = p2p;
1394 
1395 	if (ath9k_uses_beacons(vif->type))
1396 		ath9k_beacon_assign_slot(sc, vif);
1397 
1398 	ath9k_assign_hw_queues(hw, vif);
1399 	ath9k_calculate_summary_state(sc, avp->chanctx);
1400 
1401 	ath9k_set_txpower(sc, vif);
1402 
1403 	mutex_unlock(&sc->mutex);
1404 	return 0;
1405 }
1406 
1407 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1408 				   struct ieee80211_vif *vif)
1409 {
1410 	struct ath_softc *sc = hw->priv;
1411 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1412 	struct ath_vif *avp = (void *)vif->drv_priv;
1413 
1414 	ath_dbg(common, CONFIG, "Detach Interface\n");
1415 
1416 	mutex_lock(&sc->mutex);
1417 
1418 	ath9k_p2p_remove_vif(sc, vif);
1419 
1420 	sc->cur_chan->nvifs--;
1421 	sc->tx99_vif = NULL;
1422 	if (!ath9k_is_chanctx_enabled())
1423 		list_del(&avp->list);
1424 
1425 	if (ath9k_uses_beacons(vif->type))
1426 		ath9k_beacon_remove_slot(sc, vif);
1427 
1428 	ath_tx_node_cleanup(sc, &avp->mcast_node);
1429 
1430 	ath9k_calculate_summary_state(sc, avp->chanctx);
1431 
1432 	ath9k_set_txpower(sc, NULL);
1433 
1434 	mutex_unlock(&sc->mutex);
1435 }
1436 
1437 static void ath9k_enable_ps(struct ath_softc *sc)
1438 {
1439 	struct ath_hw *ah = sc->sc_ah;
1440 	struct ath_common *common = ath9k_hw_common(ah);
1441 
1442 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
1443 		return;
1444 
1445 	sc->ps_enabled = true;
1446 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1447 		if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1448 			ah->imask |= ATH9K_INT_TIM_TIMER;
1449 			ath9k_hw_set_interrupts(ah);
1450 		}
1451 		ath9k_hw_setrxabort(ah, 1);
1452 	}
1453 	ath_dbg(common, PS, "PowerSave enabled\n");
1454 }
1455 
1456 static void ath9k_disable_ps(struct ath_softc *sc)
1457 {
1458 	struct ath_hw *ah = sc->sc_ah;
1459 	struct ath_common *common = ath9k_hw_common(ah);
1460 
1461 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
1462 		return;
1463 
1464 	sc->ps_enabled = false;
1465 	ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1466 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1467 		ath9k_hw_setrxabort(ah, 0);
1468 		sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1469 				  PS_WAIT_FOR_CAB |
1470 				  PS_WAIT_FOR_PSPOLL_DATA |
1471 				  PS_WAIT_FOR_TX_ACK);
1472 		if (ah->imask & ATH9K_INT_TIM_TIMER) {
1473 			ah->imask &= ~ATH9K_INT_TIM_TIMER;
1474 			ath9k_hw_set_interrupts(ah);
1475 		}
1476 	}
1477 	ath_dbg(common, PS, "PowerSave disabled\n");
1478 }
1479 
1480 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1481 {
1482 	struct ath_softc *sc = hw->priv;
1483 	struct ath_hw *ah = sc->sc_ah;
1484 	struct ath_common *common = ath9k_hw_common(ah);
1485 	struct ieee80211_conf *conf = &hw->conf;
1486 	struct ath_chanctx *ctx = sc->cur_chan;
1487 
1488 	ath9k_ps_wakeup(sc);
1489 	mutex_lock(&sc->mutex);
1490 
1491 	if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1492 		sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1493 		if (sc->ps_idle) {
1494 			ath_cancel_work(sc);
1495 			ath9k_stop_btcoex(sc);
1496 		} else {
1497 			ath9k_start_btcoex(sc);
1498 			/*
1499 			 * The chip needs a reset to properly wake up from
1500 			 * full sleep
1501 			 */
1502 			ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1503 		}
1504 	}
1505 
1506 	/*
1507 	 * We just prepare to enable PS. We have to wait until our AP has
1508 	 * ACK'd our null data frame to disable RX otherwise we'll ignore
1509 	 * those ACKs and end up retransmitting the same null data frames.
1510 	 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1511 	 */
1512 	if (changed & IEEE80211_CONF_CHANGE_PS) {
1513 		unsigned long flags;
1514 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
1515 		if (conf->flags & IEEE80211_CONF_PS)
1516 			ath9k_enable_ps(sc);
1517 		else
1518 			ath9k_disable_ps(sc);
1519 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1520 	}
1521 
1522 	if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1523 		if (conf->flags & IEEE80211_CONF_MONITOR) {
1524 			ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1525 			sc->sc_ah->is_monitoring = true;
1526 		} else {
1527 			ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1528 			sc->sc_ah->is_monitoring = false;
1529 		}
1530 	}
1531 
1532 	if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1533 		ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1534 		ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1535 	}
1536 
1537 	if (changed & IEEE80211_CONF_CHANGE_POWER)
1538 		ath9k_set_txpower(sc, NULL);
1539 
1540 	mutex_unlock(&sc->mutex);
1541 	ath9k_ps_restore(sc);
1542 
1543 	return 0;
1544 }
1545 
1546 #define SUPPORTED_FILTERS			\
1547 	(FIF_ALLMULTI |				\
1548 	FIF_CONTROL |				\
1549 	FIF_PSPOLL |				\
1550 	FIF_OTHER_BSS |				\
1551 	FIF_BCN_PRBRESP_PROMISC |		\
1552 	FIF_PROBE_REQ |				\
1553 	FIF_MCAST_ACTION |			\
1554 	FIF_FCSFAIL)
1555 
1556 /* FIXME: sc->sc_full_reset ? */
1557 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1558 				   unsigned int changed_flags,
1559 				   unsigned int *total_flags,
1560 				   u64 multicast)
1561 {
1562 	struct ath_softc *sc = hw->priv;
1563 	struct ath_chanctx *ctx;
1564 	u32 rfilt;
1565 
1566 	changed_flags &= SUPPORTED_FILTERS;
1567 	*total_flags &= SUPPORTED_FILTERS;
1568 
1569 	spin_lock_bh(&sc->chan_lock);
1570 	ath_for_each_chanctx(sc, ctx)
1571 		ctx->rxfilter = *total_flags;
1572 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1573 	sc->offchannel.chan.rxfilter = *total_flags;
1574 #endif
1575 	spin_unlock_bh(&sc->chan_lock);
1576 
1577 	ath9k_ps_wakeup(sc);
1578 	rfilt = ath_calcrxfilter(sc);
1579 	ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1580 	ath9k_ps_restore(sc);
1581 
1582 	ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1583 		rfilt);
1584 }
1585 
1586 static int ath9k_sta_add(struct ieee80211_hw *hw,
1587 			 struct ieee80211_vif *vif,
1588 			 struct ieee80211_sta *sta)
1589 {
1590 	struct ath_softc *sc = hw->priv;
1591 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1592 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1593 	struct ieee80211_key_conf ps_key = { };
1594 	int key;
1595 
1596 	ath_node_attach(sc, sta, vif);
1597 
1598 	if (vif->type != NL80211_IFTYPE_AP &&
1599 	    vif->type != NL80211_IFTYPE_AP_VLAN)
1600 		return 0;
1601 
1602 	key = ath_key_config(common, vif, sta, &ps_key);
1603 	if (key > 0) {
1604 		an->ps_key = key;
1605 		an->key_idx[0] = key;
1606 	}
1607 
1608 	return 0;
1609 }
1610 
1611 static void ath9k_del_ps_key(struct ath_softc *sc,
1612 			     struct ieee80211_vif *vif,
1613 			     struct ieee80211_sta *sta)
1614 {
1615 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1616 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1617 
1618 	if (!an->ps_key)
1619 	    return;
1620 
1621 	ath_key_delete(common, an->ps_key);
1622 	an->ps_key = 0;
1623 	an->key_idx[0] = 0;
1624 }
1625 
1626 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1627 			    struct ieee80211_vif *vif,
1628 			    struct ieee80211_sta *sta)
1629 {
1630 	struct ath_softc *sc = hw->priv;
1631 
1632 	ath9k_del_ps_key(sc, vif, sta);
1633 	ath_node_detach(sc, sta);
1634 
1635 	return 0;
1636 }
1637 
1638 static int ath9k_sta_state(struct ieee80211_hw *hw,
1639 			   struct ieee80211_vif *vif,
1640 			   struct ieee80211_sta *sta,
1641 			   enum ieee80211_sta_state old_state,
1642 			   enum ieee80211_sta_state new_state)
1643 {
1644 	struct ath_softc *sc = hw->priv;
1645 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1646 	int ret = 0;
1647 
1648 	if (old_state == IEEE80211_STA_NOTEXIST &&
1649 	    new_state == IEEE80211_STA_NONE) {
1650 		ret = ath9k_sta_add(hw, vif, sta);
1651 		ath_dbg(common, CONFIG,
1652 			"Add station: %pM\n", sta->addr);
1653 	} else if (old_state == IEEE80211_STA_NONE &&
1654 		   new_state == IEEE80211_STA_NOTEXIST) {
1655 		ret = ath9k_sta_remove(hw, vif, sta);
1656 		ath_dbg(common, CONFIG,
1657 			"Remove station: %pM\n", sta->addr);
1658 	}
1659 
1660 	if (ath9k_is_chanctx_enabled()) {
1661 		if (vif->type == NL80211_IFTYPE_STATION) {
1662 			if (old_state == IEEE80211_STA_ASSOC &&
1663 			    new_state == IEEE80211_STA_AUTHORIZED)
1664 				ath_chanctx_event(sc, vif,
1665 						  ATH_CHANCTX_EVENT_AUTHORIZED);
1666 		}
1667 	}
1668 
1669 	return ret;
1670 }
1671 
1672 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1673 				    struct ath_node *an,
1674 				    bool set)
1675 {
1676 	int i;
1677 
1678 	for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1679 		if (!an->key_idx[i])
1680 			continue;
1681 		ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1682 	}
1683 }
1684 
1685 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1686 			 struct ieee80211_vif *vif,
1687 			 enum sta_notify_cmd cmd,
1688 			 struct ieee80211_sta *sta)
1689 {
1690 	struct ath_softc *sc = hw->priv;
1691 	struct ath_node *an = (struct ath_node *) sta->drv_priv;
1692 
1693 	switch (cmd) {
1694 	case STA_NOTIFY_SLEEP:
1695 		an->sleeping = true;
1696 		ath_tx_aggr_sleep(sta, sc, an);
1697 		ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1698 		break;
1699 	case STA_NOTIFY_AWAKE:
1700 		ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1701 		an->sleeping = false;
1702 		ath_tx_aggr_wakeup(sc, an);
1703 		break;
1704 	}
1705 }
1706 
1707 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1708 			 struct ieee80211_vif *vif, u16 queue,
1709 			 const struct ieee80211_tx_queue_params *params)
1710 {
1711 	struct ath_softc *sc = hw->priv;
1712 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1713 	struct ath_txq *txq;
1714 	struct ath9k_tx_queue_info qi;
1715 	int ret = 0;
1716 
1717 	if (queue >= IEEE80211_NUM_ACS)
1718 		return 0;
1719 
1720 	txq = sc->tx.txq_map[queue];
1721 
1722 	ath9k_ps_wakeup(sc);
1723 	mutex_lock(&sc->mutex);
1724 
1725 	memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1726 
1727 	qi.tqi_aifs = params->aifs;
1728 	qi.tqi_cwmin = params->cw_min;
1729 	qi.tqi_cwmax = params->cw_max;
1730 	qi.tqi_burstTime = params->txop * 32;
1731 
1732 	ath_dbg(common, CONFIG,
1733 		"Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1734 		queue, txq->axq_qnum, params->aifs, params->cw_min,
1735 		params->cw_max, params->txop);
1736 
1737 	ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1738 	ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1739 	if (ret)
1740 		ath_err(common, "TXQ Update failed\n");
1741 
1742 	mutex_unlock(&sc->mutex);
1743 	ath9k_ps_restore(sc);
1744 
1745 	return ret;
1746 }
1747 
1748 static int ath9k_set_key(struct ieee80211_hw *hw,
1749 			 enum set_key_cmd cmd,
1750 			 struct ieee80211_vif *vif,
1751 			 struct ieee80211_sta *sta,
1752 			 struct ieee80211_key_conf *key)
1753 {
1754 	struct ath_softc *sc = hw->priv;
1755 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1756 	struct ath_node *an = NULL;
1757 	int ret = 0, i;
1758 
1759 	if (ath9k_modparam_nohwcrypt)
1760 		return -ENOSPC;
1761 
1762 	if ((vif->type == NL80211_IFTYPE_ADHOC ||
1763 	     vif->type == NL80211_IFTYPE_MESH_POINT) &&
1764 	    (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1765 	     key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1766 	    !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1767 		/*
1768 		 * For now, disable hw crypto for the RSN IBSS group keys. This
1769 		 * could be optimized in the future to use a modified key cache
1770 		 * design to support per-STA RX GTK, but until that gets
1771 		 * implemented, use of software crypto for group addressed
1772 		 * frames is a acceptable to allow RSN IBSS to be used.
1773 		 */
1774 		return -EOPNOTSUPP;
1775 	}
1776 
1777 	/* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1778 	 * make sure these are not send unencrypted or with a wrong (new) key
1779 	 */
1780 	if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1781 		ieee80211_stop_queues(hw);
1782 		ath9k_flush(hw, vif, 0, true);
1783 		ieee80211_wake_queues(hw);
1784 	}
1785 
1786 	mutex_lock(&sc->mutex);
1787 	ath9k_ps_wakeup(sc);
1788 	ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1789 	if (sta)
1790 		an = (struct ath_node *)sta->drv_priv;
1791 
1792 	/* Delete pending key cache entries if no more frames are pointing to
1793 	 * them in TXQs.
1794 	 */
1795 	for (i = 0; i < ATH_KEYMAX; i++)
1796 		ath9k_pending_key_del(sc, i);
1797 
1798 	switch (cmd) {
1799 	case SET_KEY:
1800 		if (sta)
1801 			ath9k_del_ps_key(sc, vif, sta);
1802 
1803 		key->hw_key_idx = 0;
1804 		ret = ath_key_config(common, vif, sta, key);
1805 		if (ret >= 0) {
1806 			key->hw_key_idx = ret;
1807 			/* push IV and Michael MIC generation to stack */
1808 			key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1809 			if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1810 				key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1811 			if (sc->sc_ah->sw_mgmt_crypto_tx &&
1812 			    key->cipher == WLAN_CIPHER_SUITE_CCMP)
1813 				key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1814 			ret = 0;
1815 		}
1816 		if (an && key->hw_key_idx) {
1817 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1818 				if (an->key_idx[i])
1819 					continue;
1820 				an->key_idx[i] = key->hw_key_idx;
1821 				break;
1822 			}
1823 			WARN_ON(i == ARRAY_SIZE(an->key_idx));
1824 		}
1825 		break;
1826 	case DISABLE_KEY:
1827 		if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1828 			/* Delay key cache entry deletion until there are no
1829 			 * remaining TXQ frames pointing to this entry.
1830 			 */
1831 			set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1832 			ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1833 		} else {
1834 			ath_key_delete(common, key->hw_key_idx);
1835 		}
1836 		if (an) {
1837 			for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1838 				if (an->key_idx[i] != key->hw_key_idx)
1839 					continue;
1840 				an->key_idx[i] = 0;
1841 				break;
1842 			}
1843 		}
1844 		key->hw_key_idx = 0;
1845 		break;
1846 	default:
1847 		ret = -EINVAL;
1848 	}
1849 
1850 	ath9k_ps_restore(sc);
1851 	mutex_unlock(&sc->mutex);
1852 
1853 	return ret;
1854 }
1855 
1856 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1857 				   struct ieee80211_vif *vif,
1858 				   struct ieee80211_bss_conf *bss_conf,
1859 				   u32 changed)
1860 {
1861 #define CHECK_ANI				\
1862 	(BSS_CHANGED_ASSOC |			\
1863 	 BSS_CHANGED_IBSS |			\
1864 	 BSS_CHANGED_BEACON_ENABLED)
1865 
1866 	struct ath_softc *sc = hw->priv;
1867 	struct ath_hw *ah = sc->sc_ah;
1868 	struct ath_common *common = ath9k_hw_common(ah);
1869 	struct ath_vif *avp = (void *)vif->drv_priv;
1870 	int slottime;
1871 
1872 	ath9k_ps_wakeup(sc);
1873 	mutex_lock(&sc->mutex);
1874 
1875 	if (changed & BSS_CHANGED_ASSOC) {
1876 		ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1877 			bss_conf->bssid, bss_conf->assoc);
1878 
1879 		memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1880 		avp->aid = bss_conf->aid;
1881 		avp->assoc = bss_conf->assoc;
1882 
1883 		ath9k_calculate_summary_state(sc, avp->chanctx);
1884 	}
1885 
1886 	if ((changed & BSS_CHANGED_IBSS) ||
1887 	      (changed & BSS_CHANGED_OCB)) {
1888 		memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1889 		common->curaid = bss_conf->aid;
1890 		ath9k_hw_write_associd(sc->sc_ah);
1891 	}
1892 
1893 	if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1894 	    (changed & BSS_CHANGED_BEACON_INT) ||
1895 	    (changed & BSS_CHANGED_BEACON_INFO)) {
1896 		ath9k_calculate_summary_state(sc, avp->chanctx);
1897 	}
1898 
1899 	if ((avp->chanctx == sc->cur_chan) &&
1900 	    (changed & BSS_CHANGED_ERP_SLOT)) {
1901 		if (bss_conf->use_short_slot)
1902 			slottime = 9;
1903 		else
1904 			slottime = 20;
1905 
1906 		if (vif->type == NL80211_IFTYPE_AP) {
1907 			/*
1908 			 * Defer update, so that connected stations can adjust
1909 			 * their settings at the same time.
1910 			 * See beacon.c for more details
1911 			 */
1912 			sc->beacon.slottime = slottime;
1913 			sc->beacon.updateslot = UPDATE;
1914 		} else {
1915 			ah->slottime = slottime;
1916 			ath9k_hw_init_global_settings(ah);
1917 		}
1918 	}
1919 
1920 	if (changed & BSS_CHANGED_P2P_PS)
1921 		ath9k_p2p_bss_info_changed(sc, vif);
1922 
1923 	if (changed & CHECK_ANI)
1924 		ath_check_ani(sc);
1925 
1926 	if (changed & BSS_CHANGED_TXPOWER) {
1927 		ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1928 			vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1929 		ath9k_set_txpower(sc, vif);
1930 	}
1931 
1932 	mutex_unlock(&sc->mutex);
1933 	ath9k_ps_restore(sc);
1934 
1935 #undef CHECK_ANI
1936 }
1937 
1938 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1939 {
1940 	struct ath_softc *sc = hw->priv;
1941 	struct ath_vif *avp = (void *)vif->drv_priv;
1942 	u64 tsf;
1943 
1944 	mutex_lock(&sc->mutex);
1945 	ath9k_ps_wakeup(sc);
1946 	/* Get current TSF either from HW or kernel time. */
1947 	if (sc->cur_chan == avp->chanctx) {
1948 		tsf = ath9k_hw_gettsf64(sc->sc_ah);
1949 	} else {
1950 		tsf = sc->cur_chan->tsf_val +
1951 		      ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1952 	}
1953 	tsf += le64_to_cpu(avp->tsf_adjust);
1954 	ath9k_ps_restore(sc);
1955 	mutex_unlock(&sc->mutex);
1956 
1957 	return tsf;
1958 }
1959 
1960 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1961 			  struct ieee80211_vif *vif,
1962 			  u64 tsf)
1963 {
1964 	struct ath_softc *sc = hw->priv;
1965 	struct ath_vif *avp = (void *)vif->drv_priv;
1966 
1967 	mutex_lock(&sc->mutex);
1968 	ath9k_ps_wakeup(sc);
1969 	tsf -= le64_to_cpu(avp->tsf_adjust);
1970 	ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1971 	if (sc->cur_chan == avp->chanctx)
1972 		ath9k_hw_settsf64(sc->sc_ah, tsf);
1973 	avp->chanctx->tsf_val = tsf;
1974 	ath9k_ps_restore(sc);
1975 	mutex_unlock(&sc->mutex);
1976 }
1977 
1978 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1979 {
1980 	struct ath_softc *sc = hw->priv;
1981 	struct ath_vif *avp = (void *)vif->drv_priv;
1982 
1983 	mutex_lock(&sc->mutex);
1984 
1985 	ath9k_ps_wakeup(sc);
1986 	ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1987 	if (sc->cur_chan == avp->chanctx)
1988 		ath9k_hw_reset_tsf(sc->sc_ah);
1989 	avp->chanctx->tsf_val = 0;
1990 	ath9k_ps_restore(sc);
1991 
1992 	mutex_unlock(&sc->mutex);
1993 }
1994 
1995 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1996 			      struct ieee80211_vif *vif,
1997 			      struct ieee80211_ampdu_params *params)
1998 {
1999 	struct ath_softc *sc = hw->priv;
2000 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2001 	bool flush = false;
2002 	int ret = 0;
2003 	struct ieee80211_sta *sta = params->sta;
2004 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
2005 	enum ieee80211_ampdu_mlme_action action = params->action;
2006 	u16 tid = params->tid;
2007 	u16 *ssn = &params->ssn;
2008 	struct ath_atx_tid *atid;
2009 
2010 	mutex_lock(&sc->mutex);
2011 
2012 	switch (action) {
2013 	case IEEE80211_AMPDU_RX_START:
2014 		break;
2015 	case IEEE80211_AMPDU_RX_STOP:
2016 		break;
2017 	case IEEE80211_AMPDU_TX_START:
2018 		if (ath9k_is_chanctx_enabled()) {
2019 			if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2020 				ret = -EBUSY;
2021 				break;
2022 			}
2023 		}
2024 		ath9k_ps_wakeup(sc);
2025 		ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2026 		if (!ret)
2027 			ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2028 		ath9k_ps_restore(sc);
2029 		break;
2030 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
2031 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2032 		flush = true;
2033 		fallthrough;
2034 	case IEEE80211_AMPDU_TX_STOP_CONT:
2035 		ath9k_ps_wakeup(sc);
2036 		ath_tx_aggr_stop(sc, sta, tid);
2037 		if (!flush)
2038 			ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2039 		ath9k_ps_restore(sc);
2040 		break;
2041 	case IEEE80211_AMPDU_TX_OPERATIONAL:
2042 		atid = ath_node_to_tid(an, tid);
2043 		atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2044 			        sta->ht_cap.ampdu_factor;
2045 		break;
2046 	default:
2047 		ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2048 	}
2049 
2050 	mutex_unlock(&sc->mutex);
2051 
2052 	return ret;
2053 }
2054 
2055 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2056 			     struct survey_info *survey)
2057 {
2058 	struct ath_softc *sc = hw->priv;
2059 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2060 	struct ieee80211_supported_band *sband;
2061 	struct ieee80211_channel *chan;
2062 	unsigned long flags;
2063 	int pos;
2064 
2065 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
2066 		return -EOPNOTSUPP;
2067 
2068 	spin_lock_irqsave(&common->cc_lock, flags);
2069 	if (idx == 0)
2070 		ath_update_survey_stats(sc);
2071 
2072 	sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2073 	if (sband && idx >= sband->n_channels) {
2074 		idx -= sband->n_channels;
2075 		sband = NULL;
2076 	}
2077 
2078 	if (!sband)
2079 		sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2080 
2081 	if (!sband || idx >= sband->n_channels) {
2082 		spin_unlock_irqrestore(&common->cc_lock, flags);
2083 		return -ENOENT;
2084 	}
2085 
2086 	chan = &sband->channels[idx];
2087 	pos = chan->hw_value;
2088 	memcpy(survey, &sc->survey[pos], sizeof(*survey));
2089 	survey->channel = chan;
2090 	spin_unlock_irqrestore(&common->cc_lock, flags);
2091 
2092 	return 0;
2093 }
2094 
2095 static void ath9k_enable_dynack(struct ath_softc *sc)
2096 {
2097 #ifdef CONFIG_ATH9K_DYNACK
2098 	u32 rfilt;
2099 	struct ath_hw *ah = sc->sc_ah;
2100 
2101 	ath_dynack_reset(ah);
2102 
2103 	ah->dynack.enabled = true;
2104 	rfilt = ath_calcrxfilter(sc);
2105 	ath9k_hw_setrxfilter(ah, rfilt);
2106 #endif
2107 }
2108 
2109 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2110 				     s16 coverage_class)
2111 {
2112 	struct ath_softc *sc = hw->priv;
2113 	struct ath_hw *ah = sc->sc_ah;
2114 
2115 	if (IS_ENABLED(CONFIG_ATH9K_TX99))
2116 		return;
2117 
2118 	mutex_lock(&sc->mutex);
2119 
2120 	if (coverage_class >= 0) {
2121 		ah->coverage_class = coverage_class;
2122 		if (ah->dynack.enabled) {
2123 			u32 rfilt;
2124 
2125 			ah->dynack.enabled = false;
2126 			rfilt = ath_calcrxfilter(sc);
2127 			ath9k_hw_setrxfilter(ah, rfilt);
2128 		}
2129 		ath9k_ps_wakeup(sc);
2130 		ath9k_hw_init_global_settings(ah);
2131 		ath9k_ps_restore(sc);
2132 	} else if (!ah->dynack.enabled) {
2133 		ath9k_enable_dynack(sc);
2134 	}
2135 
2136 	mutex_unlock(&sc->mutex);
2137 }
2138 
2139 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2140 				 bool sw_pending)
2141 {
2142 	int i, npend = 0;
2143 
2144 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2145 		if (!ATH_TXQ_SETUP(sc, i))
2146 			continue;
2147 
2148 		npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2149 						 sw_pending);
2150 		if (npend)
2151 			break;
2152 	}
2153 
2154 	return !!npend;
2155 }
2156 
2157 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2158 			u32 queues, bool drop)
2159 {
2160 	struct ath_softc *sc = hw->priv;
2161 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2162 
2163 	if (ath9k_is_chanctx_enabled()) {
2164 		if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2165 			goto flush;
2166 
2167 		/*
2168 		 * If MCC is active, extend the flush timeout
2169 		 * and wait for the HW/SW queues to become
2170 		 * empty. This needs to be done outside the
2171 		 * sc->mutex lock to allow the channel scheduler
2172 		 * to switch channel contexts.
2173 		 *
2174 		 * The vif queues have been stopped in mac80211,
2175 		 * so there won't be any incoming frames.
2176 		 */
2177 		__ath9k_flush(hw, queues, drop, true, true);
2178 		return;
2179 	}
2180 flush:
2181 	mutex_lock(&sc->mutex);
2182 	__ath9k_flush(hw, queues, drop, true, false);
2183 	mutex_unlock(&sc->mutex);
2184 }
2185 
2186 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2187 		   bool sw_pending, bool timeout_override)
2188 {
2189 	struct ath_softc *sc = hw->priv;
2190 	struct ath_hw *ah = sc->sc_ah;
2191 	struct ath_common *common = ath9k_hw_common(ah);
2192 	int timeout;
2193 	bool drain_txq;
2194 
2195 	cancel_delayed_work_sync(&sc->hw_check_work);
2196 
2197 	if (ah->ah_flags & AH_UNPLUGGED) {
2198 		ath_dbg(common, ANY, "Device has been unplugged!\n");
2199 		return;
2200 	}
2201 
2202 	if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2203 		ath_dbg(common, ANY, "Device not present\n");
2204 		return;
2205 	}
2206 
2207 	spin_lock_bh(&sc->chan_lock);
2208 	if (timeout_override)
2209 		timeout = HZ / 5;
2210 	else
2211 		timeout = sc->cur_chan->flush_timeout;
2212 	spin_unlock_bh(&sc->chan_lock);
2213 
2214 	ath_dbg(common, CHAN_CTX,
2215 		"Flush timeout: %d\n", jiffies_to_msecs(timeout));
2216 
2217 	if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2218 			       timeout) > 0)
2219 		drop = false;
2220 
2221 	if (drop) {
2222 		ath9k_ps_wakeup(sc);
2223 		spin_lock_bh(&sc->sc_pcu_lock);
2224 		drain_txq = ath_drain_all_txq(sc);
2225 		spin_unlock_bh(&sc->sc_pcu_lock);
2226 
2227 		if (!drain_txq)
2228 			ath_reset(sc, NULL);
2229 
2230 		ath9k_ps_restore(sc);
2231 	}
2232 
2233 	ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2234 				     ATH_HW_CHECK_POLL_INT);
2235 }
2236 
2237 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2238 {
2239 	struct ath_softc *sc = hw->priv;
2240 
2241 	return ath9k_has_tx_pending(sc, true);
2242 }
2243 
2244 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2245 {
2246 	struct ath_softc *sc = hw->priv;
2247 	struct ath_hw *ah = sc->sc_ah;
2248 	struct ieee80211_vif *vif;
2249 	struct ath_vif *avp;
2250 	struct ath_buf *bf;
2251 	struct ath_tx_status ts;
2252 	bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2253 	int status;
2254 
2255 	vif = sc->beacon.bslot[0];
2256 	if (!vif)
2257 		return 0;
2258 
2259 	if (!vif->bss_conf.enable_beacon)
2260 		return 0;
2261 
2262 	avp = (void *)vif->drv_priv;
2263 
2264 	if (!sc->beacon.tx_processed && !edma) {
2265 		tasklet_disable(&sc->bcon_tasklet);
2266 
2267 		bf = avp->av_bcbuf;
2268 		if (!bf || !bf->bf_mpdu)
2269 			goto skip;
2270 
2271 		status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2272 		if (status == -EINPROGRESS)
2273 			goto skip;
2274 
2275 		sc->beacon.tx_processed = true;
2276 		sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2277 
2278 skip:
2279 		tasklet_enable(&sc->bcon_tasklet);
2280 	}
2281 
2282 	return sc->beacon.tx_last;
2283 }
2284 
2285 static int ath9k_get_stats(struct ieee80211_hw *hw,
2286 			   struct ieee80211_low_level_stats *stats)
2287 {
2288 	struct ath_softc *sc = hw->priv;
2289 	struct ath_hw *ah = sc->sc_ah;
2290 	struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2291 
2292 	stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2293 	stats->dot11RTSFailureCount = mib_stats->rts_bad;
2294 	stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2295 	stats->dot11RTSSuccessCount = mib_stats->rts_good;
2296 	return 0;
2297 }
2298 
2299 static u32 fill_chainmask(u32 cap, u32 new)
2300 {
2301 	u32 filled = 0;
2302 	int i;
2303 
2304 	for (i = 0; cap && new; i++, cap >>= 1) {
2305 		if (!(cap & BIT(0)))
2306 			continue;
2307 
2308 		if (new & BIT(0))
2309 			filled |= BIT(i);
2310 
2311 		new >>= 1;
2312 	}
2313 
2314 	return filled;
2315 }
2316 
2317 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2318 {
2319 	if (AR_SREV_9300_20_OR_LATER(ah))
2320 		return true;
2321 
2322 	switch (val & 0x7) {
2323 	case 0x1:
2324 	case 0x3:
2325 	case 0x7:
2326 		return true;
2327 	case 0x2:
2328 		return (ah->caps.rx_chainmask == 1);
2329 	default:
2330 		return false;
2331 	}
2332 }
2333 
2334 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2335 {
2336 	struct ath_softc *sc = hw->priv;
2337 	struct ath_hw *ah = sc->sc_ah;
2338 
2339 	if (ah->caps.rx_chainmask != 1)
2340 		rx_ant |= tx_ant;
2341 
2342 	if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2343 		return -EINVAL;
2344 
2345 	sc->ant_rx = rx_ant;
2346 	sc->ant_tx = tx_ant;
2347 
2348 	if (ah->caps.rx_chainmask == 1)
2349 		return 0;
2350 
2351 	/* AR9100 runs into calibration issues if not all rx chains are enabled */
2352 	if (AR_SREV_9100(ah))
2353 		ah->rxchainmask = 0x7;
2354 	else
2355 		ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2356 
2357 	ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2358 	ath9k_cmn_reload_chainmask(ah);
2359 
2360 	return 0;
2361 }
2362 
2363 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2364 {
2365 	struct ath_softc *sc = hw->priv;
2366 
2367 	*tx_ant = sc->ant_tx;
2368 	*rx_ant = sc->ant_rx;
2369 	return 0;
2370 }
2371 
2372 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2373 				struct ieee80211_vif *vif,
2374 				const u8 *mac_addr)
2375 {
2376 	struct ath_softc *sc = hw->priv;
2377 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2378 	set_bit(ATH_OP_SCANNING, &common->op_flags);
2379 }
2380 
2381 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2382 				   struct ieee80211_vif *vif)
2383 {
2384 	struct ath_softc *sc = hw->priv;
2385 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2386 	clear_bit(ATH_OP_SCANNING, &common->op_flags);
2387 }
2388 
2389 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2390 
2391 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2392 {
2393 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2394 
2395 	if (sc->offchannel.roc_vif) {
2396 		ath_dbg(common, CHAN_CTX,
2397 			"%s: Aborting RoC\n", __func__);
2398 
2399 		del_timer_sync(&sc->offchannel.timer);
2400 		if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2401 			ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2402 	}
2403 
2404 	if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2405 		ath_dbg(common, CHAN_CTX,
2406 			"%s: Aborting HW scan\n", __func__);
2407 
2408 		del_timer_sync(&sc->offchannel.timer);
2409 		ath_scan_complete(sc, true);
2410 	}
2411 }
2412 
2413 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2414 			 struct ieee80211_scan_request *hw_req)
2415 {
2416 	struct cfg80211_scan_request *req = &hw_req->req;
2417 	struct ath_softc *sc = hw->priv;
2418 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2419 	int ret = 0;
2420 
2421 	mutex_lock(&sc->mutex);
2422 
2423 	if (WARN_ON(sc->offchannel.scan_req)) {
2424 		ret = -EBUSY;
2425 		goto out;
2426 	}
2427 
2428 	ath9k_ps_wakeup(sc);
2429 	set_bit(ATH_OP_SCANNING, &common->op_flags);
2430 	sc->offchannel.scan_vif = vif;
2431 	sc->offchannel.scan_req = req;
2432 	sc->offchannel.scan_idx = 0;
2433 
2434 	ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2435 		vif->addr);
2436 
2437 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2438 		ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2439 		ath_offchannel_next(sc);
2440 	}
2441 
2442 out:
2443 	mutex_unlock(&sc->mutex);
2444 
2445 	return ret;
2446 }
2447 
2448 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2449 				 struct ieee80211_vif *vif)
2450 {
2451 	struct ath_softc *sc = hw->priv;
2452 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2453 
2454 	ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2455 
2456 	mutex_lock(&sc->mutex);
2457 	del_timer_sync(&sc->offchannel.timer);
2458 	ath_scan_complete(sc, true);
2459 	mutex_unlock(&sc->mutex);
2460 }
2461 
2462 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2463 				   struct ieee80211_vif *vif,
2464 				   struct ieee80211_channel *chan, int duration,
2465 				   enum ieee80211_roc_type type)
2466 {
2467 	struct ath_softc *sc = hw->priv;
2468 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2469 	int ret = 0;
2470 
2471 	mutex_lock(&sc->mutex);
2472 
2473 	if (WARN_ON(sc->offchannel.roc_vif)) {
2474 		ret = -EBUSY;
2475 		goto out;
2476 	}
2477 
2478 	ath9k_ps_wakeup(sc);
2479 	sc->offchannel.roc_vif = vif;
2480 	sc->offchannel.roc_chan = chan;
2481 	sc->offchannel.roc_duration = duration;
2482 
2483 	ath_dbg(common, CHAN_CTX,
2484 		"RoC request on vif: %pM, type: %d duration: %d\n",
2485 		vif->addr, type, duration);
2486 
2487 	if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2488 		ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2489 		ath_offchannel_next(sc);
2490 	}
2491 
2492 out:
2493 	mutex_unlock(&sc->mutex);
2494 
2495 	return ret;
2496 }
2497 
2498 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2499 					  struct ieee80211_vif *vif)
2500 {
2501 	struct ath_softc *sc = hw->priv;
2502 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2503 
2504 	mutex_lock(&sc->mutex);
2505 
2506 	ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2507 	del_timer_sync(&sc->offchannel.timer);
2508 
2509 	if (sc->offchannel.roc_vif) {
2510 		if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2511 			ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2512 	}
2513 
2514 	mutex_unlock(&sc->mutex);
2515 
2516 	return 0;
2517 }
2518 
2519 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2520 			     struct ieee80211_chanctx_conf *conf)
2521 {
2522 	struct ath_softc *sc = hw->priv;
2523 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2524 	struct ath_chanctx *ctx, **ptr;
2525 	int pos;
2526 
2527 	mutex_lock(&sc->mutex);
2528 
2529 	ath_for_each_chanctx(sc, ctx) {
2530 		if (ctx->assigned)
2531 			continue;
2532 
2533 		ptr = (void *) conf->drv_priv;
2534 		*ptr = ctx;
2535 		ctx->assigned = true;
2536 		pos = ctx - &sc->chanctx[0];
2537 		ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2538 
2539 		ath_dbg(common, CHAN_CTX,
2540 			"Add channel context: %d MHz\n",
2541 			conf->def.chan->center_freq);
2542 
2543 		ath_chanctx_set_channel(sc, ctx, &conf->def);
2544 
2545 		mutex_unlock(&sc->mutex);
2546 		return 0;
2547 	}
2548 
2549 	mutex_unlock(&sc->mutex);
2550 	return -ENOSPC;
2551 }
2552 
2553 
2554 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2555 				 struct ieee80211_chanctx_conf *conf)
2556 {
2557 	struct ath_softc *sc = hw->priv;
2558 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2559 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2560 
2561 	mutex_lock(&sc->mutex);
2562 
2563 	ath_dbg(common, CHAN_CTX,
2564 		"Remove channel context: %d MHz\n",
2565 		conf->def.chan->center_freq);
2566 
2567 	ctx->assigned = false;
2568 	ctx->hw_queue_base = 0;
2569 	ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2570 
2571 	mutex_unlock(&sc->mutex);
2572 }
2573 
2574 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2575 				 struct ieee80211_chanctx_conf *conf,
2576 				 u32 changed)
2577 {
2578 	struct ath_softc *sc = hw->priv;
2579 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2580 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2581 
2582 	mutex_lock(&sc->mutex);
2583 	ath_dbg(common, CHAN_CTX,
2584 		"Change channel context: %d MHz\n",
2585 		conf->def.chan->center_freq);
2586 	ath_chanctx_set_channel(sc, ctx, &conf->def);
2587 	mutex_unlock(&sc->mutex);
2588 }
2589 
2590 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2591 				    struct ieee80211_vif *vif,
2592 				    struct ieee80211_chanctx_conf *conf)
2593 {
2594 	struct ath_softc *sc = hw->priv;
2595 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2596 	struct ath_vif *avp = (void *)vif->drv_priv;
2597 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2598 	int i;
2599 
2600 	ath9k_cancel_pending_offchannel(sc);
2601 
2602 	mutex_lock(&sc->mutex);
2603 
2604 	ath_dbg(common, CHAN_CTX,
2605 		"Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2606 		vif->addr, vif->type, vif->p2p,
2607 		conf->def.chan->center_freq);
2608 
2609 	avp->chanctx = ctx;
2610 	ctx->nvifs_assigned++;
2611 	list_add_tail(&avp->list, &ctx->vifs);
2612 	ath9k_calculate_summary_state(sc, ctx);
2613 	for (i = 0; i < IEEE80211_NUM_ACS; i++)
2614 		vif->hw_queue[i] = ctx->hw_queue_base + i;
2615 
2616 	mutex_unlock(&sc->mutex);
2617 
2618 	return 0;
2619 }
2620 
2621 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2622 				       struct ieee80211_vif *vif,
2623 				       struct ieee80211_chanctx_conf *conf)
2624 {
2625 	struct ath_softc *sc = hw->priv;
2626 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2627 	struct ath_vif *avp = (void *)vif->drv_priv;
2628 	struct ath_chanctx *ctx = ath_chanctx_get(conf);
2629 	int ac;
2630 
2631 	ath9k_cancel_pending_offchannel(sc);
2632 
2633 	mutex_lock(&sc->mutex);
2634 
2635 	ath_dbg(common, CHAN_CTX,
2636 		"Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2637 		vif->addr, vif->type, vif->p2p,
2638 		conf->def.chan->center_freq);
2639 
2640 	avp->chanctx = NULL;
2641 	ctx->nvifs_assigned--;
2642 	list_del(&avp->list);
2643 	ath9k_calculate_summary_state(sc, ctx);
2644 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2645 		vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2646 
2647 	mutex_unlock(&sc->mutex);
2648 }
2649 
2650 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2651 				 struct ieee80211_vif *vif,
2652 				 u16 duration)
2653 {
2654 	struct ath_softc *sc = hw->priv;
2655 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2656 	struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2657 	struct ath_beacon_config *cur_conf;
2658 	struct ath_chanctx *go_ctx;
2659 	unsigned long timeout;
2660 	bool changed = false;
2661 	u32 beacon_int;
2662 
2663 	if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2664 		return;
2665 
2666 	if (!avp->chanctx)
2667 		return;
2668 
2669 	mutex_lock(&sc->mutex);
2670 
2671 	spin_lock_bh(&sc->chan_lock);
2672 	if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2673 		changed = true;
2674 	spin_unlock_bh(&sc->chan_lock);
2675 
2676 	if (!changed)
2677 		goto out;
2678 
2679 	ath9k_cancel_pending_offchannel(sc);
2680 
2681 	go_ctx = ath_is_go_chanctx_present(sc);
2682 
2683 	if (go_ctx) {
2684 		/*
2685 		 * Wait till the GO interface gets a chance
2686 		 * to send out an NoA.
2687 		 */
2688 		spin_lock_bh(&sc->chan_lock);
2689 		sc->sched.mgd_prepare_tx = true;
2690 		cur_conf = &go_ctx->beacon;
2691 		beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2692 		spin_unlock_bh(&sc->chan_lock);
2693 
2694 		timeout = usecs_to_jiffies(beacon_int * 2);
2695 		init_completion(&sc->go_beacon);
2696 
2697 		mutex_unlock(&sc->mutex);
2698 
2699 		if (wait_for_completion_timeout(&sc->go_beacon,
2700 						timeout) == 0) {
2701 			ath_dbg(common, CHAN_CTX,
2702 				"Failed to send new NoA\n");
2703 
2704 			spin_lock_bh(&sc->chan_lock);
2705 			sc->sched.mgd_prepare_tx = false;
2706 			spin_unlock_bh(&sc->chan_lock);
2707 		}
2708 
2709 		mutex_lock(&sc->mutex);
2710 	}
2711 
2712 	ath_dbg(common, CHAN_CTX,
2713 		"%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2714 		__func__, vif->addr);
2715 
2716 	spin_lock_bh(&sc->chan_lock);
2717 	sc->next_chan = avp->chanctx;
2718 	sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2719 	spin_unlock_bh(&sc->chan_lock);
2720 
2721 	ath_chanctx_set_next(sc, true);
2722 out:
2723 	mutex_unlock(&sc->mutex);
2724 }
2725 
2726 void ath9k_fill_chanctx_ops(void)
2727 {
2728 	if (!ath9k_is_chanctx_enabled())
2729 		return;
2730 
2731 	ath9k_ops.hw_scan                  = ath9k_hw_scan;
2732 	ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2733 	ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2734 	ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2735 	ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2736 	ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2737 	ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2738 	ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2739 	ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2740 	ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2741 }
2742 
2743 #endif
2744 
2745 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2746 			     int *dbm)
2747 {
2748 	struct ath_softc *sc = hw->priv;
2749 	struct ath_vif *avp = (void *)vif->drv_priv;
2750 
2751 	mutex_lock(&sc->mutex);
2752 	if (avp->chanctx)
2753 		*dbm = avp->chanctx->cur_txpower;
2754 	else
2755 		*dbm = sc->cur_chan->cur_txpower;
2756 	mutex_unlock(&sc->mutex);
2757 
2758 	*dbm /= 2;
2759 
2760 	return 0;
2761 }
2762 
2763 struct ieee80211_ops ath9k_ops = {
2764 	.tx 		    = ath9k_tx,
2765 	.start 		    = ath9k_start,
2766 	.stop 		    = ath9k_stop,
2767 	.add_interface 	    = ath9k_add_interface,
2768 	.change_interface   = ath9k_change_interface,
2769 	.remove_interface   = ath9k_remove_interface,
2770 	.config 	    = ath9k_config,
2771 	.configure_filter   = ath9k_configure_filter,
2772 	.sta_state          = ath9k_sta_state,
2773 	.sta_notify         = ath9k_sta_notify,
2774 	.conf_tx 	    = ath9k_conf_tx,
2775 	.bss_info_changed   = ath9k_bss_info_changed,
2776 	.set_key            = ath9k_set_key,
2777 	.get_tsf 	    = ath9k_get_tsf,
2778 	.set_tsf 	    = ath9k_set_tsf,
2779 	.reset_tsf 	    = ath9k_reset_tsf,
2780 	.ampdu_action       = ath9k_ampdu_action,
2781 	.get_survey	    = ath9k_get_survey,
2782 	.rfkill_poll        = ath9k_rfkill_poll_state,
2783 	.set_coverage_class = ath9k_set_coverage_class,
2784 	.flush		    = ath9k_flush,
2785 	.tx_frames_pending  = ath9k_tx_frames_pending,
2786 	.tx_last_beacon     = ath9k_tx_last_beacon,
2787 	.release_buffered_frames = ath9k_release_buffered_frames,
2788 	.get_stats	    = ath9k_get_stats,
2789 	.set_antenna	    = ath9k_set_antenna,
2790 	.get_antenna	    = ath9k_get_antenna,
2791 
2792 #ifdef CONFIG_ATH9K_WOW
2793 	.suspend	    = ath9k_suspend,
2794 	.resume		    = ath9k_resume,
2795 	.set_wakeup	    = ath9k_set_wakeup,
2796 #endif
2797 
2798 #ifdef CONFIG_ATH9K_DEBUGFS
2799 	.get_et_sset_count  = ath9k_get_et_sset_count,
2800 	.get_et_stats       = ath9k_get_et_stats,
2801 	.get_et_strings     = ath9k_get_et_strings,
2802 #endif
2803 
2804 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2805 	.sta_add_debugfs    = ath9k_sta_add_debugfs,
2806 #endif
2807 	.sw_scan_start	    = ath9k_sw_scan_start,
2808 	.sw_scan_complete   = ath9k_sw_scan_complete,
2809 	.get_txpower        = ath9k_get_txpower,
2810 	.wake_tx_queue      = ath9k_wake_tx_queue,
2811 };
2812