1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath_ps_full_sleep(unsigned long data) 86 { 87 struct ath_softc *sc = (struct ath_softc *) data; 88 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 89 bool reset; 90 91 spin_lock(&common->cc_lock); 92 ath_hw_cycle_counters_update(common); 93 spin_unlock(&common->cc_lock); 94 95 ath9k_hw_setrxabort(sc->sc_ah, 1); 96 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 97 98 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 99 } 100 101 void ath9k_ps_wakeup(struct ath_softc *sc) 102 { 103 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 104 unsigned long flags; 105 enum ath9k_power_mode power_mode; 106 107 spin_lock_irqsave(&sc->sc_pm_lock, flags); 108 if (++sc->ps_usecount != 1) 109 goto unlock; 110 111 del_timer_sync(&sc->sleep_timer); 112 power_mode = sc->sc_ah->power_mode; 113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 114 115 /* 116 * While the hardware is asleep, the cycle counters contain no 117 * useful data. Better clear them now so that they don't mess up 118 * survey data results. 119 */ 120 if (power_mode != ATH9K_PM_AWAKE) { 121 spin_lock(&common->cc_lock); 122 ath_hw_cycle_counters_update(common); 123 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 124 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 125 spin_unlock(&common->cc_lock); 126 } 127 128 unlock: 129 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 130 } 131 132 void ath9k_ps_restore(struct ath_softc *sc) 133 { 134 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 135 enum ath9k_power_mode mode; 136 unsigned long flags; 137 138 spin_lock_irqsave(&sc->sc_pm_lock, flags); 139 if (--sc->ps_usecount != 0) 140 goto unlock; 141 142 if (sc->ps_idle) { 143 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 144 goto unlock; 145 } 146 147 if (sc->ps_enabled && 148 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 149 PS_WAIT_FOR_CAB | 150 PS_WAIT_FOR_PSPOLL_DATA | 151 PS_WAIT_FOR_TX_ACK | 152 PS_WAIT_FOR_ANI))) { 153 mode = ATH9K_PM_NETWORK_SLEEP; 154 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 155 ath9k_btcoex_stop_gen_timer(sc); 156 } else { 157 goto unlock; 158 } 159 160 spin_lock(&common->cc_lock); 161 ath_hw_cycle_counters_update(common); 162 spin_unlock(&common->cc_lock); 163 164 ath9k_hw_setpower(sc->sc_ah, mode); 165 166 unlock: 167 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 168 } 169 170 static void __ath_cancel_work(struct ath_softc *sc) 171 { 172 cancel_work_sync(&sc->paprd_work); 173 cancel_delayed_work_sync(&sc->tx_complete_work); 174 cancel_delayed_work_sync(&sc->hw_pll_work); 175 176 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 177 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 178 cancel_work_sync(&sc->mci_work); 179 #endif 180 } 181 182 void ath_cancel_work(struct ath_softc *sc) 183 { 184 __ath_cancel_work(sc); 185 cancel_work_sync(&sc->hw_reset_work); 186 } 187 188 void ath_restart_work(struct ath_softc *sc) 189 { 190 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 191 192 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 193 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 194 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 195 196 ath_start_ani(sc); 197 } 198 199 static bool ath_prepare_reset(struct ath_softc *sc) 200 { 201 struct ath_hw *ah = sc->sc_ah; 202 bool ret = true; 203 204 ieee80211_stop_queues(sc->hw); 205 ath_stop_ani(sc); 206 ath9k_hw_disable_interrupts(ah); 207 208 if (!ath_drain_all_txq(sc)) 209 ret = false; 210 211 if (!ath_stoprecv(sc)) 212 ret = false; 213 214 return ret; 215 } 216 217 static bool ath_complete_reset(struct ath_softc *sc, bool start) 218 { 219 struct ath_hw *ah = sc->sc_ah; 220 struct ath_common *common = ath9k_hw_common(ah); 221 unsigned long flags; 222 int i; 223 224 if (ath_startrecv(sc) != 0) { 225 ath_err(common, "Unable to restart recv logic\n"); 226 return false; 227 } 228 229 ath9k_cmn_update_txpow(ah, sc->curtxpow, 230 sc->config.txpowlimit, &sc->curtxpow); 231 232 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 233 ath9k_hw_set_interrupts(ah); 234 ath9k_hw_enable_interrupts(ah); 235 236 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 237 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 238 goto work; 239 240 if (ah->opmode == NL80211_IFTYPE_STATION && 241 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 242 spin_lock_irqsave(&sc->sc_pm_lock, flags); 243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 245 } else { 246 ath9k_set_beacon(sc); 247 } 248 work: 249 ath_restart_work(sc); 250 251 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 252 if (!ATH_TXQ_SETUP(sc, i)) 253 continue; 254 255 spin_lock_bh(&sc->tx.txq[i].axq_lock); 256 ath_txq_schedule(sc, &sc->tx.txq[i]); 257 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 258 } 259 } 260 261 sc->gtt_cnt = 0; 262 ieee80211_wake_queues(sc->hw); 263 264 ath9k_p2p_ps_timer(sc); 265 266 return true; 267 } 268 269 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 270 { 271 struct ath_hw *ah = sc->sc_ah; 272 struct ath_common *common = ath9k_hw_common(ah); 273 struct ath9k_hw_cal_data *caldata = NULL; 274 bool fastcc = true; 275 int r; 276 277 __ath_cancel_work(sc); 278 279 tasklet_disable(&sc->intr_tq); 280 spin_lock_bh(&sc->sc_pcu_lock); 281 282 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 283 fastcc = false; 284 caldata = &sc->caldata; 285 } 286 287 if (!hchan) { 288 fastcc = false; 289 hchan = ah->curchan; 290 } 291 292 if (!ath_prepare_reset(sc)) 293 fastcc = false; 294 295 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 296 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 297 298 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 299 if (r) { 300 ath_err(common, 301 "Unable to reset channel, reset status %d\n", r); 302 303 ath9k_hw_enable_interrupts(ah); 304 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 305 306 goto out; 307 } 308 309 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 310 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 311 ath9k_mci_set_txpower(sc, true, false); 312 313 if (!ath_complete_reset(sc, true)) 314 r = -EIO; 315 316 out: 317 spin_unlock_bh(&sc->sc_pcu_lock); 318 tasklet_enable(&sc->intr_tq); 319 320 return r; 321 } 322 323 324 /* 325 * Set/change channels. If the channel is really being changed, it's done 326 * by reseting the chip. To accomplish this we must first cleanup any pending 327 * DMA, then restart stuff. 328 */ 329 static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef) 330 { 331 struct ath_hw *ah = sc->sc_ah; 332 struct ath_common *common = ath9k_hw_common(ah); 333 struct ieee80211_hw *hw = sc->hw; 334 struct ath9k_channel *hchan; 335 struct ieee80211_channel *chan = chandef->chan; 336 bool offchannel; 337 int pos = chan->hw_value; 338 int old_pos = -1; 339 int r; 340 341 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 342 return -EIO; 343 344 offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); 345 346 if (ah->curchan) 347 old_pos = ah->curchan - &ah->channels[0]; 348 349 ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n", 350 chan->center_freq, chandef->width); 351 352 /* update survey stats for the old channel before switching */ 353 spin_lock_bh(&common->cc_lock); 354 ath_update_survey_stats(sc); 355 spin_unlock_bh(&common->cc_lock); 356 357 ath9k_cmn_get_channel(hw, ah, chandef); 358 359 /* 360 * If the operating channel changes, change the survey in-use flags 361 * along with it. 362 * Reset the survey data for the new channel, unless we're switching 363 * back to the operating channel from an off-channel operation. 364 */ 365 if (!offchannel && sc->cur_survey != &sc->survey[pos]) { 366 if (sc->cur_survey) 367 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 368 369 sc->cur_survey = &sc->survey[pos]; 370 371 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 372 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 373 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 374 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 375 } 376 377 hchan = &sc->sc_ah->channels[pos]; 378 r = ath_reset_internal(sc, hchan); 379 if (r) 380 return r; 381 382 /* 383 * The most recent snapshot of channel->noisefloor for the old 384 * channel is only available after the hardware reset. Copy it to 385 * the survey stats now. 386 */ 387 if (old_pos >= 0) 388 ath_update_survey_nf(sc, old_pos); 389 390 /* 391 * Enable radar pulse detection if on a DFS channel. Spectral 392 * scanning and radar detection can not be used concurrently. 393 */ 394 if (hw->conf.radar_enabled) { 395 u32 rxfilter; 396 397 /* set HW specific DFS configuration */ 398 ath9k_hw_set_radar_params(ah); 399 rxfilter = ath9k_hw_getrxfilter(ah); 400 rxfilter |= ATH9K_RX_FILTER_PHYRADAR | 401 ATH9K_RX_FILTER_PHYERR; 402 ath9k_hw_setrxfilter(ah, rxfilter); 403 ath_dbg(common, DFS, "DFS enabled at freq %d\n", 404 chan->center_freq); 405 } else { 406 /* perform spectral scan if requested. */ 407 if (test_bit(ATH_OP_SCANNING, &common->op_flags) && 408 sc->spectral_mode == SPECTRAL_CHANSCAN) 409 ath9k_spectral_scan_trigger(hw); 410 } 411 412 return 0; 413 } 414 415 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 416 struct ieee80211_vif *vif) 417 { 418 struct ath_node *an; 419 an = (struct ath_node *)sta->drv_priv; 420 421 an->sc = sc; 422 an->sta = sta; 423 an->vif = vif; 424 memset(&an->key_idx, 0, sizeof(an->key_idx)); 425 426 ath_tx_node_init(sc, an); 427 } 428 429 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 430 { 431 struct ath_node *an = (struct ath_node *)sta->drv_priv; 432 ath_tx_node_cleanup(sc, an); 433 } 434 435 void ath9k_tasklet(unsigned long data) 436 { 437 struct ath_softc *sc = (struct ath_softc *)data; 438 struct ath_hw *ah = sc->sc_ah; 439 struct ath_common *common = ath9k_hw_common(ah); 440 enum ath_reset_type type; 441 unsigned long flags; 442 u32 status = sc->intrstatus; 443 u32 rxmask; 444 445 ath9k_ps_wakeup(sc); 446 spin_lock(&sc->sc_pcu_lock); 447 448 if (status & ATH9K_INT_FATAL) { 449 type = RESET_TYPE_FATAL_INT; 450 ath9k_queue_reset(sc, type); 451 452 /* 453 * Increment the ref. counter here so that 454 * interrupts are enabled in the reset routine. 455 */ 456 atomic_inc(&ah->intr_ref_cnt); 457 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 458 goto out; 459 } 460 461 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 462 (status & ATH9K_INT_BB_WATCHDOG)) { 463 spin_lock(&common->cc_lock); 464 ath_hw_cycle_counters_update(common); 465 ar9003_hw_bb_watchdog_dbg_info(ah); 466 spin_unlock(&common->cc_lock); 467 468 if (ar9003_hw_bb_watchdog_check(ah)) { 469 type = RESET_TYPE_BB_WATCHDOG; 470 ath9k_queue_reset(sc, type); 471 472 /* 473 * Increment the ref. counter here so that 474 * interrupts are enabled in the reset routine. 475 */ 476 atomic_inc(&ah->intr_ref_cnt); 477 ath_dbg(common, RESET, 478 "BB_WATCHDOG: Skipping interrupts\n"); 479 goto out; 480 } 481 } 482 483 if (status & ATH9K_INT_GTT) { 484 sc->gtt_cnt++; 485 486 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 487 type = RESET_TYPE_TX_GTT; 488 ath9k_queue_reset(sc, type); 489 atomic_inc(&ah->intr_ref_cnt); 490 ath_dbg(common, RESET, 491 "GTT: Skipping interrupts\n"); 492 goto out; 493 } 494 } 495 496 spin_lock_irqsave(&sc->sc_pm_lock, flags); 497 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 498 /* 499 * TSF sync does not look correct; remain awake to sync with 500 * the next Beacon. 501 */ 502 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 503 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 504 } 505 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 506 507 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 508 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 509 ATH9K_INT_RXORN); 510 else 511 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 512 513 if (status & rxmask) { 514 /* Check for high priority Rx first */ 515 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 516 (status & ATH9K_INT_RXHP)) 517 ath_rx_tasklet(sc, 0, true); 518 519 ath_rx_tasklet(sc, 0, false); 520 } 521 522 if (status & ATH9K_INT_TX) { 523 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 524 /* 525 * For EDMA chips, TX completion is enabled for the 526 * beacon queue, so if a beacon has been transmitted 527 * successfully after a GTT interrupt, the GTT counter 528 * gets reset to zero here. 529 */ 530 sc->gtt_cnt = 0; 531 532 ath_tx_edma_tasklet(sc); 533 } else { 534 ath_tx_tasklet(sc); 535 } 536 537 wake_up(&sc->tx_wait); 538 } 539 540 if (status & ATH9K_INT_GENTIMER) 541 ath_gen_timer_isr(sc->sc_ah); 542 543 ath9k_btcoex_handle_interrupt(sc, status); 544 545 /* re-enable hardware interrupt */ 546 ath9k_hw_enable_interrupts(ah); 547 out: 548 spin_unlock(&sc->sc_pcu_lock); 549 ath9k_ps_restore(sc); 550 } 551 552 irqreturn_t ath_isr(int irq, void *dev) 553 { 554 #define SCHED_INTR ( \ 555 ATH9K_INT_FATAL | \ 556 ATH9K_INT_BB_WATCHDOG | \ 557 ATH9K_INT_RXORN | \ 558 ATH9K_INT_RXEOL | \ 559 ATH9K_INT_RX | \ 560 ATH9K_INT_RXLP | \ 561 ATH9K_INT_RXHP | \ 562 ATH9K_INT_TX | \ 563 ATH9K_INT_BMISS | \ 564 ATH9K_INT_CST | \ 565 ATH9K_INT_GTT | \ 566 ATH9K_INT_TSFOOR | \ 567 ATH9K_INT_GENTIMER | \ 568 ATH9K_INT_MCI) 569 570 struct ath_softc *sc = dev; 571 struct ath_hw *ah = sc->sc_ah; 572 struct ath_common *common = ath9k_hw_common(ah); 573 enum ath9k_int status; 574 u32 sync_cause = 0; 575 bool sched = false; 576 577 /* 578 * The hardware is not ready/present, don't 579 * touch anything. Note this can happen early 580 * on if the IRQ is shared. 581 */ 582 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 583 return IRQ_NONE; 584 585 /* shared irq, not for us */ 586 587 if (!ath9k_hw_intrpend(ah)) 588 return IRQ_NONE; 589 590 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 591 ath9k_hw_kill_interrupts(ah); 592 return IRQ_HANDLED; 593 } 594 595 /* 596 * Figure out the reason(s) for the interrupt. Note 597 * that the hal returns a pseudo-ISR that may include 598 * bits we haven't explicitly enabled so we mask the 599 * value to insure we only process bits we requested. 600 */ 601 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 602 ath9k_debug_sync_cause(sc, sync_cause); 603 status &= ah->imask; /* discard unasked-for bits */ 604 605 /* 606 * If there are no status bits set, then this interrupt was not 607 * for me (should have been caught above). 608 */ 609 if (!status) 610 return IRQ_NONE; 611 612 /* Cache the status */ 613 sc->intrstatus = status; 614 615 if (status & SCHED_INTR) 616 sched = true; 617 618 /* 619 * If a FATAL or RXORN interrupt is received, we have to reset the 620 * chip immediately. 621 */ 622 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 623 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 624 goto chip_reset; 625 626 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 627 (status & ATH9K_INT_BB_WATCHDOG)) 628 goto chip_reset; 629 630 #ifdef CONFIG_ATH9K_WOW 631 if (status & ATH9K_INT_BMISS) { 632 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 633 atomic_inc(&sc->wow_got_bmiss_intr); 634 atomic_dec(&sc->wow_sleep_proc_intr); 635 } 636 } 637 #endif 638 639 if (status & ATH9K_INT_SWBA) 640 tasklet_schedule(&sc->bcon_tasklet); 641 642 if (status & ATH9K_INT_TXURN) 643 ath9k_hw_updatetxtriglevel(ah, true); 644 645 if (status & ATH9K_INT_RXEOL) { 646 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 647 ath9k_hw_set_interrupts(ah); 648 } 649 650 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 651 if (status & ATH9K_INT_TIM_TIMER) { 652 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 653 goto chip_reset; 654 /* Clear RxAbort bit so that we can 655 * receive frames */ 656 ath9k_setpower(sc, ATH9K_PM_AWAKE); 657 spin_lock(&sc->sc_pm_lock); 658 ath9k_hw_setrxabort(sc->sc_ah, 0); 659 sc->ps_flags |= PS_WAIT_FOR_BEACON; 660 spin_unlock(&sc->sc_pm_lock); 661 } 662 663 chip_reset: 664 665 ath_debug_stat_interrupt(sc, status); 666 667 if (sched) { 668 /* turn off every interrupt */ 669 ath9k_hw_disable_interrupts(ah); 670 tasklet_schedule(&sc->intr_tq); 671 } 672 673 return IRQ_HANDLED; 674 675 #undef SCHED_INTR 676 } 677 678 int ath_reset(struct ath_softc *sc) 679 { 680 int r; 681 682 ath9k_ps_wakeup(sc); 683 r = ath_reset_internal(sc, NULL); 684 ath9k_ps_restore(sc); 685 686 return r; 687 } 688 689 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 690 { 691 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 692 #ifdef CONFIG_ATH9K_DEBUGFS 693 RESET_STAT_INC(sc, type); 694 #endif 695 set_bit(ATH_OP_HW_RESET, &common->op_flags); 696 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 697 } 698 699 void ath_reset_work(struct work_struct *work) 700 { 701 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 702 703 ath_reset(sc); 704 } 705 706 /**********************/ 707 /* mac80211 callbacks */ 708 /**********************/ 709 710 static int ath9k_start(struct ieee80211_hw *hw) 711 { 712 struct ath_softc *sc = hw->priv; 713 struct ath_hw *ah = sc->sc_ah; 714 struct ath_common *common = ath9k_hw_common(ah); 715 struct ieee80211_channel *curchan = hw->conf.chandef.chan; 716 struct ath9k_channel *init_channel; 717 int r; 718 719 ath_dbg(common, CONFIG, 720 "Starting driver with initial channel: %d MHz\n", 721 curchan->center_freq); 722 723 ath9k_ps_wakeup(sc); 724 mutex_lock(&sc->mutex); 725 726 init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 727 728 /* Reset SERDES registers */ 729 ath9k_hw_configpcipowersave(ah, false); 730 731 /* 732 * The basic interface to setting the hardware in a good 733 * state is ``reset''. On return the hardware is known to 734 * be powered up and with interrupts disabled. This must 735 * be followed by initialization of the appropriate bits 736 * and then setup of the interrupt mask. 737 */ 738 spin_lock_bh(&sc->sc_pcu_lock); 739 740 atomic_set(&ah->intr_ref_cnt, -1); 741 742 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 743 if (r) { 744 ath_err(common, 745 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 746 r, curchan->center_freq); 747 ah->reset_power_on = false; 748 } 749 750 /* Setup our intr mask. */ 751 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 752 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 753 ATH9K_INT_GLOBAL; 754 755 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 756 ah->imask |= ATH9K_INT_RXHP | 757 ATH9K_INT_RXLP; 758 else 759 ah->imask |= ATH9K_INT_RX; 760 761 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 762 ah->imask |= ATH9K_INT_BB_WATCHDOG; 763 764 /* 765 * Enable GTT interrupts only for AR9003/AR9004 chips 766 * for now. 767 */ 768 if (AR_SREV_9300_20_OR_LATER(ah)) 769 ah->imask |= ATH9K_INT_GTT; 770 771 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 772 ah->imask |= ATH9K_INT_CST; 773 774 ath_mci_enable(sc); 775 776 clear_bit(ATH_OP_INVALID, &common->op_flags); 777 sc->sc_ah->is_monitoring = false; 778 779 if (!ath_complete_reset(sc, false)) 780 ah->reset_power_on = false; 781 782 if (ah->led_pin >= 0) { 783 ath9k_hw_cfg_output(ah, ah->led_pin, 784 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 785 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 786 } 787 788 /* 789 * Reset key cache to sane defaults (all entries cleared) instead of 790 * semi-random values after suspend/resume. 791 */ 792 ath9k_cmn_init_crypto(sc->sc_ah); 793 794 ath9k_hw_reset_tsf(ah); 795 796 spin_unlock_bh(&sc->sc_pcu_lock); 797 798 mutex_unlock(&sc->mutex); 799 800 ath9k_ps_restore(sc); 801 802 return 0; 803 } 804 805 static void ath9k_tx(struct ieee80211_hw *hw, 806 struct ieee80211_tx_control *control, 807 struct sk_buff *skb) 808 { 809 struct ath_softc *sc = hw->priv; 810 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 811 struct ath_tx_control txctl; 812 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 813 unsigned long flags; 814 815 if (sc->ps_enabled) { 816 /* 817 * mac80211 does not set PM field for normal data frames, so we 818 * need to update that based on the current PS mode. 819 */ 820 if (ieee80211_is_data(hdr->frame_control) && 821 !ieee80211_is_nullfunc(hdr->frame_control) && 822 !ieee80211_has_pm(hdr->frame_control)) { 823 ath_dbg(common, PS, 824 "Add PM=1 for a TX frame while in PS mode\n"); 825 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 826 } 827 } 828 829 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 830 /* 831 * We are using PS-Poll and mac80211 can request TX while in 832 * power save mode. Need to wake up hardware for the TX to be 833 * completed and if needed, also for RX of buffered frames. 834 */ 835 ath9k_ps_wakeup(sc); 836 spin_lock_irqsave(&sc->sc_pm_lock, flags); 837 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 838 ath9k_hw_setrxabort(sc->sc_ah, 0); 839 if (ieee80211_is_pspoll(hdr->frame_control)) { 840 ath_dbg(common, PS, 841 "Sending PS-Poll to pick a buffered frame\n"); 842 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 843 } else { 844 ath_dbg(common, PS, "Wake up to complete TX\n"); 845 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 846 } 847 /* 848 * The actual restore operation will happen only after 849 * the ps_flags bit is cleared. We are just dropping 850 * the ps_usecount here. 851 */ 852 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 853 ath9k_ps_restore(sc); 854 } 855 856 /* 857 * Cannot tx while the hardware is in full sleep, it first needs a full 858 * chip reset to recover from that 859 */ 860 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 861 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 862 goto exit; 863 } 864 865 memset(&txctl, 0, sizeof(struct ath_tx_control)); 866 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 867 txctl.sta = control->sta; 868 869 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 870 871 if (ath_tx_start(hw, skb, &txctl) != 0) { 872 ath_dbg(common, XMIT, "TX failed\n"); 873 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 874 goto exit; 875 } 876 877 return; 878 exit: 879 ieee80211_free_txskb(hw, skb); 880 } 881 882 static void ath9k_stop(struct ieee80211_hw *hw) 883 { 884 struct ath_softc *sc = hw->priv; 885 struct ath_hw *ah = sc->sc_ah; 886 struct ath_common *common = ath9k_hw_common(ah); 887 bool prev_idle; 888 889 mutex_lock(&sc->mutex); 890 891 ath_cancel_work(sc); 892 893 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 894 ath_dbg(common, ANY, "Device not present\n"); 895 mutex_unlock(&sc->mutex); 896 return; 897 } 898 899 /* Ensure HW is awake when we try to shut it down. */ 900 ath9k_ps_wakeup(sc); 901 902 spin_lock_bh(&sc->sc_pcu_lock); 903 904 /* prevent tasklets to enable interrupts once we disable them */ 905 ah->imask &= ~ATH9K_INT_GLOBAL; 906 907 /* make sure h/w will not generate any interrupt 908 * before setting the invalid flag. */ 909 ath9k_hw_disable_interrupts(ah); 910 911 spin_unlock_bh(&sc->sc_pcu_lock); 912 913 /* we can now sync irq and kill any running tasklets, since we already 914 * disabled interrupts and not holding a spin lock */ 915 synchronize_irq(sc->irq); 916 tasklet_kill(&sc->intr_tq); 917 tasklet_kill(&sc->bcon_tasklet); 918 919 prev_idle = sc->ps_idle; 920 sc->ps_idle = true; 921 922 spin_lock_bh(&sc->sc_pcu_lock); 923 924 if (ah->led_pin >= 0) { 925 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 926 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 927 } 928 929 ath_prepare_reset(sc); 930 931 if (sc->rx.frag) { 932 dev_kfree_skb_any(sc->rx.frag); 933 sc->rx.frag = NULL; 934 } 935 936 if (!ah->curchan) 937 ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 938 939 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 940 ath9k_hw_phy_disable(ah); 941 942 ath9k_hw_configpcipowersave(ah, true); 943 944 spin_unlock_bh(&sc->sc_pcu_lock); 945 946 ath9k_ps_restore(sc); 947 948 set_bit(ATH_OP_INVALID, &common->op_flags); 949 sc->ps_idle = prev_idle; 950 951 mutex_unlock(&sc->mutex); 952 953 ath_dbg(common, CONFIG, "Driver halt\n"); 954 } 955 956 static bool ath9k_uses_beacons(int type) 957 { 958 switch (type) { 959 case NL80211_IFTYPE_AP: 960 case NL80211_IFTYPE_ADHOC: 961 case NL80211_IFTYPE_MESH_POINT: 962 return true; 963 default: 964 return false; 965 } 966 } 967 968 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 969 { 970 struct ath9k_vif_iter_data *iter_data = data; 971 int i; 972 973 if (iter_data->has_hw_macaddr) { 974 for (i = 0; i < ETH_ALEN; i++) 975 iter_data->mask[i] &= 976 ~(iter_data->hw_macaddr[i] ^ mac[i]); 977 } else { 978 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 979 iter_data->has_hw_macaddr = true; 980 } 981 982 switch (vif->type) { 983 case NL80211_IFTYPE_AP: 984 iter_data->naps++; 985 break; 986 case NL80211_IFTYPE_STATION: 987 iter_data->nstations++; 988 break; 989 case NL80211_IFTYPE_ADHOC: 990 iter_data->nadhocs++; 991 break; 992 case NL80211_IFTYPE_MESH_POINT: 993 iter_data->nmeshes++; 994 break; 995 case NL80211_IFTYPE_WDS: 996 iter_data->nwds++; 997 break; 998 default: 999 break; 1000 } 1001 } 1002 1003 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1004 { 1005 struct ath_softc *sc = data; 1006 struct ath_vif *avp = (void *)vif->drv_priv; 1007 1008 if (vif->type != NL80211_IFTYPE_STATION) 1009 return; 1010 1011 if (avp->primary_sta_vif) 1012 ath9k_set_assoc_state(sc, vif); 1013 } 1014 1015 /* Called with sc->mutex held. */ 1016 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 1017 struct ieee80211_vif *vif, 1018 struct ath9k_vif_iter_data *iter_data) 1019 { 1020 struct ath_softc *sc = hw->priv; 1021 struct ath_hw *ah = sc->sc_ah; 1022 struct ath_common *common = ath9k_hw_common(ah); 1023 1024 /* 1025 * Pick the MAC address of the first interface as the new hardware 1026 * MAC address. The hardware will use it together with the BSSID mask 1027 * when matching addresses. 1028 */ 1029 memset(iter_data, 0, sizeof(*iter_data)); 1030 memset(&iter_data->mask, 0xff, ETH_ALEN); 1031 1032 if (vif) 1033 ath9k_vif_iter(iter_data, vif->addr, vif); 1034 1035 /* Get list of all active MAC addresses */ 1036 ieee80211_iterate_active_interfaces_atomic( 1037 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1038 ath9k_vif_iter, iter_data); 1039 1040 memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN); 1041 } 1042 1043 /* Called with sc->mutex held. */ 1044 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 1045 struct ieee80211_vif *vif) 1046 { 1047 struct ath_softc *sc = hw->priv; 1048 struct ath_hw *ah = sc->sc_ah; 1049 struct ath_common *common = ath9k_hw_common(ah); 1050 struct ath9k_vif_iter_data iter_data; 1051 enum nl80211_iftype old_opmode = ah->opmode; 1052 1053 ath9k_calculate_iter_data(hw, vif, &iter_data); 1054 1055 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1056 ath_hw_setbssidmask(common); 1057 1058 if (iter_data.naps > 0) { 1059 ath9k_hw_set_tsfadjust(ah, true); 1060 ah->opmode = NL80211_IFTYPE_AP; 1061 } else { 1062 ath9k_hw_set_tsfadjust(ah, false); 1063 1064 if (iter_data.nmeshes) 1065 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1066 else if (iter_data.nwds) 1067 ah->opmode = NL80211_IFTYPE_AP; 1068 else if (iter_data.nadhocs) 1069 ah->opmode = NL80211_IFTYPE_ADHOC; 1070 else 1071 ah->opmode = NL80211_IFTYPE_STATION; 1072 } 1073 1074 ath9k_hw_setopmode(ah); 1075 1076 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1077 ah->imask |= ATH9K_INT_TSFOOR; 1078 else 1079 ah->imask &= ~ATH9K_INT_TSFOOR; 1080 1081 ath9k_hw_set_interrupts(ah); 1082 1083 /* 1084 * If we are changing the opmode to STATION, 1085 * a beacon sync needs to be done. 1086 */ 1087 if (ah->opmode == NL80211_IFTYPE_STATION && 1088 old_opmode == NL80211_IFTYPE_AP && 1089 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 1090 ieee80211_iterate_active_interfaces_atomic( 1091 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1092 ath9k_sta_vif_iter, sc); 1093 } 1094 } 1095 1096 static int ath9k_add_interface(struct ieee80211_hw *hw, 1097 struct ieee80211_vif *vif) 1098 { 1099 struct ath_softc *sc = hw->priv; 1100 struct ath_hw *ah = sc->sc_ah; 1101 struct ath_common *common = ath9k_hw_common(ah); 1102 struct ath_vif *avp = (void *)vif->drv_priv; 1103 struct ath_node *an = &avp->mcast_node; 1104 1105 mutex_lock(&sc->mutex); 1106 1107 if (config_enabled(CONFIG_ATH9K_TX99)) { 1108 if (sc->nvifs >= 1) { 1109 mutex_unlock(&sc->mutex); 1110 return -EOPNOTSUPP; 1111 } 1112 sc->tx99_vif = vif; 1113 } 1114 1115 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1116 sc->nvifs++; 1117 1118 ath9k_ps_wakeup(sc); 1119 ath9k_calculate_summary_state(hw, vif); 1120 ath9k_ps_restore(sc); 1121 1122 if (ath9k_uses_beacons(vif->type)) 1123 ath9k_beacon_assign_slot(sc, vif); 1124 1125 avp->vif = vif; 1126 1127 an->sc = sc; 1128 an->sta = NULL; 1129 an->vif = vif; 1130 an->no_ps_filter = true; 1131 ath_tx_node_init(sc, an); 1132 1133 mutex_unlock(&sc->mutex); 1134 return 0; 1135 } 1136 1137 static int ath9k_change_interface(struct ieee80211_hw *hw, 1138 struct ieee80211_vif *vif, 1139 enum nl80211_iftype new_type, 1140 bool p2p) 1141 { 1142 struct ath_softc *sc = hw->priv; 1143 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1144 1145 mutex_lock(&sc->mutex); 1146 1147 if (config_enabled(CONFIG_ATH9K_TX99)) { 1148 mutex_unlock(&sc->mutex); 1149 return -EOPNOTSUPP; 1150 } 1151 1152 ath_dbg(common, CONFIG, "Change Interface\n"); 1153 1154 if (ath9k_uses_beacons(vif->type)) 1155 ath9k_beacon_remove_slot(sc, vif); 1156 1157 vif->type = new_type; 1158 vif->p2p = p2p; 1159 1160 ath9k_ps_wakeup(sc); 1161 ath9k_calculate_summary_state(hw, vif); 1162 ath9k_ps_restore(sc); 1163 1164 if (ath9k_uses_beacons(vif->type)) 1165 ath9k_beacon_assign_slot(sc, vif); 1166 1167 mutex_unlock(&sc->mutex); 1168 return 0; 1169 } 1170 1171 static void 1172 ath9k_update_p2p_ps_timer(struct ath_softc *sc, struct ath_vif *avp) 1173 { 1174 struct ath_hw *ah = sc->sc_ah; 1175 s32 tsf, target_tsf; 1176 1177 if (!avp || !avp->noa.has_next_tsf) 1178 return; 1179 1180 ath9k_hw_gen_timer_stop(ah, sc->p2p_ps_timer); 1181 1182 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1183 1184 target_tsf = avp->noa.next_tsf; 1185 if (!avp->noa.absent) 1186 target_tsf -= ATH_P2P_PS_STOP_TIME; 1187 1188 if (target_tsf - tsf < ATH_P2P_PS_STOP_TIME) 1189 target_tsf = tsf + ATH_P2P_PS_STOP_TIME; 1190 1191 ath9k_hw_gen_timer_start(ah, sc->p2p_ps_timer, (u32) target_tsf, 1000000); 1192 } 1193 1194 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1195 struct ieee80211_vif *vif) 1196 { 1197 struct ath_softc *sc = hw->priv; 1198 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1199 struct ath_vif *avp = (void *)vif->drv_priv; 1200 1201 ath_dbg(common, CONFIG, "Detach Interface\n"); 1202 1203 mutex_lock(&sc->mutex); 1204 1205 spin_lock_bh(&sc->sc_pcu_lock); 1206 if (avp == sc->p2p_ps_vif) { 1207 sc->p2p_ps_vif = NULL; 1208 ath9k_update_p2p_ps_timer(sc, NULL); 1209 } 1210 spin_unlock_bh(&sc->sc_pcu_lock); 1211 1212 sc->nvifs--; 1213 sc->tx99_vif = NULL; 1214 1215 if (ath9k_uses_beacons(vif->type)) 1216 ath9k_beacon_remove_slot(sc, vif); 1217 1218 ath9k_ps_wakeup(sc); 1219 ath9k_calculate_summary_state(hw, NULL); 1220 ath9k_ps_restore(sc); 1221 1222 ath_tx_node_cleanup(sc, &avp->mcast_node); 1223 1224 mutex_unlock(&sc->mutex); 1225 } 1226 1227 static void ath9k_enable_ps(struct ath_softc *sc) 1228 { 1229 struct ath_hw *ah = sc->sc_ah; 1230 struct ath_common *common = ath9k_hw_common(ah); 1231 1232 if (config_enabled(CONFIG_ATH9K_TX99)) 1233 return; 1234 1235 sc->ps_enabled = true; 1236 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1237 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1238 ah->imask |= ATH9K_INT_TIM_TIMER; 1239 ath9k_hw_set_interrupts(ah); 1240 } 1241 ath9k_hw_setrxabort(ah, 1); 1242 } 1243 ath_dbg(common, PS, "PowerSave enabled\n"); 1244 } 1245 1246 static void ath9k_disable_ps(struct ath_softc *sc) 1247 { 1248 struct ath_hw *ah = sc->sc_ah; 1249 struct ath_common *common = ath9k_hw_common(ah); 1250 1251 if (config_enabled(CONFIG_ATH9K_TX99)) 1252 return; 1253 1254 sc->ps_enabled = false; 1255 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1256 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1257 ath9k_hw_setrxabort(ah, 0); 1258 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1259 PS_WAIT_FOR_CAB | 1260 PS_WAIT_FOR_PSPOLL_DATA | 1261 PS_WAIT_FOR_TX_ACK); 1262 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1263 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1264 ath9k_hw_set_interrupts(ah); 1265 } 1266 } 1267 ath_dbg(common, PS, "PowerSave disabled\n"); 1268 } 1269 1270 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1271 { 1272 struct ath_softc *sc = hw->priv; 1273 struct ath_hw *ah = sc->sc_ah; 1274 struct ath_common *common = ath9k_hw_common(ah); 1275 u32 rxfilter; 1276 1277 if (config_enabled(CONFIG_ATH9K_TX99)) 1278 return; 1279 1280 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1281 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1282 return; 1283 } 1284 1285 ath9k_ps_wakeup(sc); 1286 rxfilter = ath9k_hw_getrxfilter(ah); 1287 ath9k_hw_setrxfilter(ah, rxfilter | 1288 ATH9K_RX_FILTER_PHYRADAR | 1289 ATH9K_RX_FILTER_PHYERR); 1290 1291 /* TODO: usually this should not be neccesary, but for some reason 1292 * (or in some mode?) the trigger must be called after the 1293 * configuration, otherwise the register will have its values reset 1294 * (on my ar9220 to value 0x01002310) 1295 */ 1296 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1297 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1298 ath9k_ps_restore(sc); 1299 } 1300 1301 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1302 enum spectral_mode spectral_mode) 1303 { 1304 struct ath_softc *sc = hw->priv; 1305 struct ath_hw *ah = sc->sc_ah; 1306 struct ath_common *common = ath9k_hw_common(ah); 1307 1308 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1309 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1310 return -1; 1311 } 1312 1313 switch (spectral_mode) { 1314 case SPECTRAL_DISABLED: 1315 sc->spec_config.enabled = 0; 1316 break; 1317 case SPECTRAL_BACKGROUND: 1318 /* send endless samples. 1319 * TODO: is this really useful for "background"? 1320 */ 1321 sc->spec_config.endless = 1; 1322 sc->spec_config.enabled = 1; 1323 break; 1324 case SPECTRAL_CHANSCAN: 1325 case SPECTRAL_MANUAL: 1326 sc->spec_config.endless = 0; 1327 sc->spec_config.enabled = 1; 1328 break; 1329 default: 1330 return -1; 1331 } 1332 1333 ath9k_ps_wakeup(sc); 1334 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1335 ath9k_ps_restore(sc); 1336 1337 sc->spectral_mode = spectral_mode; 1338 1339 return 0; 1340 } 1341 1342 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1343 { 1344 struct ath_softc *sc = hw->priv; 1345 struct ath_hw *ah = sc->sc_ah; 1346 struct ath_common *common = ath9k_hw_common(ah); 1347 struct ieee80211_conf *conf = &hw->conf; 1348 bool reset_channel = false; 1349 1350 ath9k_ps_wakeup(sc); 1351 mutex_lock(&sc->mutex); 1352 1353 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1354 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1355 if (sc->ps_idle) { 1356 ath_cancel_work(sc); 1357 ath9k_stop_btcoex(sc); 1358 } else { 1359 ath9k_start_btcoex(sc); 1360 /* 1361 * The chip needs a reset to properly wake up from 1362 * full sleep 1363 */ 1364 reset_channel = ah->chip_fullsleep; 1365 } 1366 } 1367 1368 /* 1369 * We just prepare to enable PS. We have to wait until our AP has 1370 * ACK'd our null data frame to disable RX otherwise we'll ignore 1371 * those ACKs and end up retransmitting the same null data frames. 1372 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1373 */ 1374 if (changed & IEEE80211_CONF_CHANGE_PS) { 1375 unsigned long flags; 1376 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1377 if (conf->flags & IEEE80211_CONF_PS) 1378 ath9k_enable_ps(sc); 1379 else 1380 ath9k_disable_ps(sc); 1381 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1382 } 1383 1384 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1385 if (conf->flags & IEEE80211_CONF_MONITOR) { 1386 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1387 sc->sc_ah->is_monitoring = true; 1388 } else { 1389 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1390 sc->sc_ah->is_monitoring = false; 1391 } 1392 } 1393 1394 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1395 if (ath_set_channel(sc, &hw->conf.chandef) < 0) { 1396 ath_err(common, "Unable to set channel\n"); 1397 mutex_unlock(&sc->mutex); 1398 ath9k_ps_restore(sc); 1399 return -EINVAL; 1400 } 1401 } 1402 1403 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1404 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1405 sc->config.txpowlimit = 2 * conf->power_level; 1406 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1407 sc->config.txpowlimit, &sc->curtxpow); 1408 } 1409 1410 mutex_unlock(&sc->mutex); 1411 ath9k_ps_restore(sc); 1412 1413 return 0; 1414 } 1415 1416 #define SUPPORTED_FILTERS \ 1417 (FIF_PROMISC_IN_BSS | \ 1418 FIF_ALLMULTI | \ 1419 FIF_CONTROL | \ 1420 FIF_PSPOLL | \ 1421 FIF_OTHER_BSS | \ 1422 FIF_BCN_PRBRESP_PROMISC | \ 1423 FIF_PROBE_REQ | \ 1424 FIF_FCSFAIL) 1425 1426 /* FIXME: sc->sc_full_reset ? */ 1427 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1428 unsigned int changed_flags, 1429 unsigned int *total_flags, 1430 u64 multicast) 1431 { 1432 struct ath_softc *sc = hw->priv; 1433 u32 rfilt; 1434 1435 changed_flags &= SUPPORTED_FILTERS; 1436 *total_flags &= SUPPORTED_FILTERS; 1437 1438 sc->rx.rxfilter = *total_flags; 1439 ath9k_ps_wakeup(sc); 1440 rfilt = ath_calcrxfilter(sc); 1441 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1442 ath9k_ps_restore(sc); 1443 1444 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1445 rfilt); 1446 } 1447 1448 static int ath9k_sta_add(struct ieee80211_hw *hw, 1449 struct ieee80211_vif *vif, 1450 struct ieee80211_sta *sta) 1451 { 1452 struct ath_softc *sc = hw->priv; 1453 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1454 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1455 struct ieee80211_key_conf ps_key = { }; 1456 int key; 1457 1458 ath_node_attach(sc, sta, vif); 1459 1460 if (vif->type != NL80211_IFTYPE_AP && 1461 vif->type != NL80211_IFTYPE_AP_VLAN) 1462 return 0; 1463 1464 key = ath_key_config(common, vif, sta, &ps_key); 1465 if (key > 0) { 1466 an->ps_key = key; 1467 an->key_idx[0] = key; 1468 } 1469 1470 return 0; 1471 } 1472 1473 static void ath9k_del_ps_key(struct ath_softc *sc, 1474 struct ieee80211_vif *vif, 1475 struct ieee80211_sta *sta) 1476 { 1477 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1478 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1479 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1480 1481 if (!an->ps_key) 1482 return; 1483 1484 ath_key_delete(common, &ps_key); 1485 an->ps_key = 0; 1486 an->key_idx[0] = 0; 1487 } 1488 1489 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1490 struct ieee80211_vif *vif, 1491 struct ieee80211_sta *sta) 1492 { 1493 struct ath_softc *sc = hw->priv; 1494 1495 ath9k_del_ps_key(sc, vif, sta); 1496 ath_node_detach(sc, sta); 1497 1498 return 0; 1499 } 1500 1501 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1502 struct ath_node *an, 1503 bool set) 1504 { 1505 int i; 1506 1507 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1508 if (!an->key_idx[i]) 1509 continue; 1510 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1511 } 1512 } 1513 1514 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1515 struct ieee80211_vif *vif, 1516 enum sta_notify_cmd cmd, 1517 struct ieee80211_sta *sta) 1518 { 1519 struct ath_softc *sc = hw->priv; 1520 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1521 1522 switch (cmd) { 1523 case STA_NOTIFY_SLEEP: 1524 an->sleeping = true; 1525 ath_tx_aggr_sleep(sta, sc, an); 1526 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1527 break; 1528 case STA_NOTIFY_AWAKE: 1529 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1530 an->sleeping = false; 1531 ath_tx_aggr_wakeup(sc, an); 1532 break; 1533 } 1534 } 1535 1536 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1537 struct ieee80211_vif *vif, u16 queue, 1538 const struct ieee80211_tx_queue_params *params) 1539 { 1540 struct ath_softc *sc = hw->priv; 1541 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1542 struct ath_txq *txq; 1543 struct ath9k_tx_queue_info qi; 1544 int ret = 0; 1545 1546 if (queue >= IEEE80211_NUM_ACS) 1547 return 0; 1548 1549 txq = sc->tx.txq_map[queue]; 1550 1551 ath9k_ps_wakeup(sc); 1552 mutex_lock(&sc->mutex); 1553 1554 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1555 1556 qi.tqi_aifs = params->aifs; 1557 qi.tqi_cwmin = params->cw_min; 1558 qi.tqi_cwmax = params->cw_max; 1559 qi.tqi_burstTime = params->txop * 32; 1560 1561 ath_dbg(common, CONFIG, 1562 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1563 queue, txq->axq_qnum, params->aifs, params->cw_min, 1564 params->cw_max, params->txop); 1565 1566 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1567 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1568 if (ret) 1569 ath_err(common, "TXQ Update failed\n"); 1570 1571 mutex_unlock(&sc->mutex); 1572 ath9k_ps_restore(sc); 1573 1574 return ret; 1575 } 1576 1577 static int ath9k_set_key(struct ieee80211_hw *hw, 1578 enum set_key_cmd cmd, 1579 struct ieee80211_vif *vif, 1580 struct ieee80211_sta *sta, 1581 struct ieee80211_key_conf *key) 1582 { 1583 struct ath_softc *sc = hw->priv; 1584 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1585 struct ath_node *an = NULL; 1586 int ret = 0, i; 1587 1588 if (ath9k_modparam_nohwcrypt) 1589 return -ENOSPC; 1590 1591 if ((vif->type == NL80211_IFTYPE_ADHOC || 1592 vif->type == NL80211_IFTYPE_MESH_POINT) && 1593 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1594 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1595 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1596 /* 1597 * For now, disable hw crypto for the RSN IBSS group keys. This 1598 * could be optimized in the future to use a modified key cache 1599 * design to support per-STA RX GTK, but until that gets 1600 * implemented, use of software crypto for group addressed 1601 * frames is a acceptable to allow RSN IBSS to be used. 1602 */ 1603 return -EOPNOTSUPP; 1604 } 1605 1606 mutex_lock(&sc->mutex); 1607 ath9k_ps_wakeup(sc); 1608 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1609 if (sta) 1610 an = (struct ath_node *)sta->drv_priv; 1611 1612 switch (cmd) { 1613 case SET_KEY: 1614 if (sta) 1615 ath9k_del_ps_key(sc, vif, sta); 1616 1617 key->hw_key_idx = 0; 1618 ret = ath_key_config(common, vif, sta, key); 1619 if (ret >= 0) { 1620 key->hw_key_idx = ret; 1621 /* push IV and Michael MIC generation to stack */ 1622 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1623 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1624 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1625 if (sc->sc_ah->sw_mgmt_crypto && 1626 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1627 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1628 ret = 0; 1629 } 1630 if (an && key->hw_key_idx) { 1631 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1632 if (an->key_idx[i]) 1633 continue; 1634 an->key_idx[i] = key->hw_key_idx; 1635 break; 1636 } 1637 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1638 } 1639 break; 1640 case DISABLE_KEY: 1641 ath_key_delete(common, key); 1642 if (an) { 1643 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1644 if (an->key_idx[i] != key->hw_key_idx) 1645 continue; 1646 an->key_idx[i] = 0; 1647 break; 1648 } 1649 } 1650 key->hw_key_idx = 0; 1651 break; 1652 default: 1653 ret = -EINVAL; 1654 } 1655 1656 ath9k_ps_restore(sc); 1657 mutex_unlock(&sc->mutex); 1658 1659 return ret; 1660 } 1661 1662 static void ath9k_set_assoc_state(struct ath_softc *sc, 1663 struct ieee80211_vif *vif) 1664 { 1665 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1666 struct ath_vif *avp = (void *)vif->drv_priv; 1667 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1668 unsigned long flags; 1669 1670 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1671 avp->primary_sta_vif = true; 1672 1673 /* 1674 * Set the AID, BSSID and do beacon-sync only when 1675 * the HW opmode is STATION. 1676 * 1677 * But the primary bit is set above in any case. 1678 */ 1679 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1680 return; 1681 1682 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1683 common->curaid = bss_conf->aid; 1684 ath9k_hw_write_associd(sc->sc_ah); 1685 1686 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1687 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1688 1689 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1690 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1691 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1692 1693 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1694 ath9k_mci_update_wlan_channels(sc, false); 1695 1696 ath_dbg(common, CONFIG, 1697 "Primary Station interface: %pM, BSSID: %pM\n", 1698 vif->addr, common->curbssid); 1699 } 1700 1701 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1702 { 1703 struct ath_softc *sc = data; 1704 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1705 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1706 1707 if (test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) 1708 return; 1709 1710 if (bss_conf->assoc) 1711 ath9k_set_assoc_state(sc, vif); 1712 } 1713 1714 void ath9k_p2p_ps_timer(void *priv) 1715 { 1716 struct ath_softc *sc = priv; 1717 struct ath_vif *avp = sc->p2p_ps_vif; 1718 struct ieee80211_vif *vif; 1719 struct ieee80211_sta *sta; 1720 struct ath_node *an; 1721 u32 tsf; 1722 1723 if (!avp) 1724 return; 1725 1726 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1727 if (!avp->noa.absent) 1728 tsf += ATH_P2P_PS_STOP_TIME; 1729 1730 if (!avp->noa.has_next_tsf || 1731 avp->noa.next_tsf - tsf > BIT(31)) 1732 ieee80211_update_p2p_noa(&avp->noa, tsf); 1733 1734 ath9k_update_p2p_ps_timer(sc, avp); 1735 1736 rcu_read_lock(); 1737 1738 vif = avp->vif; 1739 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 1740 if (!sta) 1741 goto out; 1742 1743 an = (void *) sta->drv_priv; 1744 if (an->sleeping == !!avp->noa.absent) 1745 goto out; 1746 1747 an->sleeping = avp->noa.absent; 1748 if (an->sleeping) 1749 ath_tx_aggr_sleep(sta, sc, an); 1750 else 1751 ath_tx_aggr_wakeup(sc, an); 1752 1753 out: 1754 rcu_read_unlock(); 1755 } 1756 1757 void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif) 1758 { 1759 struct ath_vif *avp = (void *)vif->drv_priv; 1760 u32 tsf; 1761 1762 if (!sc->p2p_ps_timer) 1763 return; 1764 1765 if (vif->type != NL80211_IFTYPE_STATION || !vif->p2p) 1766 return; 1767 1768 sc->p2p_ps_vif = avp; 1769 tsf = ath9k_hw_gettsf32(sc->sc_ah); 1770 ieee80211_parse_p2p_noa(&vif->bss_conf.p2p_noa_attr, &avp->noa, tsf); 1771 ath9k_update_p2p_ps_timer(sc, avp); 1772 } 1773 1774 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1775 struct ieee80211_vif *vif, 1776 struct ieee80211_bss_conf *bss_conf, 1777 u32 changed) 1778 { 1779 #define CHECK_ANI \ 1780 (BSS_CHANGED_ASSOC | \ 1781 BSS_CHANGED_IBSS | \ 1782 BSS_CHANGED_BEACON_ENABLED) 1783 1784 struct ath_softc *sc = hw->priv; 1785 struct ath_hw *ah = sc->sc_ah; 1786 struct ath_common *common = ath9k_hw_common(ah); 1787 struct ath_vif *avp = (void *)vif->drv_priv; 1788 unsigned long flags; 1789 int slottime; 1790 1791 ath9k_ps_wakeup(sc); 1792 mutex_lock(&sc->mutex); 1793 1794 if (changed & BSS_CHANGED_ASSOC) { 1795 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1796 bss_conf->bssid, bss_conf->assoc); 1797 1798 if (avp->primary_sta_vif && !bss_conf->assoc) { 1799 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1800 avp->primary_sta_vif = false; 1801 1802 if (ah->opmode == NL80211_IFTYPE_STATION) 1803 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1804 } 1805 1806 ieee80211_iterate_active_interfaces_atomic( 1807 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1808 ath9k_bss_assoc_iter, sc); 1809 1810 if (!test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags) && 1811 ah->opmode == NL80211_IFTYPE_STATION) { 1812 memset(common->curbssid, 0, ETH_ALEN); 1813 common->curaid = 0; 1814 ath9k_hw_write_associd(sc->sc_ah); 1815 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1816 ath9k_mci_update_wlan_channels(sc, true); 1817 } 1818 } 1819 1820 if (changed & BSS_CHANGED_IBSS) { 1821 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1822 common->curaid = bss_conf->aid; 1823 ath9k_hw_write_associd(sc->sc_ah); 1824 } 1825 1826 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1827 (changed & BSS_CHANGED_BEACON_INT)) 1828 ath9k_beacon_config(sc, vif, changed); 1829 1830 if (changed & BSS_CHANGED_ERP_SLOT) { 1831 if (bss_conf->use_short_slot) 1832 slottime = 9; 1833 else 1834 slottime = 20; 1835 if (vif->type == NL80211_IFTYPE_AP) { 1836 /* 1837 * Defer update, so that connected stations can adjust 1838 * their settings at the same time. 1839 * See beacon.c for more details 1840 */ 1841 sc->beacon.slottime = slottime; 1842 sc->beacon.updateslot = UPDATE; 1843 } else { 1844 ah->slottime = slottime; 1845 ath9k_hw_init_global_settings(ah); 1846 } 1847 } 1848 1849 if (changed & BSS_CHANGED_P2P_PS) { 1850 spin_lock_bh(&sc->sc_pcu_lock); 1851 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1852 if (!(sc->ps_flags & PS_BEACON_SYNC)) 1853 ath9k_update_p2p_ps(sc, vif); 1854 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1855 spin_unlock_bh(&sc->sc_pcu_lock); 1856 } 1857 1858 if (changed & CHECK_ANI) 1859 ath_check_ani(sc); 1860 1861 mutex_unlock(&sc->mutex); 1862 ath9k_ps_restore(sc); 1863 1864 #undef CHECK_ANI 1865 } 1866 1867 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1868 { 1869 struct ath_softc *sc = hw->priv; 1870 u64 tsf; 1871 1872 mutex_lock(&sc->mutex); 1873 ath9k_ps_wakeup(sc); 1874 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1875 ath9k_ps_restore(sc); 1876 mutex_unlock(&sc->mutex); 1877 1878 return tsf; 1879 } 1880 1881 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1882 struct ieee80211_vif *vif, 1883 u64 tsf) 1884 { 1885 struct ath_softc *sc = hw->priv; 1886 1887 mutex_lock(&sc->mutex); 1888 ath9k_ps_wakeup(sc); 1889 ath9k_hw_settsf64(sc->sc_ah, tsf); 1890 ath9k_ps_restore(sc); 1891 mutex_unlock(&sc->mutex); 1892 } 1893 1894 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1895 { 1896 struct ath_softc *sc = hw->priv; 1897 1898 mutex_lock(&sc->mutex); 1899 1900 ath9k_ps_wakeup(sc); 1901 ath9k_hw_reset_tsf(sc->sc_ah); 1902 ath9k_ps_restore(sc); 1903 1904 mutex_unlock(&sc->mutex); 1905 } 1906 1907 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1908 struct ieee80211_vif *vif, 1909 enum ieee80211_ampdu_mlme_action action, 1910 struct ieee80211_sta *sta, 1911 u16 tid, u16 *ssn, u8 buf_size) 1912 { 1913 struct ath_softc *sc = hw->priv; 1914 bool flush = false; 1915 int ret = 0; 1916 1917 mutex_lock(&sc->mutex); 1918 1919 switch (action) { 1920 case IEEE80211_AMPDU_RX_START: 1921 break; 1922 case IEEE80211_AMPDU_RX_STOP: 1923 break; 1924 case IEEE80211_AMPDU_TX_START: 1925 ath9k_ps_wakeup(sc); 1926 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1927 if (!ret) 1928 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1929 ath9k_ps_restore(sc); 1930 break; 1931 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1932 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1933 flush = true; 1934 case IEEE80211_AMPDU_TX_STOP_CONT: 1935 ath9k_ps_wakeup(sc); 1936 ath_tx_aggr_stop(sc, sta, tid); 1937 if (!flush) 1938 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1939 ath9k_ps_restore(sc); 1940 break; 1941 case IEEE80211_AMPDU_TX_OPERATIONAL: 1942 ath9k_ps_wakeup(sc); 1943 ath_tx_aggr_resume(sc, sta, tid); 1944 ath9k_ps_restore(sc); 1945 break; 1946 default: 1947 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1948 } 1949 1950 mutex_unlock(&sc->mutex); 1951 1952 return ret; 1953 } 1954 1955 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1956 struct survey_info *survey) 1957 { 1958 struct ath_softc *sc = hw->priv; 1959 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1960 struct ieee80211_supported_band *sband; 1961 struct ieee80211_channel *chan; 1962 int pos; 1963 1964 if (config_enabled(CONFIG_ATH9K_TX99)) 1965 return -EOPNOTSUPP; 1966 1967 spin_lock_bh(&common->cc_lock); 1968 if (idx == 0) 1969 ath_update_survey_stats(sc); 1970 1971 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1972 if (sband && idx >= sband->n_channels) { 1973 idx -= sband->n_channels; 1974 sband = NULL; 1975 } 1976 1977 if (!sband) 1978 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1979 1980 if (!sband || idx >= sband->n_channels) { 1981 spin_unlock_bh(&common->cc_lock); 1982 return -ENOENT; 1983 } 1984 1985 chan = &sband->channels[idx]; 1986 pos = chan->hw_value; 1987 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1988 survey->channel = chan; 1989 spin_unlock_bh(&common->cc_lock); 1990 1991 return 0; 1992 } 1993 1994 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1995 { 1996 struct ath_softc *sc = hw->priv; 1997 struct ath_hw *ah = sc->sc_ah; 1998 1999 if (config_enabled(CONFIG_ATH9K_TX99)) 2000 return; 2001 2002 mutex_lock(&sc->mutex); 2003 ah->coverage_class = coverage_class; 2004 2005 ath9k_ps_wakeup(sc); 2006 ath9k_hw_init_global_settings(ah); 2007 ath9k_ps_restore(sc); 2008 2009 mutex_unlock(&sc->mutex); 2010 } 2011 2012 static bool ath9k_has_tx_pending(struct ath_softc *sc) 2013 { 2014 int i, npend = 0; 2015 2016 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2017 if (!ATH_TXQ_SETUP(sc, i)) 2018 continue; 2019 2020 if (!sc->tx.txq[i].axq_depth) 2021 continue; 2022 2023 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 2024 if (npend) 2025 break; 2026 } 2027 2028 return !!npend; 2029 } 2030 2031 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2032 u32 queues, bool drop) 2033 { 2034 struct ath_softc *sc = hw->priv; 2035 struct ath_hw *ah = sc->sc_ah; 2036 struct ath_common *common = ath9k_hw_common(ah); 2037 int timeout = HZ / 5; /* 200 ms */ 2038 bool drain_txq; 2039 2040 mutex_lock(&sc->mutex); 2041 cancel_delayed_work_sync(&sc->tx_complete_work); 2042 2043 if (ah->ah_flags & AH_UNPLUGGED) { 2044 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2045 mutex_unlock(&sc->mutex); 2046 return; 2047 } 2048 2049 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2050 ath_dbg(common, ANY, "Device not present\n"); 2051 mutex_unlock(&sc->mutex); 2052 return; 2053 } 2054 2055 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 2056 timeout) > 0) 2057 drop = false; 2058 2059 if (drop) { 2060 ath9k_ps_wakeup(sc); 2061 spin_lock_bh(&sc->sc_pcu_lock); 2062 drain_txq = ath_drain_all_txq(sc); 2063 spin_unlock_bh(&sc->sc_pcu_lock); 2064 2065 if (!drain_txq) 2066 ath_reset(sc); 2067 2068 ath9k_ps_restore(sc); 2069 ieee80211_wake_queues(hw); 2070 } 2071 2072 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2073 mutex_unlock(&sc->mutex); 2074 } 2075 2076 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2077 { 2078 struct ath_softc *sc = hw->priv; 2079 int i; 2080 2081 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2082 if (!ATH_TXQ_SETUP(sc, i)) 2083 continue; 2084 2085 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 2086 return true; 2087 } 2088 return false; 2089 } 2090 2091 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2092 { 2093 struct ath_softc *sc = hw->priv; 2094 struct ath_hw *ah = sc->sc_ah; 2095 struct ieee80211_vif *vif; 2096 struct ath_vif *avp; 2097 struct ath_buf *bf; 2098 struct ath_tx_status ts; 2099 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2100 int status; 2101 2102 vif = sc->beacon.bslot[0]; 2103 if (!vif) 2104 return 0; 2105 2106 if (!vif->bss_conf.enable_beacon) 2107 return 0; 2108 2109 avp = (void *)vif->drv_priv; 2110 2111 if (!sc->beacon.tx_processed && !edma) { 2112 tasklet_disable(&sc->bcon_tasklet); 2113 2114 bf = avp->av_bcbuf; 2115 if (!bf || !bf->bf_mpdu) 2116 goto skip; 2117 2118 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2119 if (status == -EINPROGRESS) 2120 goto skip; 2121 2122 sc->beacon.tx_processed = true; 2123 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2124 2125 skip: 2126 tasklet_enable(&sc->bcon_tasklet); 2127 } 2128 2129 return sc->beacon.tx_last; 2130 } 2131 2132 static int ath9k_get_stats(struct ieee80211_hw *hw, 2133 struct ieee80211_low_level_stats *stats) 2134 { 2135 struct ath_softc *sc = hw->priv; 2136 struct ath_hw *ah = sc->sc_ah; 2137 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2138 2139 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2140 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2141 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2142 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2143 return 0; 2144 } 2145 2146 static u32 fill_chainmask(u32 cap, u32 new) 2147 { 2148 u32 filled = 0; 2149 int i; 2150 2151 for (i = 0; cap && new; i++, cap >>= 1) { 2152 if (!(cap & BIT(0))) 2153 continue; 2154 2155 if (new & BIT(0)) 2156 filled |= BIT(i); 2157 2158 new >>= 1; 2159 } 2160 2161 return filled; 2162 } 2163 2164 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2165 { 2166 if (AR_SREV_9300_20_OR_LATER(ah)) 2167 return true; 2168 2169 switch (val & 0x7) { 2170 case 0x1: 2171 case 0x3: 2172 case 0x7: 2173 return true; 2174 case 0x2: 2175 return (ah->caps.rx_chainmask == 1); 2176 default: 2177 return false; 2178 } 2179 } 2180 2181 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2182 { 2183 struct ath_softc *sc = hw->priv; 2184 struct ath_hw *ah = sc->sc_ah; 2185 2186 if (ah->caps.rx_chainmask != 1) 2187 rx_ant |= tx_ant; 2188 2189 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2190 return -EINVAL; 2191 2192 sc->ant_rx = rx_ant; 2193 sc->ant_tx = tx_ant; 2194 2195 if (ah->caps.rx_chainmask == 1) 2196 return 0; 2197 2198 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2199 if (AR_SREV_9100(ah)) 2200 ah->rxchainmask = 0x7; 2201 else 2202 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2203 2204 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2205 ath9k_cmn_reload_chainmask(ah); 2206 2207 return 0; 2208 } 2209 2210 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2211 { 2212 struct ath_softc *sc = hw->priv; 2213 2214 *tx_ant = sc->ant_tx; 2215 *rx_ant = sc->ant_rx; 2216 return 0; 2217 } 2218 2219 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2220 { 2221 struct ath_softc *sc = hw->priv; 2222 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2223 set_bit(ATH_OP_SCANNING, &common->op_flags); 2224 } 2225 2226 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2227 { 2228 struct ath_softc *sc = hw->priv; 2229 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2230 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2231 } 2232 2233 struct ieee80211_ops ath9k_ops = { 2234 .tx = ath9k_tx, 2235 .start = ath9k_start, 2236 .stop = ath9k_stop, 2237 .add_interface = ath9k_add_interface, 2238 .change_interface = ath9k_change_interface, 2239 .remove_interface = ath9k_remove_interface, 2240 .config = ath9k_config, 2241 .configure_filter = ath9k_configure_filter, 2242 .sta_add = ath9k_sta_add, 2243 .sta_remove = ath9k_sta_remove, 2244 .sta_notify = ath9k_sta_notify, 2245 .conf_tx = ath9k_conf_tx, 2246 .bss_info_changed = ath9k_bss_info_changed, 2247 .set_key = ath9k_set_key, 2248 .get_tsf = ath9k_get_tsf, 2249 .set_tsf = ath9k_set_tsf, 2250 .reset_tsf = ath9k_reset_tsf, 2251 .ampdu_action = ath9k_ampdu_action, 2252 .get_survey = ath9k_get_survey, 2253 .rfkill_poll = ath9k_rfkill_poll_state, 2254 .set_coverage_class = ath9k_set_coverage_class, 2255 .flush = ath9k_flush, 2256 .tx_frames_pending = ath9k_tx_frames_pending, 2257 .tx_last_beacon = ath9k_tx_last_beacon, 2258 .release_buffered_frames = ath9k_release_buffered_frames, 2259 .get_stats = ath9k_get_stats, 2260 .set_antenna = ath9k_set_antenna, 2261 .get_antenna = ath9k_get_antenna, 2262 2263 #ifdef CONFIG_ATH9K_WOW 2264 .suspend = ath9k_suspend, 2265 .resume = ath9k_resume, 2266 .set_wakeup = ath9k_set_wakeup, 2267 #endif 2268 2269 #ifdef CONFIG_ATH9K_DEBUGFS 2270 .get_et_sset_count = ath9k_get_et_sset_count, 2271 .get_et_stats = ath9k_get_et_stats, 2272 .get_et_strings = ath9k_get_et_strings, 2273 #endif 2274 2275 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2276 .sta_add_debugfs = ath9k_sta_add_debugfs, 2277 #endif 2278 .sw_scan_start = ath9k_sw_scan_start, 2279 .sw_scan_complete = ath9k_sw_scan_complete, 2280 }; 2281