1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 23 u32 queues, bool drop); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq, 61 bool sw_pending) 62 { 63 bool pending = false; 64 65 spin_lock_bh(&txq->axq_lock); 66 67 if (txq->axq_depth) { 68 pending = true; 69 goto out; 70 } 71 72 if (!sw_pending) 73 goto out; 74 75 if (txq->mac80211_qnum >= 0) { 76 struct ath_acq *acq; 77 78 acq = &sc->cur_chan->acq[txq->mac80211_qnum]; 79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old)) 80 pending = true; 81 } 82 out: 83 spin_unlock_bh(&txq->axq_lock); 84 return pending; 85 } 86 87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 88 { 89 unsigned long flags; 90 bool ret; 91 92 spin_lock_irqsave(&sc->sc_pm_lock, flags); 93 ret = ath9k_hw_setpower(sc->sc_ah, mode); 94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 95 96 return ret; 97 } 98 99 void ath_ps_full_sleep(struct timer_list *t) 100 { 101 struct ath_softc *sc = from_timer(sc, t, sleep_timer); 102 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 103 unsigned long flags; 104 bool reset; 105 106 spin_lock_irqsave(&common->cc_lock, flags); 107 ath_hw_cycle_counters_update(common); 108 spin_unlock_irqrestore(&common->cc_lock, flags); 109 110 ath9k_hw_setrxabort(sc->sc_ah, 1); 111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 112 113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 114 } 115 116 void ath9k_ps_wakeup(struct ath_softc *sc) 117 { 118 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 119 unsigned long flags; 120 enum ath9k_power_mode power_mode; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (++sc->ps_usecount != 1) 124 goto unlock; 125 126 del_timer_sync(&sc->sleep_timer); 127 power_mode = sc->sc_ah->power_mode; 128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 129 130 /* 131 * While the hardware is asleep, the cycle counters contain no 132 * useful data. Better clear them now so that they don't mess up 133 * survey data results. 134 */ 135 if (power_mode != ATH9K_PM_AWAKE) { 136 spin_lock(&common->cc_lock); 137 ath_hw_cycle_counters_update(common); 138 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 139 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 140 spin_unlock(&common->cc_lock); 141 } 142 143 unlock: 144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 145 } 146 147 void ath9k_ps_restore(struct ath_softc *sc) 148 { 149 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 150 enum ath9k_power_mode mode; 151 unsigned long flags; 152 153 spin_lock_irqsave(&sc->sc_pm_lock, flags); 154 if (--sc->ps_usecount != 0) 155 goto unlock; 156 157 if (sc->ps_idle) { 158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 159 goto unlock; 160 } 161 162 if (sc->ps_enabled && 163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 164 PS_WAIT_FOR_CAB | 165 PS_WAIT_FOR_PSPOLL_DATA | 166 PS_WAIT_FOR_TX_ACK | 167 PS_WAIT_FOR_ANI))) { 168 mode = ATH9K_PM_NETWORK_SLEEP; 169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 170 ath9k_btcoex_stop_gen_timer(sc); 171 } else { 172 goto unlock; 173 } 174 175 spin_lock(&common->cc_lock); 176 ath_hw_cycle_counters_update(common); 177 spin_unlock(&common->cc_lock); 178 179 ath9k_hw_setpower(sc->sc_ah, mode); 180 181 unlock: 182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 183 } 184 185 static void __ath_cancel_work(struct ath_softc *sc) 186 { 187 cancel_work_sync(&sc->paprd_work); 188 cancel_delayed_work_sync(&sc->hw_check_work); 189 cancel_delayed_work_sync(&sc->hw_pll_work); 190 191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 192 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 193 cancel_work_sync(&sc->mci_work); 194 #endif 195 } 196 197 void ath_cancel_work(struct ath_softc *sc) 198 { 199 __ath_cancel_work(sc); 200 cancel_work_sync(&sc->hw_reset_work); 201 } 202 203 void ath_restart_work(struct ath_softc *sc) 204 { 205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, 206 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); 207 208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 211 212 ath_start_ani(sc); 213 } 214 215 static bool ath_prepare_reset(struct ath_softc *sc) 216 { 217 struct ath_hw *ah = sc->sc_ah; 218 bool ret = true; 219 220 ieee80211_stop_queues(sc->hw); 221 ath_stop_ani(sc); 222 ath9k_hw_disable_interrupts(ah); 223 224 if (AR_SREV_9300_20_OR_LATER(ah)) { 225 ret &= ath_stoprecv(sc); 226 ret &= ath_drain_all_txq(sc); 227 } else { 228 ret &= ath_drain_all_txq(sc); 229 ret &= ath_stoprecv(sc); 230 } 231 232 return ret; 233 } 234 235 static bool ath_complete_reset(struct ath_softc *sc, bool start) 236 { 237 struct ath_hw *ah = sc->sc_ah; 238 struct ath_common *common = ath9k_hw_common(ah); 239 unsigned long flags; 240 241 ath9k_calculate_summary_state(sc, sc->cur_chan); 242 ath_startrecv(sc); 243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 244 sc->cur_chan->txpower, 245 &sc->cur_chan->cur_txpower); 246 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 247 248 if (!sc->cur_chan->offchannel && start) { 249 /* restore per chanctx TSF timer */ 250 if (sc->cur_chan->tsf_val) { 251 u32 offset; 252 253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 254 NULL); 255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 256 } 257 258 259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 260 goto work; 261 262 if (ah->opmode == NL80211_IFTYPE_STATION && 263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 264 spin_lock_irqsave(&sc->sc_pm_lock, flags); 265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 267 } else { 268 ath9k_set_beacon(sc); 269 } 270 work: 271 ath_restart_work(sc); 272 ath_txq_schedule_all(sc); 273 } 274 275 sc->gtt_cnt = 0; 276 277 ath9k_hw_set_interrupts(ah); 278 ath9k_hw_enable_interrupts(ah); 279 ieee80211_wake_queues(sc->hw); 280 ath9k_p2p_ps_timer(sc); 281 282 return true; 283 } 284 285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 286 { 287 struct ath_hw *ah = sc->sc_ah; 288 struct ath_common *common = ath9k_hw_common(ah); 289 struct ath9k_hw_cal_data *caldata = NULL; 290 bool fastcc = true; 291 int r; 292 293 __ath_cancel_work(sc); 294 295 disable_irq(sc->irq); 296 tasklet_disable(&sc->intr_tq); 297 tasklet_disable(&sc->bcon_tasklet); 298 spin_lock_bh(&sc->sc_pcu_lock); 299 300 if (!sc->cur_chan->offchannel) { 301 fastcc = false; 302 caldata = &sc->cur_chan->caldata; 303 } 304 305 if (!hchan) { 306 fastcc = false; 307 hchan = ah->curchan; 308 } 309 310 if (!hchan) { 311 fastcc = false; 312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef); 313 } 314 315 if (!ath_prepare_reset(sc)) 316 fastcc = false; 317 318 if (ath9k_is_chanctx_enabled()) 319 fastcc = false; 320 321 spin_lock_bh(&sc->chan_lock); 322 sc->cur_chandef = sc->cur_chan->chandef; 323 spin_unlock_bh(&sc->chan_lock); 324 325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 326 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 327 328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 329 if (r) { 330 ath_err(common, 331 "Unable to reset channel, reset status %d\n", r); 332 333 ath9k_hw_enable_interrupts(ah); 334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 335 336 goto out; 337 } 338 339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 340 sc->cur_chan->offchannel) 341 ath9k_mci_set_txpower(sc, true, false); 342 343 if (!ath_complete_reset(sc, true)) 344 r = -EIO; 345 346 out: 347 enable_irq(sc->irq); 348 spin_unlock_bh(&sc->sc_pcu_lock); 349 tasklet_enable(&sc->bcon_tasklet); 350 tasklet_enable(&sc->intr_tq); 351 352 return r; 353 } 354 355 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 356 struct ieee80211_vif *vif) 357 { 358 struct ath_node *an; 359 an = (struct ath_node *)sta->drv_priv; 360 361 an->sc = sc; 362 an->sta = sta; 363 an->vif = vif; 364 memset(&an->key_idx, 0, sizeof(an->key_idx)); 365 366 ath_tx_node_init(sc, an); 367 368 ath_dynack_node_init(sc->sc_ah, an); 369 } 370 371 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 372 { 373 struct ath_node *an = (struct ath_node *)sta->drv_priv; 374 ath_tx_node_cleanup(sc, an); 375 376 ath_dynack_node_deinit(sc->sc_ah, an); 377 } 378 379 void ath9k_tasklet(struct tasklet_struct *t) 380 { 381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq); 382 struct ath_hw *ah = sc->sc_ah; 383 struct ath_common *common = ath9k_hw_common(ah); 384 enum ath_reset_type type; 385 unsigned long flags; 386 u32 status; 387 u32 rxmask; 388 389 spin_lock_irqsave(&sc->intr_lock, flags); 390 status = sc->intrstatus; 391 sc->intrstatus = 0; 392 spin_unlock_irqrestore(&sc->intr_lock, flags); 393 394 ath9k_ps_wakeup(sc); 395 spin_lock(&sc->sc_pcu_lock); 396 397 if (status & ATH9K_INT_FATAL) { 398 type = RESET_TYPE_FATAL_INT; 399 ath9k_queue_reset(sc, type); 400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 401 goto out; 402 } 403 404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 405 (status & ATH9K_INT_BB_WATCHDOG)) { 406 spin_lock_irqsave(&common->cc_lock, flags); 407 ath_hw_cycle_counters_update(common); 408 ar9003_hw_bb_watchdog_dbg_info(ah); 409 spin_unlock_irqrestore(&common->cc_lock, flags); 410 411 if (ar9003_hw_bb_watchdog_check(ah)) { 412 type = RESET_TYPE_BB_WATCHDOG; 413 ath9k_queue_reset(sc, type); 414 415 ath_dbg(common, RESET, 416 "BB_WATCHDOG: Skipping interrupts\n"); 417 goto out; 418 } 419 } 420 421 if (status & ATH9K_INT_GTT) { 422 sc->gtt_cnt++; 423 424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 425 type = RESET_TYPE_TX_GTT; 426 ath9k_queue_reset(sc, type); 427 ath_dbg(common, RESET, 428 "GTT: Skipping interrupts\n"); 429 goto out; 430 } 431 } 432 433 spin_lock_irqsave(&sc->sc_pm_lock, flags); 434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 435 /* 436 * TSF sync does not look correct; remain awake to sync with 437 * the next Beacon. 438 */ 439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 441 } 442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 443 444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 446 ATH9K_INT_RXORN); 447 else 448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 449 450 if (status & rxmask) { 451 /* Check for high priority Rx first */ 452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 453 (status & ATH9K_INT_RXHP)) 454 ath_rx_tasklet(sc, 0, true); 455 456 ath_rx_tasklet(sc, 0, false); 457 } 458 459 if (status & ATH9K_INT_TX) { 460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 461 /* 462 * For EDMA chips, TX completion is enabled for the 463 * beacon queue, so if a beacon has been transmitted 464 * successfully after a GTT interrupt, the GTT counter 465 * gets reset to zero here. 466 */ 467 sc->gtt_cnt = 0; 468 469 ath_tx_edma_tasklet(sc); 470 } else { 471 ath_tx_tasklet(sc); 472 } 473 474 wake_up(&sc->tx_wait); 475 } 476 477 if (status & ATH9K_INT_GENTIMER) 478 ath_gen_timer_isr(sc->sc_ah); 479 480 ath9k_btcoex_handle_interrupt(sc, status); 481 482 /* re-enable hardware interrupt */ 483 ath9k_hw_resume_interrupts(ah); 484 out: 485 spin_unlock(&sc->sc_pcu_lock); 486 ath9k_ps_restore(sc); 487 } 488 489 irqreturn_t ath_isr(int irq, void *dev) 490 { 491 #define SCHED_INTR ( \ 492 ATH9K_INT_FATAL | \ 493 ATH9K_INT_BB_WATCHDOG | \ 494 ATH9K_INT_RXORN | \ 495 ATH9K_INT_RXEOL | \ 496 ATH9K_INT_RX | \ 497 ATH9K_INT_RXLP | \ 498 ATH9K_INT_RXHP | \ 499 ATH9K_INT_TX | \ 500 ATH9K_INT_BMISS | \ 501 ATH9K_INT_CST | \ 502 ATH9K_INT_GTT | \ 503 ATH9K_INT_TSFOOR | \ 504 ATH9K_INT_GENTIMER | \ 505 ATH9K_INT_MCI) 506 507 struct ath_softc *sc = dev; 508 struct ath_hw *ah = sc->sc_ah; 509 struct ath_common *common = ath9k_hw_common(ah); 510 enum ath9k_int status; 511 u32 sync_cause = 0; 512 bool sched = false; 513 514 /* 515 * The hardware is not ready/present, don't 516 * touch anything. Note this can happen early 517 * on if the IRQ is shared. 518 */ 519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 520 return IRQ_NONE; 521 522 /* shared irq, not for us */ 523 if (!ath9k_hw_intrpend(ah)) 524 return IRQ_NONE; 525 526 /* 527 * Figure out the reason(s) for the interrupt. Note 528 * that the hal returns a pseudo-ISR that may include 529 * bits we haven't explicitly enabled so we mask the 530 * value to insure we only process bits we requested. 531 */ 532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 533 ath9k_debug_sync_cause(sc, sync_cause); 534 status &= ah->imask; /* discard unasked-for bits */ 535 536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 537 ath9k_hw_kill_interrupts(sc->sc_ah); 538 return IRQ_HANDLED; 539 } 540 541 /* 542 * If there are no status bits set, then this interrupt was not 543 * for me (should have been caught above). 544 */ 545 if (!status) 546 return IRQ_NONE; 547 548 /* Cache the status */ 549 spin_lock(&sc->intr_lock); 550 sc->intrstatus |= status; 551 spin_unlock(&sc->intr_lock); 552 553 if (status & SCHED_INTR) 554 sched = true; 555 556 /* 557 * If a FATAL interrupt is received, we have to reset the chip 558 * immediately. 559 */ 560 if (status & ATH9K_INT_FATAL) 561 goto chip_reset; 562 563 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 564 (status & ATH9K_INT_BB_WATCHDOG)) 565 goto chip_reset; 566 567 if (status & ATH9K_INT_SWBA) 568 tasklet_schedule(&sc->bcon_tasklet); 569 570 if (status & ATH9K_INT_TXURN) 571 ath9k_hw_updatetxtriglevel(ah, true); 572 573 if (status & ATH9K_INT_RXEOL) { 574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 575 ath9k_hw_set_interrupts(ah); 576 } 577 578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 579 if (status & ATH9K_INT_TIM_TIMER) { 580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 581 goto chip_reset; 582 /* Clear RxAbort bit so that we can 583 * receive frames */ 584 ath9k_setpower(sc, ATH9K_PM_AWAKE); 585 spin_lock(&sc->sc_pm_lock); 586 ath9k_hw_setrxabort(sc->sc_ah, 0); 587 sc->ps_flags |= PS_WAIT_FOR_BEACON; 588 spin_unlock(&sc->sc_pm_lock); 589 } 590 591 chip_reset: 592 593 ath_debug_stat_interrupt(sc, status); 594 595 if (sched) { 596 /* turn off every interrupt */ 597 ath9k_hw_kill_interrupts(ah); 598 tasklet_schedule(&sc->intr_tq); 599 } 600 601 return IRQ_HANDLED; 602 603 #undef SCHED_INTR 604 } 605 606 /* 607 * This function is called when a HW reset cannot be deferred 608 * and has to be immediate. 609 */ 610 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan) 611 { 612 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 613 int r; 614 615 ath9k_hw_kill_interrupts(sc->sc_ah); 616 set_bit(ATH_OP_HW_RESET, &common->op_flags); 617 618 ath9k_ps_wakeup(sc); 619 r = ath_reset_internal(sc, hchan); 620 ath9k_ps_restore(sc); 621 622 return r; 623 } 624 625 /* 626 * When a HW reset can be deferred, it is added to the 627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before 628 * queueing. 629 */ 630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 631 { 632 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 633 #ifdef CONFIG_ATH9K_DEBUGFS 634 RESET_STAT_INC(sc, type); 635 #endif 636 ath9k_hw_kill_interrupts(sc->sc_ah); 637 set_bit(ATH_OP_HW_RESET, &common->op_flags); 638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 639 } 640 641 void ath_reset_work(struct work_struct *work) 642 { 643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 644 645 ath9k_ps_wakeup(sc); 646 ath_reset_internal(sc, NULL); 647 ath9k_ps_restore(sc); 648 } 649 650 /**********************/ 651 /* mac80211 callbacks */ 652 /**********************/ 653 654 static int ath9k_start(struct ieee80211_hw *hw) 655 { 656 struct ath_softc *sc = hw->priv; 657 struct ath_hw *ah = sc->sc_ah; 658 struct ath_common *common = ath9k_hw_common(ah); 659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 660 struct ath_chanctx *ctx = sc->cur_chan; 661 struct ath9k_channel *init_channel; 662 int r; 663 664 ath_dbg(common, CONFIG, 665 "Starting driver with initial channel: %d MHz\n", 666 curchan->center_freq); 667 668 ath9k_ps_wakeup(sc); 669 mutex_lock(&sc->mutex); 670 671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 672 sc->cur_chandef = hw->conf.chandef; 673 674 /* Reset SERDES registers */ 675 ath9k_hw_configpcipowersave(ah, false); 676 677 /* 678 * The basic interface to setting the hardware in a good 679 * state is ``reset''. On return the hardware is known to 680 * be powered up and with interrupts disabled. This must 681 * be followed by initialization of the appropriate bits 682 * and then setup of the interrupt mask. 683 */ 684 spin_lock_bh(&sc->sc_pcu_lock); 685 686 atomic_set(&ah->intr_ref_cnt, -1); 687 688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 689 if (r) { 690 ath_err(common, 691 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 692 r, curchan->center_freq); 693 ah->reset_power_on = false; 694 } 695 696 /* Setup our intr mask. */ 697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 698 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 699 ATH9K_INT_GLOBAL; 700 701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 702 ah->imask |= ATH9K_INT_RXHP | 703 ATH9K_INT_RXLP; 704 else 705 ah->imask |= ATH9K_INT_RX; 706 707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 708 ah->imask |= ATH9K_INT_BB_WATCHDOG; 709 710 /* 711 * Enable GTT interrupts only for AR9003/AR9004 chips 712 * for now. 713 */ 714 if (AR_SREV_9300_20_OR_LATER(ah)) 715 ah->imask |= ATH9K_INT_GTT; 716 717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 718 ah->imask |= ATH9K_INT_CST; 719 720 ath_mci_enable(sc); 721 722 clear_bit(ATH_OP_INVALID, &common->op_flags); 723 sc->sc_ah->is_monitoring = false; 724 725 if (!ath_complete_reset(sc, false)) 726 ah->reset_power_on = false; 727 728 if (ah->led_pin >= 0) { 729 ath9k_hw_set_gpio(ah, ah->led_pin, 730 (ah->config.led_active_high) ? 1 : 0); 731 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL, 732 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 733 } 734 735 /* 736 * Reset key cache to sane defaults (all entries cleared) instead of 737 * semi-random values after suspend/resume. 738 */ 739 ath9k_cmn_init_crypto(sc->sc_ah); 740 741 ath9k_hw_reset_tsf(ah); 742 743 spin_unlock_bh(&sc->sc_pcu_lock); 744 745 ath9k_rng_start(sc); 746 747 mutex_unlock(&sc->mutex); 748 749 ath9k_ps_restore(sc); 750 751 return 0; 752 } 753 754 static void ath9k_tx(struct ieee80211_hw *hw, 755 struct ieee80211_tx_control *control, 756 struct sk_buff *skb) 757 { 758 struct ath_softc *sc = hw->priv; 759 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 760 struct ath_tx_control txctl; 761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 762 unsigned long flags; 763 764 if (sc->ps_enabled) { 765 /* 766 * mac80211 does not set PM field for normal data frames, so we 767 * need to update that based on the current PS mode. 768 */ 769 if (ieee80211_is_data(hdr->frame_control) && 770 !ieee80211_is_nullfunc(hdr->frame_control) && 771 !ieee80211_has_pm(hdr->frame_control)) { 772 ath_dbg(common, PS, 773 "Add PM=1 for a TX frame while in PS mode\n"); 774 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 775 } 776 } 777 778 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 779 /* 780 * We are using PS-Poll and mac80211 can request TX while in 781 * power save mode. Need to wake up hardware for the TX to be 782 * completed and if needed, also for RX of buffered frames. 783 */ 784 ath9k_ps_wakeup(sc); 785 spin_lock_irqsave(&sc->sc_pm_lock, flags); 786 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 787 ath9k_hw_setrxabort(sc->sc_ah, 0); 788 if (ieee80211_is_pspoll(hdr->frame_control)) { 789 ath_dbg(common, PS, 790 "Sending PS-Poll to pick a buffered frame\n"); 791 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 792 } else { 793 ath_dbg(common, PS, "Wake up to complete TX\n"); 794 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 795 } 796 /* 797 * The actual restore operation will happen only after 798 * the ps_flags bit is cleared. We are just dropping 799 * the ps_usecount here. 800 */ 801 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 802 ath9k_ps_restore(sc); 803 } 804 805 /* 806 * Cannot tx while the hardware is in full sleep, it first needs a full 807 * chip reset to recover from that 808 */ 809 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 810 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 811 goto exit; 812 } 813 814 memset(&txctl, 0, sizeof(struct ath_tx_control)); 815 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 816 txctl.sta = control->sta; 817 818 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 819 820 if (ath_tx_start(hw, skb, &txctl) != 0) { 821 ath_dbg(common, XMIT, "TX failed\n"); 822 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed); 823 goto exit; 824 } 825 826 return; 827 exit: 828 ieee80211_free_txskb(hw, skb); 829 } 830 831 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix) 832 { 833 struct ath_buf *bf; 834 struct ieee80211_tx_info *txinfo; 835 struct ath_frame_info *fi; 836 837 list_for_each_entry(bf, txq_list, list) { 838 if (bf->bf_state.stale || !bf->bf_mpdu) 839 continue; 840 841 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu); 842 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0]; 843 if (fi->keyix == keyix) 844 return true; 845 } 846 847 return false; 848 } 849 850 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) 851 { 852 struct ath_hw *ah = sc->sc_ah; 853 int i, j; 854 struct ath_txq *txq; 855 bool key_in_use = false; 856 857 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) { 858 if (!ATH_TXQ_SETUP(sc, i)) 859 continue; 860 txq = &sc->tx.txq[i]; 861 if (!txq->axq_depth) 862 continue; 863 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum)) 864 continue; 865 866 ath_txq_lock(sc, txq); 867 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix); 868 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 869 int idx = txq->txq_tailidx; 870 871 for (j = 0; !key_in_use && 872 !list_empty(&txq->txq_fifo[idx]) && 873 j < ATH_TXFIFO_DEPTH; j++) { 874 key_in_use = ath9k_txq_list_has_key( 875 &txq->txq_fifo[idx], keyix); 876 INCR(idx, ATH_TXFIFO_DEPTH); 877 } 878 } 879 ath_txq_unlock(sc, txq); 880 } 881 882 return key_in_use; 883 } 884 885 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix) 886 { 887 struct ath_hw *ah = sc->sc_ah; 888 struct ath_common *common = ath9k_hw_common(ah); 889 890 if (!test_bit(keyix, ah->pending_del_keymap) || 891 ath9k_txq_has_key(sc, keyix)) 892 return; 893 894 /* No more TXQ frames point to this key cache entry, so delete it. */ 895 clear_bit(keyix, ah->pending_del_keymap); 896 ath_key_delete(common, keyix); 897 } 898 899 static void ath9k_stop(struct ieee80211_hw *hw) 900 { 901 struct ath_softc *sc = hw->priv; 902 struct ath_hw *ah = sc->sc_ah; 903 struct ath_common *common = ath9k_hw_common(ah); 904 bool prev_idle; 905 int i; 906 907 ath9k_deinit_channel_context(sc); 908 909 mutex_lock(&sc->mutex); 910 911 ath9k_rng_stop(sc); 912 913 ath_cancel_work(sc); 914 915 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 916 ath_dbg(common, ANY, "Device not present\n"); 917 mutex_unlock(&sc->mutex); 918 return; 919 } 920 921 /* Ensure HW is awake when we try to shut it down. */ 922 ath9k_ps_wakeup(sc); 923 924 spin_lock_bh(&sc->sc_pcu_lock); 925 926 /* prevent tasklets to enable interrupts once we disable them */ 927 ah->imask &= ~ATH9K_INT_GLOBAL; 928 929 /* make sure h/w will not generate any interrupt 930 * before setting the invalid flag. */ 931 ath9k_hw_disable_interrupts(ah); 932 933 spin_unlock_bh(&sc->sc_pcu_lock); 934 935 /* we can now sync irq and kill any running tasklets, since we already 936 * disabled interrupts and not holding a spin lock */ 937 synchronize_irq(sc->irq); 938 tasklet_kill(&sc->intr_tq); 939 tasklet_kill(&sc->bcon_tasklet); 940 941 prev_idle = sc->ps_idle; 942 sc->ps_idle = true; 943 944 spin_lock_bh(&sc->sc_pcu_lock); 945 946 if (ah->led_pin >= 0) { 947 ath9k_hw_set_gpio(ah, ah->led_pin, 948 (ah->config.led_active_high) ? 0 : 1); 949 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL); 950 } 951 952 ath_prepare_reset(sc); 953 954 if (sc->rx.frag) { 955 dev_kfree_skb_any(sc->rx.frag); 956 sc->rx.frag = NULL; 957 } 958 959 if (!ah->curchan) 960 ah->curchan = ath9k_cmn_get_channel(hw, ah, 961 &sc->cur_chan->chandef); 962 963 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 964 965 set_bit(ATH_OP_INVALID, &common->op_flags); 966 967 ath9k_hw_phy_disable(ah); 968 969 ath9k_hw_configpcipowersave(ah, true); 970 971 spin_unlock_bh(&sc->sc_pcu_lock); 972 973 for (i = 0; i < ATH_KEYMAX; i++) 974 ath9k_pending_key_del(sc, i); 975 976 /* Clear key cache entries explicitly to get rid of any potentially 977 * remaining keys. 978 */ 979 ath9k_cmn_init_crypto(sc->sc_ah); 980 981 ath9k_ps_restore(sc); 982 983 sc->ps_idle = prev_idle; 984 985 mutex_unlock(&sc->mutex); 986 987 ath_dbg(common, CONFIG, "Driver halt\n"); 988 } 989 990 static bool ath9k_uses_beacons(int type) 991 { 992 switch (type) { 993 case NL80211_IFTYPE_AP: 994 case NL80211_IFTYPE_ADHOC: 995 case NL80211_IFTYPE_MESH_POINT: 996 return true; 997 default: 998 return false; 999 } 1000 } 1001 1002 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data, 1003 struct ieee80211_vif *vif) 1004 { 1005 /* Use the first (configured) interface, but prefering AP interfaces. */ 1006 if (!iter_data->primary_beacon_vif) { 1007 iter_data->primary_beacon_vif = vif; 1008 } else { 1009 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP && 1010 vif->type == NL80211_IFTYPE_AP) 1011 iter_data->primary_beacon_vif = vif; 1012 } 1013 1014 iter_data->beacons = true; 1015 iter_data->nbcnvifs += 1; 1016 } 1017 1018 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 1019 u8 *mac, struct ieee80211_vif *vif) 1020 { 1021 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 1022 int i; 1023 1024 if (iter_data->has_hw_macaddr) { 1025 for (i = 0; i < ETH_ALEN; i++) 1026 iter_data->mask[i] &= 1027 ~(iter_data->hw_macaddr[i] ^ mac[i]); 1028 } else { 1029 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 1030 iter_data->has_hw_macaddr = true; 1031 } 1032 1033 if (!vif->bss_conf.use_short_slot) 1034 iter_data->slottime = 20; 1035 1036 switch (vif->type) { 1037 case NL80211_IFTYPE_AP: 1038 iter_data->naps++; 1039 if (vif->bss_conf.enable_beacon) 1040 ath9k_vif_iter_set_beacon(iter_data, vif); 1041 break; 1042 case NL80211_IFTYPE_STATION: 1043 iter_data->nstations++; 1044 if (avp->assoc && !iter_data->primary_sta) 1045 iter_data->primary_sta = vif; 1046 break; 1047 case NL80211_IFTYPE_OCB: 1048 iter_data->nocbs++; 1049 break; 1050 case NL80211_IFTYPE_ADHOC: 1051 iter_data->nadhocs++; 1052 if (vif->bss_conf.enable_beacon) 1053 ath9k_vif_iter_set_beacon(iter_data, vif); 1054 break; 1055 case NL80211_IFTYPE_MESH_POINT: 1056 iter_data->nmeshes++; 1057 if (vif->bss_conf.enable_beacon) 1058 ath9k_vif_iter_set_beacon(iter_data, vif); 1059 break; 1060 default: 1061 break; 1062 } 1063 } 1064 1065 static void ath9k_update_bssid_mask(struct ath_softc *sc, 1066 struct ath_chanctx *ctx, 1067 struct ath9k_vif_iter_data *iter_data) 1068 { 1069 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1070 struct ath_vif *avp; 1071 int i; 1072 1073 if (!ath9k_is_chanctx_enabled()) 1074 return; 1075 1076 list_for_each_entry(avp, &ctx->vifs, list) { 1077 if (ctx->nvifs_assigned != 1) 1078 continue; 1079 1080 if (!iter_data->has_hw_macaddr) 1081 continue; 1082 1083 ether_addr_copy(common->curbssid, avp->bssid); 1084 1085 /* perm_addr will be used as the p2p device address. */ 1086 for (i = 0; i < ETH_ALEN; i++) 1087 iter_data->mask[i] &= 1088 ~(iter_data->hw_macaddr[i] ^ 1089 sc->hw->wiphy->perm_addr[i]); 1090 } 1091 } 1092 1093 /* Called with sc->mutex held. */ 1094 void ath9k_calculate_iter_data(struct ath_softc *sc, 1095 struct ath_chanctx *ctx, 1096 struct ath9k_vif_iter_data *iter_data) 1097 { 1098 struct ath_vif *avp; 1099 1100 /* 1101 * The hardware will use primary station addr together with the 1102 * BSSID mask when matching addresses. 1103 */ 1104 memset(iter_data, 0, sizeof(*iter_data)); 1105 eth_broadcast_addr(iter_data->mask); 1106 iter_data->slottime = 9; 1107 1108 list_for_each_entry(avp, &ctx->vifs, list) 1109 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 1110 1111 ath9k_update_bssid_mask(sc, ctx, iter_data); 1112 } 1113 1114 static void ath9k_set_assoc_state(struct ath_softc *sc, 1115 struct ieee80211_vif *vif, bool changed) 1116 { 1117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1118 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 1119 unsigned long flags; 1120 1121 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1122 1123 ether_addr_copy(common->curbssid, avp->bssid); 1124 common->curaid = avp->aid; 1125 ath9k_hw_write_associd(sc->sc_ah); 1126 1127 if (changed) { 1128 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1129 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1130 1131 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1132 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1134 } 1135 1136 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1137 ath9k_mci_update_wlan_channels(sc, false); 1138 1139 ath_dbg(common, CONFIG, 1140 "Primary Station interface: %pM, BSSID: %pM\n", 1141 vif->addr, common->curbssid); 1142 } 1143 1144 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1145 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1146 { 1147 struct ath_hw *ah = sc->sc_ah; 1148 struct ath_common *common = ath9k_hw_common(ah); 1149 struct ieee80211_vif *vif = NULL; 1150 1151 ath9k_ps_wakeup(sc); 1152 1153 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1154 vif = sc->offchannel.scan_vif; 1155 else 1156 vif = sc->offchannel.roc_vif; 1157 1158 if (WARN_ON(!vif)) 1159 goto exit; 1160 1161 eth_zero_addr(common->curbssid); 1162 eth_broadcast_addr(common->bssidmask); 1163 memcpy(common->macaddr, vif->addr, ETH_ALEN); 1164 common->curaid = 0; 1165 ah->opmode = vif->type; 1166 ah->imask &= ~ATH9K_INT_SWBA; 1167 ah->imask &= ~ATH9K_INT_TSFOOR; 1168 ah->slottime = 9; 1169 1170 ath_hw_setbssidmask(common); 1171 ath9k_hw_setopmode(ah); 1172 ath9k_hw_write_associd(sc->sc_ah); 1173 ath9k_hw_set_interrupts(ah); 1174 ath9k_hw_init_global_settings(ah); 1175 1176 exit: 1177 ath9k_ps_restore(sc); 1178 } 1179 #endif 1180 1181 /* Called with sc->mutex held. */ 1182 void ath9k_calculate_summary_state(struct ath_softc *sc, 1183 struct ath_chanctx *ctx) 1184 { 1185 struct ath_hw *ah = sc->sc_ah; 1186 struct ath_common *common = ath9k_hw_common(ah); 1187 struct ath9k_vif_iter_data iter_data; 1188 1189 ath_chanctx_check_active(sc, ctx); 1190 1191 if (ctx != sc->cur_chan) 1192 return; 1193 1194 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1195 if (ctx == &sc->offchannel.chan) 1196 return ath9k_set_offchannel_state(sc); 1197 #endif 1198 1199 ath9k_ps_wakeup(sc); 1200 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1201 1202 if (iter_data.has_hw_macaddr) 1203 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN); 1204 1205 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1206 ath_hw_setbssidmask(common); 1207 1208 if (iter_data.naps > 0) { 1209 ath9k_hw_set_tsfadjust(ah, true); 1210 ah->opmode = NL80211_IFTYPE_AP; 1211 } else { 1212 ath9k_hw_set_tsfadjust(ah, false); 1213 if (iter_data.beacons) 1214 ath9k_beacon_ensure_primary_slot(sc); 1215 1216 if (iter_data.nmeshes) 1217 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1218 else if (iter_data.nocbs) 1219 ah->opmode = NL80211_IFTYPE_OCB; 1220 else if (iter_data.nadhocs) 1221 ah->opmode = NL80211_IFTYPE_ADHOC; 1222 else 1223 ah->opmode = NL80211_IFTYPE_STATION; 1224 } 1225 1226 ath9k_hw_setopmode(ah); 1227 1228 ctx->switch_after_beacon = false; 1229 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1230 ah->imask |= ATH9K_INT_TSFOOR; 1231 else { 1232 ah->imask &= ~ATH9K_INT_TSFOOR; 1233 if (iter_data.naps == 1 && iter_data.beacons) 1234 ctx->switch_after_beacon = true; 1235 } 1236 1237 if (ah->opmode == NL80211_IFTYPE_STATION) { 1238 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1239 1240 if (iter_data.primary_sta) { 1241 iter_data.primary_beacon_vif = iter_data.primary_sta; 1242 iter_data.beacons = true; 1243 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1244 changed); 1245 ctx->primary_sta = iter_data.primary_sta; 1246 } else { 1247 ctx->primary_sta = NULL; 1248 eth_zero_addr(common->curbssid); 1249 common->curaid = 0; 1250 ath9k_hw_write_associd(sc->sc_ah); 1251 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1252 ath9k_mci_update_wlan_channels(sc, true); 1253 } 1254 } 1255 sc->nbcnvifs = iter_data.nbcnvifs; 1256 ath9k_beacon_config(sc, iter_data.primary_beacon_vif, 1257 iter_data.beacons); 1258 ath9k_hw_set_interrupts(ah); 1259 1260 if (ah->slottime != iter_data.slottime) { 1261 ah->slottime = iter_data.slottime; 1262 ath9k_hw_init_global_settings(ah); 1263 } 1264 1265 if (iter_data.primary_sta) 1266 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1267 else 1268 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1269 1270 ath_dbg(common, CONFIG, 1271 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1272 common->macaddr, common->curbssid, common->bssidmask); 1273 1274 ath9k_ps_restore(sc); 1275 } 1276 1277 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1278 { 1279 int *power = data; 1280 1281 if (vif->bss_conf.txpower == INT_MIN) 1282 return; 1283 1284 if (*power < vif->bss_conf.txpower) 1285 *power = vif->bss_conf.txpower; 1286 } 1287 1288 /* Called with sc->mutex held. */ 1289 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif) 1290 { 1291 int power; 1292 struct ath_hw *ah = sc->sc_ah; 1293 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 1294 1295 ath9k_ps_wakeup(sc); 1296 if (ah->tpc_enabled) { 1297 power = (vif) ? vif->bss_conf.txpower : -1; 1298 ieee80211_iterate_active_interfaces_atomic( 1299 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1300 ath9k_tpc_vif_iter, &power); 1301 if (power == -1) 1302 power = sc->hw->conf.power_level; 1303 } else { 1304 power = sc->hw->conf.power_level; 1305 } 1306 sc->cur_chan->txpower = 2 * power; 1307 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 1308 sc->cur_chan->cur_txpower = reg->max_power_level; 1309 ath9k_ps_restore(sc); 1310 } 1311 1312 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1313 struct ieee80211_vif *vif) 1314 { 1315 int i; 1316 1317 if (!ath9k_is_chanctx_enabled()) 1318 return; 1319 1320 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1321 vif->hw_queue[i] = i; 1322 1323 if (vif->type == NL80211_IFTYPE_AP || 1324 vif->type == NL80211_IFTYPE_MESH_POINT) 1325 vif->cab_queue = hw->queues - 2; 1326 else 1327 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1328 } 1329 1330 static int ath9k_add_interface(struct ieee80211_hw *hw, 1331 struct ieee80211_vif *vif) 1332 { 1333 struct ath_softc *sc = hw->priv; 1334 struct ath_hw *ah = sc->sc_ah; 1335 struct ath_common *common = ath9k_hw_common(ah); 1336 struct ath_vif *avp = (void *)vif->drv_priv; 1337 struct ath_node *an = &avp->mcast_node; 1338 1339 mutex_lock(&sc->mutex); 1340 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1341 if (sc->cur_chan->nvifs >= 1) { 1342 mutex_unlock(&sc->mutex); 1343 return -EOPNOTSUPP; 1344 } 1345 sc->tx99_vif = vif; 1346 } 1347 1348 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1349 sc->cur_chan->nvifs++; 1350 1351 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled()) 1352 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE; 1353 1354 if (ath9k_uses_beacons(vif->type)) 1355 ath9k_beacon_assign_slot(sc, vif); 1356 1357 avp->vif = vif; 1358 if (!ath9k_is_chanctx_enabled()) { 1359 avp->chanctx = sc->cur_chan; 1360 list_add_tail(&avp->list, &avp->chanctx->vifs); 1361 } 1362 1363 ath9k_calculate_summary_state(sc, avp->chanctx); 1364 1365 ath9k_assign_hw_queues(hw, vif); 1366 1367 ath9k_set_txpower(sc, vif); 1368 1369 an->sc = sc; 1370 an->sta = NULL; 1371 an->vif = vif; 1372 an->no_ps_filter = true; 1373 ath_tx_node_init(sc, an); 1374 1375 mutex_unlock(&sc->mutex); 1376 return 0; 1377 } 1378 1379 static int ath9k_change_interface(struct ieee80211_hw *hw, 1380 struct ieee80211_vif *vif, 1381 enum nl80211_iftype new_type, 1382 bool p2p) 1383 { 1384 struct ath_softc *sc = hw->priv; 1385 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1386 struct ath_vif *avp = (void *)vif->drv_priv; 1387 1388 mutex_lock(&sc->mutex); 1389 1390 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1391 mutex_unlock(&sc->mutex); 1392 return -EOPNOTSUPP; 1393 } 1394 1395 ath_dbg(common, CONFIG, "Change Interface\n"); 1396 1397 if (ath9k_uses_beacons(vif->type)) 1398 ath9k_beacon_remove_slot(sc, vif); 1399 1400 vif->type = new_type; 1401 vif->p2p = p2p; 1402 1403 if (ath9k_uses_beacons(vif->type)) 1404 ath9k_beacon_assign_slot(sc, vif); 1405 1406 ath9k_assign_hw_queues(hw, vif); 1407 ath9k_calculate_summary_state(sc, avp->chanctx); 1408 1409 ath9k_set_txpower(sc, vif); 1410 1411 mutex_unlock(&sc->mutex); 1412 return 0; 1413 } 1414 1415 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1416 struct ieee80211_vif *vif) 1417 { 1418 struct ath_softc *sc = hw->priv; 1419 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1420 struct ath_vif *avp = (void *)vif->drv_priv; 1421 1422 ath_dbg(common, CONFIG, "Detach Interface\n"); 1423 1424 mutex_lock(&sc->mutex); 1425 1426 ath9k_p2p_remove_vif(sc, vif); 1427 1428 sc->cur_chan->nvifs--; 1429 sc->tx99_vif = NULL; 1430 if (!ath9k_is_chanctx_enabled()) 1431 list_del(&avp->list); 1432 1433 if (ath9k_uses_beacons(vif->type)) 1434 ath9k_beacon_remove_slot(sc, vif); 1435 1436 ath_tx_node_cleanup(sc, &avp->mcast_node); 1437 1438 ath9k_calculate_summary_state(sc, avp->chanctx); 1439 1440 ath9k_set_txpower(sc, NULL); 1441 1442 mutex_unlock(&sc->mutex); 1443 } 1444 1445 static void ath9k_enable_ps(struct ath_softc *sc) 1446 { 1447 struct ath_hw *ah = sc->sc_ah; 1448 struct ath_common *common = ath9k_hw_common(ah); 1449 1450 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1451 return; 1452 1453 sc->ps_enabled = true; 1454 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1455 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1456 ah->imask |= ATH9K_INT_TIM_TIMER; 1457 ath9k_hw_set_interrupts(ah); 1458 } 1459 ath9k_hw_setrxabort(ah, 1); 1460 } 1461 ath_dbg(common, PS, "PowerSave enabled\n"); 1462 } 1463 1464 static void ath9k_disable_ps(struct ath_softc *sc) 1465 { 1466 struct ath_hw *ah = sc->sc_ah; 1467 struct ath_common *common = ath9k_hw_common(ah); 1468 1469 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1470 return; 1471 1472 sc->ps_enabled = false; 1473 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1474 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1475 ath9k_hw_setrxabort(ah, 0); 1476 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1477 PS_WAIT_FOR_CAB | 1478 PS_WAIT_FOR_PSPOLL_DATA | 1479 PS_WAIT_FOR_TX_ACK); 1480 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1481 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1482 ath9k_hw_set_interrupts(ah); 1483 } 1484 } 1485 ath_dbg(common, PS, "PowerSave disabled\n"); 1486 } 1487 1488 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1489 { 1490 struct ath_softc *sc = hw->priv; 1491 struct ath_hw *ah = sc->sc_ah; 1492 struct ath_common *common = ath9k_hw_common(ah); 1493 struct ieee80211_conf *conf = &hw->conf; 1494 struct ath_chanctx *ctx = sc->cur_chan; 1495 1496 ath9k_ps_wakeup(sc); 1497 mutex_lock(&sc->mutex); 1498 1499 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1500 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1501 if (sc->ps_idle) { 1502 ath_cancel_work(sc); 1503 ath9k_stop_btcoex(sc); 1504 } else { 1505 ath9k_start_btcoex(sc); 1506 /* 1507 * The chip needs a reset to properly wake up from 1508 * full sleep 1509 */ 1510 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1511 } 1512 } 1513 1514 /* 1515 * We just prepare to enable PS. We have to wait until our AP has 1516 * ACK'd our null data frame to disable RX otherwise we'll ignore 1517 * those ACKs and end up retransmitting the same null data frames. 1518 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1519 */ 1520 if (changed & IEEE80211_CONF_CHANGE_PS) { 1521 unsigned long flags; 1522 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1523 if (conf->flags & IEEE80211_CONF_PS) 1524 ath9k_enable_ps(sc); 1525 else 1526 ath9k_disable_ps(sc); 1527 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1528 } 1529 1530 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1531 if (conf->flags & IEEE80211_CONF_MONITOR) { 1532 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1533 sc->sc_ah->is_monitoring = true; 1534 } else { 1535 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1536 sc->sc_ah->is_monitoring = false; 1537 } 1538 } 1539 1540 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1541 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1542 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1543 } 1544 1545 if (changed & IEEE80211_CONF_CHANGE_POWER) 1546 ath9k_set_txpower(sc, NULL); 1547 1548 mutex_unlock(&sc->mutex); 1549 ath9k_ps_restore(sc); 1550 1551 return 0; 1552 } 1553 1554 #define SUPPORTED_FILTERS \ 1555 (FIF_ALLMULTI | \ 1556 FIF_CONTROL | \ 1557 FIF_PSPOLL | \ 1558 FIF_OTHER_BSS | \ 1559 FIF_BCN_PRBRESP_PROMISC | \ 1560 FIF_PROBE_REQ | \ 1561 FIF_MCAST_ACTION | \ 1562 FIF_FCSFAIL) 1563 1564 /* FIXME: sc->sc_full_reset ? */ 1565 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1566 unsigned int changed_flags, 1567 unsigned int *total_flags, 1568 u64 multicast) 1569 { 1570 struct ath_softc *sc = hw->priv; 1571 struct ath_chanctx *ctx; 1572 u32 rfilt; 1573 1574 changed_flags &= SUPPORTED_FILTERS; 1575 *total_flags &= SUPPORTED_FILTERS; 1576 1577 spin_lock_bh(&sc->chan_lock); 1578 ath_for_each_chanctx(sc, ctx) 1579 ctx->rxfilter = *total_flags; 1580 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1581 sc->offchannel.chan.rxfilter = *total_flags; 1582 #endif 1583 spin_unlock_bh(&sc->chan_lock); 1584 1585 ath9k_ps_wakeup(sc); 1586 rfilt = ath_calcrxfilter(sc); 1587 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1588 ath9k_ps_restore(sc); 1589 1590 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1591 rfilt); 1592 } 1593 1594 static int ath9k_sta_add(struct ieee80211_hw *hw, 1595 struct ieee80211_vif *vif, 1596 struct ieee80211_sta *sta) 1597 { 1598 struct ath_softc *sc = hw->priv; 1599 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1600 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1601 struct ieee80211_key_conf ps_key = { }; 1602 int key; 1603 1604 ath_node_attach(sc, sta, vif); 1605 1606 if (vif->type != NL80211_IFTYPE_AP && 1607 vif->type != NL80211_IFTYPE_AP_VLAN) 1608 return 0; 1609 1610 key = ath_key_config(common, vif, sta, &ps_key); 1611 if (key > 0) { 1612 an->ps_key = key; 1613 an->key_idx[0] = key; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static void ath9k_del_ps_key(struct ath_softc *sc, 1620 struct ieee80211_vif *vif, 1621 struct ieee80211_sta *sta) 1622 { 1623 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1624 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1625 1626 if (!an->ps_key) 1627 return; 1628 1629 ath_key_delete(common, an->ps_key); 1630 an->ps_key = 0; 1631 an->key_idx[0] = 0; 1632 } 1633 1634 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1635 struct ieee80211_vif *vif, 1636 struct ieee80211_sta *sta) 1637 { 1638 struct ath_softc *sc = hw->priv; 1639 1640 ath9k_del_ps_key(sc, vif, sta); 1641 ath_node_detach(sc, sta); 1642 1643 return 0; 1644 } 1645 1646 static int ath9k_sta_state(struct ieee80211_hw *hw, 1647 struct ieee80211_vif *vif, 1648 struct ieee80211_sta *sta, 1649 enum ieee80211_sta_state old_state, 1650 enum ieee80211_sta_state new_state) 1651 { 1652 struct ath_softc *sc = hw->priv; 1653 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1654 int ret = 0; 1655 1656 if (old_state == IEEE80211_STA_NOTEXIST && 1657 new_state == IEEE80211_STA_NONE) { 1658 ret = ath9k_sta_add(hw, vif, sta); 1659 ath_dbg(common, CONFIG, 1660 "Add station: %pM\n", sta->addr); 1661 } else if (old_state == IEEE80211_STA_NONE && 1662 new_state == IEEE80211_STA_NOTEXIST) { 1663 ret = ath9k_sta_remove(hw, vif, sta); 1664 ath_dbg(common, CONFIG, 1665 "Remove station: %pM\n", sta->addr); 1666 } 1667 1668 if (ath9k_is_chanctx_enabled()) { 1669 if (vif->type == NL80211_IFTYPE_STATION) { 1670 if (old_state == IEEE80211_STA_ASSOC && 1671 new_state == IEEE80211_STA_AUTHORIZED) 1672 ath_chanctx_event(sc, vif, 1673 ATH_CHANCTX_EVENT_AUTHORIZED); 1674 } 1675 } 1676 1677 return ret; 1678 } 1679 1680 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1681 struct ath_node *an, 1682 bool set) 1683 { 1684 int i; 1685 1686 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1687 if (!an->key_idx[i]) 1688 continue; 1689 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1690 } 1691 } 1692 1693 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1694 struct ieee80211_vif *vif, 1695 enum sta_notify_cmd cmd, 1696 struct ieee80211_sta *sta) 1697 { 1698 struct ath_softc *sc = hw->priv; 1699 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1700 1701 switch (cmd) { 1702 case STA_NOTIFY_SLEEP: 1703 an->sleeping = true; 1704 ath_tx_aggr_sleep(sta, sc, an); 1705 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1706 break; 1707 case STA_NOTIFY_AWAKE: 1708 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1709 an->sleeping = false; 1710 ath_tx_aggr_wakeup(sc, an); 1711 break; 1712 } 1713 } 1714 1715 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1716 struct ieee80211_vif *vif, 1717 unsigned int link_id, u16 queue, 1718 const struct ieee80211_tx_queue_params *params) 1719 { 1720 struct ath_softc *sc = hw->priv; 1721 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1722 struct ath_txq *txq; 1723 struct ath9k_tx_queue_info qi; 1724 int ret = 0; 1725 1726 if (queue >= IEEE80211_NUM_ACS) 1727 return 0; 1728 1729 txq = sc->tx.txq_map[queue]; 1730 1731 ath9k_ps_wakeup(sc); 1732 mutex_lock(&sc->mutex); 1733 1734 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1735 1736 qi.tqi_aifs = params->aifs; 1737 qi.tqi_cwmin = params->cw_min; 1738 qi.tqi_cwmax = params->cw_max; 1739 qi.tqi_burstTime = params->txop * 32; 1740 1741 ath_dbg(common, CONFIG, 1742 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1743 queue, txq->axq_qnum, params->aifs, params->cw_min, 1744 params->cw_max, params->txop); 1745 1746 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1747 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1748 if (ret) 1749 ath_err(common, "TXQ Update failed\n"); 1750 1751 mutex_unlock(&sc->mutex); 1752 ath9k_ps_restore(sc); 1753 1754 return ret; 1755 } 1756 1757 static int ath9k_set_key(struct ieee80211_hw *hw, 1758 enum set_key_cmd cmd, 1759 struct ieee80211_vif *vif, 1760 struct ieee80211_sta *sta, 1761 struct ieee80211_key_conf *key) 1762 { 1763 struct ath_softc *sc = hw->priv; 1764 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1765 struct ath_node *an = NULL; 1766 int ret = 0, i; 1767 1768 if (ath9k_modparam_nohwcrypt) 1769 return -ENOSPC; 1770 1771 if ((vif->type == NL80211_IFTYPE_ADHOC || 1772 vif->type == NL80211_IFTYPE_MESH_POINT) && 1773 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1774 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1775 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1776 /* 1777 * For now, disable hw crypto for the RSN IBSS group keys. This 1778 * could be optimized in the future to use a modified key cache 1779 * design to support per-STA RX GTK, but until that gets 1780 * implemented, use of software crypto for group addressed 1781 * frames is a acceptable to allow RSN IBSS to be used. 1782 */ 1783 return -EOPNOTSUPP; 1784 } 1785 1786 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to 1787 * make sure these are not send unencrypted or with a wrong (new) key 1788 */ 1789 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 1790 ieee80211_stop_queues(hw); 1791 ath9k_flush(hw, vif, 0, true); 1792 ieee80211_wake_queues(hw); 1793 } 1794 1795 mutex_lock(&sc->mutex); 1796 ath9k_ps_wakeup(sc); 1797 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1798 if (sta) 1799 an = (struct ath_node *)sta->drv_priv; 1800 1801 /* Delete pending key cache entries if no more frames are pointing to 1802 * them in TXQs. 1803 */ 1804 for (i = 0; i < ATH_KEYMAX; i++) 1805 ath9k_pending_key_del(sc, i); 1806 1807 switch (cmd) { 1808 case SET_KEY: 1809 if (sta) 1810 ath9k_del_ps_key(sc, vif, sta); 1811 1812 key->hw_key_idx = 0; 1813 ret = ath_key_config(common, vif, sta, key); 1814 if (ret >= 0) { 1815 key->hw_key_idx = ret; 1816 /* push IV and Michael MIC generation to stack */ 1817 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1818 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1819 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1820 if (sc->sc_ah->sw_mgmt_crypto_tx && 1821 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1822 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1823 ret = 0; 1824 } 1825 if (an && key->hw_key_idx) { 1826 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1827 if (an->key_idx[i]) 1828 continue; 1829 an->key_idx[i] = key->hw_key_idx; 1830 break; 1831 } 1832 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1833 } 1834 break; 1835 case DISABLE_KEY: 1836 if (ath9k_txq_has_key(sc, key->hw_key_idx)) { 1837 /* Delay key cache entry deletion until there are no 1838 * remaining TXQ frames pointing to this entry. 1839 */ 1840 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap); 1841 ath_hw_keysetmac(common, key->hw_key_idx, NULL); 1842 } else { 1843 ath_key_delete(common, key->hw_key_idx); 1844 } 1845 if (an) { 1846 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1847 if (an->key_idx[i] != key->hw_key_idx) 1848 continue; 1849 an->key_idx[i] = 0; 1850 break; 1851 } 1852 } 1853 key->hw_key_idx = 0; 1854 break; 1855 default: 1856 ret = -EINVAL; 1857 } 1858 1859 ath9k_ps_restore(sc); 1860 mutex_unlock(&sc->mutex); 1861 1862 return ret; 1863 } 1864 1865 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1866 struct ieee80211_vif *vif, 1867 struct ieee80211_bss_conf *bss_conf, 1868 u64 changed) 1869 { 1870 #define CHECK_ANI \ 1871 (BSS_CHANGED_ASSOC | \ 1872 BSS_CHANGED_IBSS | \ 1873 BSS_CHANGED_BEACON_ENABLED) 1874 1875 struct ath_softc *sc = hw->priv; 1876 struct ath_hw *ah = sc->sc_ah; 1877 struct ath_common *common = ath9k_hw_common(ah); 1878 struct ath_vif *avp = (void *)vif->drv_priv; 1879 int slottime; 1880 1881 ath9k_ps_wakeup(sc); 1882 mutex_lock(&sc->mutex); 1883 1884 if (changed & BSS_CHANGED_ASSOC) { 1885 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1886 bss_conf->bssid, vif->cfg.assoc); 1887 1888 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1889 avp->aid = vif->cfg.aid; 1890 avp->assoc = vif->cfg.assoc; 1891 1892 ath9k_calculate_summary_state(sc, avp->chanctx); 1893 } 1894 1895 if ((changed & BSS_CHANGED_IBSS) || 1896 (changed & BSS_CHANGED_OCB)) { 1897 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1898 common->curaid = vif->cfg.aid; 1899 ath9k_hw_write_associd(sc->sc_ah); 1900 } 1901 1902 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1903 (changed & BSS_CHANGED_BEACON_INT) || 1904 (changed & BSS_CHANGED_BEACON_INFO)) { 1905 ath9k_calculate_summary_state(sc, avp->chanctx); 1906 } 1907 1908 if ((avp->chanctx == sc->cur_chan) && 1909 (changed & BSS_CHANGED_ERP_SLOT)) { 1910 if (bss_conf->use_short_slot) 1911 slottime = 9; 1912 else 1913 slottime = 20; 1914 1915 if (vif->type == NL80211_IFTYPE_AP) { 1916 /* 1917 * Defer update, so that connected stations can adjust 1918 * their settings at the same time. 1919 * See beacon.c for more details 1920 */ 1921 sc->beacon.slottime = slottime; 1922 sc->beacon.updateslot = UPDATE; 1923 } else { 1924 ah->slottime = slottime; 1925 ath9k_hw_init_global_settings(ah); 1926 } 1927 } 1928 1929 if (changed & BSS_CHANGED_P2P_PS) 1930 ath9k_p2p_bss_info_changed(sc, vif); 1931 1932 if (changed & CHECK_ANI) 1933 ath_check_ani(sc); 1934 1935 if (changed & BSS_CHANGED_TXPOWER) { 1936 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n", 1937 vif->addr, bss_conf->txpower, bss_conf->txpower_type); 1938 ath9k_set_txpower(sc, vif); 1939 } 1940 1941 mutex_unlock(&sc->mutex); 1942 ath9k_ps_restore(sc); 1943 1944 #undef CHECK_ANI 1945 } 1946 1947 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1948 { 1949 struct ath_softc *sc = hw->priv; 1950 struct ath_vif *avp = (void *)vif->drv_priv; 1951 u64 tsf; 1952 1953 mutex_lock(&sc->mutex); 1954 ath9k_ps_wakeup(sc); 1955 /* Get current TSF either from HW or kernel time. */ 1956 if (sc->cur_chan == avp->chanctx) { 1957 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1958 } else { 1959 tsf = sc->cur_chan->tsf_val + 1960 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL); 1961 } 1962 tsf += le64_to_cpu(avp->tsf_adjust); 1963 ath9k_ps_restore(sc); 1964 mutex_unlock(&sc->mutex); 1965 1966 return tsf; 1967 } 1968 1969 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1970 struct ieee80211_vif *vif, 1971 u64 tsf) 1972 { 1973 struct ath_softc *sc = hw->priv; 1974 struct ath_vif *avp = (void *)vif->drv_priv; 1975 1976 mutex_lock(&sc->mutex); 1977 ath9k_ps_wakeup(sc); 1978 tsf -= le64_to_cpu(avp->tsf_adjust); 1979 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1980 if (sc->cur_chan == avp->chanctx) 1981 ath9k_hw_settsf64(sc->sc_ah, tsf); 1982 avp->chanctx->tsf_val = tsf; 1983 ath9k_ps_restore(sc); 1984 mutex_unlock(&sc->mutex); 1985 } 1986 1987 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1988 { 1989 struct ath_softc *sc = hw->priv; 1990 struct ath_vif *avp = (void *)vif->drv_priv; 1991 1992 mutex_lock(&sc->mutex); 1993 1994 ath9k_ps_wakeup(sc); 1995 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1996 if (sc->cur_chan == avp->chanctx) 1997 ath9k_hw_reset_tsf(sc->sc_ah); 1998 avp->chanctx->tsf_val = 0; 1999 ath9k_ps_restore(sc); 2000 2001 mutex_unlock(&sc->mutex); 2002 } 2003 2004 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 2005 struct ieee80211_vif *vif, 2006 struct ieee80211_ampdu_params *params) 2007 { 2008 struct ath_softc *sc = hw->priv; 2009 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2010 bool flush = false; 2011 int ret = 0; 2012 struct ieee80211_sta *sta = params->sta; 2013 struct ath_node *an = (struct ath_node *)sta->drv_priv; 2014 enum ieee80211_ampdu_mlme_action action = params->action; 2015 u16 tid = params->tid; 2016 u16 *ssn = ¶ms->ssn; 2017 struct ath_atx_tid *atid; 2018 2019 mutex_lock(&sc->mutex); 2020 2021 switch (action) { 2022 case IEEE80211_AMPDU_RX_START: 2023 break; 2024 case IEEE80211_AMPDU_RX_STOP: 2025 break; 2026 case IEEE80211_AMPDU_TX_START: 2027 if (ath9k_is_chanctx_enabled()) { 2028 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 2029 ret = -EBUSY; 2030 break; 2031 } 2032 } 2033 ath9k_ps_wakeup(sc); 2034 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 2035 if (!ret) 2036 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 2037 ath9k_ps_restore(sc); 2038 break; 2039 case IEEE80211_AMPDU_TX_STOP_FLUSH: 2040 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 2041 flush = true; 2042 fallthrough; 2043 case IEEE80211_AMPDU_TX_STOP_CONT: 2044 ath9k_ps_wakeup(sc); 2045 ath_tx_aggr_stop(sc, sta, tid); 2046 if (!flush) 2047 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2048 ath9k_ps_restore(sc); 2049 break; 2050 case IEEE80211_AMPDU_TX_OPERATIONAL: 2051 atid = ath_node_to_tid(an, tid); 2052 atid->baw_size = IEEE80211_MIN_AMPDU_BUF << 2053 sta->deflink.ht_cap.ampdu_factor; 2054 break; 2055 default: 2056 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 2057 } 2058 2059 mutex_unlock(&sc->mutex); 2060 2061 return ret; 2062 } 2063 2064 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 2065 struct survey_info *survey) 2066 { 2067 struct ath_softc *sc = hw->priv; 2068 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2069 struct ieee80211_supported_band *sband; 2070 struct ieee80211_channel *chan; 2071 unsigned long flags; 2072 int pos; 2073 2074 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 2075 return -EOPNOTSUPP; 2076 2077 spin_lock_irqsave(&common->cc_lock, flags); 2078 if (idx == 0) 2079 ath_update_survey_stats(sc); 2080 2081 sband = hw->wiphy->bands[NL80211_BAND_2GHZ]; 2082 if (sband && idx >= sband->n_channels) { 2083 idx -= sband->n_channels; 2084 sband = NULL; 2085 } 2086 2087 if (!sband) 2088 sband = hw->wiphy->bands[NL80211_BAND_5GHZ]; 2089 2090 if (!sband || idx >= sband->n_channels) { 2091 spin_unlock_irqrestore(&common->cc_lock, flags); 2092 return -ENOENT; 2093 } 2094 2095 chan = &sband->channels[idx]; 2096 pos = chan->hw_value; 2097 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 2098 survey->channel = chan; 2099 spin_unlock_irqrestore(&common->cc_lock, flags); 2100 2101 return 0; 2102 } 2103 2104 static void ath9k_enable_dynack(struct ath_softc *sc) 2105 { 2106 #ifdef CONFIG_ATH9K_DYNACK 2107 u32 rfilt; 2108 struct ath_hw *ah = sc->sc_ah; 2109 2110 ath_dynack_reset(ah); 2111 2112 ah->dynack.enabled = true; 2113 rfilt = ath_calcrxfilter(sc); 2114 ath9k_hw_setrxfilter(ah, rfilt); 2115 #endif 2116 } 2117 2118 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 2119 s16 coverage_class) 2120 { 2121 struct ath_softc *sc = hw->priv; 2122 struct ath_hw *ah = sc->sc_ah; 2123 2124 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 2125 return; 2126 2127 mutex_lock(&sc->mutex); 2128 2129 if (coverage_class >= 0) { 2130 ah->coverage_class = coverage_class; 2131 if (ah->dynack.enabled) { 2132 u32 rfilt; 2133 2134 ah->dynack.enabled = false; 2135 rfilt = ath_calcrxfilter(sc); 2136 ath9k_hw_setrxfilter(ah, rfilt); 2137 } 2138 ath9k_ps_wakeup(sc); 2139 ath9k_hw_init_global_settings(ah); 2140 ath9k_ps_restore(sc); 2141 } else if (!ah->dynack.enabled) { 2142 ath9k_enable_dynack(sc); 2143 } 2144 2145 mutex_unlock(&sc->mutex); 2146 } 2147 2148 static bool ath9k_has_tx_pending(struct ath_softc *sc, 2149 bool sw_pending) 2150 { 2151 int i, npend = 0; 2152 2153 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2154 if (!ATH_TXQ_SETUP(sc, i)) 2155 continue; 2156 2157 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i], 2158 sw_pending); 2159 if (npend) 2160 break; 2161 } 2162 2163 return !!npend; 2164 } 2165 2166 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2167 u32 queues, bool drop) 2168 { 2169 struct ath_softc *sc = hw->priv; 2170 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2171 2172 if (ath9k_is_chanctx_enabled()) { 2173 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2174 goto flush; 2175 2176 /* 2177 * If MCC is active, extend the flush timeout 2178 * and wait for the HW/SW queues to become 2179 * empty. This needs to be done outside the 2180 * sc->mutex lock to allow the channel scheduler 2181 * to switch channel contexts. 2182 * 2183 * The vif queues have been stopped in mac80211, 2184 * so there won't be any incoming frames. 2185 */ 2186 __ath9k_flush(hw, queues, drop, true, true); 2187 return; 2188 } 2189 flush: 2190 mutex_lock(&sc->mutex); 2191 __ath9k_flush(hw, queues, drop, true, false); 2192 mutex_unlock(&sc->mutex); 2193 } 2194 2195 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, 2196 bool sw_pending, bool timeout_override) 2197 { 2198 struct ath_softc *sc = hw->priv; 2199 struct ath_hw *ah = sc->sc_ah; 2200 struct ath_common *common = ath9k_hw_common(ah); 2201 int timeout; 2202 bool drain_txq; 2203 2204 cancel_delayed_work_sync(&sc->hw_check_work); 2205 2206 if (ah->ah_flags & AH_UNPLUGGED) { 2207 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2208 return; 2209 } 2210 2211 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2212 ath_dbg(common, ANY, "Device not present\n"); 2213 return; 2214 } 2215 2216 spin_lock_bh(&sc->chan_lock); 2217 if (timeout_override) 2218 timeout = HZ / 5; 2219 else 2220 timeout = sc->cur_chan->flush_timeout; 2221 spin_unlock_bh(&sc->chan_lock); 2222 2223 ath_dbg(common, CHAN_CTX, 2224 "Flush timeout: %d\n", jiffies_to_msecs(timeout)); 2225 2226 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending), 2227 timeout) > 0) 2228 drop = false; 2229 2230 if (drop) { 2231 ath9k_ps_wakeup(sc); 2232 spin_lock_bh(&sc->sc_pcu_lock); 2233 drain_txq = ath_drain_all_txq(sc); 2234 spin_unlock_bh(&sc->sc_pcu_lock); 2235 2236 if (!drain_txq) 2237 ath_reset(sc, NULL); 2238 2239 ath9k_ps_restore(sc); 2240 } 2241 2242 ieee80211_queue_delayed_work(hw, &sc->hw_check_work, 2243 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); 2244 } 2245 2246 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2247 { 2248 struct ath_softc *sc = hw->priv; 2249 2250 return ath9k_has_tx_pending(sc, true); 2251 } 2252 2253 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2254 { 2255 struct ath_softc *sc = hw->priv; 2256 struct ath_hw *ah = sc->sc_ah; 2257 struct ieee80211_vif *vif; 2258 struct ath_vif *avp; 2259 struct ath_buf *bf; 2260 struct ath_tx_status ts; 2261 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2262 int status; 2263 2264 vif = sc->beacon.bslot[0]; 2265 if (!vif) 2266 return 0; 2267 2268 if (!vif->bss_conf.enable_beacon) 2269 return 0; 2270 2271 avp = (void *)vif->drv_priv; 2272 2273 if (!sc->beacon.tx_processed && !edma) { 2274 tasklet_disable(&sc->bcon_tasklet); 2275 2276 bf = avp->av_bcbuf; 2277 if (!bf || !bf->bf_mpdu) 2278 goto skip; 2279 2280 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2281 if (status == -EINPROGRESS) 2282 goto skip; 2283 2284 sc->beacon.tx_processed = true; 2285 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2286 2287 skip: 2288 tasklet_enable(&sc->bcon_tasklet); 2289 } 2290 2291 return sc->beacon.tx_last; 2292 } 2293 2294 static int ath9k_get_stats(struct ieee80211_hw *hw, 2295 struct ieee80211_low_level_stats *stats) 2296 { 2297 struct ath_softc *sc = hw->priv; 2298 struct ath_hw *ah = sc->sc_ah; 2299 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2300 2301 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2302 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2303 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2304 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2305 return 0; 2306 } 2307 2308 static u32 fill_chainmask(u32 cap, u32 new) 2309 { 2310 u32 filled = 0; 2311 int i; 2312 2313 for (i = 0; cap && new; i++, cap >>= 1) { 2314 if (!(cap & BIT(0))) 2315 continue; 2316 2317 if (new & BIT(0)) 2318 filled |= BIT(i); 2319 2320 new >>= 1; 2321 } 2322 2323 return filled; 2324 } 2325 2326 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2327 { 2328 if (AR_SREV_9300_20_OR_LATER(ah)) 2329 return true; 2330 2331 switch (val & 0x7) { 2332 case 0x1: 2333 case 0x3: 2334 case 0x7: 2335 return true; 2336 case 0x2: 2337 return (ah->caps.rx_chainmask == 1); 2338 default: 2339 return false; 2340 } 2341 } 2342 2343 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2344 { 2345 struct ath_softc *sc = hw->priv; 2346 struct ath_hw *ah = sc->sc_ah; 2347 2348 if (ah->caps.rx_chainmask != 1) 2349 rx_ant |= tx_ant; 2350 2351 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2352 return -EINVAL; 2353 2354 sc->ant_rx = rx_ant; 2355 sc->ant_tx = tx_ant; 2356 2357 if (ah->caps.rx_chainmask == 1) 2358 return 0; 2359 2360 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2361 if (AR_SREV_9100(ah)) 2362 ah->rxchainmask = 0x7; 2363 else 2364 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2365 2366 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2367 ath9k_cmn_reload_chainmask(ah); 2368 2369 return 0; 2370 } 2371 2372 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2373 { 2374 struct ath_softc *sc = hw->priv; 2375 2376 *tx_ant = sc->ant_tx; 2377 *rx_ant = sc->ant_rx; 2378 return 0; 2379 } 2380 2381 static void ath9k_sw_scan_start(struct ieee80211_hw *hw, 2382 struct ieee80211_vif *vif, 2383 const u8 *mac_addr) 2384 { 2385 struct ath_softc *sc = hw->priv; 2386 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2387 set_bit(ATH_OP_SCANNING, &common->op_flags); 2388 } 2389 2390 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, 2391 struct ieee80211_vif *vif) 2392 { 2393 struct ath_softc *sc = hw->priv; 2394 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2395 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2396 } 2397 2398 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2399 2400 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc) 2401 { 2402 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2403 2404 if (sc->offchannel.roc_vif) { 2405 ath_dbg(common, CHAN_CTX, 2406 "%s: Aborting RoC\n", __func__); 2407 2408 del_timer_sync(&sc->offchannel.timer); 2409 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2410 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT); 2411 } 2412 2413 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 2414 ath_dbg(common, CHAN_CTX, 2415 "%s: Aborting HW scan\n", __func__); 2416 2417 del_timer_sync(&sc->offchannel.timer); 2418 ath_scan_complete(sc, true); 2419 } 2420 } 2421 2422 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2423 struct ieee80211_scan_request *hw_req) 2424 { 2425 struct cfg80211_scan_request *req = &hw_req->req; 2426 struct ath_softc *sc = hw->priv; 2427 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2428 int ret = 0; 2429 2430 mutex_lock(&sc->mutex); 2431 2432 if (WARN_ON(sc->offchannel.scan_req)) { 2433 ret = -EBUSY; 2434 goto out; 2435 } 2436 2437 ath9k_ps_wakeup(sc); 2438 set_bit(ATH_OP_SCANNING, &common->op_flags); 2439 sc->offchannel.scan_vif = vif; 2440 sc->offchannel.scan_req = req; 2441 sc->offchannel.scan_idx = 0; 2442 2443 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2444 vif->addr); 2445 2446 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2447 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2448 ath_offchannel_next(sc); 2449 } 2450 2451 out: 2452 mutex_unlock(&sc->mutex); 2453 2454 return ret; 2455 } 2456 2457 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2458 struct ieee80211_vif *vif) 2459 { 2460 struct ath_softc *sc = hw->priv; 2461 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2462 2463 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2464 2465 mutex_lock(&sc->mutex); 2466 del_timer_sync(&sc->offchannel.timer); 2467 ath_scan_complete(sc, true); 2468 mutex_unlock(&sc->mutex); 2469 } 2470 2471 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2472 struct ieee80211_vif *vif, 2473 struct ieee80211_channel *chan, int duration, 2474 enum ieee80211_roc_type type) 2475 { 2476 struct ath_softc *sc = hw->priv; 2477 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2478 int ret = 0; 2479 2480 mutex_lock(&sc->mutex); 2481 2482 if (WARN_ON(sc->offchannel.roc_vif)) { 2483 ret = -EBUSY; 2484 goto out; 2485 } 2486 2487 ath9k_ps_wakeup(sc); 2488 sc->offchannel.roc_vif = vif; 2489 sc->offchannel.roc_chan = chan; 2490 sc->offchannel.roc_duration = duration; 2491 2492 ath_dbg(common, CHAN_CTX, 2493 "RoC request on vif: %pM, type: %d duration: %d\n", 2494 vif->addr, type, duration); 2495 2496 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2497 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2498 ath_offchannel_next(sc); 2499 } 2500 2501 out: 2502 mutex_unlock(&sc->mutex); 2503 2504 return ret; 2505 } 2506 2507 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw, 2508 struct ieee80211_vif *vif) 2509 { 2510 struct ath_softc *sc = hw->priv; 2511 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2512 2513 mutex_lock(&sc->mutex); 2514 2515 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2516 del_timer_sync(&sc->offchannel.timer); 2517 2518 if (sc->offchannel.roc_vif) { 2519 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2520 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL); 2521 } 2522 2523 mutex_unlock(&sc->mutex); 2524 2525 return 0; 2526 } 2527 2528 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2529 struct ieee80211_chanctx_conf *conf) 2530 { 2531 struct ath_softc *sc = hw->priv; 2532 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2533 struct ath_chanctx *ctx, **ptr; 2534 int pos; 2535 2536 mutex_lock(&sc->mutex); 2537 2538 ath_for_each_chanctx(sc, ctx) { 2539 if (ctx->assigned) 2540 continue; 2541 2542 ptr = (void *) conf->drv_priv; 2543 *ptr = ctx; 2544 ctx->assigned = true; 2545 pos = ctx - &sc->chanctx[0]; 2546 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2547 2548 ath_dbg(common, CHAN_CTX, 2549 "Add channel context: %d MHz\n", 2550 conf->def.chan->center_freq); 2551 2552 ath_chanctx_set_channel(sc, ctx, &conf->def); 2553 2554 mutex_unlock(&sc->mutex); 2555 return 0; 2556 } 2557 2558 mutex_unlock(&sc->mutex); 2559 return -ENOSPC; 2560 } 2561 2562 2563 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2564 struct ieee80211_chanctx_conf *conf) 2565 { 2566 struct ath_softc *sc = hw->priv; 2567 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2568 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2569 2570 mutex_lock(&sc->mutex); 2571 2572 ath_dbg(common, CHAN_CTX, 2573 "Remove channel context: %d MHz\n", 2574 conf->def.chan->center_freq); 2575 2576 ctx->assigned = false; 2577 ctx->hw_queue_base = 0; 2578 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2579 2580 mutex_unlock(&sc->mutex); 2581 } 2582 2583 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2584 struct ieee80211_chanctx_conf *conf, 2585 u32 changed) 2586 { 2587 struct ath_softc *sc = hw->priv; 2588 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2589 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2590 2591 mutex_lock(&sc->mutex); 2592 ath_dbg(common, CHAN_CTX, 2593 "Change channel context: %d MHz\n", 2594 conf->def.chan->center_freq); 2595 ath_chanctx_set_channel(sc, ctx, &conf->def); 2596 mutex_unlock(&sc->mutex); 2597 } 2598 2599 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2600 struct ieee80211_vif *vif, 2601 struct ieee80211_bss_conf *link_conf, 2602 struct ieee80211_chanctx_conf *conf) 2603 { 2604 struct ath_softc *sc = hw->priv; 2605 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2606 struct ath_vif *avp = (void *)vif->drv_priv; 2607 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2608 int i; 2609 2610 ath9k_cancel_pending_offchannel(sc); 2611 2612 mutex_lock(&sc->mutex); 2613 2614 ath_dbg(common, CHAN_CTX, 2615 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2616 vif->addr, vif->type, vif->p2p, 2617 conf->def.chan->center_freq); 2618 2619 avp->chanctx = ctx; 2620 ctx->nvifs_assigned++; 2621 list_add_tail(&avp->list, &ctx->vifs); 2622 ath9k_calculate_summary_state(sc, ctx); 2623 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2624 vif->hw_queue[i] = ctx->hw_queue_base + i; 2625 2626 mutex_unlock(&sc->mutex); 2627 2628 return 0; 2629 } 2630 2631 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2632 struct ieee80211_vif *vif, 2633 struct ieee80211_bss_conf *link_conf, 2634 struct ieee80211_chanctx_conf *conf) 2635 { 2636 struct ath_softc *sc = hw->priv; 2637 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2638 struct ath_vif *avp = (void *)vif->drv_priv; 2639 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2640 int ac; 2641 2642 ath9k_cancel_pending_offchannel(sc); 2643 2644 mutex_lock(&sc->mutex); 2645 2646 ath_dbg(common, CHAN_CTX, 2647 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2648 vif->addr, vif->type, vif->p2p, 2649 conf->def.chan->center_freq); 2650 2651 avp->chanctx = NULL; 2652 ctx->nvifs_assigned--; 2653 list_del(&avp->list); 2654 ath9k_calculate_summary_state(sc, ctx); 2655 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2656 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2657 2658 mutex_unlock(&sc->mutex); 2659 } 2660 2661 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2662 struct ieee80211_vif *vif, 2663 struct ieee80211_prep_tx_info *info) 2664 { 2665 struct ath_softc *sc = hw->priv; 2666 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2667 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2668 struct ath_beacon_config *cur_conf; 2669 struct ath_chanctx *go_ctx; 2670 unsigned long timeout; 2671 bool changed = false; 2672 u32 beacon_int; 2673 2674 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2675 return; 2676 2677 if (!avp->chanctx) 2678 return; 2679 2680 mutex_lock(&sc->mutex); 2681 2682 spin_lock_bh(&sc->chan_lock); 2683 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) 2684 changed = true; 2685 spin_unlock_bh(&sc->chan_lock); 2686 2687 if (!changed) 2688 goto out; 2689 2690 ath9k_cancel_pending_offchannel(sc); 2691 2692 go_ctx = ath_is_go_chanctx_present(sc); 2693 2694 if (go_ctx) { 2695 /* 2696 * Wait till the GO interface gets a chance 2697 * to send out an NoA. 2698 */ 2699 spin_lock_bh(&sc->chan_lock); 2700 sc->sched.mgd_prepare_tx = true; 2701 cur_conf = &go_ctx->beacon; 2702 beacon_int = TU_TO_USEC(cur_conf->beacon_interval); 2703 spin_unlock_bh(&sc->chan_lock); 2704 2705 timeout = usecs_to_jiffies(beacon_int * 2); 2706 init_completion(&sc->go_beacon); 2707 2708 mutex_unlock(&sc->mutex); 2709 2710 if (wait_for_completion_timeout(&sc->go_beacon, 2711 timeout) == 0) { 2712 ath_dbg(common, CHAN_CTX, 2713 "Failed to send new NoA\n"); 2714 2715 spin_lock_bh(&sc->chan_lock); 2716 sc->sched.mgd_prepare_tx = false; 2717 spin_unlock_bh(&sc->chan_lock); 2718 } 2719 2720 mutex_lock(&sc->mutex); 2721 } 2722 2723 ath_dbg(common, CHAN_CTX, 2724 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n", 2725 __func__, vif->addr); 2726 2727 spin_lock_bh(&sc->chan_lock); 2728 sc->next_chan = avp->chanctx; 2729 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2730 spin_unlock_bh(&sc->chan_lock); 2731 2732 ath_chanctx_set_next(sc, true); 2733 out: 2734 mutex_unlock(&sc->mutex); 2735 } 2736 2737 void ath9k_fill_chanctx_ops(void) 2738 { 2739 if (!ath9k_is_chanctx_enabled()) 2740 return; 2741 2742 ath9k_ops.hw_scan = ath9k_hw_scan; 2743 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2744 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2745 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2746 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2747 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2748 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2749 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2750 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2751 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2752 } 2753 2754 #endif 2755 2756 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2757 int *dbm) 2758 { 2759 struct ath_softc *sc = hw->priv; 2760 struct ath_vif *avp = (void *)vif->drv_priv; 2761 2762 mutex_lock(&sc->mutex); 2763 if (avp->chanctx) 2764 *dbm = avp->chanctx->cur_txpower; 2765 else 2766 *dbm = sc->cur_chan->cur_txpower; 2767 mutex_unlock(&sc->mutex); 2768 2769 *dbm /= 2; 2770 2771 return 0; 2772 } 2773 2774 struct ieee80211_ops ath9k_ops = { 2775 .tx = ath9k_tx, 2776 .start = ath9k_start, 2777 .stop = ath9k_stop, 2778 .add_interface = ath9k_add_interface, 2779 .change_interface = ath9k_change_interface, 2780 .remove_interface = ath9k_remove_interface, 2781 .config = ath9k_config, 2782 .configure_filter = ath9k_configure_filter, 2783 .sta_state = ath9k_sta_state, 2784 .sta_notify = ath9k_sta_notify, 2785 .conf_tx = ath9k_conf_tx, 2786 .bss_info_changed = ath9k_bss_info_changed, 2787 .set_key = ath9k_set_key, 2788 .get_tsf = ath9k_get_tsf, 2789 .set_tsf = ath9k_set_tsf, 2790 .reset_tsf = ath9k_reset_tsf, 2791 .ampdu_action = ath9k_ampdu_action, 2792 .get_survey = ath9k_get_survey, 2793 .rfkill_poll = ath9k_rfkill_poll_state, 2794 .set_coverage_class = ath9k_set_coverage_class, 2795 .flush = ath9k_flush, 2796 .tx_frames_pending = ath9k_tx_frames_pending, 2797 .tx_last_beacon = ath9k_tx_last_beacon, 2798 .release_buffered_frames = ath9k_release_buffered_frames, 2799 .get_stats = ath9k_get_stats, 2800 .set_antenna = ath9k_set_antenna, 2801 .get_antenna = ath9k_get_antenna, 2802 2803 #ifdef CONFIG_ATH9K_WOW 2804 .suspend = ath9k_suspend, 2805 .resume = ath9k_resume, 2806 .set_wakeup = ath9k_set_wakeup, 2807 #endif 2808 2809 #ifdef CONFIG_ATH9K_DEBUGFS 2810 .get_et_sset_count = ath9k_get_et_sset_count, 2811 .get_et_stats = ath9k_get_et_stats, 2812 .get_et_strings = ath9k_get_et_strings, 2813 #endif 2814 2815 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2816 .sta_add_debugfs = ath9k_sta_add_debugfs, 2817 #endif 2818 .sw_scan_start = ath9k_sw_scan_start, 2819 .sw_scan_complete = ath9k_sw_scan_complete, 2820 .get_txpower = ath9k_get_txpower, 2821 .wake_tx_queue = ath9k_wake_tx_queue, 2822 }; 2823