1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef MAC_H 18 #define MAC_H 19 20 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \ 21 MS(ads->ds_rxstatus0, AR_RxRate) : \ 22 (ads->ds_rxstatus3 >> 2) & 0xFF) 23 24 #define set11nTries(_series, _index) \ 25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 26 27 #define set11nRate(_series, _index) \ 28 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 29 30 #define set11nPktDurRTSCTS(_series, _index) \ 31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 33 AR_RTSCTSQual##_index : 0)) 34 35 #define set11nRateFlags(_series, _index) \ 36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 37 AR_2040_##_index : 0) \ 38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 39 AR_GI##_index : 0) \ 40 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 41 42 #define CCK_SIFS_TIME 10 43 #define CCK_PREAMBLE_BITS 144 44 #define CCK_PLCP_BITS 48 45 46 #define OFDM_SIFS_TIME 16 47 #define OFDM_PREAMBLE_TIME 20 48 #define OFDM_PLCP_BITS 22 49 #define OFDM_SYMBOL_TIME 4 50 51 #define OFDM_SIFS_TIME_HALF 32 52 #define OFDM_PREAMBLE_TIME_HALF 40 53 #define OFDM_PLCP_BITS_HALF 22 54 #define OFDM_SYMBOL_TIME_HALF 8 55 56 #define OFDM_SIFS_TIME_QUARTER 64 57 #define OFDM_PREAMBLE_TIME_QUARTER 80 58 #define OFDM_PLCP_BITS_QUARTER 22 59 #define OFDM_SYMBOL_TIME_QUARTER 16 60 61 #define INIT_AIFS 2 62 #define INIT_CWMIN 15 63 #define INIT_CWMIN_11B 31 64 #define INIT_CWMAX 1023 65 #define INIT_SH_RETRY 10 66 #define INIT_LG_RETRY 10 67 #define INIT_SSH_RETRY 32 68 #define INIT_SLG_RETRY 32 69 70 #define ATH9K_SLOT_TIME_6 6 71 #define ATH9K_SLOT_TIME_9 9 72 #define ATH9K_SLOT_TIME_20 20 73 74 #define ATH9K_TXERR_XRETRY 0x01 75 #define ATH9K_TXERR_FILT 0x02 76 #define ATH9K_TXERR_FIFO 0x04 77 #define ATH9K_TXERR_XTXOP 0x08 78 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 79 80 #define ATH9K_TX_BA 0x01 81 #define ATH9K_TX_PWRMGMT 0x02 82 #define ATH9K_TX_DESC_CFG_ERR 0x04 83 #define ATH9K_TX_DATA_UNDERRUN 0x08 84 #define ATH9K_TX_DELIM_UNDERRUN 0x10 85 #define ATH9K_TX_SW_ABORTED 0x40 86 #define ATH9K_TX_SW_FILTERED 0x80 87 88 #define MIN_TX_FIFO_THRESHOLD 0x1 89 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 90 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 91 92 struct ath_tx_status { 93 u32 ts_tstamp; 94 u16 ts_seqnum; 95 u8 ts_status; 96 u8 ts_ratecode; 97 u8 ts_rateindex; 98 int8_t ts_rssi; 99 u8 ts_shortretry; 100 u8 ts_longretry; 101 u8 ts_virtcol; 102 u8 ts_antenna; 103 u8 ts_flags; 104 int8_t ts_rssi_ctl0; 105 int8_t ts_rssi_ctl1; 106 int8_t ts_rssi_ctl2; 107 int8_t ts_rssi_ext0; 108 int8_t ts_rssi_ext1; 109 int8_t ts_rssi_ext2; 110 u8 pad[3]; 111 u32 ba_low; 112 u32 ba_high; 113 u32 evm0; 114 u32 evm1; 115 u32 evm2; 116 }; 117 118 struct ath_rx_status { 119 u32 rs_tstamp; 120 u16 rs_datalen; 121 u8 rs_status; 122 u8 rs_phyerr; 123 int8_t rs_rssi; 124 u8 rs_keyix; 125 u8 rs_rate; 126 u8 rs_antenna; 127 u8 rs_more; 128 int8_t rs_rssi_ctl0; 129 int8_t rs_rssi_ctl1; 130 int8_t rs_rssi_ctl2; 131 int8_t rs_rssi_ext0; 132 int8_t rs_rssi_ext1; 133 int8_t rs_rssi_ext2; 134 u8 rs_isaggr; 135 u8 rs_moreaggr; 136 u8 rs_num_delims; 137 u8 rs_flags; 138 u32 evm0; 139 u32 evm1; 140 u32 evm2; 141 }; 142 143 #define ATH9K_RXERR_CRC 0x01 144 #define ATH9K_RXERR_PHY 0x02 145 #define ATH9K_RXERR_FIFO 0x04 146 #define ATH9K_RXERR_DECRYPT 0x08 147 #define ATH9K_RXERR_MIC 0x10 148 149 #define ATH9K_RX_MORE 0x01 150 #define ATH9K_RX_MORE_AGGR 0x02 151 #define ATH9K_RX_GI 0x04 152 #define ATH9K_RX_2040 0x08 153 #define ATH9K_RX_DELIM_CRC_PRE 0x10 154 #define ATH9K_RX_DELIM_CRC_POST 0x20 155 #define ATH9K_RX_DECRYPT_BUSY 0x40 156 157 #define ATH9K_RXKEYIX_INVALID ((u8)-1) 158 #define ATH9K_TXKEYIX_INVALID ((u32)-1) 159 160 struct ath_desc { 161 u32 ds_link; 162 u32 ds_data; 163 u32 ds_ctl0; 164 u32 ds_ctl1; 165 u32 ds_hw[20]; 166 union { 167 struct ath_tx_status tx; 168 struct ath_rx_status rx; 169 void *stats; 170 } ds_us; 171 void *ds_vdata; 172 } __packed; 173 174 #define ds_txstat ds_us.tx 175 #define ds_rxstat ds_us.rx 176 #define ds_stat ds_us.stats 177 178 #define ATH9K_TXDESC_CLRDMASK 0x0001 179 #define ATH9K_TXDESC_NOACK 0x0002 180 #define ATH9K_TXDESC_RTSENA 0x0004 181 #define ATH9K_TXDESC_CTSENA 0x0008 182 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 183 * the descriptor its marked on. We take a tx interrupt to reap 184 * descriptors when the h/w hits an EOL condition or 185 * when the descriptor is specifically marked to generate 186 * an interrupt with this flag. Descriptors should be 187 * marked periodically to insure timely replenishing of the 188 * supply needed for sending frames. Defering interrupts 189 * reduces system load and potentially allows more concurrent 190 * work to be done but if done to aggressively can cause 191 * senders to backup. When the hardware queue is left too 192 * large rate control information may also be too out of 193 * date. An Alternative for this is TX interrupt mitigation 194 * but this needs more testing. */ 195 #define ATH9K_TXDESC_INTREQ 0x0010 196 #define ATH9K_TXDESC_VEOL 0x0020 197 #define ATH9K_TXDESC_EXT_ONLY 0x0040 198 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 199 #define ATH9K_TXDESC_VMF 0x0100 200 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 201 #define ATH9K_TXDESC_CAB 0x0400 202 203 #define ATH9K_RXDESC_INTREQ 0x0020 204 205 struct ar5416_desc { 206 u32 ds_link; 207 u32 ds_data; 208 u32 ds_ctl0; 209 u32 ds_ctl1; 210 union { 211 struct { 212 u32 ctl2; 213 u32 ctl3; 214 u32 ctl4; 215 u32 ctl5; 216 u32 ctl6; 217 u32 ctl7; 218 u32 ctl8; 219 u32 ctl9; 220 u32 ctl10; 221 u32 ctl11; 222 u32 status0; 223 u32 status1; 224 u32 status2; 225 u32 status3; 226 u32 status4; 227 u32 status5; 228 u32 status6; 229 u32 status7; 230 u32 status8; 231 u32 status9; 232 } tx; 233 struct { 234 u32 status0; 235 u32 status1; 236 u32 status2; 237 u32 status3; 238 u32 status4; 239 u32 status5; 240 u32 status6; 241 u32 status7; 242 u32 status8; 243 } rx; 244 } u; 245 } __packed; 246 247 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 248 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 249 250 #define ds_ctl2 u.tx.ctl2 251 #define ds_ctl3 u.tx.ctl3 252 #define ds_ctl4 u.tx.ctl4 253 #define ds_ctl5 u.tx.ctl5 254 #define ds_ctl6 u.tx.ctl6 255 #define ds_ctl7 u.tx.ctl7 256 #define ds_ctl8 u.tx.ctl8 257 #define ds_ctl9 u.tx.ctl9 258 #define ds_ctl10 u.tx.ctl10 259 #define ds_ctl11 u.tx.ctl11 260 261 #define ds_txstatus0 u.tx.status0 262 #define ds_txstatus1 u.tx.status1 263 #define ds_txstatus2 u.tx.status2 264 #define ds_txstatus3 u.tx.status3 265 #define ds_txstatus4 u.tx.status4 266 #define ds_txstatus5 u.tx.status5 267 #define ds_txstatus6 u.tx.status6 268 #define ds_txstatus7 u.tx.status7 269 #define ds_txstatus8 u.tx.status8 270 #define ds_txstatus9 u.tx.status9 271 272 #define ds_rxstatus0 u.rx.status0 273 #define ds_rxstatus1 u.rx.status1 274 #define ds_rxstatus2 u.rx.status2 275 #define ds_rxstatus3 u.rx.status3 276 #define ds_rxstatus4 u.rx.status4 277 #define ds_rxstatus5 u.rx.status5 278 #define ds_rxstatus6 u.rx.status6 279 #define ds_rxstatus7 u.rx.status7 280 #define ds_rxstatus8 u.rx.status8 281 282 #define AR_FrameLen 0x00000fff 283 #define AR_VirtMoreFrag 0x00001000 284 #define AR_TxCtlRsvd00 0x0000e000 285 #define AR_XmitPower 0x003f0000 286 #define AR_XmitPower_S 16 287 #define AR_RTSEnable 0x00400000 288 #define AR_VEOL 0x00800000 289 #define AR_ClrDestMask 0x01000000 290 #define AR_TxCtlRsvd01 0x1e000000 291 #define AR_TxIntrReq 0x20000000 292 #define AR_DestIdxValid 0x40000000 293 #define AR_CTSEnable 0x80000000 294 295 #define AR_BufLen 0x00000fff 296 #define AR_TxMore 0x00001000 297 #define AR_DestIdx 0x000fe000 298 #define AR_DestIdx_S 13 299 #define AR_FrameType 0x00f00000 300 #define AR_FrameType_S 20 301 #define AR_NoAck 0x01000000 302 #define AR_InsertTS 0x02000000 303 #define AR_CorruptFCS 0x04000000 304 #define AR_ExtOnly 0x08000000 305 #define AR_ExtAndCtl 0x10000000 306 #define AR_MoreAggr 0x20000000 307 #define AR_IsAggr 0x40000000 308 309 #define AR_BurstDur 0x00007fff 310 #define AR_BurstDur_S 0 311 #define AR_DurUpdateEna 0x00008000 312 #define AR_XmitDataTries0 0x000f0000 313 #define AR_XmitDataTries0_S 16 314 #define AR_XmitDataTries1 0x00f00000 315 #define AR_XmitDataTries1_S 20 316 #define AR_XmitDataTries2 0x0f000000 317 #define AR_XmitDataTries2_S 24 318 #define AR_XmitDataTries3 0xf0000000 319 #define AR_XmitDataTries3_S 28 320 321 #define AR_XmitRate0 0x000000ff 322 #define AR_XmitRate0_S 0 323 #define AR_XmitRate1 0x0000ff00 324 #define AR_XmitRate1_S 8 325 #define AR_XmitRate2 0x00ff0000 326 #define AR_XmitRate2_S 16 327 #define AR_XmitRate3 0xff000000 328 #define AR_XmitRate3_S 24 329 330 #define AR_PacketDur0 0x00007fff 331 #define AR_PacketDur0_S 0 332 #define AR_RTSCTSQual0 0x00008000 333 #define AR_PacketDur1 0x7fff0000 334 #define AR_PacketDur1_S 16 335 #define AR_RTSCTSQual1 0x80000000 336 337 #define AR_PacketDur2 0x00007fff 338 #define AR_PacketDur2_S 0 339 #define AR_RTSCTSQual2 0x00008000 340 #define AR_PacketDur3 0x7fff0000 341 #define AR_PacketDur3_S 16 342 #define AR_RTSCTSQual3 0x80000000 343 344 #define AR_AggrLen 0x0000ffff 345 #define AR_AggrLen_S 0 346 #define AR_TxCtlRsvd60 0x00030000 347 #define AR_PadDelim 0x03fc0000 348 #define AR_PadDelim_S 18 349 #define AR_EncrType 0x0c000000 350 #define AR_EncrType_S 26 351 #define AR_TxCtlRsvd61 0xf0000000 352 353 #define AR_2040_0 0x00000001 354 #define AR_GI0 0x00000002 355 #define AR_ChainSel0 0x0000001c 356 #define AR_ChainSel0_S 2 357 #define AR_2040_1 0x00000020 358 #define AR_GI1 0x00000040 359 #define AR_ChainSel1 0x00000380 360 #define AR_ChainSel1_S 7 361 #define AR_2040_2 0x00000400 362 #define AR_GI2 0x00000800 363 #define AR_ChainSel2 0x00007000 364 #define AR_ChainSel2_S 12 365 #define AR_2040_3 0x00008000 366 #define AR_GI3 0x00010000 367 #define AR_ChainSel3 0x000e0000 368 #define AR_ChainSel3_S 17 369 #define AR_RTSCTSRate 0x0ff00000 370 #define AR_RTSCTSRate_S 20 371 #define AR_TxCtlRsvd70 0xf0000000 372 373 #define AR_TxRSSIAnt00 0x000000ff 374 #define AR_TxRSSIAnt00_S 0 375 #define AR_TxRSSIAnt01 0x0000ff00 376 #define AR_TxRSSIAnt01_S 8 377 #define AR_TxRSSIAnt02 0x00ff0000 378 #define AR_TxRSSIAnt02_S 16 379 #define AR_TxStatusRsvd00 0x3f000000 380 #define AR_TxBaStatus 0x40000000 381 #define AR_TxStatusRsvd01 0x80000000 382 383 #define AR_FrmXmitOK 0x00000001 384 #define AR_ExcessiveRetries 0x00000002 385 #define AR_FIFOUnderrun 0x00000004 386 #define AR_Filtered 0x00000008 387 #define AR_RTSFailCnt 0x000000f0 388 #define AR_RTSFailCnt_S 4 389 #define AR_DataFailCnt 0x00000f00 390 #define AR_DataFailCnt_S 8 391 #define AR_VirtRetryCnt 0x0000f000 392 #define AR_VirtRetryCnt_S 12 393 #define AR_TxDelimUnderrun 0x00010000 394 #define AR_TxDataUnderrun 0x00020000 395 #define AR_DescCfgErr 0x00040000 396 #define AR_TxTimerExpired 0x00080000 397 #define AR_TxStatusRsvd10 0xfff00000 398 399 #define AR_SendTimestamp ds_txstatus2 400 #define AR_BaBitmapLow ds_txstatus3 401 #define AR_BaBitmapHigh ds_txstatus4 402 403 #define AR_TxRSSIAnt10 0x000000ff 404 #define AR_TxRSSIAnt10_S 0 405 #define AR_TxRSSIAnt11 0x0000ff00 406 #define AR_TxRSSIAnt11_S 8 407 #define AR_TxRSSIAnt12 0x00ff0000 408 #define AR_TxRSSIAnt12_S 16 409 #define AR_TxRSSICombined 0xff000000 410 #define AR_TxRSSICombined_S 24 411 412 #define AR_TxEVM0 ds_txstatus5 413 #define AR_TxEVM1 ds_txstatus6 414 #define AR_TxEVM2 ds_txstatus7 415 416 #define AR_TxDone 0x00000001 417 #define AR_SeqNum 0x00001ffe 418 #define AR_SeqNum_S 1 419 #define AR_TxStatusRsvd80 0x0001e000 420 #define AR_TxOpExceeded 0x00020000 421 #define AR_TxStatusRsvd81 0x001c0000 422 #define AR_FinalTxIdx 0x00600000 423 #define AR_FinalTxIdx_S 21 424 #define AR_TxStatusRsvd82 0x01800000 425 #define AR_PowerMgmt 0x02000000 426 #define AR_TxStatusRsvd83 0xfc000000 427 428 #define AR_RxCTLRsvd00 0xffffffff 429 430 #define AR_BufLen 0x00000fff 431 #define AR_RxCtlRsvd00 0x00001000 432 #define AR_RxIntrReq 0x00002000 433 #define AR_RxCtlRsvd01 0xffffc000 434 435 #define AR_RxRSSIAnt00 0x000000ff 436 #define AR_RxRSSIAnt00_S 0 437 #define AR_RxRSSIAnt01 0x0000ff00 438 #define AR_RxRSSIAnt01_S 8 439 #define AR_RxRSSIAnt02 0x00ff0000 440 #define AR_RxRSSIAnt02_S 16 441 #define AR_RxRate 0xff000000 442 #define AR_RxRate_S 24 443 #define AR_RxStatusRsvd00 0xff000000 444 445 #define AR_DataLen 0x00000fff 446 #define AR_RxMore 0x00001000 447 #define AR_NumDelim 0x003fc000 448 #define AR_NumDelim_S 14 449 #define AR_RxStatusRsvd10 0xff800000 450 451 #define AR_RcvTimestamp ds_rxstatus2 452 453 #define AR_GI 0x00000001 454 #define AR_2040 0x00000002 455 #define AR_Parallel40 0x00000004 456 #define AR_Parallel40_S 2 457 #define AR_RxStatusRsvd30 0x000000f8 458 #define AR_RxAntenna 0xffffff00 459 #define AR_RxAntenna_S 8 460 461 #define AR_RxRSSIAnt10 0x000000ff 462 #define AR_RxRSSIAnt10_S 0 463 #define AR_RxRSSIAnt11 0x0000ff00 464 #define AR_RxRSSIAnt11_S 8 465 #define AR_RxRSSIAnt12 0x00ff0000 466 #define AR_RxRSSIAnt12_S 16 467 #define AR_RxRSSICombined 0xff000000 468 #define AR_RxRSSICombined_S 24 469 470 #define AR_RxEVM0 ds_rxstatus4 471 #define AR_RxEVM1 ds_rxstatus5 472 #define AR_RxEVM2 ds_rxstatus6 473 474 #define AR_RxDone 0x00000001 475 #define AR_RxFrameOK 0x00000002 476 #define AR_CRCErr 0x00000004 477 #define AR_DecryptCRCErr 0x00000008 478 #define AR_PHYErr 0x00000010 479 #define AR_MichaelErr 0x00000020 480 #define AR_PreDelimCRCErr 0x00000040 481 #define AR_RxStatusRsvd70 0x00000080 482 #define AR_RxKeyIdxValid 0x00000100 483 #define AR_KeyIdx 0x0000fe00 484 #define AR_KeyIdx_S 9 485 #define AR_PHYErrCode 0x0000ff00 486 #define AR_PHYErrCode_S 8 487 #define AR_RxMoreAggr 0x00010000 488 #define AR_RxAggr 0x00020000 489 #define AR_PostDelimCRCErr 0x00040000 490 #define AR_RxStatusRsvd71 0x3ff80000 491 #define AR_DecryptBusyErr 0x40000000 492 #define AR_KeyMiss 0x80000000 493 494 enum ath9k_tx_queue { 495 ATH9K_TX_QUEUE_INACTIVE = 0, 496 ATH9K_TX_QUEUE_DATA, 497 ATH9K_TX_QUEUE_BEACON, 498 ATH9K_TX_QUEUE_CAB, 499 ATH9K_TX_QUEUE_UAPSD, 500 ATH9K_TX_QUEUE_PSPOLL 501 }; 502 503 #define ATH9K_NUM_TX_QUEUES 10 504 505 enum ath9k_tx_queue_subtype { 506 ATH9K_WME_AC_BK = 0, 507 ATH9K_WME_AC_BE, 508 ATH9K_WME_AC_VI, 509 ATH9K_WME_AC_VO, 510 ATH9K_WME_UPSD 511 }; 512 513 enum ath9k_tx_queue_flags { 514 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, 515 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, 516 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 517 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 518 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 519 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 520 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 521 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 522 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 523 }; 524 525 #define ATH9K_TXQ_USEDEFAULT ((u32) -1) 526 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 527 528 #define ATH9K_DECOMP_MASK_SIZE 128 529 #define ATH9K_READY_TIME_LO_BOUND 50 530 #define ATH9K_READY_TIME_HI_BOUND 96 531 532 enum ath9k_pkt_type { 533 ATH9K_PKT_TYPE_NORMAL = 0, 534 ATH9K_PKT_TYPE_ATIM, 535 ATH9K_PKT_TYPE_PSPOLL, 536 ATH9K_PKT_TYPE_BEACON, 537 ATH9K_PKT_TYPE_PROBE_RESP, 538 ATH9K_PKT_TYPE_CHIRP, 539 ATH9K_PKT_TYPE_GRP_POLL, 540 }; 541 542 struct ath9k_tx_queue_info { 543 u32 tqi_ver; 544 enum ath9k_tx_queue tqi_type; 545 enum ath9k_tx_queue_subtype tqi_subtype; 546 enum ath9k_tx_queue_flags tqi_qflags; 547 u32 tqi_priority; 548 u32 tqi_aifs; 549 u32 tqi_cwmin; 550 u32 tqi_cwmax; 551 u16 tqi_shretry; 552 u16 tqi_lgretry; 553 u32 tqi_cbrPeriod; 554 u32 tqi_cbrOverflowLimit; 555 u32 tqi_burstTime; 556 u32 tqi_readyTime; 557 u32 tqi_physCompBuf; 558 u32 tqi_intFlags; 559 }; 560 561 enum ath9k_rx_filter { 562 ATH9K_RX_FILTER_UCAST = 0x00000001, 563 ATH9K_RX_FILTER_MCAST = 0x00000002, 564 ATH9K_RX_FILTER_BCAST = 0x00000004, 565 ATH9K_RX_FILTER_CONTROL = 0x00000008, 566 ATH9K_RX_FILTER_BEACON = 0x00000010, 567 ATH9K_RX_FILTER_PROM = 0x00000020, 568 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 569 ATH9K_RX_FILTER_PHYERR = 0x00000100, 570 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 571 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 572 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 573 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 574 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 575 }; 576 577 #define ATH9K_RATESERIES_RTS_CTS 0x0001 578 #define ATH9K_RATESERIES_2040 0x0002 579 #define ATH9K_RATESERIES_HALFGI 0x0004 580 581 struct ath9k_11n_rate_series { 582 u32 Tries; 583 u32 Rate; 584 u32 PktDuration; 585 u32 ChSel; 586 u32 RateFlags; 587 }; 588 589 struct ath9k_keyval { 590 u8 kv_type; 591 u8 kv_pad; 592 u16 kv_len; 593 u8 kv_val[16]; /* TK */ 594 u8 kv_mic[8]; /* Michael MIC key */ 595 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 596 * supports both MIC keys in the same key cache entry; 597 * in that case, kv_mic is the RX key) */ 598 }; 599 600 enum ath9k_key_type { 601 ATH9K_KEY_TYPE_CLEAR, 602 ATH9K_KEY_TYPE_WEP, 603 ATH9K_KEY_TYPE_AES, 604 ATH9K_KEY_TYPE_TKIP, 605 }; 606 607 enum ath9k_cipher { 608 ATH9K_CIPHER_WEP = 0, 609 ATH9K_CIPHER_AES_OCB = 1, 610 ATH9K_CIPHER_AES_CCM = 2, 611 ATH9K_CIPHER_CKIP = 3, 612 ATH9K_CIPHER_TKIP = 4, 613 ATH9K_CIPHER_CLR = 5, 614 ATH9K_CIPHER_MIC = 127 615 }; 616 617 enum ath9k_ht_macmode { 618 ATH9K_HT_MACMODE_20 = 0, 619 ATH9K_HT_MACMODE_2040 = 1, 620 }; 621 622 enum ath9k_ht_extprotspacing { 623 ATH9K_HT_EXTPROTSPACING_20 = 0, 624 ATH9K_HT_EXTPROTSPACING_25 = 1, 625 }; 626 627 struct ath_hw; 628 struct ath9k_channel; 629 struct ath_rate_table; 630 631 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 632 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 633 void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 634 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 635 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 636 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); 637 void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, 638 u32 segLen, bool firstSeg, 639 bool lastSeg, const struct ath_desc *ds0); 640 void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds); 641 int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds); 642 void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, 643 u32 pktLen, enum ath9k_pkt_type type, u32 txPower, 644 u32 keyIx, enum ath9k_key_type keyType, u32 flags); 645 void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, 646 struct ath_desc *lastds, 647 u32 durUpdateEn, u32 rtsctsRate, 648 u32 rtsctsDuration, 649 struct ath9k_11n_rate_series series[], 650 u32 nseries, u32 flags); 651 void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, 652 u32 aggrLen); 653 void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, 654 u32 numDelims); 655 void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds); 656 void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds); 657 void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, 658 u32 burstDuration); 659 void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, 660 u32 vmf); 661 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 662 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 663 const struct ath9k_tx_queue_info *qinfo); 664 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 665 struct ath9k_tx_queue_info *qinfo); 666 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 667 const struct ath9k_tx_queue_info *qinfo); 668 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 669 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 670 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 671 u32 pa, struct ath_desc *nds, u64 tsf); 672 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 673 u32 size, u32 flags); 674 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 675 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 676 void ath9k_hw_rxena(struct ath_hw *ah); 677 void ath9k_hw_startpcureceive(struct ath_hw *ah); 678 void ath9k_hw_stoppcurecv(struct ath_hw *ah); 679 bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 680 681 #endif /* MAC_H */ 682