1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef MAC_H 18 #define MAC_H 19 20 #define set11nTries(_series, _index) \ 21 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 22 23 #define set11nRate(_series, _index) \ 24 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 25 26 #define set11nPktDurRTSCTS(_series, _index) \ 27 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 28 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 29 AR_RTSCTSQual##_index : 0)) 30 31 #define set11nRateFlags(_series, _index) \ 32 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 33 AR_2040_##_index : 0) \ 34 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 35 AR_GI##_index : 0) \ 36 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \ 37 AR_STBC##_index : 0) \ 38 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 39 40 #define CCK_SIFS_TIME 10 41 #define CCK_PREAMBLE_BITS 144 42 #define CCK_PLCP_BITS 48 43 44 #define OFDM_SIFS_TIME 16 45 #define OFDM_PREAMBLE_TIME 20 46 #define OFDM_PLCP_BITS 22 47 #define OFDM_SYMBOL_TIME 4 48 49 #define OFDM_SIFS_TIME_HALF 32 50 #define OFDM_PREAMBLE_TIME_HALF 40 51 #define OFDM_PLCP_BITS_HALF 22 52 #define OFDM_SYMBOL_TIME_HALF 8 53 54 #define OFDM_SIFS_TIME_QUARTER 64 55 #define OFDM_PREAMBLE_TIME_QUARTER 80 56 #define OFDM_PLCP_BITS_QUARTER 22 57 #define OFDM_SYMBOL_TIME_QUARTER 16 58 59 #define INIT_AIFS 2 60 #define INIT_CWMIN 15 61 #define INIT_CWMIN_11B 31 62 #define INIT_CWMAX 1023 63 #define INIT_SH_RETRY 10 64 #define INIT_LG_RETRY 10 65 #define INIT_SSH_RETRY 32 66 #define INIT_SLG_RETRY 32 67 68 #define ATH9K_SLOT_TIME_6 6 69 #define ATH9K_SLOT_TIME_9 9 70 #define ATH9K_SLOT_TIME_20 20 71 72 #define ATH9K_TXERR_XRETRY 0x01 73 #define ATH9K_TXERR_FILT 0x02 74 #define ATH9K_TXERR_FIFO 0x04 75 #define ATH9K_TXERR_XTXOP 0x08 76 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 77 #define ATH9K_TX_ACKED 0x20 78 #define ATH9K_TX_FLUSH 0x40 79 #define ATH9K_TXERR_MASK \ 80 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 81 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH) 82 83 #define ATH9K_TX_BA 0x01 84 #define ATH9K_TX_PWRMGMT 0x02 85 #define ATH9K_TX_DESC_CFG_ERR 0x04 86 #define ATH9K_TX_DATA_UNDERRUN 0x08 87 #define ATH9K_TX_DELIM_UNDERRUN 0x10 88 #define ATH9K_TX_SW_FILTERED 0x80 89 90 /* 64 bytes */ 91 #define MIN_TX_FIFO_THRESHOLD 0x1 92 93 /* 94 * Single stream device AR9285 and AR9271 require 2 KB 95 * to work around a hardware issue, all other devices 96 * have can use the max 4 KB limit. 97 */ 98 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 99 100 struct ath_tx_status { 101 u32 ts_tstamp; 102 u16 ts_seqnum; 103 u8 ts_status; 104 u8 ts_rateindex; 105 int8_t ts_rssi; 106 u8 ts_shortretry; 107 u8 ts_longretry; 108 u8 ts_virtcol; 109 u8 ts_flags; 110 int8_t ts_rssi_ctl0; 111 int8_t ts_rssi_ctl1; 112 int8_t ts_rssi_ctl2; 113 int8_t ts_rssi_ext0; 114 int8_t ts_rssi_ext1; 115 int8_t ts_rssi_ext2; 116 u8 qid; 117 u16 desc_id; 118 u8 tid; 119 u32 ba_low; 120 u32 ba_high; 121 u32 evm0; 122 u32 evm1; 123 u32 evm2; 124 }; 125 126 struct ath_rx_status { 127 u32 rs_tstamp; 128 u16 rs_datalen; 129 u8 rs_status; 130 u8 rs_phyerr; 131 int8_t rs_rssi; 132 u8 rs_keyix; 133 u8 rs_rate; 134 u8 rs_antenna; 135 u8 rs_more; 136 int8_t rs_rssi_ctl[3]; 137 int8_t rs_rssi_ext[3]; 138 u8 rs_isaggr; 139 u8 rs_firstaggr; 140 u8 rs_moreaggr; 141 u8 rs_num_delims; 142 u8 rs_flags; 143 bool is_mybeacon; 144 u32 evm0; 145 u32 evm1; 146 u32 evm2; 147 u32 evm3; 148 u32 evm4; 149 u32 flag; /* see enum mac80211_rx_flags */ 150 }; 151 152 struct ath_htc_rx_status { 153 __be64 rs_tstamp; 154 __be16 rs_datalen; 155 u8 rs_status; 156 u8 rs_phyerr; 157 int8_t rs_rssi; 158 int8_t rs_rssi_ctl[3]; 159 int8_t rs_rssi_ext[3]; 160 u8 rs_keyix; 161 u8 rs_rate; 162 u8 rs_antenna; 163 u8 rs_more; 164 u8 rs_isaggr; 165 u8 rs_moreaggr; 166 u8 rs_num_delims; 167 u8 rs_flags; 168 u8 rs_dummy; 169 /* FIXME: evm* never used? */ 170 __be32 evm0; 171 __be32 evm1; 172 __be32 evm2; 173 }; 174 175 #define ATH9K_RXERR_CRC 0x01 176 #define ATH9K_RXERR_PHY 0x02 177 #define ATH9K_RXERR_FIFO 0x04 178 #define ATH9K_RXERR_DECRYPT 0x08 179 #define ATH9K_RXERR_MIC 0x10 180 #define ATH9K_RXERR_KEYMISS 0x20 181 #define ATH9K_RXERR_CORRUPT_DESC 0x40 182 183 #define ATH9K_RX_MORE 0x01 184 #define ATH9K_RX_MORE_AGGR 0x02 185 #define ATH9K_RX_GI 0x04 186 #define ATH9K_RX_2040 0x08 187 #define ATH9K_RX_DELIM_CRC_PRE 0x10 188 #define ATH9K_RX_DELIM_CRC_POST 0x20 189 #define ATH9K_RX_DECRYPT_BUSY 0x40 190 191 #define ATH9K_RXKEYIX_INVALID ((u8)-1) 192 #define ATH9K_TXKEYIX_INVALID ((u8)-1) 193 194 enum ath9k_phyerr { 195 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 196 ATH9K_PHYERR_TIMING = 1, /* Timing error */ 197 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */ 198 ATH9K_PHYERR_RATE = 3, /* Illegal rate */ 199 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */ 200 ATH9K_PHYERR_RADAR = 5, /* Radar detect */ 201 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */ 202 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */ 203 204 ATH9K_PHYERR_OFDM_TIMING = 17, 205 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, 206 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, 207 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20, 208 ATH9K_PHYERR_OFDM_POWER_DROP = 21, 209 ATH9K_PHYERR_OFDM_SERVICE = 22, 210 ATH9K_PHYERR_OFDM_RESTART = 23, 211 ATH9K_PHYERR_FALSE_RADAR_EXT = 24, 212 213 ATH9K_PHYERR_CCK_TIMING = 25, 214 ATH9K_PHYERR_CCK_HEADER_CRC = 26, 215 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, 216 ATH9K_PHYERR_CCK_SERVICE = 30, 217 ATH9K_PHYERR_CCK_RESTART = 31, 218 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32, 219 ATH9K_PHYERR_CCK_POWER_DROP = 33, 220 221 ATH9K_PHYERR_HT_CRC_ERROR = 34, 222 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35, 223 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36, 224 225 ATH9K_PHYERR_SPECTRAL = 38, 226 ATH9K_PHYERR_MAX = 39, 227 }; 228 229 struct ath_desc { 230 u32 ds_link; 231 u32 ds_data; 232 u32 ds_ctl0; 233 u32 ds_ctl1; 234 u32 ds_hw[20]; 235 void *ds_vdata; 236 } __packed __aligned(4); 237 238 #define ATH9K_TXDESC_NOACK 0x0002 239 #define ATH9K_TXDESC_RTSENA 0x0004 240 #define ATH9K_TXDESC_CTSENA 0x0008 241 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 242 * the descriptor its marked on. We take a tx interrupt to reap 243 * descriptors when the h/w hits an EOL condition or 244 * when the descriptor is specifically marked to generate 245 * an interrupt with this flag. Descriptors should be 246 * marked periodically to insure timely replenishing of the 247 * supply needed for sending frames. Defering interrupts 248 * reduces system load and potentially allows more concurrent 249 * work to be done but if done to aggressively can cause 250 * senders to backup. When the hardware queue is left too 251 * large rate control information may also be too out of 252 * date. An Alternative for this is TX interrupt mitigation 253 * but this needs more testing. */ 254 #define ATH9K_TXDESC_INTREQ 0x0010 255 #define ATH9K_TXDESC_VEOL 0x0020 256 #define ATH9K_TXDESC_EXT_ONLY 0x0040 257 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 258 #define ATH9K_TXDESC_VMF 0x0100 259 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 260 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 261 #define ATH9K_TXDESC_LDPC 0x0800 262 #define ATH9K_TXDESC_CLRDMASK 0x1000 263 264 #define ATH9K_TXDESC_PAPRD 0x70000 265 #define ATH9K_TXDESC_PAPRD_S 16 266 267 #define ATH9K_RXDESC_INTREQ 0x0020 268 269 struct ar5416_desc { 270 u32 ds_link; 271 u32 ds_data; 272 u32 ds_ctl0; 273 u32 ds_ctl1; 274 union { 275 struct { 276 u32 ctl2; 277 u32 ctl3; 278 u32 ctl4; 279 u32 ctl5; 280 u32 ctl6; 281 u32 ctl7; 282 u32 ctl8; 283 u32 ctl9; 284 u32 ctl10; 285 u32 ctl11; 286 u32 status0; 287 u32 status1; 288 u32 status2; 289 u32 status3; 290 u32 status4; 291 u32 status5; 292 u32 status6; 293 u32 status7; 294 u32 status8; 295 u32 status9; 296 } tx; 297 struct { 298 u32 status0; 299 u32 status1; 300 u32 status2; 301 u32 status3; 302 u32 status4; 303 u32 status5; 304 u32 status6; 305 u32 status7; 306 u32 status8; 307 } rx; 308 } u; 309 } __packed __aligned(4); 310 311 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 312 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 313 314 #define ds_ctl2 u.tx.ctl2 315 #define ds_ctl3 u.tx.ctl3 316 #define ds_ctl4 u.tx.ctl4 317 #define ds_ctl5 u.tx.ctl5 318 #define ds_ctl6 u.tx.ctl6 319 #define ds_ctl7 u.tx.ctl7 320 #define ds_ctl8 u.tx.ctl8 321 #define ds_ctl9 u.tx.ctl9 322 #define ds_ctl10 u.tx.ctl10 323 #define ds_ctl11 u.tx.ctl11 324 325 #define ds_txstatus0 u.tx.status0 326 #define ds_txstatus1 u.tx.status1 327 #define ds_txstatus2 u.tx.status2 328 #define ds_txstatus3 u.tx.status3 329 #define ds_txstatus4 u.tx.status4 330 #define ds_txstatus5 u.tx.status5 331 #define ds_txstatus6 u.tx.status6 332 #define ds_txstatus7 u.tx.status7 333 #define ds_txstatus8 u.tx.status8 334 #define ds_txstatus9 u.tx.status9 335 336 #define ds_rxstatus0 u.rx.status0 337 #define ds_rxstatus1 u.rx.status1 338 #define ds_rxstatus2 u.rx.status2 339 #define ds_rxstatus3 u.rx.status3 340 #define ds_rxstatus4 u.rx.status4 341 #define ds_rxstatus5 u.rx.status5 342 #define ds_rxstatus6 u.rx.status6 343 #define ds_rxstatus7 u.rx.status7 344 #define ds_rxstatus8 u.rx.status8 345 346 #define AR_FrameLen 0x00000fff 347 #define AR_VirtMoreFrag 0x00001000 348 #define AR_TxCtlRsvd00 0x0000e000 349 #define AR_XmitPower 0x003f0000 350 #define AR_XmitPower_S 16 351 #define AR_RTSEnable 0x00400000 352 #define AR_VEOL 0x00800000 353 #define AR_ClrDestMask 0x01000000 354 #define AR_TxCtlRsvd01 0x1e000000 355 #define AR_TxIntrReq 0x20000000 356 #define AR_DestIdxValid 0x40000000 357 #define AR_CTSEnable 0x80000000 358 359 #define AR_TxMore 0x00001000 360 #define AR_DestIdx 0x000fe000 361 #define AR_DestIdx_S 13 362 #define AR_FrameType 0x00f00000 363 #define AR_FrameType_S 20 364 #define AR_NoAck 0x01000000 365 #define AR_InsertTS 0x02000000 366 #define AR_CorruptFCS 0x04000000 367 #define AR_ExtOnly 0x08000000 368 #define AR_ExtAndCtl 0x10000000 369 #define AR_MoreAggr 0x20000000 370 #define AR_IsAggr 0x40000000 371 372 #define AR_BurstDur 0x00007fff 373 #define AR_BurstDur_S 0 374 #define AR_DurUpdateEna 0x00008000 375 #define AR_XmitDataTries0 0x000f0000 376 #define AR_XmitDataTries0_S 16 377 #define AR_XmitDataTries1 0x00f00000 378 #define AR_XmitDataTries1_S 20 379 #define AR_XmitDataTries2 0x0f000000 380 #define AR_XmitDataTries2_S 24 381 #define AR_XmitDataTries3 0xf0000000 382 #define AR_XmitDataTries3_S 28 383 384 #define AR_XmitRate0 0x000000ff 385 #define AR_XmitRate0_S 0 386 #define AR_XmitRate1 0x0000ff00 387 #define AR_XmitRate1_S 8 388 #define AR_XmitRate2 0x00ff0000 389 #define AR_XmitRate2_S 16 390 #define AR_XmitRate3 0xff000000 391 #define AR_XmitRate3_S 24 392 393 #define AR_PacketDur0 0x00007fff 394 #define AR_PacketDur0_S 0 395 #define AR_RTSCTSQual0 0x00008000 396 #define AR_PacketDur1 0x7fff0000 397 #define AR_PacketDur1_S 16 398 #define AR_RTSCTSQual1 0x80000000 399 400 #define AR_PacketDur2 0x00007fff 401 #define AR_PacketDur2_S 0 402 #define AR_RTSCTSQual2 0x00008000 403 #define AR_PacketDur3 0x7fff0000 404 #define AR_PacketDur3_S 16 405 #define AR_RTSCTSQual3 0x80000000 406 407 #define AR_AggrLen 0x0000ffff 408 #define AR_AggrLen_S 0 409 #define AR_TxCtlRsvd60 0x00030000 410 #define AR_PadDelim 0x03fc0000 411 #define AR_PadDelim_S 18 412 #define AR_EncrType 0x0c000000 413 #define AR_EncrType_S 26 414 #define AR_TxCtlRsvd61 0xf0000000 415 #define AR_LDPC 0x80000000 416 417 #define AR_2040_0 0x00000001 418 #define AR_GI0 0x00000002 419 #define AR_ChainSel0 0x0000001c 420 #define AR_ChainSel0_S 2 421 #define AR_2040_1 0x00000020 422 #define AR_GI1 0x00000040 423 #define AR_ChainSel1 0x00000380 424 #define AR_ChainSel1_S 7 425 #define AR_2040_2 0x00000400 426 #define AR_GI2 0x00000800 427 #define AR_ChainSel2 0x00007000 428 #define AR_ChainSel2_S 12 429 #define AR_2040_3 0x00008000 430 #define AR_GI3 0x00010000 431 #define AR_ChainSel3 0x000e0000 432 #define AR_ChainSel3_S 17 433 #define AR_RTSCTSRate 0x0ff00000 434 #define AR_RTSCTSRate_S 20 435 #define AR_STBC0 0x10000000 436 #define AR_STBC1 0x20000000 437 #define AR_STBC2 0x40000000 438 #define AR_STBC3 0x80000000 439 440 #define AR_TxRSSIAnt00 0x000000ff 441 #define AR_TxRSSIAnt00_S 0 442 #define AR_TxRSSIAnt01 0x0000ff00 443 #define AR_TxRSSIAnt01_S 8 444 #define AR_TxRSSIAnt02 0x00ff0000 445 #define AR_TxRSSIAnt02_S 16 446 #define AR_TxStatusRsvd00 0x3f000000 447 #define AR_TxBaStatus 0x40000000 448 #define AR_TxStatusRsvd01 0x80000000 449 450 /* 451 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was 452 * transmitted successfully. If clear, no ACK or BA was received to indicate 453 * successful transmission when we were expecting an ACK or BA. 454 */ 455 #define AR_FrmXmitOK 0x00000001 456 #define AR_ExcessiveRetries 0x00000002 457 #define AR_FIFOUnderrun 0x00000004 458 #define AR_Filtered 0x00000008 459 #define AR_RTSFailCnt 0x000000f0 460 #define AR_RTSFailCnt_S 4 461 #define AR_DataFailCnt 0x00000f00 462 #define AR_DataFailCnt_S 8 463 #define AR_VirtRetryCnt 0x0000f000 464 #define AR_VirtRetryCnt_S 12 465 #define AR_TxDelimUnderrun 0x00010000 466 #define AR_TxDataUnderrun 0x00020000 467 #define AR_DescCfgErr 0x00040000 468 #define AR_TxTimerExpired 0x00080000 469 #define AR_TxStatusRsvd10 0xfff00000 470 471 #define AR_SendTimestamp ds_txstatus2 472 #define AR_BaBitmapLow ds_txstatus3 473 #define AR_BaBitmapHigh ds_txstatus4 474 475 #define AR_TxRSSIAnt10 0x000000ff 476 #define AR_TxRSSIAnt10_S 0 477 #define AR_TxRSSIAnt11 0x0000ff00 478 #define AR_TxRSSIAnt11_S 8 479 #define AR_TxRSSIAnt12 0x00ff0000 480 #define AR_TxRSSIAnt12_S 16 481 #define AR_TxRSSICombined 0xff000000 482 #define AR_TxRSSICombined_S 24 483 484 #define AR_TxTid 0xf0000000 485 #define AR_TxTid_S 28 486 487 #define AR_TxEVM0 ds_txstatus5 488 #define AR_TxEVM1 ds_txstatus6 489 #define AR_TxEVM2 ds_txstatus7 490 491 #define AR_TxDone 0x00000001 492 #define AR_SeqNum 0x00001ffe 493 #define AR_SeqNum_S 1 494 #define AR_TxStatusRsvd80 0x0001e000 495 #define AR_TxOpExceeded 0x00020000 496 #define AR_TxStatusRsvd81 0x001c0000 497 #define AR_FinalTxIdx 0x00600000 498 #define AR_FinalTxIdx_S 21 499 #define AR_TxStatusRsvd82 0x01800000 500 #define AR_PowerMgmt 0x02000000 501 #define AR_TxStatusRsvd83 0xfc000000 502 503 #define AR_RxCTLRsvd00 0xffffffff 504 505 #define AR_RxCtlRsvd00 0x00001000 506 #define AR_RxIntrReq 0x00002000 507 #define AR_RxCtlRsvd01 0xffffc000 508 509 #define AR_RxRSSIAnt00 0x000000ff 510 #define AR_RxRSSIAnt00_S 0 511 #define AR_RxRSSIAnt01 0x0000ff00 512 #define AR_RxRSSIAnt01_S 8 513 #define AR_RxRSSIAnt02 0x00ff0000 514 #define AR_RxRSSIAnt02_S 16 515 #define AR_RxRate 0xff000000 516 #define AR_RxRate_S 24 517 #define AR_RxStatusRsvd00 0xff000000 518 519 #define AR_DataLen 0x00000fff 520 #define AR_RxMore 0x00001000 521 #define AR_NumDelim 0x003fc000 522 #define AR_NumDelim_S 14 523 #define AR_RxStatusRsvd10 0xff800000 524 525 #define AR_RcvTimestamp ds_rxstatus2 526 527 #define AR_GI 0x00000001 528 #define AR_2040 0x00000002 529 #define AR_Parallel40 0x00000004 530 #define AR_Parallel40_S 2 531 #define AR_STBC 0x00000008 /* on ar9280 and later */ 532 #define AR_RxStatusRsvd30 0x000000f0 533 #define AR_RxAntenna 0xffffff00 534 #define AR_RxAntenna_S 8 535 536 #define AR_RxRSSIAnt10 0x000000ff 537 #define AR_RxRSSIAnt10_S 0 538 #define AR_RxRSSIAnt11 0x0000ff00 539 #define AR_RxRSSIAnt11_S 8 540 #define AR_RxRSSIAnt12 0x00ff0000 541 #define AR_RxRSSIAnt12_S 16 542 #define AR_RxRSSICombined 0xff000000 543 #define AR_RxRSSICombined_S 24 544 545 #define AR_RxEVM0 ds_rxstatus4 546 #define AR_RxEVM1 ds_rxstatus5 547 #define AR_RxEVM2 ds_rxstatus6 548 549 #define AR_RxDone 0x00000001 550 #define AR_RxFrameOK 0x00000002 551 #define AR_CRCErr 0x00000004 552 #define AR_DecryptCRCErr 0x00000008 553 #define AR_PHYErr 0x00000010 554 #define AR_MichaelErr 0x00000020 555 #define AR_PreDelimCRCErr 0x00000040 556 #define AR_RxStatusRsvd70 0x00000080 557 #define AR_RxKeyIdxValid 0x00000100 558 #define AR_KeyIdx 0x0000fe00 559 #define AR_KeyIdx_S 9 560 #define AR_PHYErrCode 0x0000ff00 561 #define AR_PHYErrCode_S 8 562 #define AR_RxMoreAggr 0x00010000 563 #define AR_RxAggr 0x00020000 564 #define AR_PostDelimCRCErr 0x00040000 565 #define AR_RxStatusRsvd71 0x3ff80000 566 #define AR_RxFirstAggr 0x20000000 567 #define AR_DecryptBusyErr 0x40000000 568 #define AR_KeyMiss 0x80000000 569 570 enum ath9k_tx_queue { 571 ATH9K_TX_QUEUE_INACTIVE = 0, 572 ATH9K_TX_QUEUE_DATA, 573 ATH9K_TX_QUEUE_BEACON, 574 ATH9K_TX_QUEUE_CAB, 575 ATH9K_TX_QUEUE_UAPSD, 576 ATH9K_TX_QUEUE_PSPOLL 577 }; 578 579 #define ATH9K_NUM_TX_QUEUES 10 580 581 /* Used as a queue subtype instead of a WMM AC */ 582 #define ATH9K_WME_UPSD 4 583 584 enum ath9k_tx_queue_flags { 585 TXQ_FLAG_TXINT_ENABLE = 0x0001, 586 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 587 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 588 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 589 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 590 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 591 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 592 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 593 }; 594 595 #define ATH9K_TXQ_USEDEFAULT ((u32) -1) 596 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 597 598 #define ATH9K_DECOMP_MASK_SIZE 128 599 600 enum ath9k_pkt_type { 601 ATH9K_PKT_TYPE_NORMAL = 0, 602 ATH9K_PKT_TYPE_ATIM, 603 ATH9K_PKT_TYPE_PSPOLL, 604 ATH9K_PKT_TYPE_BEACON, 605 ATH9K_PKT_TYPE_PROBE_RESP, 606 ATH9K_PKT_TYPE_CHIRP, 607 ATH9K_PKT_TYPE_GRP_POLL, 608 }; 609 610 struct ath9k_tx_queue_info { 611 u32 tqi_ver; 612 enum ath9k_tx_queue tqi_type; 613 int tqi_subtype; 614 enum ath9k_tx_queue_flags tqi_qflags; 615 u32 tqi_priority; 616 u32 tqi_aifs; 617 u32 tqi_cwmin; 618 u32 tqi_cwmax; 619 u16 tqi_shretry; 620 u16 tqi_lgretry; 621 u32 tqi_cbrPeriod; 622 u32 tqi_cbrOverflowLimit; 623 u32 tqi_burstTime; 624 u32 tqi_readyTime; 625 u32 tqi_physCompBuf; 626 u32 tqi_intFlags; 627 }; 628 629 enum ath9k_rx_filter { 630 ATH9K_RX_FILTER_UCAST = 0x00000001, 631 ATH9K_RX_FILTER_MCAST = 0x00000002, 632 ATH9K_RX_FILTER_BCAST = 0x00000004, 633 ATH9K_RX_FILTER_CONTROL = 0x00000008, 634 ATH9K_RX_FILTER_BEACON = 0x00000010, 635 ATH9K_RX_FILTER_PROM = 0x00000020, 636 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 637 ATH9K_RX_FILTER_PHYERR = 0x00000100, 638 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 639 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 640 ATH9K_RX_FILTER_COMP_BA = 0x00000800, 641 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000, 642 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 643 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 644 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 645 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000, 646 ATH9K_RX_FILTER_4ADDRESS = 0x00100000, 647 }; 648 649 #define ATH9K_RATESERIES_RTS_CTS 0x0001 650 #define ATH9K_RATESERIES_2040 0x0002 651 #define ATH9K_RATESERIES_HALFGI 0x0004 652 #define ATH9K_RATESERIES_STBC 0x0008 653 654 struct ath9k_11n_rate_series { 655 u32 Tries; 656 u32 Rate; 657 u32 PktDuration; 658 u32 ChSel; 659 u32 RateFlags; 660 }; 661 662 enum aggr_type { 663 AGGR_BUF_NONE, 664 AGGR_BUF_FIRST, 665 AGGR_BUF_MIDDLE, 666 AGGR_BUF_LAST, 667 }; 668 669 enum ath9k_key_type { 670 ATH9K_KEY_TYPE_CLEAR, 671 ATH9K_KEY_TYPE_WEP, 672 ATH9K_KEY_TYPE_AES, 673 ATH9K_KEY_TYPE_TKIP, 674 }; 675 676 struct ath_tx_info { 677 u8 qcu; 678 679 bool is_first; 680 bool is_last; 681 682 enum aggr_type aggr; 683 u8 ndelim; 684 u16 aggr_len; 685 686 dma_addr_t link; 687 int pkt_len; 688 u32 flags; 689 690 dma_addr_t buf_addr[4]; 691 int buf_len[4]; 692 693 struct ath9k_11n_rate_series rates[4]; 694 u8 rtscts_rate; 695 bool dur_update; 696 697 enum ath9k_pkt_type type; 698 enum ath9k_key_type keytype; 699 u8 keyix; 700 u8 txpower; 701 }; 702 703 struct ath_hw; 704 struct ath9k_channel; 705 enum ath9k_int; 706 707 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 708 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 709 void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 710 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 711 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 712 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); 713 void ath9k_hw_abort_tx_dma(struct ath_hw *ah); 714 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 715 const struct ath9k_tx_queue_info *qinfo); 716 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 717 struct ath9k_tx_queue_info *qinfo); 718 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 719 const struct ath9k_tx_queue_info *qinfo); 720 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 721 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 722 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 723 struct ath_rx_status *rs); 724 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 725 u32 size, u32 flags); 726 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 727 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 728 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning); 729 void ath9k_hw_abortpcurecv(struct ath_hw *ah); 730 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset); 731 int ath9k_hw_beaconq_setup(struct ath_hw *ah); 732 733 /* Interrupt Handling */ 734 bool ath9k_hw_intrpend(struct ath_hw *ah); 735 void ath9k_hw_set_interrupts(struct ath_hw *ah); 736 void ath9k_hw_enable_interrupts(struct ath_hw *ah); 737 void ath9k_hw_disable_interrupts(struct ath_hw *ah); 738 void ath9k_hw_kill_interrupts(struct ath_hw *ah); 739 740 void ar9002_hw_attach_mac_ops(struct ath_hw *ah); 741 742 #endif /* MAC_H */ 743