1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include <linux/export.h> 20 21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 22 struct ath9k_tx_queue_info *qi) 23 { 24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, 25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 28 ah->txurn_interrupt_mask); 29 30 ENABLE_REGWRITE_BUFFER(ah); 31 32 REG_WRITE(ah, AR_IMR_S0, 33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); 35 REG_WRITE(ah, AR_IMR_S1, 36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) 37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 38 39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; 40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); 41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 42 43 REGWRITE_BUFFER_FLUSH(ah); 44 } 45 46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) 47 { 48 return REG_READ(ah, AR_QTXDP(q)); 49 } 50 EXPORT_SYMBOL(ath9k_hw_gettxbuf); 51 52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) 53 { 54 REG_WRITE(ah, AR_QTXDP(q), txdp); 55 } 56 EXPORT_SYMBOL(ath9k_hw_puttxbuf); 57 58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 59 { 60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); 61 REG_WRITE(ah, AR_Q_TXE, 1 << q); 62 } 63 EXPORT_SYMBOL(ath9k_hw_txstart); 64 65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) 66 { 67 u32 npend; 68 69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 70 if (npend == 0) { 71 72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) 73 npend = 1; 74 } 75 76 return npend; 77 } 78 EXPORT_SYMBOL(ath9k_hw_numtxpending); 79 80 /** 81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level 82 * 83 * @ah: atheros hardware struct 84 * @bIncTrigLevel: whether or not the frame trigger level should be updated 85 * 86 * The frame trigger level specifies the minimum number of bytes, 87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO 88 * before the PCU will initiate sending the frame on the air. This can 89 * mean we initiate transmit before a full frame is on the PCU TX FIFO. 90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs 91 * first) 92 * 93 * Caution must be taken to ensure to set the frame trigger level based 94 * on the DMA request size. For example if the DMA request size is set to 95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because 96 * there need to be enough space in the tx FIFO for the requested transfer 97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set 98 * the threshold to a value beyond 6, then the transmit will hang. 99 * 100 * Current dual stream devices have a PCU TX FIFO size of 8 KB. 101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however, 102 * there is a hardware issue which forces us to use 2 KB instead so the 103 * frame trigger level must not exceed 2 KB for these chipsets. 104 */ 105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) 106 { 107 u32 txcfg, curLevel, newLevel; 108 109 if (ah->tx_trig_level >= ah->config.max_txtrig_level) 110 return false; 111 112 ath9k_hw_disable_interrupts(ah); 113 114 txcfg = REG_READ(ah, AR_TXCFG); 115 curLevel = MS(txcfg, AR_FTRIG); 116 newLevel = curLevel; 117 if (bIncTrigLevel) { 118 if (curLevel < ah->config.max_txtrig_level) 119 newLevel++; 120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD) 121 newLevel--; 122 if (newLevel != curLevel) 123 REG_WRITE(ah, AR_TXCFG, 124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); 125 126 ath9k_hw_enable_interrupts(ah); 127 128 ah->tx_trig_level = newLevel; 129 130 return newLevel != curLevel; 131 } 132 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel); 133 134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah) 135 { 136 int maxdelay = 1000; 137 int i, q; 138 139 if (ah->curchan) { 140 if (IS_CHAN_HALF_RATE(ah->curchan)) 141 maxdelay *= 2; 142 else if (IS_CHAN_QUARTER_RATE(ah->curchan)) 143 maxdelay *= 4; 144 } 145 146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 147 148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 151 152 for (q = 0; q < AR_NUM_QCU; q++) { 153 for (i = 0; i < maxdelay; i++) { 154 if (i) 155 udelay(5); 156 157 if (!ath9k_hw_numtxpending(ah, q)) 158 break; 159 } 160 } 161 162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 165 166 REG_WRITE(ah, AR_Q_TXD, 0); 167 } 168 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma); 169 170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) 171 { 172 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */ 173 #define ATH9K_TIME_QUANTUM 100 /* usec */ 174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 175 int wait; 176 177 REG_WRITE(ah, AR_Q_TXD, 1 << q); 178 179 for (wait = wait_time; wait != 0; wait--) { 180 if (wait != wait_time) 181 udelay(ATH9K_TIME_QUANTUM); 182 183 if (ath9k_hw_numtxpending(ah, q) == 0) 184 break; 185 } 186 187 REG_WRITE(ah, AR_Q_TXD, 0); 188 189 return wait != 0; 190 191 #undef ATH9K_TX_STOP_DMA_TIMEOUT 192 #undef ATH9K_TIME_QUANTUM 193 } 194 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue); 195 196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 197 const struct ath9k_tx_queue_info *qinfo) 198 { 199 u32 cw; 200 struct ath_common *common = ath9k_hw_common(ah); 201 struct ath9k_tx_queue_info *qi; 202 203 qi = &ah->txq[q]; 204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 205 ath_dbg(common, QUEUE, 206 "Set TXQ properties, inactive queue: %u\n", q); 207 return false; 208 } 209 210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); 211 212 qi->tqi_ver = qinfo->tqi_ver; 213 qi->tqi_subtype = qinfo->tqi_subtype; 214 qi->tqi_qflags = qinfo->tqi_qflags; 215 qi->tqi_priority = qinfo->tqi_priority; 216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) 217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); 218 else 219 qi->tqi_aifs = INIT_AIFS; 220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { 221 cw = min(qinfo->tqi_cwmin, 1024U); 222 qi->tqi_cwmin = 1; 223 while (qi->tqi_cwmin < cw) 224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; 225 } else 226 qi->tqi_cwmin = qinfo->tqi_cwmin; 227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { 228 cw = min(qinfo->tqi_cwmax, 1024U); 229 qi->tqi_cwmax = 1; 230 while (qi->tqi_cwmax < cw) 231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; 232 } else 233 qi->tqi_cwmax = INIT_CWMAX; 234 235 if (qinfo->tqi_shretry != 0) 236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); 237 else 238 qi->tqi_shretry = INIT_SH_RETRY; 239 if (qinfo->tqi_lgretry != 0) 240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); 241 else 242 qi->tqi_lgretry = INIT_LG_RETRY; 243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; 244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; 245 qi->tqi_burstTime = qinfo->tqi_burstTime; 246 qi->tqi_readyTime = qinfo->tqi_readyTime; 247 248 switch (qinfo->tqi_subtype) { 249 case ATH9K_WME_UPSD: 250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) 251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; 252 break; 253 default: 254 break; 255 } 256 257 return true; 258 } 259 EXPORT_SYMBOL(ath9k_hw_set_txq_props); 260 261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 262 struct ath9k_tx_queue_info *qinfo) 263 { 264 struct ath_common *common = ath9k_hw_common(ah); 265 struct ath9k_tx_queue_info *qi; 266 267 qi = &ah->txq[q]; 268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 269 ath_dbg(common, QUEUE, 270 "Get TXQ properties, inactive queue: %u\n", q); 271 return false; 272 } 273 274 qinfo->tqi_qflags = qi->tqi_qflags; 275 qinfo->tqi_ver = qi->tqi_ver; 276 qinfo->tqi_subtype = qi->tqi_subtype; 277 qinfo->tqi_qflags = qi->tqi_qflags; 278 qinfo->tqi_priority = qi->tqi_priority; 279 qinfo->tqi_aifs = qi->tqi_aifs; 280 qinfo->tqi_cwmin = qi->tqi_cwmin; 281 qinfo->tqi_cwmax = qi->tqi_cwmax; 282 qinfo->tqi_shretry = qi->tqi_shretry; 283 qinfo->tqi_lgretry = qi->tqi_lgretry; 284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; 285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; 286 qinfo->tqi_burstTime = qi->tqi_burstTime; 287 qinfo->tqi_readyTime = qi->tqi_readyTime; 288 289 return true; 290 } 291 EXPORT_SYMBOL(ath9k_hw_get_txq_props); 292 293 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 294 const struct ath9k_tx_queue_info *qinfo) 295 { 296 struct ath_common *common = ath9k_hw_common(ah); 297 struct ath9k_tx_queue_info *qi; 298 int q; 299 300 switch (type) { 301 case ATH9K_TX_QUEUE_BEACON: 302 q = ATH9K_NUM_TX_QUEUES - 1; 303 break; 304 case ATH9K_TX_QUEUE_CAB: 305 q = ATH9K_NUM_TX_QUEUES - 2; 306 break; 307 case ATH9K_TX_QUEUE_PSPOLL: 308 q = 1; 309 break; 310 case ATH9K_TX_QUEUE_UAPSD: 311 q = ATH9K_NUM_TX_QUEUES - 3; 312 break; 313 case ATH9K_TX_QUEUE_DATA: 314 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++) 315 if (ah->txq[q].tqi_type == 316 ATH9K_TX_QUEUE_INACTIVE) 317 break; 318 if (q == ATH9K_NUM_TX_QUEUES) { 319 ath_err(common, "No available TX queue\n"); 320 return -1; 321 } 322 break; 323 default: 324 ath_err(common, "Invalid TX queue type: %u\n", type); 325 return -1; 326 } 327 328 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); 329 330 qi = &ah->txq[q]; 331 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 332 ath_err(common, "TX queue: %u already active\n", q); 333 return -1; 334 } 335 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 336 qi->tqi_type = type; 337 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; 338 (void) ath9k_hw_set_txq_props(ah, q, qinfo); 339 340 return q; 341 } 342 EXPORT_SYMBOL(ath9k_hw_setuptxqueue); 343 344 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) 345 { 346 ah->txok_interrupt_mask &= ~(1 << q); 347 ah->txerr_interrupt_mask &= ~(1 << q); 348 ah->txdesc_interrupt_mask &= ~(1 << q); 349 ah->txeol_interrupt_mask &= ~(1 << q); 350 ah->txurn_interrupt_mask &= ~(1 << q); 351 } 352 353 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 354 { 355 struct ath_common *common = ath9k_hw_common(ah); 356 struct ath9k_tx_queue_info *qi; 357 358 qi = &ah->txq[q]; 359 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 360 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); 361 return false; 362 } 363 364 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); 365 366 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 367 ath9k_hw_clear_queue_interrupts(ah, q); 368 ath9k_hw_set_txq_interrupts(ah, qi); 369 370 return true; 371 } 372 EXPORT_SYMBOL(ath9k_hw_releasetxqueue); 373 374 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 375 { 376 struct ath_common *common = ath9k_hw_common(ah); 377 struct ath9k_tx_queue_info *qi; 378 u32 cwMin, chanCwMin, value; 379 380 qi = &ah->txq[q]; 381 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 382 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); 383 return true; 384 } 385 386 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); 387 388 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 389 chanCwMin = INIT_CWMIN; 390 391 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); 392 } else 393 cwMin = qi->tqi_cwmin; 394 395 ENABLE_REGWRITE_BUFFER(ah); 396 397 REG_WRITE(ah, AR_DLCL_IFS(q), 398 SM(cwMin, AR_D_LCL_IFS_CWMIN) | 399 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | 400 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 401 402 REG_WRITE(ah, AR_DRETRY_LIMIT(q), 403 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 404 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 405 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 406 407 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); 408 409 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah)) 410 REG_WRITE(ah, AR_DMISC(q), 411 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); 412 else 413 REG_WRITE(ah, AR_DMISC(q), 414 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); 415 416 if (qi->tqi_cbrPeriod) { 417 REG_WRITE(ah, AR_QCBRCFG(q), 418 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 419 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); 420 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | 421 (qi->tqi_cbrOverflowLimit ? 422 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); 423 } 424 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { 425 REG_WRITE(ah, AR_QRDYTIMECFG(q), 426 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 427 AR_Q_RDYTIMECFG_EN); 428 } 429 430 REG_WRITE(ah, AR_DCHNTIME(q), 431 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 432 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 433 434 if (qi->tqi_burstTime 435 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) 436 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); 437 438 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) 439 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); 440 441 REGWRITE_BUFFER_FLUSH(ah); 442 443 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) 444 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); 445 446 switch (qi->tqi_type) { 447 case ATH9K_TX_QUEUE_BEACON: 448 ENABLE_REGWRITE_BUFFER(ah); 449 450 REG_SET_BIT(ah, AR_QMISC(q), 451 AR_Q_MISC_FSP_DBA_GATED 452 | AR_Q_MISC_BEACON_USE 453 | AR_Q_MISC_CBR_INCR_DIS1); 454 455 REG_SET_BIT(ah, AR_DMISC(q), 456 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 457 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 458 | AR_D_MISC_BEACON_USE 459 | AR_D_MISC_POST_FR_BKOFF_DIS); 460 461 REGWRITE_BUFFER_FLUSH(ah); 462 463 /* 464 * cwmin and cwmax should be 0 for beacon queue 465 * but not for IBSS as we would create an imbalance 466 * on beaconing fairness for participating nodes. 467 */ 468 if (AR_SREV_9300_20_OR_LATER(ah) && 469 ah->opmode != NL80211_IFTYPE_ADHOC) { 470 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 471 | SM(0, AR_D_LCL_IFS_CWMAX) 472 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 473 } 474 break; 475 case ATH9K_TX_QUEUE_CAB: 476 ENABLE_REGWRITE_BUFFER(ah); 477 478 REG_SET_BIT(ah, AR_QMISC(q), 479 AR_Q_MISC_FSP_DBA_GATED 480 | AR_Q_MISC_CBR_INCR_DIS1 481 | AR_Q_MISC_CBR_INCR_DIS0); 482 value = (qi->tqi_readyTime - 483 (ah->config.sw_beacon_response_time - 484 ah->config.dma_beacon_response_time)) * 1024; 485 REG_WRITE(ah, AR_QRDYTIMECFG(q), 486 value | AR_Q_RDYTIMECFG_EN); 487 REG_SET_BIT(ah, AR_DMISC(q), 488 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 489 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 490 491 REGWRITE_BUFFER_FLUSH(ah); 492 493 break; 494 case ATH9K_TX_QUEUE_PSPOLL: 495 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); 496 break; 497 case ATH9K_TX_QUEUE_UAPSD: 498 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); 499 break; 500 default: 501 break; 502 } 503 504 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { 505 REG_SET_BIT(ah, AR_DMISC(q), 506 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 507 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 508 AR_D_MISC_POST_FR_BKOFF_DIS); 509 } 510 511 if (AR_SREV_9300_20_OR_LATER(ah)) 512 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 513 514 ath9k_hw_clear_queue_interrupts(ah, q); 515 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) { 516 ah->txok_interrupt_mask |= 1 << q; 517 ah->txerr_interrupt_mask |= 1 << q; 518 } 519 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) 520 ah->txdesc_interrupt_mask |= 1 << q; 521 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) 522 ah->txeol_interrupt_mask |= 1 << q; 523 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) 524 ah->txurn_interrupt_mask |= 1 << q; 525 ath9k_hw_set_txq_interrupts(ah, qi); 526 527 return true; 528 } 529 EXPORT_SYMBOL(ath9k_hw_resettxqueue); 530 531 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 532 struct ath_rx_status *rs) 533 { 534 struct ar5416_desc ads; 535 struct ar5416_desc *adsp = AR5416DESC(ds); 536 u32 phyerr; 537 538 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) 539 return -EINPROGRESS; 540 541 ads.u.rx = adsp->u.rx; 542 543 rs->rs_status = 0; 544 rs->rs_flags = 0; 545 rs->flag = 0; 546 547 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; 548 rs->rs_tstamp = ads.AR_RcvTimestamp; 549 550 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { 551 rs->rs_rssi = ATH9K_RSSI_BAD; 552 rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD; 553 rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD; 554 rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD; 555 rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD; 556 rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD; 557 rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD; 558 } else { 559 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); 560 rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0, 561 AR_RxRSSIAnt00); 562 rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0, 563 AR_RxRSSIAnt01); 564 rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0, 565 AR_RxRSSIAnt02); 566 rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4, 567 AR_RxRSSIAnt10); 568 rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4, 569 AR_RxRSSIAnt11); 570 rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4, 571 AR_RxRSSIAnt12); 572 } 573 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) 574 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); 575 else 576 rs->rs_keyix = ATH9K_RXKEYIX_INVALID; 577 578 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); 579 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; 580 581 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0; 582 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 583 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 584 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); 585 586 /* directly mapped flags for ieee80211_rx_status */ 587 rs->flag |= 588 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0; 589 rs->flag |= 590 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0; 591 if (AR_SREV_9280_20_OR_LATER(ah)) 592 rs->flag |= 593 (ads.ds_rxstatus3 & AR_STBC) ? 594 /* we can only Nss=1 STBC */ 595 (1 << RX_FLAG_STBC_SHIFT) : 0; 596 597 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) 598 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 599 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) 600 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 601 if (ads.ds_rxstatus8 & AR_DecryptBusyErr) 602 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 603 604 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { 605 /* 606 * Treat these errors as mutually exclusive to avoid spurious 607 * extra error reports from the hardware. If a CRC error is 608 * reported, then decryption and MIC errors are irrelevant, 609 * the frame is going to be dropped either way 610 */ 611 if (ads.ds_rxstatus8 & AR_PHYErr) { 612 rs->rs_status |= ATH9K_RXERR_PHY; 613 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); 614 rs->rs_phyerr = phyerr; 615 } else if (ads.ds_rxstatus8 & AR_CRCErr) 616 rs->rs_status |= ATH9K_RXERR_CRC; 617 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) 618 rs->rs_status |= ATH9K_RXERR_DECRYPT; 619 else if (ads.ds_rxstatus8 & AR_MichaelErr) 620 rs->rs_status |= ATH9K_RXERR_MIC; 621 } else { 622 if (ads.ds_rxstatus8 & 623 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr)) 624 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; 625 626 /* Only up to MCS16 supported, everything above is invalid */ 627 if (rs->rs_rate >= 0x90) 628 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; 629 } 630 631 if (ads.ds_rxstatus8 & AR_KeyMiss) 632 rs->rs_status |= ATH9K_RXERR_KEYMISS; 633 634 return 0; 635 } 636 EXPORT_SYMBOL(ath9k_hw_rxprocdesc); 637 638 /* 639 * This can stop or re-enables RX. 640 * 641 * If bool is set this will kill any frame which is currently being 642 * transferred between the MAC and baseband and also prevent any new 643 * frames from getting started. 644 */ 645 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) 646 { 647 u32 reg; 648 649 if (set) { 650 REG_SET_BIT(ah, AR_DIAG_SW, 651 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 652 653 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 654 0, AH_WAIT_TIMEOUT)) { 655 REG_CLR_BIT(ah, AR_DIAG_SW, 656 (AR_DIAG_RX_DIS | 657 AR_DIAG_RX_ABORT)); 658 659 reg = REG_READ(ah, AR_OBS_BUS_1); 660 ath_err(ath9k_hw_common(ah), 661 "RX failed to go idle in 10 ms RXSM=0x%x\n", 662 reg); 663 664 return false; 665 } 666 } else { 667 REG_CLR_BIT(ah, AR_DIAG_SW, 668 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 669 } 670 671 return true; 672 } 673 EXPORT_SYMBOL(ath9k_hw_setrxabort); 674 675 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) 676 { 677 REG_WRITE(ah, AR_RXDP, rxdp); 678 } 679 EXPORT_SYMBOL(ath9k_hw_putrxbuf); 680 681 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) 682 { 683 ath9k_enable_mib_counters(ah); 684 685 ath9k_ani_reset(ah, is_scanning); 686 687 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 688 } 689 EXPORT_SYMBOL(ath9k_hw_startpcureceive); 690 691 void ath9k_hw_abortpcurecv(struct ath_hw *ah) 692 { 693 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); 694 695 ath9k_hw_disable_mib_counters(ah); 696 } 697 EXPORT_SYMBOL(ath9k_hw_abortpcurecv); 698 699 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) 700 { 701 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 702 struct ath_common *common = ath9k_hw_common(ah); 703 u32 mac_status, last_mac_status = 0; 704 int i; 705 706 /* Enable access to the DMA observation bus */ 707 REG_WRITE(ah, AR_MACMISC, 708 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 709 (AR_MACMISC_MISC_OBS_BUS_1 << 710 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 711 712 REG_WRITE(ah, AR_CR, AR_CR_RXD); 713 714 /* Wait for rx enable bit to go low */ 715 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) { 716 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) 717 break; 718 719 if (!AR_SREV_9300_20_OR_LATER(ah)) { 720 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; 721 if (mac_status == 0x1c0 && mac_status == last_mac_status) { 722 *reset = true; 723 break; 724 } 725 726 last_mac_status = mac_status; 727 } 728 729 udelay(AH_TIME_QUANTUM); 730 } 731 732 if (i == 0) { 733 ath_err(common, 734 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", 735 AH_RX_STOP_DMA_TIMEOUT / 1000, 736 REG_READ(ah, AR_CR), 737 REG_READ(ah, AR_DIAG_SW), 738 REG_READ(ah, AR_DMADBG_7)); 739 return false; 740 } else { 741 return true; 742 } 743 744 #undef AH_RX_STOP_DMA_TIMEOUT 745 } 746 EXPORT_SYMBOL(ath9k_hw_stopdmarecv); 747 748 int ath9k_hw_beaconq_setup(struct ath_hw *ah) 749 { 750 struct ath9k_tx_queue_info qi; 751 752 memset(&qi, 0, sizeof(qi)); 753 qi.tqi_aifs = 1; 754 qi.tqi_cwmin = 0; 755 qi.tqi_cwmax = 0; 756 757 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 758 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 759 760 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); 761 } 762 EXPORT_SYMBOL(ath9k_hw_beaconq_setup); 763 764 bool ath9k_hw_intrpend(struct ath_hw *ah) 765 { 766 u32 host_isr; 767 768 if (AR_SREV_9100(ah)) 769 return true; 770 771 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 772 773 if (((host_isr & AR_INTR_MAC_IRQ) || 774 (host_isr & AR_INTR_ASYNC_MASK_MCI)) && 775 (host_isr != AR_INTR_SPURIOUS)) 776 return true; 777 778 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 779 if ((host_isr & AR_INTR_SYNC_DEFAULT) 780 && (host_isr != AR_INTR_SPURIOUS)) 781 return true; 782 783 return false; 784 } 785 EXPORT_SYMBOL(ath9k_hw_intrpend); 786 787 void ath9k_hw_kill_interrupts(struct ath_hw *ah) 788 { 789 struct ath_common *common = ath9k_hw_common(ah); 790 791 ath_dbg(common, INTERRUPT, "disable IER\n"); 792 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 793 (void) REG_READ(ah, AR_IER); 794 if (!AR_SREV_9100(ah)) { 795 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 796 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 797 798 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 799 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 800 } 801 } 802 EXPORT_SYMBOL(ath9k_hw_kill_interrupts); 803 804 void ath9k_hw_disable_interrupts(struct ath_hw *ah) 805 { 806 if (!(ah->imask & ATH9K_INT_GLOBAL)) 807 atomic_set(&ah->intr_ref_cnt, -1); 808 else 809 atomic_dec(&ah->intr_ref_cnt); 810 811 ath9k_hw_kill_interrupts(ah); 812 } 813 EXPORT_SYMBOL(ath9k_hw_disable_interrupts); 814 815 void ath9k_hw_enable_interrupts(struct ath_hw *ah) 816 { 817 struct ath_common *common = ath9k_hw_common(ah); 818 u32 sync_default = AR_INTR_SYNC_DEFAULT; 819 u32 async_mask; 820 821 if (!(ah->imask & ATH9K_INT_GLOBAL)) 822 return; 823 824 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { 825 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", 826 atomic_read(&ah->intr_ref_cnt)); 827 return; 828 } 829 830 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 831 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 832 833 async_mask = AR_INTR_MAC_IRQ; 834 835 if (ah->imask & ATH9K_INT_MCI) 836 async_mask |= AR_INTR_ASYNC_MASK_MCI; 837 838 ath_dbg(common, INTERRUPT, "enable IER\n"); 839 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 840 if (!AR_SREV_9100(ah)) { 841 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); 842 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); 843 844 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 845 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); 846 } 847 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 848 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 849 } 850 EXPORT_SYMBOL(ath9k_hw_enable_interrupts); 851 852 void ath9k_hw_set_interrupts(struct ath_hw *ah) 853 { 854 enum ath9k_int ints = ah->imask; 855 u32 mask, mask2; 856 struct ath9k_hw_capabilities *pCap = &ah->caps; 857 struct ath_common *common = ath9k_hw_common(ah); 858 859 if (!(ints & ATH9K_INT_GLOBAL)) 860 ath9k_hw_disable_interrupts(ah); 861 862 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints); 863 864 mask = ints & ATH9K_INT_COMMON; 865 mask2 = 0; 866 867 if (ints & ATH9K_INT_TX) { 868 if (ah->config.tx_intr_mitigation) 869 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; 870 else { 871 if (ah->txok_interrupt_mask) 872 mask |= AR_IMR_TXOK; 873 if (ah->txdesc_interrupt_mask) 874 mask |= AR_IMR_TXDESC; 875 } 876 if (ah->txerr_interrupt_mask) 877 mask |= AR_IMR_TXERR; 878 if (ah->txeol_interrupt_mask) 879 mask |= AR_IMR_TXEOL; 880 } 881 if (ints & ATH9K_INT_RX) { 882 if (AR_SREV_9300_20_OR_LATER(ah)) { 883 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; 884 if (ah->config.rx_intr_mitigation) { 885 mask &= ~AR_IMR_RXOK_LP; 886 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 887 } else { 888 mask |= AR_IMR_RXOK_LP; 889 } 890 } else { 891 if (ah->config.rx_intr_mitigation) 892 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 893 else 894 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 895 } 896 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 897 mask |= AR_IMR_GENTMR; 898 } 899 900 if (ints & ATH9K_INT_GENTIMER) 901 mask |= AR_IMR_GENTMR; 902 903 if (ints & (ATH9K_INT_BMISC)) { 904 mask |= AR_IMR_BCNMISC; 905 if (ints & ATH9K_INT_TIM) 906 mask2 |= AR_IMR_S2_TIM; 907 if (ints & ATH9K_INT_DTIM) 908 mask2 |= AR_IMR_S2_DTIM; 909 if (ints & ATH9K_INT_DTIMSYNC) 910 mask2 |= AR_IMR_S2_DTIMSYNC; 911 if (ints & ATH9K_INT_CABEND) 912 mask2 |= AR_IMR_S2_CABEND; 913 if (ints & ATH9K_INT_TSFOOR) 914 mask2 |= AR_IMR_S2_TSFOOR; 915 } 916 917 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 918 mask |= AR_IMR_BCNMISC; 919 if (ints & ATH9K_INT_GTT) 920 mask2 |= AR_IMR_S2_GTT; 921 if (ints & ATH9K_INT_CST) 922 mask2 |= AR_IMR_S2_CST; 923 } 924 925 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { 926 if (ints & ATH9K_INT_BB_WATCHDOG) { 927 mask |= AR_IMR_BCNMISC; 928 mask2 |= AR_IMR_S2_BB_WATCHDOG; 929 } 930 } 931 932 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); 933 REG_WRITE(ah, AR_IMR, mask); 934 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | 935 AR_IMR_S2_DTIM | 936 AR_IMR_S2_DTIMSYNC | 937 AR_IMR_S2_CABEND | 938 AR_IMR_S2_CABTO | 939 AR_IMR_S2_TSFOOR | 940 AR_IMR_S2_GTT | 941 AR_IMR_S2_CST); 942 943 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { 944 if (ints & ATH9K_INT_BB_WATCHDOG) 945 ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG; 946 } 947 948 ah->imrs2_reg |= mask2; 949 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 950 951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 952 if (ints & ATH9K_INT_TIM_TIMER) 953 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 954 else 955 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 956 } 957 958 return; 959 } 960 EXPORT_SYMBOL(ath9k_hw_set_interrupts); 961