1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include <linux/export.h> 20 21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 22 struct ath9k_tx_queue_info *qi) 23 { 24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, 25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 28 ah->txurn_interrupt_mask); 29 30 ENABLE_REGWRITE_BUFFER(ah); 31 32 REG_WRITE(ah, AR_IMR_S0, 33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); 35 REG_WRITE(ah, AR_IMR_S1, 36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) 37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 38 39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; 40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); 41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 42 43 REGWRITE_BUFFER_FLUSH(ah); 44 } 45 46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) 47 { 48 return REG_READ(ah, AR_QTXDP(q)); 49 } 50 EXPORT_SYMBOL(ath9k_hw_gettxbuf); 51 52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) 53 { 54 REG_WRITE(ah, AR_QTXDP(q), txdp); 55 } 56 EXPORT_SYMBOL(ath9k_hw_puttxbuf); 57 58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 59 { 60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); 61 REG_WRITE(ah, AR_Q_TXE, 1 << q); 62 } 63 EXPORT_SYMBOL(ath9k_hw_txstart); 64 65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) 66 { 67 u32 npend; 68 69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 70 if (npend == 0) { 71 72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) 73 npend = 1; 74 } 75 76 return npend; 77 } 78 EXPORT_SYMBOL(ath9k_hw_numtxpending); 79 80 /** 81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level 82 * 83 * @ah: atheros hardware struct 84 * @bIncTrigLevel: whether or not the frame trigger level should be updated 85 * 86 * The frame trigger level specifies the minimum number of bytes, 87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO 88 * before the PCU will initiate sending the frame on the air. This can 89 * mean we initiate transmit before a full frame is on the PCU TX FIFO. 90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs 91 * first) 92 * 93 * Caution must be taken to ensure to set the frame trigger level based 94 * on the DMA request size. For example if the DMA request size is set to 95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because 96 * there need to be enough space in the tx FIFO for the requested transfer 97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set 98 * the threshold to a value beyond 6, then the transmit will hang. 99 * 100 * Current dual stream devices have a PCU TX FIFO size of 8 KB. 101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however, 102 * there is a hardware issue which forces us to use 2 KB instead so the 103 * frame trigger level must not exceed 2 KB for these chipsets. 104 */ 105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) 106 { 107 u32 txcfg, curLevel, newLevel; 108 109 if (ah->tx_trig_level >= ah->config.max_txtrig_level) 110 return false; 111 112 ath9k_hw_disable_interrupts(ah); 113 114 txcfg = REG_READ(ah, AR_TXCFG); 115 curLevel = MS(txcfg, AR_FTRIG); 116 newLevel = curLevel; 117 if (bIncTrigLevel) { 118 if (curLevel < ah->config.max_txtrig_level) 119 newLevel++; 120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD) 121 newLevel--; 122 if (newLevel != curLevel) 123 REG_WRITE(ah, AR_TXCFG, 124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); 125 126 ath9k_hw_enable_interrupts(ah); 127 128 ah->tx_trig_level = newLevel; 129 130 return newLevel != curLevel; 131 } 132 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel); 133 134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah) 135 { 136 int maxdelay = 1000; 137 int i, q; 138 139 if (ah->curchan) { 140 if (IS_CHAN_HALF_RATE(ah->curchan)) 141 maxdelay *= 2; 142 else if (IS_CHAN_QUARTER_RATE(ah->curchan)) 143 maxdelay *= 4; 144 } 145 146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 147 148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 151 152 for (q = 0; q < AR_NUM_QCU; q++) { 153 for (i = 0; i < maxdelay; i++) { 154 if (i) 155 udelay(5); 156 157 if (!ath9k_hw_numtxpending(ah, q)) 158 break; 159 } 160 } 161 162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 165 166 REG_WRITE(ah, AR_Q_TXD, 0); 167 } 168 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma); 169 170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) 171 { 172 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */ 173 #define ATH9K_TIME_QUANTUM 100 /* usec */ 174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 175 int wait; 176 177 REG_WRITE(ah, AR_Q_TXD, 1 << q); 178 179 for (wait = wait_time; wait != 0; wait--) { 180 if (wait != wait_time) 181 udelay(ATH9K_TIME_QUANTUM); 182 183 if (ath9k_hw_numtxpending(ah, q) == 0) 184 break; 185 } 186 187 REG_WRITE(ah, AR_Q_TXD, 0); 188 189 return wait != 0; 190 191 #undef ATH9K_TX_STOP_DMA_TIMEOUT 192 #undef ATH9K_TIME_QUANTUM 193 } 194 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue); 195 196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 197 const struct ath9k_tx_queue_info *qinfo) 198 { 199 u32 cw; 200 struct ath_common *common = ath9k_hw_common(ah); 201 struct ath9k_tx_queue_info *qi; 202 203 qi = &ah->txq[q]; 204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 205 ath_dbg(common, QUEUE, 206 "Set TXQ properties, inactive queue: %u\n", q); 207 return false; 208 } 209 210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); 211 212 qi->tqi_ver = qinfo->tqi_ver; 213 qi->tqi_subtype = qinfo->tqi_subtype; 214 qi->tqi_qflags = qinfo->tqi_qflags; 215 qi->tqi_priority = qinfo->tqi_priority; 216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) 217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); 218 else 219 qi->tqi_aifs = INIT_AIFS; 220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { 221 cw = min(qinfo->tqi_cwmin, 1024U); 222 qi->tqi_cwmin = 1; 223 while (qi->tqi_cwmin < cw) 224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; 225 } else 226 qi->tqi_cwmin = qinfo->tqi_cwmin; 227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { 228 cw = min(qinfo->tqi_cwmax, 1024U); 229 qi->tqi_cwmax = 1; 230 while (qi->tqi_cwmax < cw) 231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; 232 } else 233 qi->tqi_cwmax = INIT_CWMAX; 234 235 if (qinfo->tqi_shretry != 0) 236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); 237 else 238 qi->tqi_shretry = INIT_SH_RETRY; 239 if (qinfo->tqi_lgretry != 0) 240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); 241 else 242 qi->tqi_lgretry = INIT_LG_RETRY; 243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; 244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; 245 qi->tqi_burstTime = qinfo->tqi_burstTime; 246 qi->tqi_readyTime = qinfo->tqi_readyTime; 247 248 switch (qinfo->tqi_subtype) { 249 case ATH9K_WME_UPSD: 250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) 251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; 252 break; 253 default: 254 break; 255 } 256 257 return true; 258 } 259 EXPORT_SYMBOL(ath9k_hw_set_txq_props); 260 261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 262 struct ath9k_tx_queue_info *qinfo) 263 { 264 struct ath_common *common = ath9k_hw_common(ah); 265 struct ath9k_tx_queue_info *qi; 266 267 qi = &ah->txq[q]; 268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 269 ath_dbg(common, QUEUE, 270 "Get TXQ properties, inactive queue: %u\n", q); 271 return false; 272 } 273 274 qinfo->tqi_qflags = qi->tqi_qflags; 275 qinfo->tqi_ver = qi->tqi_ver; 276 qinfo->tqi_subtype = qi->tqi_subtype; 277 qinfo->tqi_qflags = qi->tqi_qflags; 278 qinfo->tqi_priority = qi->tqi_priority; 279 qinfo->tqi_aifs = qi->tqi_aifs; 280 qinfo->tqi_cwmin = qi->tqi_cwmin; 281 qinfo->tqi_cwmax = qi->tqi_cwmax; 282 qinfo->tqi_shretry = qi->tqi_shretry; 283 qinfo->tqi_lgretry = qi->tqi_lgretry; 284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; 285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; 286 qinfo->tqi_burstTime = qi->tqi_burstTime; 287 qinfo->tqi_readyTime = qi->tqi_readyTime; 288 289 return true; 290 } 291 EXPORT_SYMBOL(ath9k_hw_get_txq_props); 292 293 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 294 const struct ath9k_tx_queue_info *qinfo) 295 { 296 struct ath_common *common = ath9k_hw_common(ah); 297 struct ath9k_tx_queue_info *qi; 298 int q; 299 300 switch (type) { 301 case ATH9K_TX_QUEUE_BEACON: 302 q = ATH9K_NUM_TX_QUEUES - 1; 303 break; 304 case ATH9K_TX_QUEUE_CAB: 305 q = ATH9K_NUM_TX_QUEUES - 2; 306 break; 307 case ATH9K_TX_QUEUE_PSPOLL: 308 q = 1; 309 break; 310 case ATH9K_TX_QUEUE_UAPSD: 311 q = ATH9K_NUM_TX_QUEUES - 3; 312 break; 313 case ATH9K_TX_QUEUE_DATA: 314 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++) 315 if (ah->txq[q].tqi_type == 316 ATH9K_TX_QUEUE_INACTIVE) 317 break; 318 if (q == ATH9K_NUM_TX_QUEUES) { 319 ath_err(common, "No available TX queue\n"); 320 return -1; 321 } 322 break; 323 default: 324 ath_err(common, "Invalid TX queue type: %u\n", type); 325 return -1; 326 } 327 328 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); 329 330 qi = &ah->txq[q]; 331 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 332 ath_err(common, "TX queue: %u already active\n", q); 333 return -1; 334 } 335 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 336 qi->tqi_type = type; 337 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; 338 (void) ath9k_hw_set_txq_props(ah, q, qinfo); 339 340 return q; 341 } 342 EXPORT_SYMBOL(ath9k_hw_setuptxqueue); 343 344 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) 345 { 346 ah->txok_interrupt_mask &= ~(1 << q); 347 ah->txerr_interrupt_mask &= ~(1 << q); 348 ah->txdesc_interrupt_mask &= ~(1 << q); 349 ah->txeol_interrupt_mask &= ~(1 << q); 350 ah->txurn_interrupt_mask &= ~(1 << q); 351 } 352 353 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 354 { 355 struct ath_common *common = ath9k_hw_common(ah); 356 struct ath9k_tx_queue_info *qi; 357 358 qi = &ah->txq[q]; 359 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 360 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); 361 return false; 362 } 363 364 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); 365 366 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 367 ath9k_hw_clear_queue_interrupts(ah, q); 368 ath9k_hw_set_txq_interrupts(ah, qi); 369 370 return true; 371 } 372 EXPORT_SYMBOL(ath9k_hw_releasetxqueue); 373 374 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 375 { 376 struct ath_common *common = ath9k_hw_common(ah); 377 struct ath9k_channel *chan = ah->curchan; 378 struct ath9k_tx_queue_info *qi; 379 u32 cwMin, chanCwMin, value; 380 381 qi = &ah->txq[q]; 382 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 383 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); 384 return true; 385 } 386 387 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); 388 389 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 390 if (chan && IS_CHAN_B(chan)) 391 chanCwMin = INIT_CWMIN_11B; 392 else 393 chanCwMin = INIT_CWMIN; 394 395 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); 396 } else 397 cwMin = qi->tqi_cwmin; 398 399 ENABLE_REGWRITE_BUFFER(ah); 400 401 REG_WRITE(ah, AR_DLCL_IFS(q), 402 SM(cwMin, AR_D_LCL_IFS_CWMIN) | 403 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | 404 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 405 406 REG_WRITE(ah, AR_DRETRY_LIMIT(q), 407 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 408 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 409 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 410 411 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); 412 413 if (AR_SREV_9340(ah)) 414 REG_WRITE(ah, AR_DMISC(q), 415 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); 416 else 417 REG_WRITE(ah, AR_DMISC(q), 418 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); 419 420 if (qi->tqi_cbrPeriod) { 421 REG_WRITE(ah, AR_QCBRCFG(q), 422 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 423 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); 424 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | 425 (qi->tqi_cbrOverflowLimit ? 426 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); 427 } 428 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { 429 REG_WRITE(ah, AR_QRDYTIMECFG(q), 430 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 431 AR_Q_RDYTIMECFG_EN); 432 } 433 434 REG_WRITE(ah, AR_DCHNTIME(q), 435 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 436 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 437 438 if (qi->tqi_burstTime 439 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) 440 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); 441 442 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) 443 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); 444 445 REGWRITE_BUFFER_FLUSH(ah); 446 447 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) 448 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); 449 450 switch (qi->tqi_type) { 451 case ATH9K_TX_QUEUE_BEACON: 452 ENABLE_REGWRITE_BUFFER(ah); 453 454 REG_SET_BIT(ah, AR_QMISC(q), 455 AR_Q_MISC_FSP_DBA_GATED 456 | AR_Q_MISC_BEACON_USE 457 | AR_Q_MISC_CBR_INCR_DIS1); 458 459 REG_SET_BIT(ah, AR_DMISC(q), 460 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 461 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 462 | AR_D_MISC_BEACON_USE 463 | AR_D_MISC_POST_FR_BKOFF_DIS); 464 465 REGWRITE_BUFFER_FLUSH(ah); 466 467 /* 468 * cwmin and cwmax should be 0 for beacon queue 469 * but not for IBSS as we would create an imbalance 470 * on beaconing fairness for participating nodes. 471 */ 472 if (AR_SREV_9300_20_OR_LATER(ah) && 473 ah->opmode != NL80211_IFTYPE_ADHOC) { 474 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 475 | SM(0, AR_D_LCL_IFS_CWMAX) 476 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 477 } 478 break; 479 case ATH9K_TX_QUEUE_CAB: 480 ENABLE_REGWRITE_BUFFER(ah); 481 482 REG_SET_BIT(ah, AR_QMISC(q), 483 AR_Q_MISC_FSP_DBA_GATED 484 | AR_Q_MISC_CBR_INCR_DIS1 485 | AR_Q_MISC_CBR_INCR_DIS0); 486 value = (qi->tqi_readyTime - 487 (ah->config.sw_beacon_response_time - 488 ah->config.dma_beacon_response_time) - 489 ah->config.additional_swba_backoff) * 1024; 490 REG_WRITE(ah, AR_QRDYTIMECFG(q), 491 value | AR_Q_RDYTIMECFG_EN); 492 REG_SET_BIT(ah, AR_DMISC(q), 493 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 494 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 495 496 REGWRITE_BUFFER_FLUSH(ah); 497 498 break; 499 case ATH9K_TX_QUEUE_PSPOLL: 500 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); 501 break; 502 case ATH9K_TX_QUEUE_UAPSD: 503 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); 504 break; 505 default: 506 break; 507 } 508 509 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { 510 REG_SET_BIT(ah, AR_DMISC(q), 511 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 512 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 513 AR_D_MISC_POST_FR_BKOFF_DIS); 514 } 515 516 if (AR_SREV_9300_20_OR_LATER(ah)) 517 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 518 519 ath9k_hw_clear_queue_interrupts(ah, q); 520 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) { 521 ah->txok_interrupt_mask |= 1 << q; 522 ah->txerr_interrupt_mask |= 1 << q; 523 } 524 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) 525 ah->txdesc_interrupt_mask |= 1 << q; 526 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) 527 ah->txeol_interrupt_mask |= 1 << q; 528 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) 529 ah->txurn_interrupt_mask |= 1 << q; 530 ath9k_hw_set_txq_interrupts(ah, qi); 531 532 return true; 533 } 534 EXPORT_SYMBOL(ath9k_hw_resettxqueue); 535 536 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 537 struct ath_rx_status *rs) 538 { 539 struct ar5416_desc ads; 540 struct ar5416_desc *adsp = AR5416DESC(ds); 541 u32 phyerr; 542 543 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) 544 return -EINPROGRESS; 545 546 ads.u.rx = adsp->u.rx; 547 548 rs->rs_status = 0; 549 rs->rs_flags = 0; 550 551 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; 552 rs->rs_tstamp = ads.AR_RcvTimestamp; 553 554 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { 555 rs->rs_rssi = ATH9K_RSSI_BAD; 556 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD; 557 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD; 558 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD; 559 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD; 560 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD; 561 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD; 562 } else { 563 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); 564 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, 565 AR_RxRSSIAnt00); 566 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, 567 AR_RxRSSIAnt01); 568 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, 569 AR_RxRSSIAnt02); 570 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4, 571 AR_RxRSSIAnt10); 572 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4, 573 AR_RxRSSIAnt11); 574 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4, 575 AR_RxRSSIAnt12); 576 } 577 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) 578 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); 579 else 580 rs->rs_keyix = ATH9K_RXKEYIX_INVALID; 581 582 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); 583 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; 584 585 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 586 rs->rs_moreaggr = 587 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 588 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); 589 rs->rs_flags = 590 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0; 591 rs->rs_flags |= 592 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0; 593 594 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) 595 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 596 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) 597 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 598 if (ads.ds_rxstatus8 & AR_DecryptBusyErr) 599 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 600 601 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { 602 /* 603 * Treat these errors as mutually exclusive to avoid spurious 604 * extra error reports from the hardware. If a CRC error is 605 * reported, then decryption and MIC errors are irrelevant, 606 * the frame is going to be dropped either way 607 */ 608 if (ads.ds_rxstatus8 & AR_CRCErr) 609 rs->rs_status |= ATH9K_RXERR_CRC; 610 else if (ads.ds_rxstatus8 & AR_PHYErr) { 611 rs->rs_status |= ATH9K_RXERR_PHY; 612 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); 613 rs->rs_phyerr = phyerr; 614 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) 615 rs->rs_status |= ATH9K_RXERR_DECRYPT; 616 else if (ads.ds_rxstatus8 & AR_MichaelErr) 617 rs->rs_status |= ATH9K_RXERR_MIC; 618 } 619 620 if (ads.ds_rxstatus8 & AR_KeyMiss) 621 rs->rs_status |= ATH9K_RXERR_KEYMISS; 622 623 return 0; 624 } 625 EXPORT_SYMBOL(ath9k_hw_rxprocdesc); 626 627 /* 628 * This can stop or re-enables RX. 629 * 630 * If bool is set this will kill any frame which is currently being 631 * transferred between the MAC and baseband and also prevent any new 632 * frames from getting started. 633 */ 634 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) 635 { 636 u32 reg; 637 638 if (set) { 639 REG_SET_BIT(ah, AR_DIAG_SW, 640 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 641 642 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 643 0, AH_WAIT_TIMEOUT)) { 644 REG_CLR_BIT(ah, AR_DIAG_SW, 645 (AR_DIAG_RX_DIS | 646 AR_DIAG_RX_ABORT)); 647 648 reg = REG_READ(ah, AR_OBS_BUS_1); 649 ath_err(ath9k_hw_common(ah), 650 "RX failed to go idle in 10 ms RXSM=0x%x\n", 651 reg); 652 653 return false; 654 } 655 } else { 656 REG_CLR_BIT(ah, AR_DIAG_SW, 657 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 658 } 659 660 return true; 661 } 662 EXPORT_SYMBOL(ath9k_hw_setrxabort); 663 664 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) 665 { 666 REG_WRITE(ah, AR_RXDP, rxdp); 667 } 668 EXPORT_SYMBOL(ath9k_hw_putrxbuf); 669 670 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) 671 { 672 ath9k_enable_mib_counters(ah); 673 674 ath9k_ani_reset(ah, is_scanning); 675 676 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 677 } 678 EXPORT_SYMBOL(ath9k_hw_startpcureceive); 679 680 void ath9k_hw_abortpcurecv(struct ath_hw *ah) 681 { 682 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); 683 684 ath9k_hw_disable_mib_counters(ah); 685 } 686 EXPORT_SYMBOL(ath9k_hw_abortpcurecv); 687 688 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) 689 { 690 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 691 struct ath_common *common = ath9k_hw_common(ah); 692 u32 mac_status, last_mac_status = 0; 693 int i; 694 695 /* Enable access to the DMA observation bus */ 696 REG_WRITE(ah, AR_MACMISC, 697 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 698 (AR_MACMISC_MISC_OBS_BUS_1 << 699 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 700 701 REG_WRITE(ah, AR_CR, AR_CR_RXD); 702 703 /* Wait for rx enable bit to go low */ 704 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) { 705 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) 706 break; 707 708 if (!AR_SREV_9300_20_OR_LATER(ah)) { 709 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; 710 if (mac_status == 0x1c0 && mac_status == last_mac_status) { 711 *reset = true; 712 break; 713 } 714 715 last_mac_status = mac_status; 716 } 717 718 udelay(AH_TIME_QUANTUM); 719 } 720 721 if (i == 0) { 722 ath_err(common, 723 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", 724 AH_RX_STOP_DMA_TIMEOUT / 1000, 725 REG_READ(ah, AR_CR), 726 REG_READ(ah, AR_DIAG_SW), 727 REG_READ(ah, AR_DMADBG_7)); 728 return false; 729 } else { 730 return true; 731 } 732 733 #undef AH_RX_STOP_DMA_TIMEOUT 734 } 735 EXPORT_SYMBOL(ath9k_hw_stopdmarecv); 736 737 int ath9k_hw_beaconq_setup(struct ath_hw *ah) 738 { 739 struct ath9k_tx_queue_info qi; 740 741 memset(&qi, 0, sizeof(qi)); 742 qi.tqi_aifs = 1; 743 qi.tqi_cwmin = 0; 744 qi.tqi_cwmax = 0; 745 746 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 747 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 748 749 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); 750 } 751 EXPORT_SYMBOL(ath9k_hw_beaconq_setup); 752 753 bool ath9k_hw_intrpend(struct ath_hw *ah) 754 { 755 u32 host_isr; 756 757 if (AR_SREV_9100(ah)) 758 return true; 759 760 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 761 762 if (((host_isr & AR_INTR_MAC_IRQ) || 763 (host_isr & AR_INTR_ASYNC_MASK_MCI)) && 764 (host_isr != AR_INTR_SPURIOUS)) 765 return true; 766 767 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 768 if ((host_isr & AR_INTR_SYNC_DEFAULT) 769 && (host_isr != AR_INTR_SPURIOUS)) 770 return true; 771 772 return false; 773 } 774 EXPORT_SYMBOL(ath9k_hw_intrpend); 775 776 void ath9k_hw_kill_interrupts(struct ath_hw *ah) 777 { 778 struct ath_common *common = ath9k_hw_common(ah); 779 780 ath_dbg(common, INTERRUPT, "disable IER\n"); 781 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 782 (void) REG_READ(ah, AR_IER); 783 if (!AR_SREV_9100(ah)) { 784 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 785 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 786 787 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 788 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 789 } 790 } 791 EXPORT_SYMBOL(ath9k_hw_kill_interrupts); 792 793 void ath9k_hw_disable_interrupts(struct ath_hw *ah) 794 { 795 if (!(ah->imask & ATH9K_INT_GLOBAL)) 796 atomic_set(&ah->intr_ref_cnt, -1); 797 else 798 atomic_dec(&ah->intr_ref_cnt); 799 800 ath9k_hw_kill_interrupts(ah); 801 } 802 EXPORT_SYMBOL(ath9k_hw_disable_interrupts); 803 804 void ath9k_hw_enable_interrupts(struct ath_hw *ah) 805 { 806 struct ath_common *common = ath9k_hw_common(ah); 807 u32 sync_default = AR_INTR_SYNC_DEFAULT; 808 u32 async_mask; 809 810 if (!(ah->imask & ATH9K_INT_GLOBAL)) 811 return; 812 813 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { 814 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", 815 atomic_read(&ah->intr_ref_cnt)); 816 return; 817 } 818 819 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 820 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 821 822 async_mask = AR_INTR_MAC_IRQ; 823 824 if (ah->imask & ATH9K_INT_MCI) 825 async_mask |= AR_INTR_ASYNC_MASK_MCI; 826 827 ath_dbg(common, INTERRUPT, "enable IER\n"); 828 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 829 if (!AR_SREV_9100(ah)) { 830 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); 831 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); 832 833 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 834 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); 835 } 836 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 837 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 838 } 839 EXPORT_SYMBOL(ath9k_hw_enable_interrupts); 840 841 void ath9k_hw_set_interrupts(struct ath_hw *ah) 842 { 843 enum ath9k_int ints = ah->imask; 844 u32 mask, mask2; 845 struct ath9k_hw_capabilities *pCap = &ah->caps; 846 struct ath_common *common = ath9k_hw_common(ah); 847 848 if (!(ints & ATH9K_INT_GLOBAL)) 849 ath9k_hw_disable_interrupts(ah); 850 851 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints); 852 853 mask = ints & ATH9K_INT_COMMON; 854 mask2 = 0; 855 856 if (ints & ATH9K_INT_TX) { 857 if (ah->config.tx_intr_mitigation) 858 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; 859 else { 860 if (ah->txok_interrupt_mask) 861 mask |= AR_IMR_TXOK; 862 if (ah->txdesc_interrupt_mask) 863 mask |= AR_IMR_TXDESC; 864 } 865 if (ah->txerr_interrupt_mask) 866 mask |= AR_IMR_TXERR; 867 if (ah->txeol_interrupt_mask) 868 mask |= AR_IMR_TXEOL; 869 } 870 if (ints & ATH9K_INT_RX) { 871 if (AR_SREV_9300_20_OR_LATER(ah)) { 872 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; 873 if (ah->config.rx_intr_mitigation) { 874 mask &= ~AR_IMR_RXOK_LP; 875 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 876 } else { 877 mask |= AR_IMR_RXOK_LP; 878 } 879 } else { 880 if (ah->config.rx_intr_mitigation) 881 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 882 else 883 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 884 } 885 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 886 mask |= AR_IMR_GENTMR; 887 } 888 889 if (ints & ATH9K_INT_GENTIMER) 890 mask |= AR_IMR_GENTMR; 891 892 if (ints & (ATH9K_INT_BMISC)) { 893 mask |= AR_IMR_BCNMISC; 894 if (ints & ATH9K_INT_TIM) 895 mask2 |= AR_IMR_S2_TIM; 896 if (ints & ATH9K_INT_DTIM) 897 mask2 |= AR_IMR_S2_DTIM; 898 if (ints & ATH9K_INT_DTIMSYNC) 899 mask2 |= AR_IMR_S2_DTIMSYNC; 900 if (ints & ATH9K_INT_CABEND) 901 mask2 |= AR_IMR_S2_CABEND; 902 if (ints & ATH9K_INT_TSFOOR) 903 mask2 |= AR_IMR_S2_TSFOOR; 904 } 905 906 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 907 mask |= AR_IMR_BCNMISC; 908 if (ints & ATH9K_INT_GTT) 909 mask2 |= AR_IMR_S2_GTT; 910 if (ints & ATH9K_INT_CST) 911 mask2 |= AR_IMR_S2_CST; 912 } 913 914 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); 915 REG_WRITE(ah, AR_IMR, mask); 916 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 917 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 918 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 919 ah->imrs2_reg |= mask2; 920 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 921 922 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 923 if (ints & ATH9K_INT_TIM_TIMER) 924 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 925 else 926 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 927 } 928 929 return; 930 } 931 EXPORT_SYMBOL(ath9k_hw_set_interrupts); 932