1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 bool is_ath9k_unloaded; 65 /* We use the hw_value as an index into our private channel structure */ 66 67 #define CHAN2G(_freq, _idx) { \ 68 .band = IEEE80211_BAND_2GHZ, \ 69 .center_freq = (_freq), \ 70 .hw_value = (_idx), \ 71 .max_power = 20, \ 72 } 73 74 #define CHAN5G(_freq, _idx) { \ 75 .band = IEEE80211_BAND_5GHZ, \ 76 .center_freq = (_freq), \ 77 .hw_value = (_idx), \ 78 .max_power = 20, \ 79 } 80 81 /* Some 2 GHz radios are actually tunable on 2312-2732 82 * on 5 MHz steps, we support the channels which we know 83 * we have calibration data for all cards though to make 84 * this static */ 85 static const struct ieee80211_channel ath9k_2ghz_chantable[] = { 86 CHAN2G(2412, 0), /* Channel 1 */ 87 CHAN2G(2417, 1), /* Channel 2 */ 88 CHAN2G(2422, 2), /* Channel 3 */ 89 CHAN2G(2427, 3), /* Channel 4 */ 90 CHAN2G(2432, 4), /* Channel 5 */ 91 CHAN2G(2437, 5), /* Channel 6 */ 92 CHAN2G(2442, 6), /* Channel 7 */ 93 CHAN2G(2447, 7), /* Channel 8 */ 94 CHAN2G(2452, 8), /* Channel 9 */ 95 CHAN2G(2457, 9), /* Channel 10 */ 96 CHAN2G(2462, 10), /* Channel 11 */ 97 CHAN2G(2467, 11), /* Channel 12 */ 98 CHAN2G(2472, 12), /* Channel 13 */ 99 CHAN2G(2484, 13), /* Channel 14 */ 100 }; 101 102 /* Some 5 GHz radios are actually tunable on XXXX-YYYY 103 * on 5 MHz steps, we support the channels which we know 104 * we have calibration data for all cards though to make 105 * this static */ 106 static const struct ieee80211_channel ath9k_5ghz_chantable[] = { 107 /* _We_ call this UNII 1 */ 108 CHAN5G(5180, 14), /* Channel 36 */ 109 CHAN5G(5200, 15), /* Channel 40 */ 110 CHAN5G(5220, 16), /* Channel 44 */ 111 CHAN5G(5240, 17), /* Channel 48 */ 112 /* _We_ call this UNII 2 */ 113 CHAN5G(5260, 18), /* Channel 52 */ 114 CHAN5G(5280, 19), /* Channel 56 */ 115 CHAN5G(5300, 20), /* Channel 60 */ 116 CHAN5G(5320, 21), /* Channel 64 */ 117 /* _We_ call this "Middle band" */ 118 CHAN5G(5500, 22), /* Channel 100 */ 119 CHAN5G(5520, 23), /* Channel 104 */ 120 CHAN5G(5540, 24), /* Channel 108 */ 121 CHAN5G(5560, 25), /* Channel 112 */ 122 CHAN5G(5580, 26), /* Channel 116 */ 123 CHAN5G(5600, 27), /* Channel 120 */ 124 CHAN5G(5620, 28), /* Channel 124 */ 125 CHAN5G(5640, 29), /* Channel 128 */ 126 CHAN5G(5660, 30), /* Channel 132 */ 127 CHAN5G(5680, 31), /* Channel 136 */ 128 CHAN5G(5700, 32), /* Channel 140 */ 129 /* _We_ call this UNII 3 */ 130 CHAN5G(5745, 33), /* Channel 149 */ 131 CHAN5G(5765, 34), /* Channel 153 */ 132 CHAN5G(5785, 35), /* Channel 157 */ 133 CHAN5G(5805, 36), /* Channel 161 */ 134 CHAN5G(5825, 37), /* Channel 165 */ 135 }; 136 137 /* Atheros hardware rate code addition for short premble */ 138 #define SHPCHECK(__hw_rate, __flags) \ 139 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) 140 141 #define RATE(_bitrate, _hw_rate, _flags) { \ 142 .bitrate = (_bitrate), \ 143 .flags = (_flags), \ 144 .hw_value = (_hw_rate), \ 145 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 146 } 147 148 static struct ieee80211_rate ath9k_legacy_rates[] = { 149 RATE(10, 0x1b, 0), 150 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), 151 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), 152 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), 153 RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ | 154 IEEE80211_RATE_SUPPORTS_10MHZ)), 155 RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ | 156 IEEE80211_RATE_SUPPORTS_10MHZ)), 157 RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ | 158 IEEE80211_RATE_SUPPORTS_10MHZ)), 159 RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ | 160 IEEE80211_RATE_SUPPORTS_10MHZ)), 161 RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ | 162 IEEE80211_RATE_SUPPORTS_10MHZ)), 163 RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ | 164 IEEE80211_RATE_SUPPORTS_10MHZ)), 165 RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ | 166 IEEE80211_RATE_SUPPORTS_10MHZ)), 167 RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ | 168 IEEE80211_RATE_SUPPORTS_10MHZ)), 169 }; 170 171 #ifdef CONFIG_MAC80211_LEDS 172 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 173 { .throughput = 0 * 1024, .blink_time = 334 }, 174 { .throughput = 1 * 1024, .blink_time = 260 }, 175 { .throughput = 5 * 1024, .blink_time = 220 }, 176 { .throughput = 10 * 1024, .blink_time = 190 }, 177 { .throughput = 20 * 1024, .blink_time = 170 }, 178 { .throughput = 50 * 1024, .blink_time = 150 }, 179 { .throughput = 70 * 1024, .blink_time = 130 }, 180 { .throughput = 100 * 1024, .blink_time = 110 }, 181 { .throughput = 200 * 1024, .blink_time = 80 }, 182 { .throughput = 300 * 1024, .blink_time = 50 }, 183 }; 184 #endif 185 186 static void ath9k_deinit_softc(struct ath_softc *sc); 187 188 /* 189 * Read and write, they both share the same lock. We do this to serialize 190 * reads and writes on Atheros 802.11n PCI devices only. This is required 191 * as the FIFO on these devices can only accept sanely 2 requests. 192 */ 193 194 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 195 { 196 struct ath_hw *ah = (struct ath_hw *) hw_priv; 197 struct ath_common *common = ath9k_hw_common(ah); 198 struct ath_softc *sc = (struct ath_softc *) common->priv; 199 200 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 201 unsigned long flags; 202 spin_lock_irqsave(&sc->sc_serial_rw, flags); 203 iowrite32(val, sc->mem + reg_offset); 204 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 205 } else 206 iowrite32(val, sc->mem + reg_offset); 207 } 208 209 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 210 { 211 struct ath_hw *ah = (struct ath_hw *) hw_priv; 212 struct ath_common *common = ath9k_hw_common(ah); 213 struct ath_softc *sc = (struct ath_softc *) common->priv; 214 u32 val; 215 216 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 217 unsigned long flags; 218 spin_lock_irqsave(&sc->sc_serial_rw, flags); 219 val = ioread32(sc->mem + reg_offset); 220 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 221 } else 222 val = ioread32(sc->mem + reg_offset); 223 return val; 224 } 225 226 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 227 u32 set, u32 clr) 228 { 229 u32 val; 230 231 val = ioread32(sc->mem + reg_offset); 232 val &= ~clr; 233 val |= set; 234 iowrite32(val, sc->mem + reg_offset); 235 236 return val; 237 } 238 239 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 240 { 241 struct ath_hw *ah = (struct ath_hw *) hw_priv; 242 struct ath_common *common = ath9k_hw_common(ah); 243 struct ath_softc *sc = (struct ath_softc *) common->priv; 244 unsigned long uninitialized_var(flags); 245 u32 val; 246 247 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 248 spin_lock_irqsave(&sc->sc_serial_rw, flags); 249 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 250 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 251 } else 252 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 253 254 return val; 255 } 256 257 /**************************/ 258 /* Initialization */ 259 /**************************/ 260 261 static void setup_ht_cap(struct ath_softc *sc, 262 struct ieee80211_sta_ht_cap *ht_info) 263 { 264 struct ath_hw *ah = sc->sc_ah; 265 struct ath_common *common = ath9k_hw_common(ah); 266 u8 tx_streams, rx_streams; 267 int i, max_streams; 268 269 ht_info->ht_supported = true; 270 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 271 IEEE80211_HT_CAP_SM_PS | 272 IEEE80211_HT_CAP_SGI_40 | 273 IEEE80211_HT_CAP_DSSSCCK40; 274 275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) 276 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; 277 278 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 279 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 280 281 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 282 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 283 284 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) 285 max_streams = 1; 286 else if (AR_SREV_9462(ah)) 287 max_streams = 2; 288 else if (AR_SREV_9300_20_OR_LATER(ah)) 289 max_streams = 3; 290 else 291 max_streams = 2; 292 293 if (AR_SREV_9280_20_OR_LATER(ah)) { 294 if (max_streams >= 2) 295 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; 296 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 297 } 298 299 /* set up supported mcs set */ 300 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 301 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); 302 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); 303 304 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", 305 tx_streams, rx_streams); 306 307 if (tx_streams != rx_streams) { 308 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 309 ht_info->mcs.tx_params |= ((tx_streams - 1) << 310 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 311 } 312 313 for (i = 0; i < rx_streams; i++) 314 ht_info->mcs.rx_mask[i] = 0xff; 315 316 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 317 } 318 319 static void ath9k_reg_notifier(struct wiphy *wiphy, 320 struct regulatory_request *request) 321 { 322 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 323 struct ath_softc *sc = hw->priv; 324 struct ath_hw *ah = sc->sc_ah; 325 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 326 327 ath_reg_notifier_apply(wiphy, request, reg); 328 329 /* Set tx power */ 330 if (ah->curchan) { 331 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 332 ath9k_ps_wakeup(sc); 333 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 334 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 335 /* synchronize DFS detector if regulatory domain changed */ 336 if (sc->dfs_detector != NULL) 337 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 338 request->dfs_region); 339 ath9k_ps_restore(sc); 340 } 341 } 342 343 /* 344 * This function will allocate both the DMA descriptor structure, and the 345 * buffers it contains. These are used to contain the descriptors used 346 * by the system. 347 */ 348 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 349 struct list_head *head, const char *name, 350 int nbuf, int ndesc, bool is_tx) 351 { 352 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 353 u8 *ds; 354 int i, bsize, desc_len; 355 356 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 357 name, nbuf, ndesc); 358 359 INIT_LIST_HEAD(head); 360 361 if (is_tx) 362 desc_len = sc->sc_ah->caps.tx_desc_len; 363 else 364 desc_len = sizeof(struct ath_desc); 365 366 /* ath_desc must be a multiple of DWORDs */ 367 if ((desc_len % 4) != 0) { 368 ath_err(common, "ath_desc not DWORD aligned\n"); 369 BUG_ON((desc_len % 4) != 0); 370 return -ENOMEM; 371 } 372 373 dd->dd_desc_len = desc_len * nbuf * ndesc; 374 375 /* 376 * Need additional DMA memory because we can't use 377 * descriptors that cross the 4K page boundary. Assume 378 * one skipped descriptor per 4K page. 379 */ 380 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 381 u32 ndesc_skipped = 382 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 383 u32 dma_len; 384 385 while (ndesc_skipped) { 386 dma_len = ndesc_skipped * desc_len; 387 dd->dd_desc_len += dma_len; 388 389 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 390 } 391 } 392 393 /* allocate descriptors */ 394 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 395 &dd->dd_desc_paddr, GFP_KERNEL); 396 if (!dd->dd_desc) 397 return -ENOMEM; 398 399 ds = (u8 *) dd->dd_desc; 400 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 401 name, ds, (u32) dd->dd_desc_len, 402 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 403 404 /* allocate buffers */ 405 if (is_tx) { 406 struct ath_buf *bf; 407 408 bsize = sizeof(struct ath_buf) * nbuf; 409 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 410 if (!bf) 411 return -ENOMEM; 412 413 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 414 bf->bf_desc = ds; 415 bf->bf_daddr = DS2PHYS(dd, ds); 416 417 if (!(sc->sc_ah->caps.hw_caps & 418 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 419 /* 420 * Skip descriptor addresses which can cause 4KB 421 * boundary crossing (addr + length) with a 32 dword 422 * descriptor fetch. 423 */ 424 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 425 BUG_ON((caddr_t) bf->bf_desc >= 426 ((caddr_t) dd->dd_desc + 427 dd->dd_desc_len)); 428 429 ds += (desc_len * ndesc); 430 bf->bf_desc = ds; 431 bf->bf_daddr = DS2PHYS(dd, ds); 432 } 433 } 434 list_add_tail(&bf->list, head); 435 } 436 } else { 437 struct ath_rxbuf *bf; 438 439 bsize = sizeof(struct ath_rxbuf) * nbuf; 440 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 441 if (!bf) 442 return -ENOMEM; 443 444 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 445 bf->bf_desc = ds; 446 bf->bf_daddr = DS2PHYS(dd, ds); 447 448 if (!(sc->sc_ah->caps.hw_caps & 449 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 450 /* 451 * Skip descriptor addresses which can cause 4KB 452 * boundary crossing (addr + length) with a 32 dword 453 * descriptor fetch. 454 */ 455 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 456 BUG_ON((caddr_t) bf->bf_desc >= 457 ((caddr_t) dd->dd_desc + 458 dd->dd_desc_len)); 459 460 ds += (desc_len * ndesc); 461 bf->bf_desc = ds; 462 bf->bf_daddr = DS2PHYS(dd, ds); 463 } 464 } 465 list_add_tail(&bf->list, head); 466 } 467 } 468 return 0; 469 } 470 471 static int ath9k_init_queues(struct ath_softc *sc) 472 { 473 int i = 0; 474 475 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 476 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 477 ath_cabq_update(sc); 478 479 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 480 481 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 482 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 483 sc->tx.txq_map[i]->mac80211_qnum = i; 484 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 485 } 486 return 0; 487 } 488 489 static int ath9k_init_channels_rates(struct ath_softc *sc) 490 { 491 void *channels; 492 493 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + 494 ARRAY_SIZE(ath9k_5ghz_chantable) != 495 ATH9K_NUM_CHANNELS); 496 497 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 498 channels = devm_kzalloc(sc->dev, 499 sizeof(ath9k_2ghz_chantable), GFP_KERNEL); 500 if (!channels) 501 return -ENOMEM; 502 503 memcpy(channels, ath9k_2ghz_chantable, 504 sizeof(ath9k_2ghz_chantable)); 505 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; 506 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 507 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 508 ARRAY_SIZE(ath9k_2ghz_chantable); 509 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 510 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 511 ARRAY_SIZE(ath9k_legacy_rates); 512 } 513 514 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 515 channels = devm_kzalloc(sc->dev, 516 sizeof(ath9k_5ghz_chantable), GFP_KERNEL); 517 if (!channels) 518 return -ENOMEM; 519 520 memcpy(channels, ath9k_5ghz_chantable, 521 sizeof(ath9k_5ghz_chantable)); 522 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; 523 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 524 sc->sbands[IEEE80211_BAND_5GHZ].n_channels = 525 ARRAY_SIZE(ath9k_5ghz_chantable); 526 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 527 ath9k_legacy_rates + 4; 528 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 529 ARRAY_SIZE(ath9k_legacy_rates) - 4; 530 } 531 return 0; 532 } 533 534 static void ath9k_init_misc(struct ath_softc *sc) 535 { 536 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 537 int i = 0; 538 539 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 540 541 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 542 sc->config.txpowlimit = ATH_TXPOWER_MAX; 543 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 544 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 545 546 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 547 sc->beacon.bslot[i] = NULL; 548 549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 550 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 551 552 sc->spec_config.enabled = 0; 553 sc->spec_config.short_repeat = true; 554 sc->spec_config.count = 8; 555 sc->spec_config.endless = false; 556 sc->spec_config.period = 0xFF; 557 sc->spec_config.fft_period = 0xF; 558 } 559 560 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 561 { 562 struct ath_hw *ah = sc->sc_ah; 563 struct ath9k_hw_capabilities *pCap = &ah->caps; 564 struct ath_common *common = ath9k_hw_common(ah); 565 566 if (common->bus_ops->ath_bus_type != ATH_PCI) 567 return; 568 569 if (sc->driver_data & (ATH9K_PCI_CUS198 | 570 ATH9K_PCI_CUS230)) { 571 ah->config.xlna_gpio = 9; 572 ah->config.xatten_margin_cfg = true; 573 ah->config.alt_mingainidx = true; 574 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 575 sc->ant_comb.low_rssi_thresh = 20; 576 sc->ant_comb.fast_div_bias = 3; 577 578 ath_info(common, "Set parameters for %s\n", 579 (sc->driver_data & ATH9K_PCI_CUS198) ? 580 "CUS198" : "CUS230"); 581 } 582 583 if (sc->driver_data & ATH9K_PCI_CUS217) 584 ath_info(common, "CUS217 card detected\n"); 585 586 if (sc->driver_data & ATH9K_PCI_CUS252) 587 ath_info(common, "CUS252 card detected\n"); 588 589 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 590 ath_info(common, "WB335 1-ANT card detected\n"); 591 592 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 593 ath_info(common, "WB335 2-ANT card detected\n"); 594 595 if (sc->driver_data & ATH9K_PCI_KILLER) 596 ath_info(common, "Killer Wireless card detected\n"); 597 598 /* 599 * Some WB335 cards do not support antenna diversity. Since 600 * we use a hardcoded value for AR9565 instead of using the 601 * EEPROM/OTP data, remove the combining feature from 602 * the HW capabilities bitmap. 603 */ 604 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 605 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 606 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 607 } 608 609 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 610 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 611 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 612 } 613 614 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 615 ah->config.pcie_waen = 0x0040473b; 616 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 617 } 618 619 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 620 ah->config.no_pll_pwrsave = true; 621 ath_info(common, "Disable PLL PowerSave\n"); 622 } 623 } 624 625 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 626 void *ctx) 627 { 628 struct ath9k_eeprom_ctx *ec = ctx; 629 630 if (eeprom_blob) 631 ec->ah->eeprom_blob = eeprom_blob; 632 633 complete(&ec->complete); 634 } 635 636 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 637 { 638 struct ath9k_eeprom_ctx ec; 639 struct ath_hw *ah = ah = sc->sc_ah; 640 int err; 641 642 /* try to load the EEPROM content asynchronously */ 643 init_completion(&ec.complete); 644 ec.ah = sc->sc_ah; 645 646 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 647 &ec, ath9k_eeprom_request_cb); 648 if (err < 0) { 649 ath_err(ath9k_hw_common(ah), 650 "EEPROM request failed\n"); 651 return err; 652 } 653 654 wait_for_completion(&ec.complete); 655 656 if (!ah->eeprom_blob) { 657 ath_err(ath9k_hw_common(ah), 658 "Unable to load EEPROM file %s\n", name); 659 return -EINVAL; 660 } 661 662 return 0; 663 } 664 665 static void ath9k_eeprom_release(struct ath_softc *sc) 666 { 667 release_firmware(sc->sc_ah->eeprom_blob); 668 } 669 670 static int ath9k_init_soc_platform(struct ath_softc *sc) 671 { 672 struct ath9k_platform_data *pdata = sc->dev->platform_data; 673 struct ath_hw *ah = sc->sc_ah; 674 int ret = 0; 675 676 if (!pdata) 677 return 0; 678 679 if (pdata->eeprom_name) { 680 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 681 if (ret) 682 return ret; 683 } 684 685 if (pdata->tx_gain_buffalo) 686 ah->config.tx_gain_buffalo = true; 687 688 return ret; 689 } 690 691 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 692 const struct ath_bus_ops *bus_ops) 693 { 694 struct ath9k_platform_data *pdata = sc->dev->platform_data; 695 struct ath_hw *ah = NULL; 696 struct ath9k_hw_capabilities *pCap; 697 struct ath_common *common; 698 int ret = 0, i; 699 int csz = 0; 700 701 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 702 if (!ah) 703 return -ENOMEM; 704 705 ah->dev = sc->dev; 706 ah->hw = sc->hw; 707 ah->hw_version.devid = devid; 708 ah->reg_ops.read = ath9k_ioread32; 709 ah->reg_ops.write = ath9k_iowrite32; 710 ah->reg_ops.rmw = ath9k_reg_rmw; 711 sc->sc_ah = ah; 712 pCap = &ah->caps; 713 714 common = ath9k_hw_common(ah); 715 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 716 sc->tx99_power = MAX_RATE_POWER + 1; 717 init_waitqueue_head(&sc->tx_wait); 718 719 if (!pdata) { 720 ah->ah_flags |= AH_USE_EEPROM; 721 sc->sc_ah->led_pin = -1; 722 } else { 723 sc->sc_ah->gpio_mask = pdata->gpio_mask; 724 sc->sc_ah->gpio_val = pdata->gpio_val; 725 sc->sc_ah->led_pin = pdata->led_pin; 726 ah->is_clk_25mhz = pdata->is_clk_25mhz; 727 ah->get_mac_revision = pdata->get_mac_revision; 728 ah->external_reset = pdata->external_reset; 729 } 730 731 common->ops = &ah->reg_ops; 732 common->bus_ops = bus_ops; 733 common->ah = ah; 734 common->hw = sc->hw; 735 common->priv = sc; 736 common->debug_mask = ath9k_debug; 737 common->btcoex_enabled = ath9k_btcoex_enable == 1; 738 common->disable_ani = false; 739 740 /* 741 * Platform quirks. 742 */ 743 ath9k_init_pcoem_platform(sc); 744 745 ret = ath9k_init_soc_platform(sc); 746 if (ret) 747 return ret; 748 749 /* 750 * Enable WLAN/BT RX Antenna diversity only when: 751 * 752 * - BTCOEX is disabled. 753 * - the user manually requests the feature. 754 * - the HW cap is set using the platform data. 755 */ 756 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 757 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 758 common->bt_ant_diversity = 1; 759 760 spin_lock_init(&common->cc_lock); 761 spin_lock_init(&sc->sc_serial_rw); 762 spin_lock_init(&sc->sc_pm_lock); 763 mutex_init(&sc->mutex); 764 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 765 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 766 (unsigned long)sc); 767 768 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 769 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 770 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 771 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 772 773 /* 774 * Cache line size is used to size and align various 775 * structures used to communicate with the hardware. 776 */ 777 ath_read_cachesize(common, &csz); 778 common->cachelsz = csz << 2; /* convert to bytes */ 779 780 /* Initializes the hardware for all supported chipsets */ 781 ret = ath9k_hw_init(ah); 782 if (ret) 783 goto err_hw; 784 785 if (pdata && pdata->macaddr) 786 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 787 788 ret = ath9k_init_queues(sc); 789 if (ret) 790 goto err_queues; 791 792 ret = ath9k_init_btcoex(sc); 793 if (ret) 794 goto err_btcoex; 795 796 ret = ath9k_init_channels_rates(sc); 797 if (ret) 798 goto err_btcoex; 799 800 ath9k_cmn_init_crypto(sc->sc_ah); 801 ath9k_init_misc(sc); 802 ath_fill_led_pin(sc); 803 804 if (common->bus_ops->aspm_init) 805 common->bus_ops->aspm_init(common); 806 807 return 0; 808 809 err_btcoex: 810 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 811 if (ATH_TXQ_SETUP(sc, i)) 812 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 813 err_queues: 814 ath9k_hw_deinit(ah); 815 err_hw: 816 ath9k_eeprom_release(sc); 817 dev_kfree_skb_any(sc->tx99_skb); 818 return ret; 819 } 820 821 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 822 { 823 struct ieee80211_supported_band *sband; 824 struct ieee80211_channel *chan; 825 struct ath_hw *ah = sc->sc_ah; 826 struct cfg80211_chan_def chandef; 827 int i; 828 829 sband = &sc->sbands[band]; 830 for (i = 0; i < sband->n_channels; i++) { 831 chan = &sband->channels[i]; 832 ah->curchan = &ah->channels[chan->hw_value]; 833 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 834 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 835 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 836 } 837 } 838 839 static void ath9k_init_txpower_limits(struct ath_softc *sc) 840 { 841 struct ath_hw *ah = sc->sc_ah; 842 struct ath9k_channel *curchan = ah->curchan; 843 844 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 845 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 846 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 847 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 848 849 ah->curchan = curchan; 850 } 851 852 void ath9k_reload_chainmask_settings(struct ath_softc *sc) 853 { 854 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) 855 return; 856 857 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 858 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 859 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 860 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 861 } 862 863 static const struct ieee80211_iface_limit if_limits[] = { 864 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | 865 BIT(NL80211_IFTYPE_P2P_CLIENT) | 866 BIT(NL80211_IFTYPE_WDS) }, 867 { .max = 8, .types = 868 #ifdef CONFIG_MAC80211_MESH 869 BIT(NL80211_IFTYPE_MESH_POINT) | 870 #endif 871 BIT(NL80211_IFTYPE_AP) | 872 BIT(NL80211_IFTYPE_P2P_GO) }, 873 }; 874 875 static const struct ieee80211_iface_limit if_dfs_limits[] = { 876 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 877 #ifdef CONFIG_MAC80211_MESH 878 BIT(NL80211_IFTYPE_MESH_POINT) | 879 #endif 880 BIT(NL80211_IFTYPE_ADHOC) }, 881 }; 882 883 static const struct ieee80211_iface_combination if_comb[] = { 884 { 885 .limits = if_limits, 886 .n_limits = ARRAY_SIZE(if_limits), 887 .max_interfaces = 2048, 888 .num_different_channels = 1, 889 .beacon_int_infra_match = true, 890 }, 891 { 892 .limits = if_dfs_limits, 893 .n_limits = ARRAY_SIZE(if_dfs_limits), 894 .max_interfaces = 1, 895 .num_different_channels = 1, 896 .beacon_int_infra_match = true, 897 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 898 BIT(NL80211_CHAN_WIDTH_20), 899 } 900 }; 901 902 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 903 { 904 struct ath_hw *ah = sc->sc_ah; 905 struct ath_common *common = ath9k_hw_common(ah); 906 907 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 908 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 909 IEEE80211_HW_SIGNAL_DBM | 910 IEEE80211_HW_PS_NULLFUNC_STACK | 911 IEEE80211_HW_SPECTRUM_MGMT | 912 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 913 IEEE80211_HW_SUPPORTS_RC_TABLE | 914 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 915 916 if (ath9k_ps_enable) 917 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 918 919 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 920 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 921 922 if (AR_SREV_9280_20_OR_LATER(ah)) 923 hw->radiotap_mcs_details |= 924 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 925 } 926 927 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 928 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 929 930 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; 931 932 if (!config_enabled(CONFIG_ATH9K_TX99)) { 933 hw->wiphy->interface_modes = 934 BIT(NL80211_IFTYPE_P2P_GO) | 935 BIT(NL80211_IFTYPE_P2P_CLIENT) | 936 BIT(NL80211_IFTYPE_AP) | 937 BIT(NL80211_IFTYPE_WDS) | 938 BIT(NL80211_IFTYPE_STATION) | 939 BIT(NL80211_IFTYPE_ADHOC) | 940 BIT(NL80211_IFTYPE_MESH_POINT); 941 hw->wiphy->iface_combinations = if_comb; 942 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 943 } 944 945 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 946 947 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 948 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 949 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 950 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 951 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 952 953 hw->queues = 4; 954 hw->max_rates = 4; 955 hw->max_listen_interval = 1; 956 hw->max_rate_tries = 10; 957 hw->sta_data_size = sizeof(struct ath_node); 958 hw->vif_data_size = sizeof(struct ath_vif); 959 960 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 961 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 962 963 /* single chain devices with rx diversity */ 964 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 965 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 966 967 sc->ant_rx = hw->wiphy->available_antennas_rx; 968 sc->ant_tx = hw->wiphy->available_antennas_tx; 969 970 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 972 &sc->sbands[IEEE80211_BAND_2GHZ]; 973 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 974 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 975 &sc->sbands[IEEE80211_BAND_5GHZ]; 976 977 ath9k_init_wow(hw); 978 ath9k_reload_chainmask_settings(sc); 979 980 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 981 } 982 983 int ath9k_init_device(u16 devid, struct ath_softc *sc, 984 const struct ath_bus_ops *bus_ops) 985 { 986 struct ieee80211_hw *hw = sc->hw; 987 struct ath_common *common; 988 struct ath_hw *ah; 989 int error = 0; 990 struct ath_regulatory *reg; 991 992 /* Bring up device */ 993 error = ath9k_init_softc(devid, sc, bus_ops); 994 if (error) 995 return error; 996 997 ah = sc->sc_ah; 998 common = ath9k_hw_common(ah); 999 ath9k_set_hw_capab(sc, hw); 1000 1001 /* Initialize regulatory */ 1002 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 1003 ath9k_reg_notifier); 1004 if (error) 1005 goto deinit; 1006 1007 reg = &common->regulatory; 1008 1009 /* Setup TX DMA */ 1010 error = ath_tx_init(sc, ATH_TXBUF); 1011 if (error != 0) 1012 goto deinit; 1013 1014 /* Setup RX DMA */ 1015 error = ath_rx_init(sc, ATH_RXBUF); 1016 if (error != 0) 1017 goto deinit; 1018 1019 ath9k_init_txpower_limits(sc); 1020 1021 #ifdef CONFIG_MAC80211_LEDS 1022 /* must be initialized before ieee80211_register_hw */ 1023 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 1024 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 1025 ARRAY_SIZE(ath9k_tpt_blink)); 1026 #endif 1027 1028 /* Register with mac80211 */ 1029 error = ieee80211_register_hw(hw); 1030 if (error) 1031 goto rx_cleanup; 1032 1033 error = ath9k_init_debug(ah); 1034 if (error) { 1035 ath_err(common, "Unable to create debugfs files\n"); 1036 goto unregister; 1037 } 1038 1039 /* Handle world regulatory */ 1040 if (!ath_is_world_regd(reg)) { 1041 error = regulatory_hint(hw->wiphy, reg->alpha2); 1042 if (error) 1043 goto debug_cleanup; 1044 } 1045 1046 ath_init_leds(sc); 1047 ath_start_rfkill_poll(sc); 1048 1049 return 0; 1050 1051 debug_cleanup: 1052 ath9k_deinit_debug(sc); 1053 unregister: 1054 ieee80211_unregister_hw(hw); 1055 rx_cleanup: 1056 ath_rx_cleanup(sc); 1057 deinit: 1058 ath9k_deinit_softc(sc); 1059 return error; 1060 } 1061 1062 /*****************************/ 1063 /* De-Initialization */ 1064 /*****************************/ 1065 1066 static void ath9k_deinit_softc(struct ath_softc *sc) 1067 { 1068 int i = 0; 1069 1070 ath9k_deinit_btcoex(sc); 1071 1072 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1073 if (ATH_TXQ_SETUP(sc, i)) 1074 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1075 1076 del_timer_sync(&sc->sleep_timer); 1077 ath9k_hw_deinit(sc->sc_ah); 1078 if (sc->dfs_detector != NULL) 1079 sc->dfs_detector->exit(sc->dfs_detector); 1080 1081 ath9k_eeprom_release(sc); 1082 } 1083 1084 void ath9k_deinit_device(struct ath_softc *sc) 1085 { 1086 struct ieee80211_hw *hw = sc->hw; 1087 1088 ath9k_ps_wakeup(sc); 1089 1090 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1091 ath_deinit_leds(sc); 1092 1093 ath9k_ps_restore(sc); 1094 1095 ath9k_deinit_debug(sc); 1096 ieee80211_unregister_hw(hw); 1097 ath_rx_cleanup(sc); 1098 ath9k_deinit_softc(sc); 1099 } 1100 1101 /************************/ 1102 /* Module Hooks */ 1103 /************************/ 1104 1105 static int __init ath9k_init(void) 1106 { 1107 int error; 1108 1109 /* Register rate control algorithm */ 1110 error = ath_rate_control_register(); 1111 if (error != 0) { 1112 pr_err("Unable to register rate control algorithm: %d\n", 1113 error); 1114 goto err_out; 1115 } 1116 1117 error = ath_pci_init(); 1118 if (error < 0) { 1119 pr_err("No PCI devices found, driver not installed\n"); 1120 error = -ENODEV; 1121 goto err_rate_unregister; 1122 } 1123 1124 error = ath_ahb_init(); 1125 if (error < 0) { 1126 error = -ENODEV; 1127 goto err_pci_exit; 1128 } 1129 1130 return 0; 1131 1132 err_pci_exit: 1133 ath_pci_exit(); 1134 1135 err_rate_unregister: 1136 ath_rate_control_unregister(); 1137 err_out: 1138 return error; 1139 } 1140 module_init(ath9k_init); 1141 1142 static void __exit ath9k_exit(void) 1143 { 1144 is_ath9k_unloaded = true; 1145 ath_ahb_exit(); 1146 ath_pci_exit(); 1147 ath_rate_control_unregister(); 1148 pr_info("%s: Driver unloaded\n", dev_info); 1149 } 1150 module_exit(ath9k_exit); 1151