1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 static int ath9k_use_chanctx; 65 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 66 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 67 68 bool is_ath9k_unloaded; 69 70 #ifdef CONFIG_MAC80211_LEDS 71 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 72 { .throughput = 0 * 1024, .blink_time = 334 }, 73 { .throughput = 1 * 1024, .blink_time = 260 }, 74 { .throughput = 5 * 1024, .blink_time = 220 }, 75 { .throughput = 10 * 1024, .blink_time = 190 }, 76 { .throughput = 20 * 1024, .blink_time = 170 }, 77 { .throughput = 50 * 1024, .blink_time = 150 }, 78 { .throughput = 70 * 1024, .blink_time = 130 }, 79 { .throughput = 100 * 1024, .blink_time = 110 }, 80 { .throughput = 200 * 1024, .blink_time = 80 }, 81 { .throughput = 300 * 1024, .blink_time = 50 }, 82 }; 83 #endif 84 85 static void ath9k_deinit_softc(struct ath_softc *sc); 86 87 /* 88 * Read and write, they both share the same lock. We do this to serialize 89 * reads and writes on Atheros 802.11n PCI devices only. This is required 90 * as the FIFO on these devices can only accept sanely 2 requests. 91 */ 92 93 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 94 { 95 struct ath_hw *ah = (struct ath_hw *) hw_priv; 96 struct ath_common *common = ath9k_hw_common(ah); 97 struct ath_softc *sc = (struct ath_softc *) common->priv; 98 99 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 100 unsigned long flags; 101 spin_lock_irqsave(&sc->sc_serial_rw, flags); 102 iowrite32(val, sc->mem + reg_offset); 103 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 104 } else 105 iowrite32(val, sc->mem + reg_offset); 106 } 107 108 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 109 { 110 struct ath_hw *ah = (struct ath_hw *) hw_priv; 111 struct ath_common *common = ath9k_hw_common(ah); 112 struct ath_softc *sc = (struct ath_softc *) common->priv; 113 u32 val; 114 115 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 116 unsigned long flags; 117 spin_lock_irqsave(&sc->sc_serial_rw, flags); 118 val = ioread32(sc->mem + reg_offset); 119 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 120 } else 121 val = ioread32(sc->mem + reg_offset); 122 return val; 123 } 124 125 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 126 u32 set, u32 clr) 127 { 128 u32 val; 129 130 val = ioread32(sc->mem + reg_offset); 131 val &= ~clr; 132 val |= set; 133 iowrite32(val, sc->mem + reg_offset); 134 135 return val; 136 } 137 138 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 139 { 140 struct ath_hw *ah = (struct ath_hw *) hw_priv; 141 struct ath_common *common = ath9k_hw_common(ah); 142 struct ath_softc *sc = (struct ath_softc *) common->priv; 143 unsigned long uninitialized_var(flags); 144 u32 val; 145 146 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 147 spin_lock_irqsave(&sc->sc_serial_rw, flags); 148 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 149 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 150 } else 151 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 152 153 return val; 154 } 155 156 /**************************/ 157 /* Initialization */ 158 /**************************/ 159 160 static void ath9k_reg_notifier(struct wiphy *wiphy, 161 struct regulatory_request *request) 162 { 163 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 164 struct ath_softc *sc = hw->priv; 165 struct ath_hw *ah = sc->sc_ah; 166 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 167 168 ath_reg_notifier_apply(wiphy, request, reg); 169 170 /* Set tx power */ 171 if (ah->curchan) { 172 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 173 ath9k_ps_wakeup(sc); 174 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 175 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 176 /* synchronize DFS detector if regulatory domain changed */ 177 if (sc->dfs_detector != NULL) 178 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 179 request->dfs_region); 180 ath9k_ps_restore(sc); 181 } 182 } 183 184 /* 185 * This function will allocate both the DMA descriptor structure, and the 186 * buffers it contains. These are used to contain the descriptors used 187 * by the system. 188 */ 189 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 190 struct list_head *head, const char *name, 191 int nbuf, int ndesc, bool is_tx) 192 { 193 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 194 u8 *ds; 195 int i, bsize, desc_len; 196 197 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 198 name, nbuf, ndesc); 199 200 INIT_LIST_HEAD(head); 201 202 if (is_tx) 203 desc_len = sc->sc_ah->caps.tx_desc_len; 204 else 205 desc_len = sizeof(struct ath_desc); 206 207 /* ath_desc must be a multiple of DWORDs */ 208 if ((desc_len % 4) != 0) { 209 ath_err(common, "ath_desc not DWORD aligned\n"); 210 BUG_ON((desc_len % 4) != 0); 211 return -ENOMEM; 212 } 213 214 dd->dd_desc_len = desc_len * nbuf * ndesc; 215 216 /* 217 * Need additional DMA memory because we can't use 218 * descriptors that cross the 4K page boundary. Assume 219 * one skipped descriptor per 4K page. 220 */ 221 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 222 u32 ndesc_skipped = 223 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 224 u32 dma_len; 225 226 while (ndesc_skipped) { 227 dma_len = ndesc_skipped * desc_len; 228 dd->dd_desc_len += dma_len; 229 230 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 231 } 232 } 233 234 /* allocate descriptors */ 235 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 236 &dd->dd_desc_paddr, GFP_KERNEL); 237 if (!dd->dd_desc) 238 return -ENOMEM; 239 240 ds = (u8 *) dd->dd_desc; 241 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 242 name, ds, (u32) dd->dd_desc_len, 243 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 244 245 /* allocate buffers */ 246 if (is_tx) { 247 struct ath_buf *bf; 248 249 bsize = sizeof(struct ath_buf) * nbuf; 250 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 251 if (!bf) 252 return -ENOMEM; 253 254 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 255 bf->bf_desc = ds; 256 bf->bf_daddr = DS2PHYS(dd, ds); 257 258 if (!(sc->sc_ah->caps.hw_caps & 259 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 260 /* 261 * Skip descriptor addresses which can cause 4KB 262 * boundary crossing (addr + length) with a 32 dword 263 * descriptor fetch. 264 */ 265 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 266 BUG_ON((caddr_t) bf->bf_desc >= 267 ((caddr_t) dd->dd_desc + 268 dd->dd_desc_len)); 269 270 ds += (desc_len * ndesc); 271 bf->bf_desc = ds; 272 bf->bf_daddr = DS2PHYS(dd, ds); 273 } 274 } 275 list_add_tail(&bf->list, head); 276 } 277 } else { 278 struct ath_rxbuf *bf; 279 280 bsize = sizeof(struct ath_rxbuf) * nbuf; 281 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 282 if (!bf) 283 return -ENOMEM; 284 285 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 286 bf->bf_desc = ds; 287 bf->bf_daddr = DS2PHYS(dd, ds); 288 289 if (!(sc->sc_ah->caps.hw_caps & 290 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 291 /* 292 * Skip descriptor addresses which can cause 4KB 293 * boundary crossing (addr + length) with a 32 dword 294 * descriptor fetch. 295 */ 296 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 297 BUG_ON((caddr_t) bf->bf_desc >= 298 ((caddr_t) dd->dd_desc + 299 dd->dd_desc_len)); 300 301 ds += (desc_len * ndesc); 302 bf->bf_desc = ds; 303 bf->bf_daddr = DS2PHYS(dd, ds); 304 } 305 } 306 list_add_tail(&bf->list, head); 307 } 308 } 309 return 0; 310 } 311 312 static int ath9k_init_queues(struct ath_softc *sc) 313 { 314 int i = 0; 315 316 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 317 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 318 ath_cabq_update(sc); 319 320 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 321 322 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 323 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 324 sc->tx.txq_map[i]->mac80211_qnum = i; 325 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 326 } 327 return 0; 328 } 329 330 static void ath9k_init_misc(struct ath_softc *sc) 331 { 332 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 333 int i = 0; 334 335 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 336 337 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 338 sc->config.txpowlimit = ATH_TXPOWER_MAX; 339 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 340 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 341 342 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 343 sc->beacon.bslot[i] = NULL; 344 345 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 346 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 347 348 sc->spec_config.enabled = 0; 349 sc->spec_config.short_repeat = true; 350 sc->spec_config.count = 8; 351 sc->spec_config.endless = false; 352 sc->spec_config.period = 0xFF; 353 sc->spec_config.fft_period = 0xF; 354 } 355 356 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 357 { 358 struct ath_hw *ah = sc->sc_ah; 359 struct ath9k_hw_capabilities *pCap = &ah->caps; 360 struct ath_common *common = ath9k_hw_common(ah); 361 362 if (common->bus_ops->ath_bus_type != ATH_PCI) 363 return; 364 365 if (sc->driver_data & (ATH9K_PCI_CUS198 | 366 ATH9K_PCI_CUS230)) { 367 ah->config.xlna_gpio = 9; 368 ah->config.xatten_margin_cfg = true; 369 ah->config.alt_mingainidx = true; 370 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 371 sc->ant_comb.low_rssi_thresh = 20; 372 sc->ant_comb.fast_div_bias = 3; 373 374 ath_info(common, "Set parameters for %s\n", 375 (sc->driver_data & ATH9K_PCI_CUS198) ? 376 "CUS198" : "CUS230"); 377 } 378 379 if (sc->driver_data & ATH9K_PCI_CUS217) 380 ath_info(common, "CUS217 card detected\n"); 381 382 if (sc->driver_data & ATH9K_PCI_CUS252) 383 ath_info(common, "CUS252 card detected\n"); 384 385 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 386 ath_info(common, "WB335 1-ANT card detected\n"); 387 388 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 389 ath_info(common, "WB335 2-ANT card detected\n"); 390 391 if (sc->driver_data & ATH9K_PCI_KILLER) 392 ath_info(common, "Killer Wireless card detected\n"); 393 394 /* 395 * Some WB335 cards do not support antenna diversity. Since 396 * we use a hardcoded value for AR9565 instead of using the 397 * EEPROM/OTP data, remove the combining feature from 398 * the HW capabilities bitmap. 399 */ 400 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 401 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 402 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 403 } 404 405 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 406 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 407 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 408 } 409 410 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 411 ah->config.pcie_waen = 0x0040473b; 412 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 413 } 414 415 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 416 ah->config.no_pll_pwrsave = true; 417 ath_info(common, "Disable PLL PowerSave\n"); 418 } 419 } 420 421 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 422 void *ctx) 423 { 424 struct ath9k_eeprom_ctx *ec = ctx; 425 426 if (eeprom_blob) 427 ec->ah->eeprom_blob = eeprom_blob; 428 429 complete(&ec->complete); 430 } 431 432 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 433 { 434 struct ath9k_eeprom_ctx ec; 435 struct ath_hw *ah = ah = sc->sc_ah; 436 int err; 437 438 /* try to load the EEPROM content asynchronously */ 439 init_completion(&ec.complete); 440 ec.ah = sc->sc_ah; 441 442 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 443 &ec, ath9k_eeprom_request_cb); 444 if (err < 0) { 445 ath_err(ath9k_hw_common(ah), 446 "EEPROM request failed\n"); 447 return err; 448 } 449 450 wait_for_completion(&ec.complete); 451 452 if (!ah->eeprom_blob) { 453 ath_err(ath9k_hw_common(ah), 454 "Unable to load EEPROM file %s\n", name); 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static void ath9k_eeprom_release(struct ath_softc *sc) 462 { 463 release_firmware(sc->sc_ah->eeprom_blob); 464 } 465 466 static int ath9k_init_soc_platform(struct ath_softc *sc) 467 { 468 struct ath9k_platform_data *pdata = sc->dev->platform_data; 469 struct ath_hw *ah = sc->sc_ah; 470 int ret = 0; 471 472 if (!pdata) 473 return 0; 474 475 if (pdata->eeprom_name) { 476 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 477 if (ret) 478 return ret; 479 } 480 481 if (pdata->tx_gain_buffalo) 482 ah->config.tx_gain_buffalo = true; 483 484 return ret; 485 } 486 487 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 488 const struct ath_bus_ops *bus_ops) 489 { 490 struct ath9k_platform_data *pdata = sc->dev->platform_data; 491 struct ath_hw *ah = NULL; 492 struct ath9k_hw_capabilities *pCap; 493 struct ath_common *common; 494 int ret = 0, i; 495 int csz = 0; 496 497 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 498 if (!ah) 499 return -ENOMEM; 500 501 ah->dev = sc->dev; 502 ah->hw = sc->hw; 503 ah->hw_version.devid = devid; 504 ah->reg_ops.read = ath9k_ioread32; 505 ah->reg_ops.write = ath9k_iowrite32; 506 ah->reg_ops.rmw = ath9k_reg_rmw; 507 sc->sc_ah = ah; 508 pCap = &ah->caps; 509 510 common = ath9k_hw_common(ah); 511 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 512 sc->tx99_power = MAX_RATE_POWER + 1; 513 init_waitqueue_head(&sc->tx_wait); 514 515 if (!pdata || pdata->use_eeprom) { 516 ah->ah_flags |= AH_USE_EEPROM; 517 sc->sc_ah->led_pin = -1; 518 } else { 519 sc->sc_ah->gpio_mask = pdata->gpio_mask; 520 sc->sc_ah->gpio_val = pdata->gpio_val; 521 sc->sc_ah->led_pin = pdata->led_pin; 522 ah->is_clk_25mhz = pdata->is_clk_25mhz; 523 ah->get_mac_revision = pdata->get_mac_revision; 524 ah->external_reset = pdata->external_reset; 525 } 526 527 common->ops = &ah->reg_ops; 528 common->bus_ops = bus_ops; 529 common->ah = ah; 530 common->hw = sc->hw; 531 common->priv = sc; 532 common->debug_mask = ath9k_debug; 533 common->btcoex_enabled = ath9k_btcoex_enable == 1; 534 common->disable_ani = false; 535 536 /* 537 * Platform quirks. 538 */ 539 ath9k_init_pcoem_platform(sc); 540 541 ret = ath9k_init_soc_platform(sc); 542 if (ret) 543 return ret; 544 545 /* 546 * Enable WLAN/BT RX Antenna diversity only when: 547 * 548 * - BTCOEX is disabled. 549 * - the user manually requests the feature. 550 * - the HW cap is set using the platform data. 551 */ 552 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 553 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 554 common->bt_ant_diversity = 1; 555 556 spin_lock_init(&common->cc_lock); 557 spin_lock_init(&sc->sc_serial_rw); 558 spin_lock_init(&sc->sc_pm_lock); 559 mutex_init(&sc->mutex); 560 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 561 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 562 (unsigned long)sc); 563 564 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 565 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 566 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 567 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 568 569 /* 570 * Cache line size is used to size and align various 571 * structures used to communicate with the hardware. 572 */ 573 ath_read_cachesize(common, &csz); 574 common->cachelsz = csz << 2; /* convert to bytes */ 575 576 /* Initializes the hardware for all supported chipsets */ 577 ret = ath9k_hw_init(ah); 578 if (ret) 579 goto err_hw; 580 581 if (pdata && pdata->macaddr) 582 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 583 584 ret = ath9k_init_queues(sc); 585 if (ret) 586 goto err_queues; 587 588 ret = ath9k_init_btcoex(sc); 589 if (ret) 590 goto err_btcoex; 591 592 ret = ath9k_cmn_init_channels_rates(common); 593 if (ret) 594 goto err_btcoex; 595 596 sc->p2p_ps_timer = ath_gen_timer_alloc(sc->sc_ah, ath9k_p2p_ps_timer, 597 NULL, sc, AR_FIRST_NDP_TIMER); 598 599 ath9k_cmn_init_crypto(sc->sc_ah); 600 ath9k_init_misc(sc); 601 ath_fill_led_pin(sc); 602 603 if (common->bus_ops->aspm_init) 604 common->bus_ops->aspm_init(common); 605 606 return 0; 607 608 err_btcoex: 609 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 610 if (ATH_TXQ_SETUP(sc, i)) 611 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 612 err_queues: 613 ath9k_hw_deinit(ah); 614 err_hw: 615 ath9k_eeprom_release(sc); 616 dev_kfree_skb_any(sc->tx99_skb); 617 return ret; 618 } 619 620 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 621 { 622 struct ieee80211_supported_band *sband; 623 struct ieee80211_channel *chan; 624 struct ath_hw *ah = sc->sc_ah; 625 struct ath_common *common = ath9k_hw_common(ah); 626 struct cfg80211_chan_def chandef; 627 int i; 628 629 sband = &common->sbands[band]; 630 for (i = 0; i < sband->n_channels; i++) { 631 chan = &sband->channels[i]; 632 ah->curchan = &ah->channels[chan->hw_value]; 633 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 634 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 635 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 636 } 637 } 638 639 static void ath9k_init_txpower_limits(struct ath_softc *sc) 640 { 641 struct ath_hw *ah = sc->sc_ah; 642 struct ath9k_channel *curchan = ah->curchan; 643 644 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 645 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 646 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 647 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 648 649 ah->curchan = curchan; 650 } 651 652 static const struct ieee80211_iface_limit if_limits[] = { 653 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 654 { .max = 8, .types = 655 #ifdef CONFIG_MAC80211_MESH 656 BIT(NL80211_IFTYPE_MESH_POINT) | 657 #endif 658 BIT(NL80211_IFTYPE_AP) }, 659 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 660 BIT(NL80211_IFTYPE_P2P_GO) }, 661 }; 662 663 static const struct ieee80211_iface_limit wds_limits[] = { 664 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, 665 }; 666 667 static const struct ieee80211_iface_limit if_dfs_limits[] = { 668 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 669 #ifdef CONFIG_MAC80211_MESH 670 BIT(NL80211_IFTYPE_MESH_POINT) | 671 #endif 672 BIT(NL80211_IFTYPE_ADHOC) }, 673 }; 674 675 static const struct ieee80211_iface_combination if_comb[] = { 676 { 677 .limits = if_limits, 678 .n_limits = ARRAY_SIZE(if_limits), 679 .max_interfaces = 2048, 680 .num_different_channels = 1, 681 .beacon_int_infra_match = true, 682 }, 683 { 684 .limits = wds_limits, 685 .n_limits = ARRAY_SIZE(wds_limits), 686 .max_interfaces = 2048, 687 .num_different_channels = 1, 688 .beacon_int_infra_match = true, 689 }, 690 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 691 { 692 .limits = if_dfs_limits, 693 .n_limits = ARRAY_SIZE(if_dfs_limits), 694 .max_interfaces = 1, 695 .num_different_channels = 1, 696 .beacon_int_infra_match = true, 697 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 698 BIT(NL80211_CHAN_WIDTH_20), 699 } 700 #endif 701 }; 702 703 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 704 { 705 struct ath_hw *ah = sc->sc_ah; 706 struct ath_common *common = ath9k_hw_common(ah); 707 708 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 709 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 710 IEEE80211_HW_SIGNAL_DBM | 711 IEEE80211_HW_PS_NULLFUNC_STACK | 712 IEEE80211_HW_SPECTRUM_MGMT | 713 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 714 IEEE80211_HW_SUPPORTS_RC_TABLE | 715 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 716 717 if (ath9k_ps_enable) 718 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 719 720 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 721 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 722 723 if (AR_SREV_9280_20_OR_LATER(ah)) 724 hw->radiotap_mcs_details |= 725 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 726 } 727 728 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 729 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 730 731 hw->wiphy->features |= (NL80211_FEATURE_ACTIVE_MONITOR | 732 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE); 733 734 if (!config_enabled(CONFIG_ATH9K_TX99)) { 735 hw->wiphy->interface_modes = 736 BIT(NL80211_IFTYPE_P2P_GO) | 737 BIT(NL80211_IFTYPE_P2P_CLIENT) | 738 BIT(NL80211_IFTYPE_AP) | 739 BIT(NL80211_IFTYPE_STATION) | 740 BIT(NL80211_IFTYPE_ADHOC) | 741 BIT(NL80211_IFTYPE_MESH_POINT); 742 hw->wiphy->iface_combinations = if_comb; 743 if (!ath9k_use_chanctx) { 744 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 745 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_WDS); 746 } else 747 hw->wiphy->n_iface_combinations = 1; 748 } 749 750 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 751 752 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 753 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 754 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 755 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 756 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 757 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 758 759 hw->queues = 4; 760 hw->max_rates = 4; 761 hw->max_listen_interval = 1; 762 hw->max_rate_tries = 10; 763 hw->sta_data_size = sizeof(struct ath_node); 764 hw->vif_data_size = sizeof(struct ath_vif); 765 766 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 767 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 768 769 /* single chain devices with rx diversity */ 770 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 771 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 772 773 sc->ant_rx = hw->wiphy->available_antennas_rx; 774 sc->ant_tx = hw->wiphy->available_antennas_tx; 775 776 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 777 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 778 &common->sbands[IEEE80211_BAND_2GHZ]; 779 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 780 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 781 &common->sbands[IEEE80211_BAND_5GHZ]; 782 783 ath9k_init_wow(hw); 784 ath9k_cmn_reload_chainmask(ah); 785 786 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 787 } 788 789 int ath9k_init_device(u16 devid, struct ath_softc *sc, 790 const struct ath_bus_ops *bus_ops) 791 { 792 struct ieee80211_hw *hw = sc->hw; 793 struct ath_common *common; 794 struct ath_hw *ah; 795 int error = 0; 796 struct ath_regulatory *reg; 797 798 /* Bring up device */ 799 error = ath9k_init_softc(devid, sc, bus_ops); 800 if (error) 801 return error; 802 803 ah = sc->sc_ah; 804 common = ath9k_hw_common(ah); 805 ath9k_set_hw_capab(sc, hw); 806 807 /* Will be cleared in ath9k_start() */ 808 set_bit(ATH_OP_INVALID, &common->op_flags); 809 810 /* Initialize regulatory */ 811 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 812 ath9k_reg_notifier); 813 if (error) 814 goto deinit; 815 816 reg = &common->regulatory; 817 818 /* Setup TX DMA */ 819 error = ath_tx_init(sc, ATH_TXBUF); 820 if (error != 0) 821 goto deinit; 822 823 /* Setup RX DMA */ 824 error = ath_rx_init(sc, ATH_RXBUF); 825 if (error != 0) 826 goto deinit; 827 828 ath9k_init_txpower_limits(sc); 829 830 #ifdef CONFIG_MAC80211_LEDS 831 /* must be initialized before ieee80211_register_hw */ 832 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 833 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 834 ARRAY_SIZE(ath9k_tpt_blink)); 835 #endif 836 837 /* Register with mac80211 */ 838 error = ieee80211_register_hw(hw); 839 if (error) 840 goto rx_cleanup; 841 842 error = ath9k_init_debug(ah); 843 if (error) { 844 ath_err(common, "Unable to create debugfs files\n"); 845 goto unregister; 846 } 847 848 /* Handle world regulatory */ 849 if (!ath_is_world_regd(reg)) { 850 error = regulatory_hint(hw->wiphy, reg->alpha2); 851 if (error) 852 goto debug_cleanup; 853 } 854 855 ath_init_leds(sc); 856 ath_start_rfkill_poll(sc); 857 858 return 0; 859 860 debug_cleanup: 861 ath9k_deinit_debug(sc); 862 unregister: 863 ieee80211_unregister_hw(hw); 864 rx_cleanup: 865 ath_rx_cleanup(sc); 866 deinit: 867 ath9k_deinit_softc(sc); 868 return error; 869 } 870 871 /*****************************/ 872 /* De-Initialization */ 873 /*****************************/ 874 875 static void ath9k_deinit_softc(struct ath_softc *sc) 876 { 877 int i = 0; 878 879 if (sc->p2p_ps_timer) 880 ath_gen_timer_free(sc->sc_ah, sc->p2p_ps_timer); 881 882 ath9k_deinit_btcoex(sc); 883 884 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 885 if (ATH_TXQ_SETUP(sc, i)) 886 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 887 888 del_timer_sync(&sc->sleep_timer); 889 ath9k_hw_deinit(sc->sc_ah); 890 if (sc->dfs_detector != NULL) 891 sc->dfs_detector->exit(sc->dfs_detector); 892 893 ath9k_eeprom_release(sc); 894 } 895 896 void ath9k_deinit_device(struct ath_softc *sc) 897 { 898 struct ieee80211_hw *hw = sc->hw; 899 900 ath9k_ps_wakeup(sc); 901 902 wiphy_rfkill_stop_polling(sc->hw->wiphy); 903 ath_deinit_leds(sc); 904 905 ath9k_ps_restore(sc); 906 907 ath9k_deinit_debug(sc); 908 ieee80211_unregister_hw(hw); 909 ath_rx_cleanup(sc); 910 ath9k_deinit_softc(sc); 911 } 912 913 /************************/ 914 /* Module Hooks */ 915 /************************/ 916 917 static int __init ath9k_init(void) 918 { 919 int error; 920 921 error = ath_pci_init(); 922 if (error < 0) { 923 pr_err("No PCI devices found, driver not installed\n"); 924 error = -ENODEV; 925 goto err_out; 926 } 927 928 error = ath_ahb_init(); 929 if (error < 0) { 930 error = -ENODEV; 931 goto err_pci_exit; 932 } 933 934 return 0; 935 936 err_pci_exit: 937 ath_pci_exit(); 938 err_out: 939 return error; 940 } 941 module_init(ath9k_init); 942 943 static void __exit ath9k_exit(void) 944 { 945 is_ath9k_unloaded = true; 946 ath_ahb_exit(); 947 ath_pci_exit(); 948 pr_info("%s: Driver unloaded\n", dev_info); 949 } 950 module_exit(ath9k_exit); 951