1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 25 #include "ath9k.h" 26 27 struct ath9k_eeprom_ctx { 28 struct completion complete; 29 struct ath_hw *ah; 30 }; 31 32 static char *dev_info = "ath9k"; 33 34 MODULE_AUTHOR("Atheros Communications"); 35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 39 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 40 module_param_named(debug, ath9k_debug, uint, 0); 41 MODULE_PARM_DESC(debug, "Debugging mask"); 42 43 int ath9k_modparam_nohwcrypt; 44 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 46 47 int led_blink; 48 module_param_named(blink, led_blink, int, 0444); 49 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 50 51 static int ath9k_btcoex_enable; 52 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 53 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 54 55 static int ath9k_enable_diversity; 56 module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444); 57 MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565"); 58 59 bool is_ath9k_unloaded; 60 /* We use the hw_value as an index into our private channel structure */ 61 62 #define CHAN2G(_freq, _idx) { \ 63 .band = IEEE80211_BAND_2GHZ, \ 64 .center_freq = (_freq), \ 65 .hw_value = (_idx), \ 66 .max_power = 20, \ 67 } 68 69 #define CHAN5G(_freq, _idx) { \ 70 .band = IEEE80211_BAND_5GHZ, \ 71 .center_freq = (_freq), \ 72 .hw_value = (_idx), \ 73 .max_power = 20, \ 74 } 75 76 /* Some 2 GHz radios are actually tunable on 2312-2732 77 * on 5 MHz steps, we support the channels which we know 78 * we have calibration data for all cards though to make 79 * this static */ 80 static const struct ieee80211_channel ath9k_2ghz_chantable[] = { 81 CHAN2G(2412, 0), /* Channel 1 */ 82 CHAN2G(2417, 1), /* Channel 2 */ 83 CHAN2G(2422, 2), /* Channel 3 */ 84 CHAN2G(2427, 3), /* Channel 4 */ 85 CHAN2G(2432, 4), /* Channel 5 */ 86 CHAN2G(2437, 5), /* Channel 6 */ 87 CHAN2G(2442, 6), /* Channel 7 */ 88 CHAN2G(2447, 7), /* Channel 8 */ 89 CHAN2G(2452, 8), /* Channel 9 */ 90 CHAN2G(2457, 9), /* Channel 10 */ 91 CHAN2G(2462, 10), /* Channel 11 */ 92 CHAN2G(2467, 11), /* Channel 12 */ 93 CHAN2G(2472, 12), /* Channel 13 */ 94 CHAN2G(2484, 13), /* Channel 14 */ 95 }; 96 97 /* Some 5 GHz radios are actually tunable on XXXX-YYYY 98 * on 5 MHz steps, we support the channels which we know 99 * we have calibration data for all cards though to make 100 * this static */ 101 static const struct ieee80211_channel ath9k_5ghz_chantable[] = { 102 /* _We_ call this UNII 1 */ 103 CHAN5G(5180, 14), /* Channel 36 */ 104 CHAN5G(5200, 15), /* Channel 40 */ 105 CHAN5G(5220, 16), /* Channel 44 */ 106 CHAN5G(5240, 17), /* Channel 48 */ 107 /* _We_ call this UNII 2 */ 108 CHAN5G(5260, 18), /* Channel 52 */ 109 CHAN5G(5280, 19), /* Channel 56 */ 110 CHAN5G(5300, 20), /* Channel 60 */ 111 CHAN5G(5320, 21), /* Channel 64 */ 112 /* _We_ call this "Middle band" */ 113 CHAN5G(5500, 22), /* Channel 100 */ 114 CHAN5G(5520, 23), /* Channel 104 */ 115 CHAN5G(5540, 24), /* Channel 108 */ 116 CHAN5G(5560, 25), /* Channel 112 */ 117 CHAN5G(5580, 26), /* Channel 116 */ 118 CHAN5G(5600, 27), /* Channel 120 */ 119 CHAN5G(5620, 28), /* Channel 124 */ 120 CHAN5G(5640, 29), /* Channel 128 */ 121 CHAN5G(5660, 30), /* Channel 132 */ 122 CHAN5G(5680, 31), /* Channel 136 */ 123 CHAN5G(5700, 32), /* Channel 140 */ 124 /* _We_ call this UNII 3 */ 125 CHAN5G(5745, 33), /* Channel 149 */ 126 CHAN5G(5765, 34), /* Channel 153 */ 127 CHAN5G(5785, 35), /* Channel 157 */ 128 CHAN5G(5805, 36), /* Channel 161 */ 129 CHAN5G(5825, 37), /* Channel 165 */ 130 }; 131 132 /* Atheros hardware rate code addition for short premble */ 133 #define SHPCHECK(__hw_rate, __flags) \ 134 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) 135 136 #define RATE(_bitrate, _hw_rate, _flags) { \ 137 .bitrate = (_bitrate), \ 138 .flags = (_flags), \ 139 .hw_value = (_hw_rate), \ 140 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 141 } 142 143 static struct ieee80211_rate ath9k_legacy_rates[] = { 144 RATE(10, 0x1b, 0), 145 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), 146 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), 147 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), 148 RATE(60, 0x0b, 0), 149 RATE(90, 0x0f, 0), 150 RATE(120, 0x0a, 0), 151 RATE(180, 0x0e, 0), 152 RATE(240, 0x09, 0), 153 RATE(360, 0x0d, 0), 154 RATE(480, 0x08, 0), 155 RATE(540, 0x0c, 0), 156 }; 157 158 #ifdef CONFIG_MAC80211_LEDS 159 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 160 { .throughput = 0 * 1024, .blink_time = 334 }, 161 { .throughput = 1 * 1024, .blink_time = 260 }, 162 { .throughput = 5 * 1024, .blink_time = 220 }, 163 { .throughput = 10 * 1024, .blink_time = 190 }, 164 { .throughput = 20 * 1024, .blink_time = 170 }, 165 { .throughput = 50 * 1024, .blink_time = 150 }, 166 { .throughput = 70 * 1024, .blink_time = 130 }, 167 { .throughput = 100 * 1024, .blink_time = 110 }, 168 { .throughput = 200 * 1024, .blink_time = 80 }, 169 { .throughput = 300 * 1024, .blink_time = 50 }, 170 }; 171 #endif 172 173 static void ath9k_deinit_softc(struct ath_softc *sc); 174 175 /* 176 * Read and write, they both share the same lock. We do this to serialize 177 * reads and writes on Atheros 802.11n PCI devices only. This is required 178 * as the FIFO on these devices can only accept sanely 2 requests. 179 */ 180 181 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 182 { 183 struct ath_hw *ah = (struct ath_hw *) hw_priv; 184 struct ath_common *common = ath9k_hw_common(ah); 185 struct ath_softc *sc = (struct ath_softc *) common->priv; 186 187 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 188 unsigned long flags; 189 spin_lock_irqsave(&sc->sc_serial_rw, flags); 190 iowrite32(val, sc->mem + reg_offset); 191 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 192 } else 193 iowrite32(val, sc->mem + reg_offset); 194 } 195 196 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 197 { 198 struct ath_hw *ah = (struct ath_hw *) hw_priv; 199 struct ath_common *common = ath9k_hw_common(ah); 200 struct ath_softc *sc = (struct ath_softc *) common->priv; 201 u32 val; 202 203 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 204 unsigned long flags; 205 spin_lock_irqsave(&sc->sc_serial_rw, flags); 206 val = ioread32(sc->mem + reg_offset); 207 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 208 } else 209 val = ioread32(sc->mem + reg_offset); 210 return val; 211 } 212 213 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 214 u32 set, u32 clr) 215 { 216 u32 val; 217 218 val = ioread32(sc->mem + reg_offset); 219 val &= ~clr; 220 val |= set; 221 iowrite32(val, sc->mem + reg_offset); 222 223 return val; 224 } 225 226 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 227 { 228 struct ath_hw *ah = (struct ath_hw *) hw_priv; 229 struct ath_common *common = ath9k_hw_common(ah); 230 struct ath_softc *sc = (struct ath_softc *) common->priv; 231 unsigned long uninitialized_var(flags); 232 u32 val; 233 234 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 235 spin_lock_irqsave(&sc->sc_serial_rw, flags); 236 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 237 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 238 } else 239 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 240 241 return val; 242 } 243 244 /**************************/ 245 /* Initialization */ 246 /**************************/ 247 248 static void setup_ht_cap(struct ath_softc *sc, 249 struct ieee80211_sta_ht_cap *ht_info) 250 { 251 struct ath_hw *ah = sc->sc_ah; 252 struct ath_common *common = ath9k_hw_common(ah); 253 u8 tx_streams, rx_streams; 254 int i, max_streams; 255 256 ht_info->ht_supported = true; 257 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 258 IEEE80211_HT_CAP_SM_PS | 259 IEEE80211_HT_CAP_SGI_40 | 260 IEEE80211_HT_CAP_DSSSCCK40; 261 262 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) 263 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; 264 265 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 266 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 267 268 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 269 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 270 271 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) 272 max_streams = 1; 273 else if (AR_SREV_9462(ah)) 274 max_streams = 2; 275 else if (AR_SREV_9300_20_OR_LATER(ah)) 276 max_streams = 3; 277 else 278 max_streams = 2; 279 280 if (AR_SREV_9280_20_OR_LATER(ah)) { 281 if (max_streams >= 2) 282 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; 283 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 284 } 285 286 /* set up supported mcs set */ 287 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 288 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); 289 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); 290 291 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", 292 tx_streams, rx_streams); 293 294 if (tx_streams != rx_streams) { 295 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 296 ht_info->mcs.tx_params |= ((tx_streams - 1) << 297 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 298 } 299 300 for (i = 0; i < rx_streams; i++) 301 ht_info->mcs.rx_mask[i] = 0xff; 302 303 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 304 } 305 306 static void ath9k_reg_notifier(struct wiphy *wiphy, 307 struct regulatory_request *request) 308 { 309 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 310 struct ath_softc *sc = hw->priv; 311 struct ath_hw *ah = sc->sc_ah; 312 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 313 314 ath_reg_notifier_apply(wiphy, request, reg); 315 316 /* Set tx power */ 317 if (ah->curchan) { 318 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 319 ath9k_ps_wakeup(sc); 320 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 321 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 322 ath9k_ps_restore(sc); 323 } 324 } 325 326 /* 327 * This function will allocate both the DMA descriptor structure, and the 328 * buffers it contains. These are used to contain the descriptors used 329 * by the system. 330 */ 331 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 332 struct list_head *head, const char *name, 333 int nbuf, int ndesc, bool is_tx) 334 { 335 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 336 u8 *ds; 337 struct ath_buf *bf; 338 int i, bsize, desc_len; 339 340 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 341 name, nbuf, ndesc); 342 343 INIT_LIST_HEAD(head); 344 345 if (is_tx) 346 desc_len = sc->sc_ah->caps.tx_desc_len; 347 else 348 desc_len = sizeof(struct ath_desc); 349 350 /* ath_desc must be a multiple of DWORDs */ 351 if ((desc_len % 4) != 0) { 352 ath_err(common, "ath_desc not DWORD aligned\n"); 353 BUG_ON((desc_len % 4) != 0); 354 return -ENOMEM; 355 } 356 357 dd->dd_desc_len = desc_len * nbuf * ndesc; 358 359 /* 360 * Need additional DMA memory because we can't use 361 * descriptors that cross the 4K page boundary. Assume 362 * one skipped descriptor per 4K page. 363 */ 364 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 365 u32 ndesc_skipped = 366 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 367 u32 dma_len; 368 369 while (ndesc_skipped) { 370 dma_len = ndesc_skipped * desc_len; 371 dd->dd_desc_len += dma_len; 372 373 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 374 } 375 } 376 377 /* allocate descriptors */ 378 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 379 &dd->dd_desc_paddr, GFP_KERNEL); 380 if (!dd->dd_desc) 381 return -ENOMEM; 382 383 ds = (u8 *) dd->dd_desc; 384 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 385 name, ds, (u32) dd->dd_desc_len, 386 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 387 388 /* allocate buffers */ 389 bsize = sizeof(struct ath_buf) * nbuf; 390 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 391 if (!bf) 392 return -ENOMEM; 393 394 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 395 bf->bf_desc = ds; 396 bf->bf_daddr = DS2PHYS(dd, ds); 397 398 if (!(sc->sc_ah->caps.hw_caps & 399 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 400 /* 401 * Skip descriptor addresses which can cause 4KB 402 * boundary crossing (addr + length) with a 32 dword 403 * descriptor fetch. 404 */ 405 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 406 BUG_ON((caddr_t) bf->bf_desc >= 407 ((caddr_t) dd->dd_desc + 408 dd->dd_desc_len)); 409 410 ds += (desc_len * ndesc); 411 bf->bf_desc = ds; 412 bf->bf_daddr = DS2PHYS(dd, ds); 413 } 414 } 415 list_add_tail(&bf->list, head); 416 } 417 return 0; 418 } 419 420 static int ath9k_init_queues(struct ath_softc *sc) 421 { 422 int i = 0; 423 424 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 425 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 426 427 sc->config.cabqReadytime = ATH_CABQ_READY_TIME; 428 ath_cabq_update(sc); 429 430 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 431 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 432 sc->tx.txq_map[i]->mac80211_qnum = i; 433 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 434 } 435 return 0; 436 } 437 438 static int ath9k_init_channels_rates(struct ath_softc *sc) 439 { 440 void *channels; 441 442 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + 443 ARRAY_SIZE(ath9k_5ghz_chantable) != 444 ATH9K_NUM_CHANNELS); 445 446 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 447 channels = devm_kzalloc(sc->dev, 448 sizeof(ath9k_2ghz_chantable), GFP_KERNEL); 449 if (!channels) 450 return -ENOMEM; 451 452 memcpy(channels, ath9k_2ghz_chantable, 453 sizeof(ath9k_2ghz_chantable)); 454 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; 455 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 456 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 457 ARRAY_SIZE(ath9k_2ghz_chantable); 458 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 459 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 460 ARRAY_SIZE(ath9k_legacy_rates); 461 } 462 463 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 464 channels = devm_kzalloc(sc->dev, 465 sizeof(ath9k_5ghz_chantable), GFP_KERNEL); 466 if (!channels) 467 return -ENOMEM; 468 469 memcpy(channels, ath9k_5ghz_chantable, 470 sizeof(ath9k_5ghz_chantable)); 471 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; 472 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 473 sc->sbands[IEEE80211_BAND_5GHZ].n_channels = 474 ARRAY_SIZE(ath9k_5ghz_chantable); 475 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 476 ath9k_legacy_rates + 4; 477 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 478 ARRAY_SIZE(ath9k_legacy_rates) - 4; 479 } 480 return 0; 481 } 482 483 static void ath9k_init_misc(struct ath_softc *sc) 484 { 485 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 486 int i = 0; 487 488 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 489 490 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 491 sc->config.txpowlimit = ATH_TXPOWER_MAX; 492 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 493 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 494 495 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 496 sc->beacon.bslot[i] = NULL; 497 498 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 499 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 500 501 sc->spec_config.enabled = 0; 502 sc->spec_config.short_repeat = true; 503 sc->spec_config.count = 8; 504 sc->spec_config.endless = false; 505 sc->spec_config.period = 0xFF; 506 sc->spec_config.fft_period = 0xF; 507 } 508 509 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 510 void *ctx) 511 { 512 struct ath9k_eeprom_ctx *ec = ctx; 513 514 if (eeprom_blob) 515 ec->ah->eeprom_blob = eeprom_blob; 516 517 complete(&ec->complete); 518 } 519 520 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 521 { 522 struct ath9k_eeprom_ctx ec; 523 struct ath_hw *ah = ah = sc->sc_ah; 524 int err; 525 526 /* try to load the EEPROM content asynchronously */ 527 init_completion(&ec.complete); 528 ec.ah = sc->sc_ah; 529 530 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 531 &ec, ath9k_eeprom_request_cb); 532 if (err < 0) { 533 ath_err(ath9k_hw_common(ah), 534 "EEPROM request failed\n"); 535 return err; 536 } 537 538 wait_for_completion(&ec.complete); 539 540 if (!ah->eeprom_blob) { 541 ath_err(ath9k_hw_common(ah), 542 "Unable to load EEPROM file %s\n", name); 543 return -EINVAL; 544 } 545 546 return 0; 547 } 548 549 static void ath9k_eeprom_release(struct ath_softc *sc) 550 { 551 release_firmware(sc->sc_ah->eeprom_blob); 552 } 553 554 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 555 const struct ath_bus_ops *bus_ops) 556 { 557 struct ath9k_platform_data *pdata = sc->dev->platform_data; 558 struct ath_hw *ah = NULL; 559 struct ath_common *common; 560 int ret = 0, i; 561 int csz = 0; 562 563 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 564 if (!ah) 565 return -ENOMEM; 566 567 ah->dev = sc->dev; 568 ah->hw = sc->hw; 569 ah->hw_version.devid = devid; 570 ah->reg_ops.read = ath9k_ioread32; 571 ah->reg_ops.write = ath9k_iowrite32; 572 ah->reg_ops.rmw = ath9k_reg_rmw; 573 atomic_set(&ah->intr_ref_cnt, -1); 574 sc->sc_ah = ah; 575 576 sc->dfs_detector = dfs_pattern_detector_init(NL80211_DFS_UNSET); 577 578 if (!pdata) { 579 ah->ah_flags |= AH_USE_EEPROM; 580 sc->sc_ah->led_pin = -1; 581 } else { 582 sc->sc_ah->gpio_mask = pdata->gpio_mask; 583 sc->sc_ah->gpio_val = pdata->gpio_val; 584 sc->sc_ah->led_pin = pdata->led_pin; 585 ah->is_clk_25mhz = pdata->is_clk_25mhz; 586 ah->get_mac_revision = pdata->get_mac_revision; 587 ah->external_reset = pdata->external_reset; 588 } 589 590 common = ath9k_hw_common(ah); 591 common->ops = &ah->reg_ops; 592 common->bus_ops = bus_ops; 593 common->ah = ah; 594 common->hw = sc->hw; 595 common->priv = sc; 596 common->debug_mask = ath9k_debug; 597 common->btcoex_enabled = ath9k_btcoex_enable == 1; 598 common->disable_ani = false; 599 600 /* 601 * Enable Antenna diversity only when BTCOEX is disabled 602 * and the user manually requests the feature. 603 */ 604 if (!common->btcoex_enabled && ath9k_enable_diversity) 605 common->antenna_diversity = 1; 606 607 spin_lock_init(&common->cc_lock); 608 609 spin_lock_init(&sc->sc_serial_rw); 610 spin_lock_init(&sc->sc_pm_lock); 611 mutex_init(&sc->mutex); 612 #ifdef CONFIG_ATH9K_MAC_DEBUG 613 spin_lock_init(&sc->debug.samp_lock); 614 #endif 615 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 616 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 617 (unsigned long)sc); 618 619 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 620 INIT_WORK(&sc->hw_check_work, ath_hw_check); 621 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 622 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 623 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); 624 625 /* 626 * Cache line size is used to size and align various 627 * structures used to communicate with the hardware. 628 */ 629 ath_read_cachesize(common, &csz); 630 common->cachelsz = csz << 2; /* convert to bytes */ 631 632 if (pdata && pdata->eeprom_name) { 633 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 634 if (ret) 635 return ret; 636 } 637 638 /* Initializes the hardware for all supported chipsets */ 639 ret = ath9k_hw_init(ah); 640 if (ret) 641 goto err_hw; 642 643 if (pdata && pdata->macaddr) 644 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 645 646 ret = ath9k_init_queues(sc); 647 if (ret) 648 goto err_queues; 649 650 ret = ath9k_init_btcoex(sc); 651 if (ret) 652 goto err_btcoex; 653 654 ret = ath9k_init_channels_rates(sc); 655 if (ret) 656 goto err_btcoex; 657 658 ath9k_cmn_init_crypto(sc->sc_ah); 659 ath9k_init_misc(sc); 660 ath_fill_led_pin(sc); 661 662 if (common->bus_ops->aspm_init) 663 common->bus_ops->aspm_init(common); 664 665 return 0; 666 667 err_btcoex: 668 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 669 if (ATH_TXQ_SETUP(sc, i)) 670 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 671 err_queues: 672 ath9k_hw_deinit(ah); 673 err_hw: 674 ath9k_eeprom_release(sc); 675 return ret; 676 } 677 678 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 679 { 680 struct ieee80211_supported_band *sband; 681 struct ieee80211_channel *chan; 682 struct ath_hw *ah = sc->sc_ah; 683 int i; 684 685 sband = &sc->sbands[band]; 686 for (i = 0; i < sband->n_channels; i++) { 687 chan = &sband->channels[i]; 688 ah->curchan = &ah->channels[chan->hw_value]; 689 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); 690 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 691 } 692 } 693 694 static void ath9k_init_txpower_limits(struct ath_softc *sc) 695 { 696 struct ath_hw *ah = sc->sc_ah; 697 struct ath9k_channel *curchan = ah->curchan; 698 699 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 700 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 701 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 702 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 703 704 ah->curchan = curchan; 705 } 706 707 void ath9k_reload_chainmask_settings(struct ath_softc *sc) 708 { 709 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) 710 return; 711 712 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 713 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 714 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 715 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 716 } 717 718 static const struct ieee80211_iface_limit if_limits[] = { 719 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | 720 BIT(NL80211_IFTYPE_P2P_CLIENT) | 721 BIT(NL80211_IFTYPE_WDS) }, 722 { .max = 8, .types = 723 #ifdef CONFIG_MAC80211_MESH 724 BIT(NL80211_IFTYPE_MESH_POINT) | 725 #endif 726 BIT(NL80211_IFTYPE_AP) | 727 BIT(NL80211_IFTYPE_P2P_GO) }, 728 }; 729 730 static const struct ieee80211_iface_combination if_comb = { 731 .limits = if_limits, 732 .n_limits = ARRAY_SIZE(if_limits), 733 .max_interfaces = 2048, 734 .num_different_channels = 1, 735 .beacon_int_infra_match = true, 736 }; 737 738 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 739 { 740 struct ath_hw *ah = sc->sc_ah; 741 struct ath_common *common = ath9k_hw_common(ah); 742 743 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 744 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 745 IEEE80211_HW_SIGNAL_DBM | 746 IEEE80211_HW_SUPPORTS_PS | 747 IEEE80211_HW_PS_NULLFUNC_STACK | 748 IEEE80211_HW_SPECTRUM_MGMT | 749 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 750 751 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 752 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 753 754 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 755 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 756 757 hw->wiphy->interface_modes = 758 BIT(NL80211_IFTYPE_P2P_GO) | 759 BIT(NL80211_IFTYPE_P2P_CLIENT) | 760 BIT(NL80211_IFTYPE_AP) | 761 BIT(NL80211_IFTYPE_WDS) | 762 BIT(NL80211_IFTYPE_STATION) | 763 BIT(NL80211_IFTYPE_ADHOC) | 764 BIT(NL80211_IFTYPE_MESH_POINT); 765 766 hw->wiphy->iface_combinations = &if_comb; 767 hw->wiphy->n_iface_combinations = 1; 768 769 if (AR_SREV_5416(sc->sc_ah)) 770 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 771 772 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 773 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 774 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 775 776 #ifdef CONFIG_PM_SLEEP 777 778 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && 779 device_can_wakeup(sc->dev)) { 780 781 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT | 782 WIPHY_WOWLAN_DISCONNECT; 783 hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN; 784 hw->wiphy->wowlan.pattern_min_len = 1; 785 hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE; 786 787 } 788 789 atomic_set(&sc->wow_sleep_proc_intr, -1); 790 atomic_set(&sc->wow_got_bmiss_intr, -1); 791 792 #endif 793 794 hw->queues = 4; 795 hw->max_rates = 4; 796 hw->channel_change_time = 5000; 797 hw->max_listen_interval = 1; 798 hw->max_rate_tries = 10; 799 hw->sta_data_size = sizeof(struct ath_node); 800 hw->vif_data_size = sizeof(struct ath_vif); 801 802 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 803 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 804 805 /* single chain devices with rx diversity */ 806 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 807 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 808 809 sc->ant_rx = hw->wiphy->available_antennas_rx; 810 sc->ant_tx = hw->wiphy->available_antennas_tx; 811 812 #ifdef CONFIG_ATH9K_RATE_CONTROL 813 hw->rate_control_algorithm = "ath9k_rate_control"; 814 #endif 815 816 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 817 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 818 &sc->sbands[IEEE80211_BAND_2GHZ]; 819 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 820 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 821 &sc->sbands[IEEE80211_BAND_5GHZ]; 822 823 ath9k_reload_chainmask_settings(sc); 824 825 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 826 } 827 828 int ath9k_init_device(u16 devid, struct ath_softc *sc, 829 const struct ath_bus_ops *bus_ops) 830 { 831 struct ieee80211_hw *hw = sc->hw; 832 struct ath_common *common; 833 struct ath_hw *ah; 834 int error = 0; 835 struct ath_regulatory *reg; 836 837 /* Bring up device */ 838 error = ath9k_init_softc(devid, sc, bus_ops); 839 if (error) 840 return error; 841 842 ah = sc->sc_ah; 843 common = ath9k_hw_common(ah); 844 ath9k_set_hw_capab(sc, hw); 845 846 /* Initialize regulatory */ 847 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 848 ath9k_reg_notifier); 849 if (error) 850 goto deinit; 851 852 reg = &common->regulatory; 853 854 /* Setup TX DMA */ 855 error = ath_tx_init(sc, ATH_TXBUF); 856 if (error != 0) 857 goto deinit; 858 859 /* Setup RX DMA */ 860 error = ath_rx_init(sc, ATH_RXBUF); 861 if (error != 0) 862 goto deinit; 863 864 ath9k_init_txpower_limits(sc); 865 866 #ifdef CONFIG_MAC80211_LEDS 867 /* must be initialized before ieee80211_register_hw */ 868 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 869 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 870 ARRAY_SIZE(ath9k_tpt_blink)); 871 #endif 872 873 /* Register with mac80211 */ 874 error = ieee80211_register_hw(hw); 875 if (error) 876 goto rx_cleanup; 877 878 error = ath9k_init_debug(ah); 879 if (error) { 880 ath_err(common, "Unable to create debugfs files\n"); 881 goto unregister; 882 } 883 884 /* Handle world regulatory */ 885 if (!ath_is_world_regd(reg)) { 886 error = regulatory_hint(hw->wiphy, reg->alpha2); 887 if (error) 888 goto unregister; 889 } 890 891 ath_init_leds(sc); 892 ath_start_rfkill_poll(sc); 893 894 return 0; 895 896 unregister: 897 ieee80211_unregister_hw(hw); 898 rx_cleanup: 899 ath_rx_cleanup(sc); 900 deinit: 901 ath9k_deinit_softc(sc); 902 return error; 903 } 904 905 /*****************************/ 906 /* De-Initialization */ 907 /*****************************/ 908 909 static void ath9k_deinit_softc(struct ath_softc *sc) 910 { 911 int i = 0; 912 913 ath9k_deinit_btcoex(sc); 914 915 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 916 if (ATH_TXQ_SETUP(sc, i)) 917 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 918 919 ath9k_hw_deinit(sc->sc_ah); 920 if (sc->dfs_detector != NULL) 921 sc->dfs_detector->exit(sc->dfs_detector); 922 923 ath9k_eeprom_release(sc); 924 925 if (config_enabled(CONFIG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) { 926 relay_close(sc->rfs_chan_spec_scan); 927 sc->rfs_chan_spec_scan = NULL; 928 } 929 } 930 931 void ath9k_deinit_device(struct ath_softc *sc) 932 { 933 struct ieee80211_hw *hw = sc->hw; 934 935 ath9k_ps_wakeup(sc); 936 937 wiphy_rfkill_stop_polling(sc->hw->wiphy); 938 ath_deinit_leds(sc); 939 940 ath9k_ps_restore(sc); 941 942 ieee80211_unregister_hw(hw); 943 ath_rx_cleanup(sc); 944 ath9k_deinit_softc(sc); 945 } 946 947 /************************/ 948 /* Module Hooks */ 949 /************************/ 950 951 static int __init ath9k_init(void) 952 { 953 int error; 954 955 /* Register rate control algorithm */ 956 error = ath_rate_control_register(); 957 if (error != 0) { 958 pr_err("Unable to register rate control algorithm: %d\n", 959 error); 960 goto err_out; 961 } 962 963 error = ath_pci_init(); 964 if (error < 0) { 965 pr_err("No PCI devices found, driver not installed\n"); 966 error = -ENODEV; 967 goto err_rate_unregister; 968 } 969 970 error = ath_ahb_init(); 971 if (error < 0) { 972 error = -ENODEV; 973 goto err_pci_exit; 974 } 975 976 return 0; 977 978 err_pci_exit: 979 ath_pci_exit(); 980 981 err_rate_unregister: 982 ath_rate_control_unregister(); 983 err_out: 984 return error; 985 } 986 module_init(ath9k_init); 987 988 static void __exit ath9k_exit(void) 989 { 990 is_ath9k_unloaded = true; 991 ath_ahb_exit(); 992 ath_pci_exit(); 993 ath_rate_control_unregister(); 994 pr_info("%s: Driver unloaded\n", dev_info); 995 } 996 module_exit(ath9k_exit); 997