1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/relay.h> 26 #include <linux/dmi.h> 27 #include <net/ieee80211_radiotap.h> 28 29 #include "ath9k.h" 30 31 struct ath9k_eeprom_ctx { 32 struct completion complete; 33 struct ath_hw *ah; 34 }; 35 36 static char *dev_info = "ath9k"; 37 38 MODULE_AUTHOR("Atheros Communications"); 39 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 40 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 41 MODULE_LICENSE("Dual BSD/GPL"); 42 43 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 44 module_param_named(debug, ath9k_debug, uint, 0); 45 MODULE_PARM_DESC(debug, "Debugging mask"); 46 47 int ath9k_modparam_nohwcrypt; 48 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 49 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 50 51 int ath9k_led_blink; 52 module_param_named(blink, ath9k_led_blink, int, 0444); 53 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 54 55 static int ath9k_led_active_high = -1; 56 module_param_named(led_active_high, ath9k_led_active_high, int, 0444); 57 MODULE_PARM_DESC(led_active_high, "Invert LED polarity"); 58 59 static int ath9k_btcoex_enable; 60 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 61 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 62 63 static int ath9k_bt_ant_diversity; 64 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 65 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 66 67 static int ath9k_ps_enable; 68 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 69 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 70 71 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 72 73 int ath9k_use_chanctx; 74 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 75 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 76 77 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 78 79 int ath9k_use_msi; 80 module_param_named(use_msi, ath9k_use_msi, int, 0444); 81 MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible"); 82 83 bool is_ath9k_unloaded; 84 85 #ifdef CONFIG_MAC80211_LEDS 86 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 87 { .throughput = 0 * 1024, .blink_time = 334 }, 88 { .throughput = 1 * 1024, .blink_time = 260 }, 89 { .throughput = 5 * 1024, .blink_time = 220 }, 90 { .throughput = 10 * 1024, .blink_time = 190 }, 91 { .throughput = 20 * 1024, .blink_time = 170 }, 92 { .throughput = 50 * 1024, .blink_time = 150 }, 93 { .throughput = 70 * 1024, .blink_time = 130 }, 94 { .throughput = 100 * 1024, .blink_time = 110 }, 95 { .throughput = 200 * 1024, .blink_time = 80 }, 96 { .throughput = 300 * 1024, .blink_time = 50 }, 97 }; 98 #endif 99 100 static int __init set_use_msi(const struct dmi_system_id *dmi) 101 { 102 ath9k_use_msi = 1; 103 return 1; 104 } 105 106 static const struct dmi_system_id ath9k_quirks[] __initconst = { 107 { 108 .callback = set_use_msi, 109 .ident = "Dell Inspiron 24-3460", 110 .matches = { 111 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 112 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"), 113 }, 114 }, 115 { 116 .callback = set_use_msi, 117 .ident = "Dell Vostro 3262", 118 .matches = { 119 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 120 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"), 121 }, 122 }, 123 { 124 .callback = set_use_msi, 125 .ident = "Dell Inspiron 3472", 126 .matches = { 127 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 128 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"), 129 }, 130 }, 131 { 132 .callback = set_use_msi, 133 .ident = "Dell Vostro 15-3572", 134 .matches = { 135 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 136 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"), 137 }, 138 }, 139 { 140 .callback = set_use_msi, 141 .ident = "Dell Inspiron 14-3473", 142 .matches = { 143 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 144 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"), 145 }, 146 }, 147 {} 148 }; 149 150 static void ath9k_deinit_softc(struct ath_softc *sc); 151 152 static void ath9k_op_ps_wakeup(struct ath_common *common) 153 { 154 ath9k_ps_wakeup((struct ath_softc *) common->priv); 155 } 156 157 static void ath9k_op_ps_restore(struct ath_common *common) 158 { 159 ath9k_ps_restore((struct ath_softc *) common->priv); 160 } 161 162 static const struct ath_ps_ops ath9k_ps_ops = { 163 .wakeup = ath9k_op_ps_wakeup, 164 .restore = ath9k_op_ps_restore, 165 }; 166 167 /* 168 * Read and write, they both share the same lock. We do this to serialize 169 * reads and writes on Atheros 802.11n PCI devices only. This is required 170 * as the FIFO on these devices can only accept sanely 2 requests. 171 */ 172 173 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 174 { 175 struct ath_hw *ah = hw_priv; 176 struct ath_common *common = ath9k_hw_common(ah); 177 struct ath_softc *sc = (struct ath_softc *) common->priv; 178 179 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 180 unsigned long flags; 181 spin_lock_irqsave(&sc->sc_serial_rw, flags); 182 iowrite32(val, sc->mem + reg_offset); 183 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 184 } else 185 iowrite32(val, sc->mem + reg_offset); 186 } 187 188 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 189 { 190 struct ath_hw *ah = hw_priv; 191 struct ath_common *common = ath9k_hw_common(ah); 192 struct ath_softc *sc = (struct ath_softc *) common->priv; 193 u32 val; 194 195 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 196 unsigned long flags; 197 spin_lock_irqsave(&sc->sc_serial_rw, flags); 198 val = ioread32(sc->mem + reg_offset); 199 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 200 } else 201 val = ioread32(sc->mem + reg_offset); 202 return val; 203 } 204 205 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr, 206 u32 *val, u16 count) 207 { 208 int i; 209 210 for (i = 0; i < count; i++) 211 val[i] = ath9k_ioread32(hw_priv, addr[i]); 212 } 213 214 215 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 216 u32 set, u32 clr) 217 { 218 u32 val; 219 220 val = ioread32(sc->mem + reg_offset); 221 val &= ~clr; 222 val |= set; 223 iowrite32(val, sc->mem + reg_offset); 224 225 return val; 226 } 227 228 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 229 { 230 struct ath_hw *ah = hw_priv; 231 struct ath_common *common = ath9k_hw_common(ah); 232 struct ath_softc *sc = (struct ath_softc *) common->priv; 233 unsigned long uninitialized_var(flags); 234 u32 val; 235 236 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 237 spin_lock_irqsave(&sc->sc_serial_rw, flags); 238 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 239 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 240 } else 241 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 242 243 return val; 244 } 245 246 /**************************/ 247 /* Initialization */ 248 /**************************/ 249 250 static void ath9k_reg_notifier(struct wiphy *wiphy, 251 struct regulatory_request *request) 252 { 253 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 254 struct ath_softc *sc = hw->priv; 255 struct ath_hw *ah = sc->sc_ah; 256 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 257 258 ath_reg_notifier_apply(wiphy, request, reg); 259 260 /* Set tx power */ 261 if (!ah->curchan) 262 return; 263 264 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; 265 ath9k_ps_wakeup(sc); 266 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 267 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 268 sc->cur_chan->txpower, 269 &sc->cur_chan->cur_txpower); 270 /* synchronize DFS detector if regulatory domain changed */ 271 if (sc->dfs_detector != NULL) 272 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 273 request->dfs_region); 274 ath9k_ps_restore(sc); 275 } 276 277 /* 278 * This function will allocate both the DMA descriptor structure, and the 279 * buffers it contains. These are used to contain the descriptors used 280 * by the system. 281 */ 282 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 283 struct list_head *head, const char *name, 284 int nbuf, int ndesc, bool is_tx) 285 { 286 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 287 u8 *ds; 288 int i, bsize, desc_len; 289 290 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 291 name, nbuf, ndesc); 292 293 INIT_LIST_HEAD(head); 294 295 if (is_tx) 296 desc_len = sc->sc_ah->caps.tx_desc_len; 297 else 298 desc_len = sizeof(struct ath_desc); 299 300 /* ath_desc must be a multiple of DWORDs */ 301 if ((desc_len % 4) != 0) { 302 ath_err(common, "ath_desc not DWORD aligned\n"); 303 BUG_ON((desc_len % 4) != 0); 304 return -ENOMEM; 305 } 306 307 dd->dd_desc_len = desc_len * nbuf * ndesc; 308 309 /* 310 * Need additional DMA memory because we can't use 311 * descriptors that cross the 4K page boundary. Assume 312 * one skipped descriptor per 4K page. 313 */ 314 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 315 u32 ndesc_skipped = 316 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 317 u32 dma_len; 318 319 while (ndesc_skipped) { 320 dma_len = ndesc_skipped * desc_len; 321 dd->dd_desc_len += dma_len; 322 323 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 324 } 325 } 326 327 /* allocate descriptors */ 328 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 329 &dd->dd_desc_paddr, GFP_KERNEL); 330 if (!dd->dd_desc) 331 return -ENOMEM; 332 333 ds = dd->dd_desc; 334 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 335 name, ds, (u32) dd->dd_desc_len, 336 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 337 338 /* allocate buffers */ 339 if (is_tx) { 340 struct ath_buf *bf; 341 342 bsize = sizeof(struct ath_buf) * nbuf; 343 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 344 if (!bf) 345 return -ENOMEM; 346 347 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 348 bf->bf_desc = ds; 349 bf->bf_daddr = DS2PHYS(dd, ds); 350 351 if (!(sc->sc_ah->caps.hw_caps & 352 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 353 /* 354 * Skip descriptor addresses which can cause 4KB 355 * boundary crossing (addr + length) with a 32 dword 356 * descriptor fetch. 357 */ 358 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 359 BUG_ON((caddr_t) bf->bf_desc >= 360 ((caddr_t) dd->dd_desc + 361 dd->dd_desc_len)); 362 363 ds += (desc_len * ndesc); 364 bf->bf_desc = ds; 365 bf->bf_daddr = DS2PHYS(dd, ds); 366 } 367 } 368 list_add_tail(&bf->list, head); 369 } 370 } else { 371 struct ath_rxbuf *bf; 372 373 bsize = sizeof(struct ath_rxbuf) * nbuf; 374 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 375 if (!bf) 376 return -ENOMEM; 377 378 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 379 bf->bf_desc = ds; 380 bf->bf_daddr = DS2PHYS(dd, ds); 381 382 if (!(sc->sc_ah->caps.hw_caps & 383 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 384 /* 385 * Skip descriptor addresses which can cause 4KB 386 * boundary crossing (addr + length) with a 32 dword 387 * descriptor fetch. 388 */ 389 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 390 BUG_ON((caddr_t) bf->bf_desc >= 391 ((caddr_t) dd->dd_desc + 392 dd->dd_desc_len)); 393 394 ds += (desc_len * ndesc); 395 bf->bf_desc = ds; 396 bf->bf_daddr = DS2PHYS(dd, ds); 397 } 398 } 399 list_add_tail(&bf->list, head); 400 } 401 } 402 return 0; 403 } 404 405 static int ath9k_init_queues(struct ath_softc *sc) 406 { 407 int i = 0; 408 409 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 410 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 411 ath_cabq_update(sc); 412 413 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 414 415 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 416 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 417 sc->tx.txq_map[i]->mac80211_qnum = i; 418 } 419 return 0; 420 } 421 422 static void ath9k_init_misc(struct ath_softc *sc) 423 { 424 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 425 int i = 0; 426 427 timer_setup(&common->ani.timer, ath_ani_calibrate, 0); 428 429 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 430 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 431 sc->beacon.slottime = 9; 432 433 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 434 sc->beacon.bslot[i] = NULL; 435 436 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 437 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 438 439 sc->spec_priv.ah = sc->sc_ah; 440 sc->spec_priv.spec_config.enabled = 0; 441 sc->spec_priv.spec_config.short_repeat = true; 442 sc->spec_priv.spec_config.count = 8; 443 sc->spec_priv.spec_config.endless = false; 444 sc->spec_priv.spec_config.period = 0xFF; 445 sc->spec_priv.spec_config.fft_period = 0xF; 446 } 447 448 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 449 { 450 struct ath_hw *ah = sc->sc_ah; 451 struct ath9k_hw_capabilities *pCap = &ah->caps; 452 struct ath_common *common = ath9k_hw_common(ah); 453 454 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM)) 455 return; 456 457 if (common->bus_ops->ath_bus_type != ATH_PCI) 458 return; 459 460 if (sc->driver_data & (ATH9K_PCI_CUS198 | 461 ATH9K_PCI_CUS230)) { 462 ah->config.xlna_gpio = 9; 463 ah->config.xatten_margin_cfg = true; 464 ah->config.alt_mingainidx = true; 465 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 466 sc->ant_comb.low_rssi_thresh = 20; 467 sc->ant_comb.fast_div_bias = 3; 468 469 ath_info(common, "Set parameters for %s\n", 470 (sc->driver_data & ATH9K_PCI_CUS198) ? 471 "CUS198" : "CUS230"); 472 } 473 474 if (sc->driver_data & ATH9K_PCI_CUS217) 475 ath_info(common, "CUS217 card detected\n"); 476 477 if (sc->driver_data & ATH9K_PCI_CUS252) 478 ath_info(common, "CUS252 card detected\n"); 479 480 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 481 ath_info(common, "WB335 1-ANT card detected\n"); 482 483 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 484 ath_info(common, "WB335 2-ANT card detected\n"); 485 486 if (sc->driver_data & ATH9K_PCI_KILLER) 487 ath_info(common, "Killer Wireless card detected\n"); 488 489 /* 490 * Some WB335 cards do not support antenna diversity. Since 491 * we use a hardcoded value for AR9565 instead of using the 492 * EEPROM/OTP data, remove the combining feature from 493 * the HW capabilities bitmap. 494 */ 495 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 496 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 497 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 498 } 499 500 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 501 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 502 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 503 } 504 505 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 506 ah->config.pcie_waen = 0x0040473b; 507 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 508 } 509 510 /* 511 * The default value of pll_pwrsave is 1. 512 * For certain AR9485 cards, it is set to 0. 513 * For AR9462, AR9565 it's set to 7. 514 */ 515 ah->config.pll_pwrsave = 1; 516 517 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 518 ah->config.pll_pwrsave = 0; 519 ath_info(common, "Disable PLL PowerSave\n"); 520 } 521 522 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI) 523 ah->config.led_active_high = true; 524 } 525 526 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 527 void *ctx) 528 { 529 struct ath9k_eeprom_ctx *ec = ctx; 530 531 if (eeprom_blob) 532 ec->ah->eeprom_blob = eeprom_blob; 533 534 complete(&ec->complete); 535 } 536 537 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 538 { 539 struct ath9k_eeprom_ctx ec; 540 struct ath_hw *ah = sc->sc_ah; 541 int err; 542 543 /* try to load the EEPROM content asynchronously */ 544 init_completion(&ec.complete); 545 ec.ah = sc->sc_ah; 546 547 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 548 &ec, ath9k_eeprom_request_cb); 549 if (err < 0) { 550 ath_err(ath9k_hw_common(ah), 551 "EEPROM request failed\n"); 552 return err; 553 } 554 555 wait_for_completion(&ec.complete); 556 557 if (!ah->eeprom_blob) { 558 ath_err(ath9k_hw_common(ah), 559 "Unable to load EEPROM file %s\n", name); 560 return -EINVAL; 561 } 562 563 return 0; 564 } 565 566 static void ath9k_eeprom_release(struct ath_softc *sc) 567 { 568 release_firmware(sc->sc_ah->eeprom_blob); 569 } 570 571 static int ath9k_init_platform(struct ath_softc *sc) 572 { 573 struct ath9k_platform_data *pdata = sc->dev->platform_data; 574 struct ath_hw *ah = sc->sc_ah; 575 struct ath_common *common = ath9k_hw_common(ah); 576 int ret; 577 578 if (!pdata) 579 return 0; 580 581 if (!pdata->use_eeprom) { 582 ah->ah_flags &= ~AH_USE_EEPROM; 583 ah->gpio_mask = pdata->gpio_mask; 584 ah->gpio_val = pdata->gpio_val; 585 ah->led_pin = pdata->led_pin; 586 ah->is_clk_25mhz = pdata->is_clk_25mhz; 587 ah->get_mac_revision = pdata->get_mac_revision; 588 ah->external_reset = pdata->external_reset; 589 ah->disable_2ghz = pdata->disable_2ghz; 590 ah->disable_5ghz = pdata->disable_5ghz; 591 592 if (!pdata->endian_check) 593 ah->ah_flags |= AH_NO_EEP_SWAP; 594 } 595 596 if (pdata->eeprom_name) { 597 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 598 if (ret) 599 return ret; 600 } 601 602 if (pdata->led_active_high) 603 ah->config.led_active_high = true; 604 605 if (pdata->tx_gain_buffalo) 606 ah->config.tx_gain_buffalo = true; 607 608 if (pdata->macaddr) 609 ether_addr_copy(common->macaddr, pdata->macaddr); 610 611 return 0; 612 } 613 614 static int ath9k_of_init(struct ath_softc *sc) 615 { 616 struct device_node *np = sc->dev->of_node; 617 struct ath_hw *ah = sc->sc_ah; 618 struct ath_common *common = ath9k_hw_common(ah); 619 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type; 620 const char *mac; 621 char eeprom_name[100]; 622 int ret; 623 624 if (!of_device_is_available(np)) 625 return 0; 626 627 ath_dbg(common, CONFIG, "parsing configuration from OF node\n"); 628 629 if (of_property_read_bool(np, "qca,no-eeprom")) { 630 /* ath9k-eeprom-<bus>-<id>.bin */ 631 scnprintf(eeprom_name, sizeof(eeprom_name), 632 "ath9k-eeprom-%s-%s.bin", 633 ath_bus_type_to_string(bus_type), dev_name(ah->dev)); 634 635 ret = ath9k_eeprom_request(sc, eeprom_name); 636 if (ret) 637 return ret; 638 } 639 640 mac = of_get_mac_address(np); 641 if (mac) 642 ether_addr_copy(common->macaddr, mac); 643 644 ah->ah_flags &= ~AH_USE_EEPROM; 645 ah->ah_flags |= AH_NO_EEP_SWAP; 646 647 return 0; 648 } 649 650 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 651 const struct ath_bus_ops *bus_ops) 652 { 653 struct ath_hw *ah = NULL; 654 struct ath9k_hw_capabilities *pCap; 655 struct ath_common *common; 656 int ret = 0, i; 657 int csz = 0; 658 659 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 660 if (!ah) 661 return -ENOMEM; 662 663 ah->dev = sc->dev; 664 ah->hw = sc->hw; 665 ah->hw_version.devid = devid; 666 ah->ah_flags |= AH_USE_EEPROM; 667 ah->led_pin = -1; 668 ah->reg_ops.read = ath9k_ioread32; 669 ah->reg_ops.multi_read = ath9k_multi_ioread32; 670 ah->reg_ops.write = ath9k_iowrite32; 671 ah->reg_ops.rmw = ath9k_reg_rmw; 672 pCap = &ah->caps; 673 674 common = ath9k_hw_common(ah); 675 676 /* Will be cleared in ath9k_start() */ 677 set_bit(ATH_OP_INVALID, &common->op_flags); 678 sc->airtime_flags = (AIRTIME_USE_TX | AIRTIME_USE_RX | 679 AIRTIME_USE_NEW_QUEUES); 680 681 sc->sc_ah = ah; 682 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 683 sc->tx99_power = MAX_RATE_POWER + 1; 684 init_waitqueue_head(&sc->tx_wait); 685 sc->cur_chan = &sc->chanctx[0]; 686 if (!ath9k_is_chanctx_enabled()) 687 sc->cur_chan->hw_queue_base = 0; 688 689 common->ops = &ah->reg_ops; 690 common->bus_ops = bus_ops; 691 common->ps_ops = &ath9k_ps_ops; 692 common->ah = ah; 693 common->hw = sc->hw; 694 common->priv = sc; 695 common->debug_mask = ath9k_debug; 696 common->btcoex_enabled = ath9k_btcoex_enable == 1; 697 common->disable_ani = false; 698 699 /* 700 * Platform quirks. 701 */ 702 ath9k_init_pcoem_platform(sc); 703 704 ret = ath9k_init_platform(sc); 705 if (ret) 706 return ret; 707 708 ret = ath9k_of_init(sc); 709 if (ret) 710 return ret; 711 712 if (ath9k_led_active_high != -1) 713 ah->config.led_active_high = ath9k_led_active_high == 1; 714 715 /* 716 * Enable WLAN/BT RX Antenna diversity only when: 717 * 718 * - BTCOEX is disabled. 719 * - the user manually requests the feature. 720 * - the HW cap is set using the platform data. 721 */ 722 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 723 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 724 common->bt_ant_diversity = 1; 725 726 spin_lock_init(&common->cc_lock); 727 spin_lock_init(&sc->intr_lock); 728 spin_lock_init(&sc->sc_serial_rw); 729 spin_lock_init(&sc->sc_pm_lock); 730 spin_lock_init(&sc->chan_lock); 731 mutex_init(&sc->mutex); 732 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 733 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 734 (unsigned long)sc); 735 736 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0); 737 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 738 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 739 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 740 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work); 741 742 ath9k_init_channel_context(sc); 743 744 /* 745 * Cache line size is used to size and align various 746 * structures used to communicate with the hardware. 747 */ 748 ath_read_cachesize(common, &csz); 749 common->cachelsz = csz << 2; /* convert to bytes */ 750 751 /* Initializes the hardware for all supported chipsets */ 752 ret = ath9k_hw_init(ah); 753 if (ret) 754 goto err_hw; 755 756 ret = ath9k_init_queues(sc); 757 if (ret) 758 goto err_queues; 759 760 ret = ath9k_init_btcoex(sc); 761 if (ret) 762 goto err_btcoex; 763 764 ret = ath9k_cmn_init_channels_rates(common); 765 if (ret) 766 goto err_btcoex; 767 768 ret = ath9k_init_p2p(sc); 769 if (ret) 770 goto err_btcoex; 771 772 ath9k_cmn_init_crypto(sc->sc_ah); 773 ath9k_init_misc(sc); 774 ath_chanctx_init(sc); 775 ath9k_offchannel_init(sc); 776 777 if (common->bus_ops->aspm_init) 778 common->bus_ops->aspm_init(common); 779 780 return 0; 781 782 err_btcoex: 783 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 784 if (ATH_TXQ_SETUP(sc, i)) 785 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 786 err_queues: 787 ath9k_hw_deinit(ah); 788 err_hw: 789 ath9k_eeprom_release(sc); 790 dev_kfree_skb_any(sc->tx99_skb); 791 return ret; 792 } 793 794 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 795 { 796 struct ieee80211_supported_band *sband; 797 struct ieee80211_channel *chan; 798 struct ath_hw *ah = sc->sc_ah; 799 struct ath_common *common = ath9k_hw_common(ah); 800 struct cfg80211_chan_def chandef; 801 int i; 802 803 sband = &common->sbands[band]; 804 for (i = 0; i < sband->n_channels; i++) { 805 chan = &sband->channels[i]; 806 ah->curchan = &ah->channels[chan->hw_value]; 807 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 808 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 809 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 810 } 811 } 812 813 static void ath9k_init_txpower_limits(struct ath_softc *sc) 814 { 815 struct ath_hw *ah = sc->sc_ah; 816 struct ath9k_channel *curchan = ah->curchan; 817 818 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 819 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ); 820 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 821 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ); 822 823 ah->curchan = curchan; 824 } 825 826 static const struct ieee80211_iface_limit if_limits[] = { 827 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 828 { .max = 8, .types = 829 #ifdef CONFIG_MAC80211_MESH 830 BIT(NL80211_IFTYPE_MESH_POINT) | 831 #endif 832 BIT(NL80211_IFTYPE_AP) }, 833 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 834 BIT(NL80211_IFTYPE_P2P_GO) }, 835 }; 836 837 #ifdef CONFIG_WIRELESS_WDS 838 static const struct ieee80211_iface_limit wds_limits[] = { 839 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, 840 }; 841 #endif 842 843 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 844 845 static const struct ieee80211_iface_limit if_limits_multi[] = { 846 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | 847 BIT(NL80211_IFTYPE_AP) | 848 BIT(NL80211_IFTYPE_P2P_CLIENT) | 849 BIT(NL80211_IFTYPE_P2P_GO) }, 850 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, 851 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) }, 852 }; 853 854 static const struct ieee80211_iface_combination if_comb_multi[] = { 855 { 856 .limits = if_limits_multi, 857 .n_limits = ARRAY_SIZE(if_limits_multi), 858 .max_interfaces = 3, 859 .num_different_channels = 2, 860 .beacon_int_infra_match = true, 861 }, 862 }; 863 864 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 865 866 static const struct ieee80211_iface_combination if_comb[] = { 867 { 868 .limits = if_limits, 869 .n_limits = ARRAY_SIZE(if_limits), 870 .max_interfaces = 2048, 871 .num_different_channels = 1, 872 .beacon_int_infra_match = true, 873 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 874 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 875 BIT(NL80211_CHAN_WIDTH_20) | 876 BIT(NL80211_CHAN_WIDTH_40), 877 #endif 878 }, 879 #ifdef CONFIG_WIRELESS_WDS 880 { 881 .limits = wds_limits, 882 .n_limits = ARRAY_SIZE(wds_limits), 883 .max_interfaces = 2048, 884 .num_different_channels = 1, 885 .beacon_int_infra_match = true, 886 }, 887 #endif 888 }; 889 890 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 891 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 892 { 893 struct ath_hw *ah = sc->sc_ah; 894 struct ath_common *common = ath9k_hw_common(ah); 895 896 if (!ath9k_is_chanctx_enabled()) 897 return; 898 899 ieee80211_hw_set(hw, QUEUE_CONTROL); 900 hw->queues = ATH9K_NUM_TX_QUEUES; 901 hw->offchannel_tx_hw_queue = hw->queues - 1; 902 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); 903 hw->wiphy->iface_combinations = if_comb_multi; 904 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); 905 hw->wiphy->max_scan_ssids = 255; 906 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 907 hw->wiphy->max_remain_on_channel_duration = 10000; 908 hw->chanctx_data_size = sizeof(void *); 909 hw->extra_beacon_tailroom = 910 sizeof(struct ieee80211_p2p_noa_attr) + 9; 911 912 ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); 913 } 914 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 915 916 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 917 { 918 struct ath_hw *ah = sc->sc_ah; 919 struct ath_common *common = ath9k_hw_common(ah); 920 921 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); 922 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); 923 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 924 ieee80211_hw_set(hw, SPECTRUM_MGMT); 925 ieee80211_hw_set(hw, PS_NULLFUNC_STACK); 926 ieee80211_hw_set(hw, SIGNAL_DBM); 927 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 928 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); 929 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 930 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS); 931 932 if (ath9k_ps_enable) 933 ieee80211_hw_set(hw, SUPPORTS_PS); 934 935 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 936 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 937 938 if (AR_SREV_9280_20_OR_LATER(ah)) 939 hw->radiotap_mcs_details |= 940 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 941 } 942 943 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 944 ieee80211_hw_set(hw, MFP_CAPABLE); 945 946 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | 947 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | 948 NL80211_FEATURE_P2P_GO_CTWIN; 949 950 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) { 951 hw->wiphy->interface_modes = 952 BIT(NL80211_IFTYPE_P2P_GO) | 953 BIT(NL80211_IFTYPE_P2P_CLIENT) | 954 BIT(NL80211_IFTYPE_AP) | 955 BIT(NL80211_IFTYPE_STATION) | 956 BIT(NL80211_IFTYPE_ADHOC) | 957 BIT(NL80211_IFTYPE_MESH_POINT) | 958 #ifdef CONFIG_WIRELESS_WDS 959 BIT(NL80211_IFTYPE_WDS) | 960 #endif 961 BIT(NL80211_IFTYPE_OCB); 962 963 if (ath9k_is_chanctx_enabled()) 964 hw->wiphy->interface_modes |= 965 BIT(NL80211_IFTYPE_P2P_DEVICE); 966 967 hw->wiphy->iface_combinations = if_comb; 968 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 969 } 970 971 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 972 973 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 974 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 975 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 976 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 977 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 978 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 979 980 hw->queues = 4; 981 hw->max_rates = 4; 982 hw->max_listen_interval = 10; 983 hw->max_rate_tries = 10; 984 hw->sta_data_size = sizeof(struct ath_node); 985 hw->vif_data_size = sizeof(struct ath_vif); 986 hw->txq_data_size = sizeof(struct ath_atx_tid); 987 hw->extra_tx_headroom = 4; 988 989 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 990 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 991 992 /* single chain devices with rx diversity */ 993 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 994 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 995 996 sc->ant_rx = hw->wiphy->available_antennas_rx; 997 sc->ant_tx = hw->wiphy->available_antennas_tx; 998 999 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 1000 hw->wiphy->bands[NL80211_BAND_2GHZ] = 1001 &common->sbands[NL80211_BAND_2GHZ]; 1002 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 1003 hw->wiphy->bands[NL80211_BAND_5GHZ] = 1004 &common->sbands[NL80211_BAND_5GHZ]; 1005 1006 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1007 ath9k_set_mcc_capab(sc, hw); 1008 #endif 1009 ath9k_init_wow(hw); 1010 ath9k_cmn_reload_chainmask(ah); 1011 1012 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 1013 1014 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 1015 } 1016 1017 int ath9k_init_device(u16 devid, struct ath_softc *sc, 1018 const struct ath_bus_ops *bus_ops) 1019 { 1020 struct ieee80211_hw *hw = sc->hw; 1021 struct ath_common *common; 1022 struct ath_hw *ah; 1023 int error = 0; 1024 struct ath_regulatory *reg; 1025 1026 /* Bring up device */ 1027 error = ath9k_init_softc(devid, sc, bus_ops); 1028 if (error) 1029 return error; 1030 1031 ah = sc->sc_ah; 1032 common = ath9k_hw_common(ah); 1033 ath9k_set_hw_capab(sc, hw); 1034 1035 /* Initialize regulatory */ 1036 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 1037 ath9k_reg_notifier); 1038 if (error) 1039 goto deinit; 1040 1041 reg = &common->regulatory; 1042 1043 /* Setup TX DMA */ 1044 error = ath_tx_init(sc, ATH_TXBUF); 1045 if (error != 0) 1046 goto deinit; 1047 1048 /* Setup RX DMA */ 1049 error = ath_rx_init(sc, ATH_RXBUF); 1050 if (error != 0) 1051 goto deinit; 1052 1053 ath9k_init_txpower_limits(sc); 1054 1055 #ifdef CONFIG_MAC80211_LEDS 1056 /* must be initialized before ieee80211_register_hw */ 1057 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 1058 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 1059 ARRAY_SIZE(ath9k_tpt_blink)); 1060 #endif 1061 1062 /* Register with mac80211 */ 1063 error = ieee80211_register_hw(hw); 1064 if (error) 1065 goto rx_cleanup; 1066 1067 error = ath9k_init_debug(ah); 1068 if (error) { 1069 ath_err(common, "Unable to create debugfs files\n"); 1070 goto unregister; 1071 } 1072 1073 /* Handle world regulatory */ 1074 if (!ath_is_world_regd(reg)) { 1075 error = regulatory_hint(hw->wiphy, reg->alpha2); 1076 if (error) 1077 goto debug_cleanup; 1078 } 1079 1080 ath_init_leds(sc); 1081 ath_start_rfkill_poll(sc); 1082 1083 return 0; 1084 1085 debug_cleanup: 1086 ath9k_deinit_debug(sc); 1087 unregister: 1088 ieee80211_unregister_hw(hw); 1089 rx_cleanup: 1090 ath_rx_cleanup(sc); 1091 deinit: 1092 ath9k_deinit_softc(sc); 1093 return error; 1094 } 1095 1096 /*****************************/ 1097 /* De-Initialization */ 1098 /*****************************/ 1099 1100 static void ath9k_deinit_softc(struct ath_softc *sc) 1101 { 1102 int i = 0; 1103 1104 ath9k_deinit_p2p(sc); 1105 ath9k_deinit_btcoex(sc); 1106 1107 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1108 if (ATH_TXQ_SETUP(sc, i)) 1109 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1110 1111 del_timer_sync(&sc->sleep_timer); 1112 ath9k_hw_deinit(sc->sc_ah); 1113 if (sc->dfs_detector != NULL) 1114 sc->dfs_detector->exit(sc->dfs_detector); 1115 1116 ath9k_eeprom_release(sc); 1117 } 1118 1119 void ath9k_deinit_device(struct ath_softc *sc) 1120 { 1121 struct ieee80211_hw *hw = sc->hw; 1122 1123 ath9k_ps_wakeup(sc); 1124 1125 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1126 ath_deinit_leds(sc); 1127 1128 ath9k_ps_restore(sc); 1129 1130 ath9k_deinit_debug(sc); 1131 ath9k_deinit_wow(hw); 1132 ieee80211_unregister_hw(hw); 1133 ath_rx_cleanup(sc); 1134 ath9k_deinit_softc(sc); 1135 } 1136 1137 /************************/ 1138 /* Module Hooks */ 1139 /************************/ 1140 1141 static int __init ath9k_init(void) 1142 { 1143 int error; 1144 1145 error = ath_pci_init(); 1146 if (error < 0) { 1147 pr_err("No PCI devices found, driver not installed\n"); 1148 error = -ENODEV; 1149 goto err_out; 1150 } 1151 1152 error = ath_ahb_init(); 1153 if (error < 0) { 1154 error = -ENODEV; 1155 goto err_pci_exit; 1156 } 1157 1158 dmi_check_system(ath9k_quirks); 1159 1160 return 0; 1161 1162 err_pci_exit: 1163 ath_pci_exit(); 1164 err_out: 1165 return error; 1166 } 1167 module_init(ath9k_init); 1168 1169 static void __exit ath9k_exit(void) 1170 { 1171 is_ath9k_unloaded = true; 1172 ath_ahb_exit(); 1173 ath_pci_exit(); 1174 pr_info("%s: Driver unloaded\n", dev_info); 1175 } 1176 module_exit(ath9k_exit); 1177