1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 65 66 int ath9k_use_chanctx; 67 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 68 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 69 70 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 71 72 bool is_ath9k_unloaded; 73 74 #ifdef CONFIG_MAC80211_LEDS 75 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 76 { .throughput = 0 * 1024, .blink_time = 334 }, 77 { .throughput = 1 * 1024, .blink_time = 260 }, 78 { .throughput = 5 * 1024, .blink_time = 220 }, 79 { .throughput = 10 * 1024, .blink_time = 190 }, 80 { .throughput = 20 * 1024, .blink_time = 170 }, 81 { .throughput = 50 * 1024, .blink_time = 150 }, 82 { .throughput = 70 * 1024, .blink_time = 130 }, 83 { .throughput = 100 * 1024, .blink_time = 110 }, 84 { .throughput = 200 * 1024, .blink_time = 80 }, 85 { .throughput = 300 * 1024, .blink_time = 50 }, 86 }; 87 #endif 88 89 static void ath9k_deinit_softc(struct ath_softc *sc); 90 91 /* 92 * Read and write, they both share the same lock. We do this to serialize 93 * reads and writes on Atheros 802.11n PCI devices only. This is required 94 * as the FIFO on these devices can only accept sanely 2 requests. 95 */ 96 97 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 98 { 99 struct ath_hw *ah = (struct ath_hw *) hw_priv; 100 struct ath_common *common = ath9k_hw_common(ah); 101 struct ath_softc *sc = (struct ath_softc *) common->priv; 102 103 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 104 unsigned long flags; 105 spin_lock_irqsave(&sc->sc_serial_rw, flags); 106 iowrite32(val, sc->mem + reg_offset); 107 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 108 } else 109 iowrite32(val, sc->mem + reg_offset); 110 } 111 112 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 113 { 114 struct ath_hw *ah = (struct ath_hw *) hw_priv; 115 struct ath_common *common = ath9k_hw_common(ah); 116 struct ath_softc *sc = (struct ath_softc *) common->priv; 117 u32 val; 118 119 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 120 unsigned long flags; 121 spin_lock_irqsave(&sc->sc_serial_rw, flags); 122 val = ioread32(sc->mem + reg_offset); 123 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 124 } else 125 val = ioread32(sc->mem + reg_offset); 126 return val; 127 } 128 129 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 130 u32 set, u32 clr) 131 { 132 u32 val; 133 134 val = ioread32(sc->mem + reg_offset); 135 val &= ~clr; 136 val |= set; 137 iowrite32(val, sc->mem + reg_offset); 138 139 return val; 140 } 141 142 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 143 { 144 struct ath_hw *ah = (struct ath_hw *) hw_priv; 145 struct ath_common *common = ath9k_hw_common(ah); 146 struct ath_softc *sc = (struct ath_softc *) common->priv; 147 unsigned long uninitialized_var(flags); 148 u32 val; 149 150 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 151 spin_lock_irqsave(&sc->sc_serial_rw, flags); 152 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 153 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 154 } else 155 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 156 157 return val; 158 } 159 160 /**************************/ 161 /* Initialization */ 162 /**************************/ 163 164 static void ath9k_reg_notifier(struct wiphy *wiphy, 165 struct regulatory_request *request) 166 { 167 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 168 struct ath_softc *sc = hw->priv; 169 struct ath_hw *ah = sc->sc_ah; 170 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 171 172 ath_reg_notifier_apply(wiphy, request, reg); 173 174 /* Set tx power */ 175 if (ah->curchan) { 176 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; 177 ath9k_ps_wakeup(sc); 178 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 179 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 180 /* synchronize DFS detector if regulatory domain changed */ 181 if (sc->dfs_detector != NULL) 182 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 183 request->dfs_region); 184 ath9k_ps_restore(sc); 185 } 186 } 187 188 /* 189 * This function will allocate both the DMA descriptor structure, and the 190 * buffers it contains. These are used to contain the descriptors used 191 * by the system. 192 */ 193 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 194 struct list_head *head, const char *name, 195 int nbuf, int ndesc, bool is_tx) 196 { 197 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 198 u8 *ds; 199 int i, bsize, desc_len; 200 201 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 202 name, nbuf, ndesc); 203 204 INIT_LIST_HEAD(head); 205 206 if (is_tx) 207 desc_len = sc->sc_ah->caps.tx_desc_len; 208 else 209 desc_len = sizeof(struct ath_desc); 210 211 /* ath_desc must be a multiple of DWORDs */ 212 if ((desc_len % 4) != 0) { 213 ath_err(common, "ath_desc not DWORD aligned\n"); 214 BUG_ON((desc_len % 4) != 0); 215 return -ENOMEM; 216 } 217 218 dd->dd_desc_len = desc_len * nbuf * ndesc; 219 220 /* 221 * Need additional DMA memory because we can't use 222 * descriptors that cross the 4K page boundary. Assume 223 * one skipped descriptor per 4K page. 224 */ 225 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 226 u32 ndesc_skipped = 227 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 228 u32 dma_len; 229 230 while (ndesc_skipped) { 231 dma_len = ndesc_skipped * desc_len; 232 dd->dd_desc_len += dma_len; 233 234 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 235 } 236 } 237 238 /* allocate descriptors */ 239 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 240 &dd->dd_desc_paddr, GFP_KERNEL); 241 if (!dd->dd_desc) 242 return -ENOMEM; 243 244 ds = (u8 *) dd->dd_desc; 245 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 246 name, ds, (u32) dd->dd_desc_len, 247 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 248 249 /* allocate buffers */ 250 if (is_tx) { 251 struct ath_buf *bf; 252 253 bsize = sizeof(struct ath_buf) * nbuf; 254 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 255 if (!bf) 256 return -ENOMEM; 257 258 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 259 bf->bf_desc = ds; 260 bf->bf_daddr = DS2PHYS(dd, ds); 261 262 if (!(sc->sc_ah->caps.hw_caps & 263 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 264 /* 265 * Skip descriptor addresses which can cause 4KB 266 * boundary crossing (addr + length) with a 32 dword 267 * descriptor fetch. 268 */ 269 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 270 BUG_ON((caddr_t) bf->bf_desc >= 271 ((caddr_t) dd->dd_desc + 272 dd->dd_desc_len)); 273 274 ds += (desc_len * ndesc); 275 bf->bf_desc = ds; 276 bf->bf_daddr = DS2PHYS(dd, ds); 277 } 278 } 279 list_add_tail(&bf->list, head); 280 } 281 } else { 282 struct ath_rxbuf *bf; 283 284 bsize = sizeof(struct ath_rxbuf) * nbuf; 285 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 286 if (!bf) 287 return -ENOMEM; 288 289 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 290 bf->bf_desc = ds; 291 bf->bf_daddr = DS2PHYS(dd, ds); 292 293 if (!(sc->sc_ah->caps.hw_caps & 294 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 295 /* 296 * Skip descriptor addresses which can cause 4KB 297 * boundary crossing (addr + length) with a 32 dword 298 * descriptor fetch. 299 */ 300 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 301 BUG_ON((caddr_t) bf->bf_desc >= 302 ((caddr_t) dd->dd_desc + 303 dd->dd_desc_len)); 304 305 ds += (desc_len * ndesc); 306 bf->bf_desc = ds; 307 bf->bf_daddr = DS2PHYS(dd, ds); 308 } 309 } 310 list_add_tail(&bf->list, head); 311 } 312 } 313 return 0; 314 } 315 316 static int ath9k_init_queues(struct ath_softc *sc) 317 { 318 int i = 0; 319 320 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 321 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 322 ath_cabq_update(sc); 323 324 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 325 326 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 327 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 328 sc->tx.txq_map[i]->mac80211_qnum = i; 329 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 330 } 331 return 0; 332 } 333 334 static void ath9k_init_misc(struct ath_softc *sc) 335 { 336 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 337 int i = 0; 338 339 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 340 341 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 342 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 343 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 344 345 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 346 sc->beacon.bslot[i] = NULL; 347 348 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 349 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 350 351 sc->spec_config.enabled = 0; 352 sc->spec_config.short_repeat = true; 353 sc->spec_config.count = 8; 354 sc->spec_config.endless = false; 355 sc->spec_config.period = 0xFF; 356 sc->spec_config.fft_period = 0xF; 357 } 358 359 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 360 { 361 struct ath_hw *ah = sc->sc_ah; 362 struct ath9k_hw_capabilities *pCap = &ah->caps; 363 struct ath_common *common = ath9k_hw_common(ah); 364 365 if (common->bus_ops->ath_bus_type != ATH_PCI) 366 return; 367 368 if (sc->driver_data & (ATH9K_PCI_CUS198 | 369 ATH9K_PCI_CUS230)) { 370 ah->config.xlna_gpio = 9; 371 ah->config.xatten_margin_cfg = true; 372 ah->config.alt_mingainidx = true; 373 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 374 sc->ant_comb.low_rssi_thresh = 20; 375 sc->ant_comb.fast_div_bias = 3; 376 377 ath_info(common, "Set parameters for %s\n", 378 (sc->driver_data & ATH9K_PCI_CUS198) ? 379 "CUS198" : "CUS230"); 380 } 381 382 if (sc->driver_data & ATH9K_PCI_CUS217) 383 ath_info(common, "CUS217 card detected\n"); 384 385 if (sc->driver_data & ATH9K_PCI_CUS252) 386 ath_info(common, "CUS252 card detected\n"); 387 388 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 389 ath_info(common, "WB335 1-ANT card detected\n"); 390 391 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 392 ath_info(common, "WB335 2-ANT card detected\n"); 393 394 if (sc->driver_data & ATH9K_PCI_KILLER) 395 ath_info(common, "Killer Wireless card detected\n"); 396 397 /* 398 * Some WB335 cards do not support antenna diversity. Since 399 * we use a hardcoded value for AR9565 instead of using the 400 * EEPROM/OTP data, remove the combining feature from 401 * the HW capabilities bitmap. 402 */ 403 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 404 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 405 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 406 } 407 408 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 409 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 410 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 411 } 412 413 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 414 ah->config.pcie_waen = 0x0040473b; 415 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 416 } 417 418 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 419 ah->config.no_pll_pwrsave = true; 420 ath_info(common, "Disable PLL PowerSave\n"); 421 } 422 } 423 424 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 425 void *ctx) 426 { 427 struct ath9k_eeprom_ctx *ec = ctx; 428 429 if (eeprom_blob) 430 ec->ah->eeprom_blob = eeprom_blob; 431 432 complete(&ec->complete); 433 } 434 435 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 436 { 437 struct ath9k_eeprom_ctx ec; 438 struct ath_hw *ah = ah = sc->sc_ah; 439 int err; 440 441 /* try to load the EEPROM content asynchronously */ 442 init_completion(&ec.complete); 443 ec.ah = sc->sc_ah; 444 445 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 446 &ec, ath9k_eeprom_request_cb); 447 if (err < 0) { 448 ath_err(ath9k_hw_common(ah), 449 "EEPROM request failed\n"); 450 return err; 451 } 452 453 wait_for_completion(&ec.complete); 454 455 if (!ah->eeprom_blob) { 456 ath_err(ath9k_hw_common(ah), 457 "Unable to load EEPROM file %s\n", name); 458 return -EINVAL; 459 } 460 461 return 0; 462 } 463 464 static void ath9k_eeprom_release(struct ath_softc *sc) 465 { 466 release_firmware(sc->sc_ah->eeprom_blob); 467 } 468 469 static int ath9k_init_soc_platform(struct ath_softc *sc) 470 { 471 struct ath9k_platform_data *pdata = sc->dev->platform_data; 472 struct ath_hw *ah = sc->sc_ah; 473 int ret = 0; 474 475 if (!pdata) 476 return 0; 477 478 if (pdata->eeprom_name) { 479 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 480 if (ret) 481 return ret; 482 } 483 484 if (pdata->tx_gain_buffalo) 485 ah->config.tx_gain_buffalo = true; 486 487 return ret; 488 } 489 490 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 491 const struct ath_bus_ops *bus_ops) 492 { 493 struct ath9k_platform_data *pdata = sc->dev->platform_data; 494 struct ath_hw *ah = NULL; 495 struct ath9k_hw_capabilities *pCap; 496 struct ath_common *common; 497 int ret = 0, i; 498 int csz = 0; 499 500 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 501 if (!ah) 502 return -ENOMEM; 503 504 ah->dev = sc->dev; 505 ah->hw = sc->hw; 506 ah->hw_version.devid = devid; 507 ah->reg_ops.read = ath9k_ioread32; 508 ah->reg_ops.write = ath9k_iowrite32; 509 ah->reg_ops.rmw = ath9k_reg_rmw; 510 sc->sc_ah = ah; 511 pCap = &ah->caps; 512 513 common = ath9k_hw_common(ah); 514 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 515 sc->tx99_power = MAX_RATE_POWER + 1; 516 init_waitqueue_head(&sc->tx_wait); 517 sc->cur_chan = &sc->chanctx[0]; 518 if (!ath9k_is_chanctx_enabled()) 519 sc->cur_chan->hw_queue_base = 0; 520 521 if (!pdata || pdata->use_eeprom) { 522 ah->ah_flags |= AH_USE_EEPROM; 523 sc->sc_ah->led_pin = -1; 524 } else { 525 sc->sc_ah->gpio_mask = pdata->gpio_mask; 526 sc->sc_ah->gpio_val = pdata->gpio_val; 527 sc->sc_ah->led_pin = pdata->led_pin; 528 ah->is_clk_25mhz = pdata->is_clk_25mhz; 529 ah->get_mac_revision = pdata->get_mac_revision; 530 ah->external_reset = pdata->external_reset; 531 } 532 533 common->ops = &ah->reg_ops; 534 common->bus_ops = bus_ops; 535 common->ah = ah; 536 common->hw = sc->hw; 537 common->priv = sc; 538 common->debug_mask = ath9k_debug; 539 common->btcoex_enabled = ath9k_btcoex_enable == 1; 540 common->disable_ani = false; 541 542 /* 543 * Platform quirks. 544 */ 545 ath9k_init_pcoem_platform(sc); 546 547 ret = ath9k_init_soc_platform(sc); 548 if (ret) 549 return ret; 550 551 /* 552 * Enable WLAN/BT RX Antenna diversity only when: 553 * 554 * - BTCOEX is disabled. 555 * - the user manually requests the feature. 556 * - the HW cap is set using the platform data. 557 */ 558 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 559 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 560 common->bt_ant_diversity = 1; 561 562 spin_lock_init(&common->cc_lock); 563 spin_lock_init(&sc->sc_serial_rw); 564 spin_lock_init(&sc->sc_pm_lock); 565 spin_lock_init(&sc->chan_lock); 566 mutex_init(&sc->mutex); 567 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 568 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 569 (unsigned long)sc); 570 571 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 572 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 573 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 574 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 575 576 ath9k_init_channel_context(sc); 577 578 /* 579 * Cache line size is used to size and align various 580 * structures used to communicate with the hardware. 581 */ 582 ath_read_cachesize(common, &csz); 583 common->cachelsz = csz << 2; /* convert to bytes */ 584 585 /* Initializes the hardware for all supported chipsets */ 586 ret = ath9k_hw_init(ah); 587 if (ret) 588 goto err_hw; 589 590 if (pdata && pdata->macaddr) 591 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 592 593 ret = ath9k_init_queues(sc); 594 if (ret) 595 goto err_queues; 596 597 ret = ath9k_init_btcoex(sc); 598 if (ret) 599 goto err_btcoex; 600 601 ret = ath9k_cmn_init_channels_rates(common); 602 if (ret) 603 goto err_btcoex; 604 605 ret = ath9k_init_p2p(sc); 606 if (ret) 607 goto err_btcoex; 608 609 ath9k_cmn_init_crypto(sc->sc_ah); 610 ath9k_init_misc(sc); 611 ath_fill_led_pin(sc); 612 ath_chanctx_init(sc); 613 ath9k_offchannel_init(sc); 614 615 if (common->bus_ops->aspm_init) 616 common->bus_ops->aspm_init(common); 617 618 return 0; 619 620 err_btcoex: 621 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 622 if (ATH_TXQ_SETUP(sc, i)) 623 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 624 err_queues: 625 ath9k_hw_deinit(ah); 626 err_hw: 627 ath9k_eeprom_release(sc); 628 dev_kfree_skb_any(sc->tx99_skb); 629 return ret; 630 } 631 632 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 633 { 634 struct ieee80211_supported_band *sband; 635 struct ieee80211_channel *chan; 636 struct ath_hw *ah = sc->sc_ah; 637 struct ath_common *common = ath9k_hw_common(ah); 638 struct cfg80211_chan_def chandef; 639 int i; 640 641 sband = &common->sbands[band]; 642 for (i = 0; i < sband->n_channels; i++) { 643 chan = &sband->channels[i]; 644 ah->curchan = &ah->channels[chan->hw_value]; 645 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 646 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 647 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 648 } 649 } 650 651 static void ath9k_init_txpower_limits(struct ath_softc *sc) 652 { 653 struct ath_hw *ah = sc->sc_ah; 654 struct ath9k_channel *curchan = ah->curchan; 655 656 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 657 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 658 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 659 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 660 661 ah->curchan = curchan; 662 } 663 664 static const struct ieee80211_iface_limit if_limits[] = { 665 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 666 { .max = 8, .types = 667 #ifdef CONFIG_MAC80211_MESH 668 BIT(NL80211_IFTYPE_MESH_POINT) | 669 #endif 670 BIT(NL80211_IFTYPE_AP) }, 671 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 672 BIT(NL80211_IFTYPE_P2P_GO) }, 673 }; 674 675 static const struct ieee80211_iface_limit wds_limits[] = { 676 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, 677 }; 678 679 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 680 681 static const struct ieee80211_iface_limit if_limits_multi[] = { 682 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | 683 BIT(NL80211_IFTYPE_AP) | 684 BIT(NL80211_IFTYPE_P2P_CLIENT) | 685 BIT(NL80211_IFTYPE_P2P_GO) }, 686 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, 687 }; 688 689 static const struct ieee80211_iface_combination if_comb_multi[] = { 690 { 691 .limits = if_limits_multi, 692 .n_limits = ARRAY_SIZE(if_limits_multi), 693 .max_interfaces = 2, 694 .num_different_channels = 2, 695 .beacon_int_infra_match = true, 696 }, 697 }; 698 699 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 700 701 static const struct ieee80211_iface_limit if_dfs_limits[] = { 702 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 703 #ifdef CONFIG_MAC80211_MESH 704 BIT(NL80211_IFTYPE_MESH_POINT) | 705 #endif 706 BIT(NL80211_IFTYPE_ADHOC) }, 707 }; 708 709 static const struct ieee80211_iface_combination if_comb[] = { 710 { 711 .limits = if_limits, 712 .n_limits = ARRAY_SIZE(if_limits), 713 .max_interfaces = 2048, 714 .num_different_channels = 1, 715 .beacon_int_infra_match = true, 716 }, 717 { 718 .limits = wds_limits, 719 .n_limits = ARRAY_SIZE(wds_limits), 720 .max_interfaces = 2048, 721 .num_different_channels = 1, 722 .beacon_int_infra_match = true, 723 }, 724 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 725 { 726 .limits = if_dfs_limits, 727 .n_limits = ARRAY_SIZE(if_dfs_limits), 728 .max_interfaces = 1, 729 .num_different_channels = 1, 730 .beacon_int_infra_match = true, 731 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 732 BIT(NL80211_CHAN_WIDTH_20), 733 } 734 #endif 735 }; 736 737 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 738 { 739 struct ath_hw *ah = sc->sc_ah; 740 struct ath_common *common = ath9k_hw_common(ah); 741 742 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 743 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 744 IEEE80211_HW_SIGNAL_DBM | 745 IEEE80211_HW_PS_NULLFUNC_STACK | 746 IEEE80211_HW_SPECTRUM_MGMT | 747 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 748 IEEE80211_HW_SUPPORTS_RC_TABLE | 749 IEEE80211_HW_QUEUE_CONTROL | 750 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 751 752 if (ath9k_ps_enable) 753 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 754 755 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 756 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 757 758 if (AR_SREV_9280_20_OR_LATER(ah)) 759 hw->radiotap_mcs_details |= 760 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 761 } 762 763 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 764 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 765 766 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | 767 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | 768 NL80211_FEATURE_P2P_GO_CTWIN; 769 770 if (!config_enabled(CONFIG_ATH9K_TX99)) { 771 hw->wiphy->interface_modes = 772 BIT(NL80211_IFTYPE_P2P_GO) | 773 BIT(NL80211_IFTYPE_P2P_CLIENT) | 774 BIT(NL80211_IFTYPE_AP) | 775 BIT(NL80211_IFTYPE_STATION) | 776 BIT(NL80211_IFTYPE_ADHOC) | 777 BIT(NL80211_IFTYPE_MESH_POINT) | 778 BIT(NL80211_IFTYPE_WDS); 779 780 hw->wiphy->iface_combinations = if_comb; 781 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 782 } 783 784 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 785 786 if (ath9k_is_chanctx_enabled()) { 787 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); 788 hw->wiphy->iface_combinations = if_comb_multi; 789 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); 790 hw->wiphy->max_scan_ssids = 255; 791 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 792 hw->wiphy->max_remain_on_channel_duration = 10000; 793 hw->chanctx_data_size = sizeof(void *); 794 hw->extra_beacon_tailroom = 795 sizeof(struct ieee80211_p2p_noa_attr) + 9; 796 797 ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); 798 } 799 800 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 801 802 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 803 804 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 805 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 806 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 807 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 808 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 809 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 810 811 /* allow 4 queues per channel context + 812 * 1 cab queue + 1 offchannel tx queue 813 */ 814 hw->queues = ATH9K_NUM_TX_QUEUES; 815 /* last queue for offchannel */ 816 hw->offchannel_tx_hw_queue = hw->queues - 1; 817 hw->max_rates = 4; 818 hw->max_listen_interval = 10; 819 hw->max_rate_tries = 10; 820 hw->sta_data_size = sizeof(struct ath_node); 821 hw->vif_data_size = sizeof(struct ath_vif); 822 823 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 824 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 825 826 /* single chain devices with rx diversity */ 827 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 828 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 829 830 sc->ant_rx = hw->wiphy->available_antennas_rx; 831 sc->ant_tx = hw->wiphy->available_antennas_tx; 832 833 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 834 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 835 &common->sbands[IEEE80211_BAND_2GHZ]; 836 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 837 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 838 &common->sbands[IEEE80211_BAND_5GHZ]; 839 840 ath9k_init_wow(hw); 841 ath9k_cmn_reload_chainmask(ah); 842 843 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 844 } 845 846 int ath9k_init_device(u16 devid, struct ath_softc *sc, 847 const struct ath_bus_ops *bus_ops) 848 { 849 struct ieee80211_hw *hw = sc->hw; 850 struct ath_common *common; 851 struct ath_hw *ah; 852 int error = 0; 853 struct ath_regulatory *reg; 854 855 /* Bring up device */ 856 error = ath9k_init_softc(devid, sc, bus_ops); 857 if (error) 858 return error; 859 860 ah = sc->sc_ah; 861 common = ath9k_hw_common(ah); 862 ath9k_set_hw_capab(sc, hw); 863 864 /* Will be cleared in ath9k_start() */ 865 set_bit(ATH_OP_INVALID, &common->op_flags); 866 867 /* Initialize regulatory */ 868 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 869 ath9k_reg_notifier); 870 if (error) 871 goto deinit; 872 873 reg = &common->regulatory; 874 875 /* Setup TX DMA */ 876 error = ath_tx_init(sc, ATH_TXBUF); 877 if (error != 0) 878 goto deinit; 879 880 /* Setup RX DMA */ 881 error = ath_rx_init(sc, ATH_RXBUF); 882 if (error != 0) 883 goto deinit; 884 885 ath9k_init_txpower_limits(sc); 886 887 #ifdef CONFIG_MAC80211_LEDS 888 /* must be initialized before ieee80211_register_hw */ 889 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 890 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 891 ARRAY_SIZE(ath9k_tpt_blink)); 892 #endif 893 894 /* Register with mac80211 */ 895 error = ieee80211_register_hw(hw); 896 if (error) 897 goto rx_cleanup; 898 899 error = ath9k_init_debug(ah); 900 if (error) { 901 ath_err(common, "Unable to create debugfs files\n"); 902 goto unregister; 903 } 904 905 /* Handle world regulatory */ 906 if (!ath_is_world_regd(reg)) { 907 error = regulatory_hint(hw->wiphy, reg->alpha2); 908 if (error) 909 goto debug_cleanup; 910 } 911 912 ath_init_leds(sc); 913 ath_start_rfkill_poll(sc); 914 915 return 0; 916 917 debug_cleanup: 918 ath9k_deinit_debug(sc); 919 unregister: 920 ieee80211_unregister_hw(hw); 921 rx_cleanup: 922 ath_rx_cleanup(sc); 923 deinit: 924 ath9k_deinit_softc(sc); 925 return error; 926 } 927 928 /*****************************/ 929 /* De-Initialization */ 930 /*****************************/ 931 932 static void ath9k_deinit_softc(struct ath_softc *sc) 933 { 934 int i = 0; 935 936 ath9k_deinit_p2p(sc); 937 ath9k_deinit_btcoex(sc); 938 939 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 940 if (ATH_TXQ_SETUP(sc, i)) 941 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 942 943 del_timer_sync(&sc->sleep_timer); 944 ath9k_hw_deinit(sc->sc_ah); 945 if (sc->dfs_detector != NULL) 946 sc->dfs_detector->exit(sc->dfs_detector); 947 948 ath9k_eeprom_release(sc); 949 } 950 951 void ath9k_deinit_device(struct ath_softc *sc) 952 { 953 struct ieee80211_hw *hw = sc->hw; 954 955 ath9k_ps_wakeup(sc); 956 957 wiphy_rfkill_stop_polling(sc->hw->wiphy); 958 ath_deinit_leds(sc); 959 960 ath9k_ps_restore(sc); 961 962 ath9k_deinit_debug(sc); 963 ieee80211_unregister_hw(hw); 964 ath_rx_cleanup(sc); 965 ath9k_deinit_softc(sc); 966 } 967 968 /************************/ 969 /* Module Hooks */ 970 /************************/ 971 972 static int __init ath9k_init(void) 973 { 974 int error; 975 976 error = ath_pci_init(); 977 if (error < 0) { 978 pr_err("No PCI devices found, driver not installed\n"); 979 error = -ENODEV; 980 goto err_out; 981 } 982 983 error = ath_ahb_init(); 984 if (error < 0) { 985 error = -ENODEV; 986 goto err_pci_exit; 987 } 988 989 return 0; 990 991 err_pci_exit: 992 ath_pci_exit(); 993 err_out: 994 return error; 995 } 996 module_init(ath9k_init); 997 998 static void __exit ath9k_exit(void) 999 { 1000 is_ath9k_unloaded = true; 1001 ath_ahb_exit(); 1002 ath_pci_exit(); 1003 pr_info("%s: Driver unloaded\n", dev_info); 1004 } 1005 module_exit(ath9k_exit); 1006