1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 int ath9k_use_chanctx; 65 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 66 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 67 68 bool is_ath9k_unloaded; 69 70 #ifdef CONFIG_MAC80211_LEDS 71 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 72 { .throughput = 0 * 1024, .blink_time = 334 }, 73 { .throughput = 1 * 1024, .blink_time = 260 }, 74 { .throughput = 5 * 1024, .blink_time = 220 }, 75 { .throughput = 10 * 1024, .blink_time = 190 }, 76 { .throughput = 20 * 1024, .blink_time = 170 }, 77 { .throughput = 50 * 1024, .blink_time = 150 }, 78 { .throughput = 70 * 1024, .blink_time = 130 }, 79 { .throughput = 100 * 1024, .blink_time = 110 }, 80 { .throughput = 200 * 1024, .blink_time = 80 }, 81 { .throughput = 300 * 1024, .blink_time = 50 }, 82 }; 83 #endif 84 85 static void ath9k_deinit_softc(struct ath_softc *sc); 86 87 /* 88 * Read and write, they both share the same lock. We do this to serialize 89 * reads and writes on Atheros 802.11n PCI devices only. This is required 90 * as the FIFO on these devices can only accept sanely 2 requests. 91 */ 92 93 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 94 { 95 struct ath_hw *ah = (struct ath_hw *) hw_priv; 96 struct ath_common *common = ath9k_hw_common(ah); 97 struct ath_softc *sc = (struct ath_softc *) common->priv; 98 99 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 100 unsigned long flags; 101 spin_lock_irqsave(&sc->sc_serial_rw, flags); 102 iowrite32(val, sc->mem + reg_offset); 103 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 104 } else 105 iowrite32(val, sc->mem + reg_offset); 106 } 107 108 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 109 { 110 struct ath_hw *ah = (struct ath_hw *) hw_priv; 111 struct ath_common *common = ath9k_hw_common(ah); 112 struct ath_softc *sc = (struct ath_softc *) common->priv; 113 u32 val; 114 115 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 116 unsigned long flags; 117 spin_lock_irqsave(&sc->sc_serial_rw, flags); 118 val = ioread32(sc->mem + reg_offset); 119 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 120 } else 121 val = ioread32(sc->mem + reg_offset); 122 return val; 123 } 124 125 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 126 u32 set, u32 clr) 127 { 128 u32 val; 129 130 val = ioread32(sc->mem + reg_offset); 131 val &= ~clr; 132 val |= set; 133 iowrite32(val, sc->mem + reg_offset); 134 135 return val; 136 } 137 138 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 139 { 140 struct ath_hw *ah = (struct ath_hw *) hw_priv; 141 struct ath_common *common = ath9k_hw_common(ah); 142 struct ath_softc *sc = (struct ath_softc *) common->priv; 143 unsigned long uninitialized_var(flags); 144 u32 val; 145 146 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 147 spin_lock_irqsave(&sc->sc_serial_rw, flags); 148 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 149 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 150 } else 151 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 152 153 return val; 154 } 155 156 /**************************/ 157 /* Initialization */ 158 /**************************/ 159 160 static void ath9k_reg_notifier(struct wiphy *wiphy, 161 struct regulatory_request *request) 162 { 163 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 164 struct ath_softc *sc = hw->priv; 165 struct ath_hw *ah = sc->sc_ah; 166 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 167 168 ath_reg_notifier_apply(wiphy, request, reg); 169 170 /* Set tx power */ 171 if (ah->curchan) { 172 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; 173 ath9k_ps_wakeup(sc); 174 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 175 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 176 /* synchronize DFS detector if regulatory domain changed */ 177 if (sc->dfs_detector != NULL) 178 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 179 request->dfs_region); 180 ath9k_ps_restore(sc); 181 } 182 } 183 184 /* 185 * This function will allocate both the DMA descriptor structure, and the 186 * buffers it contains. These are used to contain the descriptors used 187 * by the system. 188 */ 189 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 190 struct list_head *head, const char *name, 191 int nbuf, int ndesc, bool is_tx) 192 { 193 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 194 u8 *ds; 195 int i, bsize, desc_len; 196 197 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 198 name, nbuf, ndesc); 199 200 INIT_LIST_HEAD(head); 201 202 if (is_tx) 203 desc_len = sc->sc_ah->caps.tx_desc_len; 204 else 205 desc_len = sizeof(struct ath_desc); 206 207 /* ath_desc must be a multiple of DWORDs */ 208 if ((desc_len % 4) != 0) { 209 ath_err(common, "ath_desc not DWORD aligned\n"); 210 BUG_ON((desc_len % 4) != 0); 211 return -ENOMEM; 212 } 213 214 dd->dd_desc_len = desc_len * nbuf * ndesc; 215 216 /* 217 * Need additional DMA memory because we can't use 218 * descriptors that cross the 4K page boundary. Assume 219 * one skipped descriptor per 4K page. 220 */ 221 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 222 u32 ndesc_skipped = 223 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 224 u32 dma_len; 225 226 while (ndesc_skipped) { 227 dma_len = ndesc_skipped * desc_len; 228 dd->dd_desc_len += dma_len; 229 230 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 231 } 232 } 233 234 /* allocate descriptors */ 235 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 236 &dd->dd_desc_paddr, GFP_KERNEL); 237 if (!dd->dd_desc) 238 return -ENOMEM; 239 240 ds = (u8 *) dd->dd_desc; 241 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 242 name, ds, (u32) dd->dd_desc_len, 243 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 244 245 /* allocate buffers */ 246 if (is_tx) { 247 struct ath_buf *bf; 248 249 bsize = sizeof(struct ath_buf) * nbuf; 250 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 251 if (!bf) 252 return -ENOMEM; 253 254 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 255 bf->bf_desc = ds; 256 bf->bf_daddr = DS2PHYS(dd, ds); 257 258 if (!(sc->sc_ah->caps.hw_caps & 259 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 260 /* 261 * Skip descriptor addresses which can cause 4KB 262 * boundary crossing (addr + length) with a 32 dword 263 * descriptor fetch. 264 */ 265 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 266 BUG_ON((caddr_t) bf->bf_desc >= 267 ((caddr_t) dd->dd_desc + 268 dd->dd_desc_len)); 269 270 ds += (desc_len * ndesc); 271 bf->bf_desc = ds; 272 bf->bf_daddr = DS2PHYS(dd, ds); 273 } 274 } 275 list_add_tail(&bf->list, head); 276 } 277 } else { 278 struct ath_rxbuf *bf; 279 280 bsize = sizeof(struct ath_rxbuf) * nbuf; 281 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 282 if (!bf) 283 return -ENOMEM; 284 285 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 286 bf->bf_desc = ds; 287 bf->bf_daddr = DS2PHYS(dd, ds); 288 289 if (!(sc->sc_ah->caps.hw_caps & 290 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 291 /* 292 * Skip descriptor addresses which can cause 4KB 293 * boundary crossing (addr + length) with a 32 dword 294 * descriptor fetch. 295 */ 296 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 297 BUG_ON((caddr_t) bf->bf_desc >= 298 ((caddr_t) dd->dd_desc + 299 dd->dd_desc_len)); 300 301 ds += (desc_len * ndesc); 302 bf->bf_desc = ds; 303 bf->bf_daddr = DS2PHYS(dd, ds); 304 } 305 } 306 list_add_tail(&bf->list, head); 307 } 308 } 309 return 0; 310 } 311 312 static int ath9k_init_queues(struct ath_softc *sc) 313 { 314 int i = 0; 315 316 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 317 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 318 ath_cabq_update(sc); 319 320 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 321 322 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 323 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 324 sc->tx.txq_map[i]->mac80211_qnum = i; 325 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 326 } 327 return 0; 328 } 329 330 static void ath9k_init_misc(struct ath_softc *sc) 331 { 332 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 333 int i = 0; 334 335 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 336 337 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 338 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 339 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 340 341 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 342 sc->beacon.bslot[i] = NULL; 343 344 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 345 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 346 347 sc->spec_config.enabled = 0; 348 sc->spec_config.short_repeat = true; 349 sc->spec_config.count = 8; 350 sc->spec_config.endless = false; 351 sc->spec_config.period = 0xFF; 352 sc->spec_config.fft_period = 0xF; 353 } 354 355 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 356 { 357 struct ath_hw *ah = sc->sc_ah; 358 struct ath9k_hw_capabilities *pCap = &ah->caps; 359 struct ath_common *common = ath9k_hw_common(ah); 360 361 if (common->bus_ops->ath_bus_type != ATH_PCI) 362 return; 363 364 if (sc->driver_data & (ATH9K_PCI_CUS198 | 365 ATH9K_PCI_CUS230)) { 366 ah->config.xlna_gpio = 9; 367 ah->config.xatten_margin_cfg = true; 368 ah->config.alt_mingainidx = true; 369 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 370 sc->ant_comb.low_rssi_thresh = 20; 371 sc->ant_comb.fast_div_bias = 3; 372 373 ath_info(common, "Set parameters for %s\n", 374 (sc->driver_data & ATH9K_PCI_CUS198) ? 375 "CUS198" : "CUS230"); 376 } 377 378 if (sc->driver_data & ATH9K_PCI_CUS217) 379 ath_info(common, "CUS217 card detected\n"); 380 381 if (sc->driver_data & ATH9K_PCI_CUS252) 382 ath_info(common, "CUS252 card detected\n"); 383 384 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 385 ath_info(common, "WB335 1-ANT card detected\n"); 386 387 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 388 ath_info(common, "WB335 2-ANT card detected\n"); 389 390 if (sc->driver_data & ATH9K_PCI_KILLER) 391 ath_info(common, "Killer Wireless card detected\n"); 392 393 /* 394 * Some WB335 cards do not support antenna diversity. Since 395 * we use a hardcoded value for AR9565 instead of using the 396 * EEPROM/OTP data, remove the combining feature from 397 * the HW capabilities bitmap. 398 */ 399 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 400 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 401 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 402 } 403 404 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 405 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 406 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 407 } 408 409 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 410 ah->config.pcie_waen = 0x0040473b; 411 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 412 } 413 414 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 415 ah->config.no_pll_pwrsave = true; 416 ath_info(common, "Disable PLL PowerSave\n"); 417 } 418 } 419 420 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 421 void *ctx) 422 { 423 struct ath9k_eeprom_ctx *ec = ctx; 424 425 if (eeprom_blob) 426 ec->ah->eeprom_blob = eeprom_blob; 427 428 complete(&ec->complete); 429 } 430 431 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 432 { 433 struct ath9k_eeprom_ctx ec; 434 struct ath_hw *ah = ah = sc->sc_ah; 435 int err; 436 437 /* try to load the EEPROM content asynchronously */ 438 init_completion(&ec.complete); 439 ec.ah = sc->sc_ah; 440 441 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 442 &ec, ath9k_eeprom_request_cb); 443 if (err < 0) { 444 ath_err(ath9k_hw_common(ah), 445 "EEPROM request failed\n"); 446 return err; 447 } 448 449 wait_for_completion(&ec.complete); 450 451 if (!ah->eeprom_blob) { 452 ath_err(ath9k_hw_common(ah), 453 "Unable to load EEPROM file %s\n", name); 454 return -EINVAL; 455 } 456 457 return 0; 458 } 459 460 static void ath9k_eeprom_release(struct ath_softc *sc) 461 { 462 release_firmware(sc->sc_ah->eeprom_blob); 463 } 464 465 static int ath9k_init_soc_platform(struct ath_softc *sc) 466 { 467 struct ath9k_platform_data *pdata = sc->dev->platform_data; 468 struct ath_hw *ah = sc->sc_ah; 469 int ret = 0; 470 471 if (!pdata) 472 return 0; 473 474 if (pdata->eeprom_name) { 475 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 476 if (ret) 477 return ret; 478 } 479 480 if (pdata->tx_gain_buffalo) 481 ah->config.tx_gain_buffalo = true; 482 483 return ret; 484 } 485 486 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 487 const struct ath_bus_ops *bus_ops) 488 { 489 struct ath9k_platform_data *pdata = sc->dev->platform_data; 490 struct ath_hw *ah = NULL; 491 struct ath9k_hw_capabilities *pCap; 492 struct ath_common *common; 493 int ret = 0, i; 494 int csz = 0; 495 496 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 497 if (!ah) 498 return -ENOMEM; 499 500 ah->dev = sc->dev; 501 ah->hw = sc->hw; 502 ah->hw_version.devid = devid; 503 ah->reg_ops.read = ath9k_ioread32; 504 ah->reg_ops.write = ath9k_iowrite32; 505 ah->reg_ops.rmw = ath9k_reg_rmw; 506 sc->sc_ah = ah; 507 pCap = &ah->caps; 508 509 common = ath9k_hw_common(ah); 510 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 511 sc->tx99_power = MAX_RATE_POWER + 1; 512 init_waitqueue_head(&sc->tx_wait); 513 sc->cur_chan = &sc->chanctx[0]; 514 if (!ath9k_use_chanctx) 515 sc->cur_chan->hw_queue_base = 0; 516 517 if (!pdata || pdata->use_eeprom) { 518 ah->ah_flags |= AH_USE_EEPROM; 519 sc->sc_ah->led_pin = -1; 520 } else { 521 sc->sc_ah->gpio_mask = pdata->gpio_mask; 522 sc->sc_ah->gpio_val = pdata->gpio_val; 523 sc->sc_ah->led_pin = pdata->led_pin; 524 ah->is_clk_25mhz = pdata->is_clk_25mhz; 525 ah->get_mac_revision = pdata->get_mac_revision; 526 ah->external_reset = pdata->external_reset; 527 } 528 529 common->ops = &ah->reg_ops; 530 common->bus_ops = bus_ops; 531 common->ah = ah; 532 common->hw = sc->hw; 533 common->priv = sc; 534 common->debug_mask = ath9k_debug; 535 common->btcoex_enabled = ath9k_btcoex_enable == 1; 536 common->disable_ani = false; 537 538 /* 539 * Platform quirks. 540 */ 541 ath9k_init_pcoem_platform(sc); 542 543 ret = ath9k_init_soc_platform(sc); 544 if (ret) 545 return ret; 546 547 /* 548 * Enable WLAN/BT RX Antenna diversity only when: 549 * 550 * - BTCOEX is disabled. 551 * - the user manually requests the feature. 552 * - the HW cap is set using the platform data. 553 */ 554 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 555 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 556 common->bt_ant_diversity = 1; 557 558 spin_lock_init(&common->cc_lock); 559 spin_lock_init(&sc->sc_serial_rw); 560 spin_lock_init(&sc->sc_pm_lock); 561 spin_lock_init(&sc->chan_lock); 562 mutex_init(&sc->mutex); 563 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 564 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 565 (unsigned long)sc); 566 567 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 568 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 569 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 570 INIT_WORK(&sc->chanctx_work, ath_chanctx_work); 571 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 572 setup_timer(&sc->offchannel.timer, ath_offchannel_timer, 573 (unsigned long)sc); 574 setup_timer(&sc->sched.timer, ath_chanctx_timer, (unsigned long)sc); 575 576 /* 577 * Cache line size is used to size and align various 578 * structures used to communicate with the hardware. 579 */ 580 ath_read_cachesize(common, &csz); 581 common->cachelsz = csz << 2; /* convert to bytes */ 582 583 /* Initializes the hardware for all supported chipsets */ 584 ret = ath9k_hw_init(ah); 585 if (ret) 586 goto err_hw; 587 588 if (pdata && pdata->macaddr) 589 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 590 591 ret = ath9k_init_queues(sc); 592 if (ret) 593 goto err_queues; 594 595 ret = ath9k_init_btcoex(sc); 596 if (ret) 597 goto err_btcoex; 598 599 ret = ath9k_cmn_init_channels_rates(common); 600 if (ret) 601 goto err_btcoex; 602 603 sc->p2p_ps_timer = ath_gen_timer_alloc(sc->sc_ah, ath9k_p2p_ps_timer, 604 NULL, sc, AR_FIRST_NDP_TIMER); 605 606 ath9k_cmn_init_crypto(sc->sc_ah); 607 ath9k_init_misc(sc); 608 ath_fill_led_pin(sc); 609 ath_chanctx_init(sc); 610 611 if (common->bus_ops->aspm_init) 612 common->bus_ops->aspm_init(common); 613 614 return 0; 615 616 err_btcoex: 617 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 618 if (ATH_TXQ_SETUP(sc, i)) 619 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 620 err_queues: 621 ath9k_hw_deinit(ah); 622 err_hw: 623 ath9k_eeprom_release(sc); 624 dev_kfree_skb_any(sc->tx99_skb); 625 return ret; 626 } 627 628 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 629 { 630 struct ieee80211_supported_band *sband; 631 struct ieee80211_channel *chan; 632 struct ath_hw *ah = sc->sc_ah; 633 struct ath_common *common = ath9k_hw_common(ah); 634 struct cfg80211_chan_def chandef; 635 int i; 636 637 sband = &common->sbands[band]; 638 for (i = 0; i < sband->n_channels; i++) { 639 chan = &sband->channels[i]; 640 ah->curchan = &ah->channels[chan->hw_value]; 641 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 642 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 643 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 644 } 645 } 646 647 static void ath9k_init_txpower_limits(struct ath_softc *sc) 648 { 649 struct ath_hw *ah = sc->sc_ah; 650 struct ath9k_channel *curchan = ah->curchan; 651 652 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 653 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 654 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 655 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 656 657 ah->curchan = curchan; 658 } 659 660 static const struct ieee80211_iface_limit if_limits[] = { 661 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 662 { .max = 8, .types = 663 #ifdef CONFIG_MAC80211_MESH 664 BIT(NL80211_IFTYPE_MESH_POINT) | 665 #endif 666 BIT(NL80211_IFTYPE_AP) }, 667 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 668 BIT(NL80211_IFTYPE_P2P_GO) }, 669 }; 670 671 static const struct ieee80211_iface_limit wds_limits[] = { 672 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, 673 }; 674 675 static const struct ieee80211_iface_limit if_limits_multi[] = { 676 { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) }, 677 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 678 BIT(NL80211_IFTYPE_P2P_GO) }, 679 }; 680 681 static const struct ieee80211_iface_limit if_dfs_limits[] = { 682 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 683 #ifdef CONFIG_MAC80211_MESH 684 BIT(NL80211_IFTYPE_MESH_POINT) | 685 #endif 686 BIT(NL80211_IFTYPE_ADHOC) }, 687 }; 688 689 static const struct ieee80211_iface_combination if_comb_multi[] = { 690 { 691 .limits = if_limits_multi, 692 .n_limits = ARRAY_SIZE(if_limits_multi), 693 .max_interfaces = 2, 694 .num_different_channels = 2, 695 .beacon_int_infra_match = true, 696 }, 697 }; 698 699 static const struct ieee80211_iface_combination if_comb[] = { 700 { 701 .limits = if_limits, 702 .n_limits = ARRAY_SIZE(if_limits), 703 .max_interfaces = 2048, 704 .num_different_channels = 1, 705 .beacon_int_infra_match = true, 706 }, 707 { 708 .limits = wds_limits, 709 .n_limits = ARRAY_SIZE(wds_limits), 710 .max_interfaces = 2048, 711 .num_different_channels = 1, 712 .beacon_int_infra_match = true, 713 }, 714 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 715 { 716 .limits = if_dfs_limits, 717 .n_limits = ARRAY_SIZE(if_dfs_limits), 718 .max_interfaces = 1, 719 .num_different_channels = 1, 720 .beacon_int_infra_match = true, 721 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 722 BIT(NL80211_CHAN_WIDTH_20), 723 } 724 #endif 725 }; 726 727 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 728 { 729 struct ath_hw *ah = sc->sc_ah; 730 struct ath_common *common = ath9k_hw_common(ah); 731 732 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 733 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 734 IEEE80211_HW_SIGNAL_DBM | 735 IEEE80211_HW_PS_NULLFUNC_STACK | 736 IEEE80211_HW_SPECTRUM_MGMT | 737 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 738 IEEE80211_HW_SUPPORTS_RC_TABLE | 739 IEEE80211_HW_QUEUE_CONTROL | 740 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 741 742 if (ath9k_ps_enable) 743 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 744 745 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 746 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 747 748 if (AR_SREV_9280_20_OR_LATER(ah)) 749 hw->radiotap_mcs_details |= 750 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 751 } 752 753 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 754 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 755 756 hw->wiphy->features |= (NL80211_FEATURE_ACTIVE_MONITOR | 757 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE); 758 759 if (!config_enabled(CONFIG_ATH9K_TX99)) { 760 hw->wiphy->interface_modes = 761 BIT(NL80211_IFTYPE_P2P_GO) | 762 BIT(NL80211_IFTYPE_P2P_CLIENT) | 763 BIT(NL80211_IFTYPE_AP) | 764 BIT(NL80211_IFTYPE_STATION) | 765 BIT(NL80211_IFTYPE_ADHOC) | 766 BIT(NL80211_IFTYPE_MESH_POINT); 767 if (!ath9k_use_chanctx) { 768 hw->wiphy->iface_combinations = if_comb; 769 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 770 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_WDS); 771 } else { 772 hw->wiphy->iface_combinations = if_comb_multi; 773 hw->wiphy->n_iface_combinations = 774 ARRAY_SIZE(if_comb_multi); 775 hw->wiphy->max_scan_ssids = 255; 776 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 777 hw->wiphy->max_remain_on_channel_duration = 10000; 778 hw->chanctx_data_size = sizeof(void *); 779 hw->extra_beacon_tailroom = 780 sizeof(struct ieee80211_p2p_noa_attr) + 9; 781 } 782 } 783 784 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 785 786 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 787 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 788 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 789 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 790 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 791 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 792 793 /* allow 4 queues per channel context + 794 * 1 cab queue + 1 offchannel tx queue 795 */ 796 hw->queues = 10; 797 /* last queue for offchannel */ 798 hw->offchannel_tx_hw_queue = hw->queues - 1; 799 hw->max_rates = 4; 800 hw->max_listen_interval = 10; 801 hw->max_rate_tries = 10; 802 hw->sta_data_size = sizeof(struct ath_node); 803 hw->vif_data_size = sizeof(struct ath_vif); 804 805 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 806 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 807 808 /* single chain devices with rx diversity */ 809 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 810 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 811 812 sc->ant_rx = hw->wiphy->available_antennas_rx; 813 sc->ant_tx = hw->wiphy->available_antennas_tx; 814 815 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 816 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 817 &common->sbands[IEEE80211_BAND_2GHZ]; 818 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 819 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 820 &common->sbands[IEEE80211_BAND_5GHZ]; 821 822 ath9k_init_wow(hw); 823 ath9k_cmn_reload_chainmask(ah); 824 825 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 826 } 827 828 int ath9k_init_device(u16 devid, struct ath_softc *sc, 829 const struct ath_bus_ops *bus_ops) 830 { 831 struct ieee80211_hw *hw = sc->hw; 832 struct ath_common *common; 833 struct ath_hw *ah; 834 int error = 0; 835 struct ath_regulatory *reg; 836 837 /* Bring up device */ 838 error = ath9k_init_softc(devid, sc, bus_ops); 839 if (error) 840 return error; 841 842 ah = sc->sc_ah; 843 common = ath9k_hw_common(ah); 844 ath9k_set_hw_capab(sc, hw); 845 846 /* Will be cleared in ath9k_start() */ 847 set_bit(ATH_OP_INVALID, &common->op_flags); 848 849 /* Initialize regulatory */ 850 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 851 ath9k_reg_notifier); 852 if (error) 853 goto deinit; 854 855 reg = &common->regulatory; 856 857 /* Setup TX DMA */ 858 error = ath_tx_init(sc, ATH_TXBUF); 859 if (error != 0) 860 goto deinit; 861 862 /* Setup RX DMA */ 863 error = ath_rx_init(sc, ATH_RXBUF); 864 if (error != 0) 865 goto deinit; 866 867 ath9k_init_txpower_limits(sc); 868 869 #ifdef CONFIG_MAC80211_LEDS 870 /* must be initialized before ieee80211_register_hw */ 871 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 872 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 873 ARRAY_SIZE(ath9k_tpt_blink)); 874 #endif 875 876 /* Register with mac80211 */ 877 error = ieee80211_register_hw(hw); 878 if (error) 879 goto rx_cleanup; 880 881 error = ath9k_init_debug(ah); 882 if (error) { 883 ath_err(common, "Unable to create debugfs files\n"); 884 goto unregister; 885 } 886 887 /* Handle world regulatory */ 888 if (!ath_is_world_regd(reg)) { 889 error = regulatory_hint(hw->wiphy, reg->alpha2); 890 if (error) 891 goto debug_cleanup; 892 } 893 894 ath_init_leds(sc); 895 ath_start_rfkill_poll(sc); 896 897 return 0; 898 899 debug_cleanup: 900 ath9k_deinit_debug(sc); 901 unregister: 902 ieee80211_unregister_hw(hw); 903 rx_cleanup: 904 ath_rx_cleanup(sc); 905 deinit: 906 ath9k_deinit_softc(sc); 907 return error; 908 } 909 910 /*****************************/ 911 /* De-Initialization */ 912 /*****************************/ 913 914 static void ath9k_deinit_softc(struct ath_softc *sc) 915 { 916 int i = 0; 917 918 if (sc->p2p_ps_timer) 919 ath_gen_timer_free(sc->sc_ah, sc->p2p_ps_timer); 920 921 ath9k_deinit_btcoex(sc); 922 923 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 924 if (ATH_TXQ_SETUP(sc, i)) 925 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 926 927 del_timer_sync(&sc->sleep_timer); 928 ath9k_hw_deinit(sc->sc_ah); 929 if (sc->dfs_detector != NULL) 930 sc->dfs_detector->exit(sc->dfs_detector); 931 932 ath9k_eeprom_release(sc); 933 } 934 935 void ath9k_deinit_device(struct ath_softc *sc) 936 { 937 struct ieee80211_hw *hw = sc->hw; 938 939 ath9k_ps_wakeup(sc); 940 941 wiphy_rfkill_stop_polling(sc->hw->wiphy); 942 ath_deinit_leds(sc); 943 944 ath9k_ps_restore(sc); 945 946 ath9k_deinit_debug(sc); 947 ieee80211_unregister_hw(hw); 948 ath_rx_cleanup(sc); 949 ath9k_deinit_softc(sc); 950 } 951 952 /************************/ 953 /* Module Hooks */ 954 /************************/ 955 956 static int __init ath9k_init(void) 957 { 958 int error; 959 960 error = ath_pci_init(); 961 if (error < 0) { 962 pr_err("No PCI devices found, driver not installed\n"); 963 error = -ENODEV; 964 goto err_out; 965 } 966 967 error = ath_ahb_init(); 968 if (error < 0) { 969 error = -ENODEV; 970 goto err_pci_exit; 971 } 972 973 return 0; 974 975 err_pci_exit: 976 ath_pci_exit(); 977 err_out: 978 return error; 979 } 980 module_init(ath9k_init); 981 982 static void __exit ath9k_exit(void) 983 { 984 is_ath9k_unloaded = true; 985 ath_ahb_exit(); 986 ath_pci_exit(); 987 pr_info("%s: Driver unloaded\n", dev_info); 988 } 989 module_exit(ath9k_exit); 990