1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 bool is_ath9k_unloaded; 65 66 #ifdef CONFIG_MAC80211_LEDS 67 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 68 { .throughput = 0 * 1024, .blink_time = 334 }, 69 { .throughput = 1 * 1024, .blink_time = 260 }, 70 { .throughput = 5 * 1024, .blink_time = 220 }, 71 { .throughput = 10 * 1024, .blink_time = 190 }, 72 { .throughput = 20 * 1024, .blink_time = 170 }, 73 { .throughput = 50 * 1024, .blink_time = 150 }, 74 { .throughput = 70 * 1024, .blink_time = 130 }, 75 { .throughput = 100 * 1024, .blink_time = 110 }, 76 { .throughput = 200 * 1024, .blink_time = 80 }, 77 { .throughput = 300 * 1024, .blink_time = 50 }, 78 }; 79 #endif 80 81 static void ath9k_deinit_softc(struct ath_softc *sc); 82 83 /* 84 * Read and write, they both share the same lock. We do this to serialize 85 * reads and writes on Atheros 802.11n PCI devices only. This is required 86 * as the FIFO on these devices can only accept sanely 2 requests. 87 */ 88 89 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 90 { 91 struct ath_hw *ah = (struct ath_hw *) hw_priv; 92 struct ath_common *common = ath9k_hw_common(ah); 93 struct ath_softc *sc = (struct ath_softc *) common->priv; 94 95 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 96 unsigned long flags; 97 spin_lock_irqsave(&sc->sc_serial_rw, flags); 98 iowrite32(val, sc->mem + reg_offset); 99 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 100 } else 101 iowrite32(val, sc->mem + reg_offset); 102 } 103 104 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 105 { 106 struct ath_hw *ah = (struct ath_hw *) hw_priv; 107 struct ath_common *common = ath9k_hw_common(ah); 108 struct ath_softc *sc = (struct ath_softc *) common->priv; 109 u32 val; 110 111 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 112 unsigned long flags; 113 spin_lock_irqsave(&sc->sc_serial_rw, flags); 114 val = ioread32(sc->mem + reg_offset); 115 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 116 } else 117 val = ioread32(sc->mem + reg_offset); 118 return val; 119 } 120 121 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 122 u32 set, u32 clr) 123 { 124 u32 val; 125 126 val = ioread32(sc->mem + reg_offset); 127 val &= ~clr; 128 val |= set; 129 iowrite32(val, sc->mem + reg_offset); 130 131 return val; 132 } 133 134 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 135 { 136 struct ath_hw *ah = (struct ath_hw *) hw_priv; 137 struct ath_common *common = ath9k_hw_common(ah); 138 struct ath_softc *sc = (struct ath_softc *) common->priv; 139 unsigned long uninitialized_var(flags); 140 u32 val; 141 142 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 143 spin_lock_irqsave(&sc->sc_serial_rw, flags); 144 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 145 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 146 } else 147 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 148 149 return val; 150 } 151 152 /**************************/ 153 /* Initialization */ 154 /**************************/ 155 156 static void ath9k_reg_notifier(struct wiphy *wiphy, 157 struct regulatory_request *request) 158 { 159 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 160 struct ath_softc *sc = hw->priv; 161 struct ath_hw *ah = sc->sc_ah; 162 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 163 164 ath_reg_notifier_apply(wiphy, request, reg); 165 166 /* Set tx power */ 167 if (ah->curchan) { 168 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 169 ath9k_ps_wakeup(sc); 170 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 171 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 172 /* synchronize DFS detector if regulatory domain changed */ 173 if (sc->dfs_detector != NULL) 174 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 175 request->dfs_region); 176 ath9k_ps_restore(sc); 177 } 178 } 179 180 /* 181 * This function will allocate both the DMA descriptor structure, and the 182 * buffers it contains. These are used to contain the descriptors used 183 * by the system. 184 */ 185 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 186 struct list_head *head, const char *name, 187 int nbuf, int ndesc, bool is_tx) 188 { 189 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 190 u8 *ds; 191 int i, bsize, desc_len; 192 193 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 194 name, nbuf, ndesc); 195 196 INIT_LIST_HEAD(head); 197 198 if (is_tx) 199 desc_len = sc->sc_ah->caps.tx_desc_len; 200 else 201 desc_len = sizeof(struct ath_desc); 202 203 /* ath_desc must be a multiple of DWORDs */ 204 if ((desc_len % 4) != 0) { 205 ath_err(common, "ath_desc not DWORD aligned\n"); 206 BUG_ON((desc_len % 4) != 0); 207 return -ENOMEM; 208 } 209 210 dd->dd_desc_len = desc_len * nbuf * ndesc; 211 212 /* 213 * Need additional DMA memory because we can't use 214 * descriptors that cross the 4K page boundary. Assume 215 * one skipped descriptor per 4K page. 216 */ 217 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 218 u32 ndesc_skipped = 219 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 220 u32 dma_len; 221 222 while (ndesc_skipped) { 223 dma_len = ndesc_skipped * desc_len; 224 dd->dd_desc_len += dma_len; 225 226 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 227 } 228 } 229 230 /* allocate descriptors */ 231 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 232 &dd->dd_desc_paddr, GFP_KERNEL); 233 if (!dd->dd_desc) 234 return -ENOMEM; 235 236 ds = (u8 *) dd->dd_desc; 237 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 238 name, ds, (u32) dd->dd_desc_len, 239 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 240 241 /* allocate buffers */ 242 if (is_tx) { 243 struct ath_buf *bf; 244 245 bsize = sizeof(struct ath_buf) * nbuf; 246 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 247 if (!bf) 248 return -ENOMEM; 249 250 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 251 bf->bf_desc = ds; 252 bf->bf_daddr = DS2PHYS(dd, ds); 253 254 if (!(sc->sc_ah->caps.hw_caps & 255 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 256 /* 257 * Skip descriptor addresses which can cause 4KB 258 * boundary crossing (addr + length) with a 32 dword 259 * descriptor fetch. 260 */ 261 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 262 BUG_ON((caddr_t) bf->bf_desc >= 263 ((caddr_t) dd->dd_desc + 264 dd->dd_desc_len)); 265 266 ds += (desc_len * ndesc); 267 bf->bf_desc = ds; 268 bf->bf_daddr = DS2PHYS(dd, ds); 269 } 270 } 271 list_add_tail(&bf->list, head); 272 } 273 } else { 274 struct ath_rxbuf *bf; 275 276 bsize = sizeof(struct ath_rxbuf) * nbuf; 277 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 278 if (!bf) 279 return -ENOMEM; 280 281 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 282 bf->bf_desc = ds; 283 bf->bf_daddr = DS2PHYS(dd, ds); 284 285 if (!(sc->sc_ah->caps.hw_caps & 286 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 287 /* 288 * Skip descriptor addresses which can cause 4KB 289 * boundary crossing (addr + length) with a 32 dword 290 * descriptor fetch. 291 */ 292 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 293 BUG_ON((caddr_t) bf->bf_desc >= 294 ((caddr_t) dd->dd_desc + 295 dd->dd_desc_len)); 296 297 ds += (desc_len * ndesc); 298 bf->bf_desc = ds; 299 bf->bf_daddr = DS2PHYS(dd, ds); 300 } 301 } 302 list_add_tail(&bf->list, head); 303 } 304 } 305 return 0; 306 } 307 308 static int ath9k_init_queues(struct ath_softc *sc) 309 { 310 int i = 0; 311 312 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 313 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 314 ath_cabq_update(sc); 315 316 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 317 318 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 319 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 320 sc->tx.txq_map[i]->mac80211_qnum = i; 321 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 322 } 323 return 0; 324 } 325 326 static void ath9k_init_misc(struct ath_softc *sc) 327 { 328 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 329 int i = 0; 330 331 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 332 333 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 334 sc->config.txpowlimit = ATH_TXPOWER_MAX; 335 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 336 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 337 338 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 339 sc->beacon.bslot[i] = NULL; 340 341 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 342 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 343 344 sc->spec_config.enabled = 0; 345 sc->spec_config.short_repeat = true; 346 sc->spec_config.count = 8; 347 sc->spec_config.endless = false; 348 sc->spec_config.period = 0xFF; 349 sc->spec_config.fft_period = 0xF; 350 } 351 352 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 353 { 354 struct ath_hw *ah = sc->sc_ah; 355 struct ath9k_hw_capabilities *pCap = &ah->caps; 356 struct ath_common *common = ath9k_hw_common(ah); 357 358 if (common->bus_ops->ath_bus_type != ATH_PCI) 359 return; 360 361 if (sc->driver_data & (ATH9K_PCI_CUS198 | 362 ATH9K_PCI_CUS230)) { 363 ah->config.xlna_gpio = 9; 364 ah->config.xatten_margin_cfg = true; 365 ah->config.alt_mingainidx = true; 366 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 367 sc->ant_comb.low_rssi_thresh = 20; 368 sc->ant_comb.fast_div_bias = 3; 369 370 ath_info(common, "Set parameters for %s\n", 371 (sc->driver_data & ATH9K_PCI_CUS198) ? 372 "CUS198" : "CUS230"); 373 } 374 375 if (sc->driver_data & ATH9K_PCI_CUS217) 376 ath_info(common, "CUS217 card detected\n"); 377 378 if (sc->driver_data & ATH9K_PCI_CUS252) 379 ath_info(common, "CUS252 card detected\n"); 380 381 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 382 ath_info(common, "WB335 1-ANT card detected\n"); 383 384 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 385 ath_info(common, "WB335 2-ANT card detected\n"); 386 387 if (sc->driver_data & ATH9K_PCI_KILLER) 388 ath_info(common, "Killer Wireless card detected\n"); 389 390 /* 391 * Some WB335 cards do not support antenna diversity. Since 392 * we use a hardcoded value for AR9565 instead of using the 393 * EEPROM/OTP data, remove the combining feature from 394 * the HW capabilities bitmap. 395 */ 396 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 397 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 398 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 399 } 400 401 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 402 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 403 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 404 } 405 406 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 407 ah->config.pcie_waen = 0x0040473b; 408 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 409 } 410 411 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 412 ah->config.no_pll_pwrsave = true; 413 ath_info(common, "Disable PLL PowerSave\n"); 414 } 415 } 416 417 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 418 void *ctx) 419 { 420 struct ath9k_eeprom_ctx *ec = ctx; 421 422 if (eeprom_blob) 423 ec->ah->eeprom_blob = eeprom_blob; 424 425 complete(&ec->complete); 426 } 427 428 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 429 { 430 struct ath9k_eeprom_ctx ec; 431 struct ath_hw *ah = ah = sc->sc_ah; 432 int err; 433 434 /* try to load the EEPROM content asynchronously */ 435 init_completion(&ec.complete); 436 ec.ah = sc->sc_ah; 437 438 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 439 &ec, ath9k_eeprom_request_cb); 440 if (err < 0) { 441 ath_err(ath9k_hw_common(ah), 442 "EEPROM request failed\n"); 443 return err; 444 } 445 446 wait_for_completion(&ec.complete); 447 448 if (!ah->eeprom_blob) { 449 ath_err(ath9k_hw_common(ah), 450 "Unable to load EEPROM file %s\n", name); 451 return -EINVAL; 452 } 453 454 return 0; 455 } 456 457 static void ath9k_eeprom_release(struct ath_softc *sc) 458 { 459 release_firmware(sc->sc_ah->eeprom_blob); 460 } 461 462 static int ath9k_init_soc_platform(struct ath_softc *sc) 463 { 464 struct ath9k_platform_data *pdata = sc->dev->platform_data; 465 struct ath_hw *ah = sc->sc_ah; 466 int ret = 0; 467 468 if (!pdata) 469 return 0; 470 471 if (pdata->eeprom_name) { 472 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 473 if (ret) 474 return ret; 475 } 476 477 if (pdata->tx_gain_buffalo) 478 ah->config.tx_gain_buffalo = true; 479 480 return ret; 481 } 482 483 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 484 const struct ath_bus_ops *bus_ops) 485 { 486 struct ath9k_platform_data *pdata = sc->dev->platform_data; 487 struct ath_hw *ah = NULL; 488 struct ath9k_hw_capabilities *pCap; 489 struct ath_common *common; 490 int ret = 0, i; 491 int csz = 0; 492 493 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 494 if (!ah) 495 return -ENOMEM; 496 497 ah->dev = sc->dev; 498 ah->hw = sc->hw; 499 ah->hw_version.devid = devid; 500 ah->reg_ops.read = ath9k_ioread32; 501 ah->reg_ops.write = ath9k_iowrite32; 502 ah->reg_ops.rmw = ath9k_reg_rmw; 503 sc->sc_ah = ah; 504 pCap = &ah->caps; 505 506 common = ath9k_hw_common(ah); 507 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 508 sc->tx99_power = MAX_RATE_POWER + 1; 509 init_waitqueue_head(&sc->tx_wait); 510 511 if (!pdata) { 512 ah->ah_flags |= AH_USE_EEPROM; 513 sc->sc_ah->led_pin = -1; 514 } else { 515 sc->sc_ah->gpio_mask = pdata->gpio_mask; 516 sc->sc_ah->gpio_val = pdata->gpio_val; 517 sc->sc_ah->led_pin = pdata->led_pin; 518 ah->is_clk_25mhz = pdata->is_clk_25mhz; 519 ah->get_mac_revision = pdata->get_mac_revision; 520 ah->external_reset = pdata->external_reset; 521 } 522 523 common->ops = &ah->reg_ops; 524 common->bus_ops = bus_ops; 525 common->ah = ah; 526 common->hw = sc->hw; 527 common->priv = sc; 528 common->debug_mask = ath9k_debug; 529 common->btcoex_enabled = ath9k_btcoex_enable == 1; 530 common->disable_ani = false; 531 532 /* 533 * Platform quirks. 534 */ 535 ath9k_init_pcoem_platform(sc); 536 537 ret = ath9k_init_soc_platform(sc); 538 if (ret) 539 return ret; 540 541 /* 542 * Enable WLAN/BT RX Antenna diversity only when: 543 * 544 * - BTCOEX is disabled. 545 * - the user manually requests the feature. 546 * - the HW cap is set using the platform data. 547 */ 548 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 549 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 550 common->bt_ant_diversity = 1; 551 552 spin_lock_init(&common->cc_lock); 553 spin_lock_init(&sc->sc_serial_rw); 554 spin_lock_init(&sc->sc_pm_lock); 555 mutex_init(&sc->mutex); 556 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 557 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 558 (unsigned long)sc); 559 560 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 561 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 562 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 563 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 564 565 /* 566 * Cache line size is used to size and align various 567 * structures used to communicate with the hardware. 568 */ 569 ath_read_cachesize(common, &csz); 570 common->cachelsz = csz << 2; /* convert to bytes */ 571 572 /* Initializes the hardware for all supported chipsets */ 573 ret = ath9k_hw_init(ah); 574 if (ret) 575 goto err_hw; 576 577 if (pdata && pdata->macaddr) 578 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 579 580 ret = ath9k_init_queues(sc); 581 if (ret) 582 goto err_queues; 583 584 ret = ath9k_init_btcoex(sc); 585 if (ret) 586 goto err_btcoex; 587 588 ret = ath9k_cmn_init_channels_rates(common); 589 if (ret) 590 goto err_btcoex; 591 592 ath9k_cmn_init_crypto(sc->sc_ah); 593 ath9k_init_misc(sc); 594 ath_fill_led_pin(sc); 595 596 if (common->bus_ops->aspm_init) 597 common->bus_ops->aspm_init(common); 598 599 return 0; 600 601 err_btcoex: 602 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 603 if (ATH_TXQ_SETUP(sc, i)) 604 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 605 err_queues: 606 ath9k_hw_deinit(ah); 607 err_hw: 608 ath9k_eeprom_release(sc); 609 dev_kfree_skb_any(sc->tx99_skb); 610 return ret; 611 } 612 613 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 614 { 615 struct ieee80211_supported_band *sband; 616 struct ieee80211_channel *chan; 617 struct ath_hw *ah = sc->sc_ah; 618 struct ath_common *common = ath9k_hw_common(ah); 619 struct cfg80211_chan_def chandef; 620 int i; 621 622 sband = &common->sbands[band]; 623 for (i = 0; i < sband->n_channels; i++) { 624 chan = &sband->channels[i]; 625 ah->curchan = &ah->channels[chan->hw_value]; 626 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 627 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 628 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 629 } 630 } 631 632 static void ath9k_init_txpower_limits(struct ath_softc *sc) 633 { 634 struct ath_hw *ah = sc->sc_ah; 635 struct ath9k_channel *curchan = ah->curchan; 636 637 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 638 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 639 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 640 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 641 642 ah->curchan = curchan; 643 } 644 645 static const struct ieee80211_iface_limit if_limits[] = { 646 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | 647 BIT(NL80211_IFTYPE_P2P_CLIENT) | 648 BIT(NL80211_IFTYPE_WDS) }, 649 { .max = 8, .types = 650 #ifdef CONFIG_MAC80211_MESH 651 BIT(NL80211_IFTYPE_MESH_POINT) | 652 #endif 653 BIT(NL80211_IFTYPE_AP) | 654 BIT(NL80211_IFTYPE_P2P_GO) }, 655 }; 656 657 static const struct ieee80211_iface_limit if_dfs_limits[] = { 658 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 659 #ifdef CONFIG_MAC80211_MESH 660 BIT(NL80211_IFTYPE_MESH_POINT) | 661 #endif 662 BIT(NL80211_IFTYPE_ADHOC) }, 663 }; 664 665 static const struct ieee80211_iface_combination if_comb[] = { 666 { 667 .limits = if_limits, 668 .n_limits = ARRAY_SIZE(if_limits), 669 .max_interfaces = 2048, 670 .num_different_channels = 1, 671 .beacon_int_infra_match = true, 672 }, 673 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 674 { 675 .limits = if_dfs_limits, 676 .n_limits = ARRAY_SIZE(if_dfs_limits), 677 .max_interfaces = 1, 678 .num_different_channels = 1, 679 .beacon_int_infra_match = true, 680 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 681 BIT(NL80211_CHAN_WIDTH_20), 682 } 683 #endif 684 }; 685 686 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 687 { 688 struct ath_hw *ah = sc->sc_ah; 689 struct ath_common *common = ath9k_hw_common(ah); 690 691 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 692 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 693 IEEE80211_HW_SIGNAL_DBM | 694 IEEE80211_HW_PS_NULLFUNC_STACK | 695 IEEE80211_HW_SPECTRUM_MGMT | 696 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 697 IEEE80211_HW_SUPPORTS_RC_TABLE | 698 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 699 700 if (ath9k_ps_enable) 701 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 702 703 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 704 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 705 706 if (AR_SREV_9280_20_OR_LATER(ah)) 707 hw->radiotap_mcs_details |= 708 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 709 } 710 711 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 712 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 713 714 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; 715 716 if (!config_enabled(CONFIG_ATH9K_TX99)) { 717 hw->wiphy->interface_modes = 718 BIT(NL80211_IFTYPE_P2P_GO) | 719 BIT(NL80211_IFTYPE_P2P_CLIENT) | 720 BIT(NL80211_IFTYPE_AP) | 721 BIT(NL80211_IFTYPE_WDS) | 722 BIT(NL80211_IFTYPE_STATION) | 723 BIT(NL80211_IFTYPE_ADHOC) | 724 BIT(NL80211_IFTYPE_MESH_POINT); 725 hw->wiphy->iface_combinations = if_comb; 726 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 727 } 728 729 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 730 731 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 732 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 733 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 734 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 735 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 736 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 737 738 hw->queues = 4; 739 hw->max_rates = 4; 740 hw->max_listen_interval = 1; 741 hw->max_rate_tries = 10; 742 hw->sta_data_size = sizeof(struct ath_node); 743 hw->vif_data_size = sizeof(struct ath_vif); 744 745 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 746 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 747 748 /* single chain devices with rx diversity */ 749 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 750 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 751 752 sc->ant_rx = hw->wiphy->available_antennas_rx; 753 sc->ant_tx = hw->wiphy->available_antennas_tx; 754 755 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 756 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 757 &common->sbands[IEEE80211_BAND_2GHZ]; 758 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 759 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 760 &common->sbands[IEEE80211_BAND_5GHZ]; 761 762 ath9k_init_wow(hw); 763 ath9k_cmn_reload_chainmask(ah); 764 765 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 766 } 767 768 int ath9k_init_device(u16 devid, struct ath_softc *sc, 769 const struct ath_bus_ops *bus_ops) 770 { 771 struct ieee80211_hw *hw = sc->hw; 772 struct ath_common *common; 773 struct ath_hw *ah; 774 int error = 0; 775 struct ath_regulatory *reg; 776 777 /* Bring up device */ 778 error = ath9k_init_softc(devid, sc, bus_ops); 779 if (error) 780 return error; 781 782 ah = sc->sc_ah; 783 common = ath9k_hw_common(ah); 784 ath9k_set_hw_capab(sc, hw); 785 786 /* Initialize regulatory */ 787 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 788 ath9k_reg_notifier); 789 if (error) 790 goto deinit; 791 792 reg = &common->regulatory; 793 794 /* Setup TX DMA */ 795 error = ath_tx_init(sc, ATH_TXBUF); 796 if (error != 0) 797 goto deinit; 798 799 /* Setup RX DMA */ 800 error = ath_rx_init(sc, ATH_RXBUF); 801 if (error != 0) 802 goto deinit; 803 804 ath9k_init_txpower_limits(sc); 805 806 #ifdef CONFIG_MAC80211_LEDS 807 /* must be initialized before ieee80211_register_hw */ 808 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 809 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 810 ARRAY_SIZE(ath9k_tpt_blink)); 811 #endif 812 813 /* Register with mac80211 */ 814 error = ieee80211_register_hw(hw); 815 if (error) 816 goto rx_cleanup; 817 818 error = ath9k_init_debug(ah); 819 if (error) { 820 ath_err(common, "Unable to create debugfs files\n"); 821 goto unregister; 822 } 823 824 /* Handle world regulatory */ 825 if (!ath_is_world_regd(reg)) { 826 error = regulatory_hint(hw->wiphy, reg->alpha2); 827 if (error) 828 goto debug_cleanup; 829 } 830 831 ath_init_leds(sc); 832 ath_start_rfkill_poll(sc); 833 834 return 0; 835 836 debug_cleanup: 837 ath9k_deinit_debug(sc); 838 unregister: 839 ieee80211_unregister_hw(hw); 840 rx_cleanup: 841 ath_rx_cleanup(sc); 842 deinit: 843 ath9k_deinit_softc(sc); 844 return error; 845 } 846 847 /*****************************/ 848 /* De-Initialization */ 849 /*****************************/ 850 851 static void ath9k_deinit_softc(struct ath_softc *sc) 852 { 853 int i = 0; 854 855 ath9k_deinit_btcoex(sc); 856 857 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 858 if (ATH_TXQ_SETUP(sc, i)) 859 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 860 861 del_timer_sync(&sc->sleep_timer); 862 ath9k_hw_deinit(sc->sc_ah); 863 if (sc->dfs_detector != NULL) 864 sc->dfs_detector->exit(sc->dfs_detector); 865 866 ath9k_eeprom_release(sc); 867 } 868 869 void ath9k_deinit_device(struct ath_softc *sc) 870 { 871 struct ieee80211_hw *hw = sc->hw; 872 873 ath9k_ps_wakeup(sc); 874 875 wiphy_rfkill_stop_polling(sc->hw->wiphy); 876 ath_deinit_leds(sc); 877 878 ath9k_ps_restore(sc); 879 880 ath9k_deinit_debug(sc); 881 ieee80211_unregister_hw(hw); 882 ath_rx_cleanup(sc); 883 ath9k_deinit_softc(sc); 884 } 885 886 /************************/ 887 /* Module Hooks */ 888 /************************/ 889 890 static int __init ath9k_init(void) 891 { 892 int error; 893 894 error = ath_pci_init(); 895 if (error < 0) { 896 pr_err("No PCI devices found, driver not installed\n"); 897 error = -ENODEV; 898 goto err_out; 899 } 900 901 error = ath_ahb_init(); 902 if (error < 0) { 903 error = -ENODEV; 904 goto err_pci_exit; 905 } 906 907 return 0; 908 909 err_pci_exit: 910 ath_pci_exit(); 911 err_out: 912 return error; 913 } 914 module_init(ath9k_init); 915 916 static void __exit ath9k_exit(void) 917 { 918 is_ath9k_unloaded = true; 919 ath_ahb_exit(); 920 ath_pci_exit(); 921 pr_info("%s: Driver unloaded\n", dev_info); 922 } 923 module_exit(ath9k_exit); 924