1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 bool is_ath9k_unloaded; 61 /* We use the hw_value as an index into our private channel structure */ 62 63 #define CHAN2G(_freq, _idx) { \ 64 .band = IEEE80211_BAND_2GHZ, \ 65 .center_freq = (_freq), \ 66 .hw_value = (_idx), \ 67 .max_power = 20, \ 68 } 69 70 #define CHAN5G(_freq, _idx) { \ 71 .band = IEEE80211_BAND_5GHZ, \ 72 .center_freq = (_freq), \ 73 .hw_value = (_idx), \ 74 .max_power = 20, \ 75 } 76 77 /* Some 2 GHz radios are actually tunable on 2312-2732 78 * on 5 MHz steps, we support the channels which we know 79 * we have calibration data for all cards though to make 80 * this static */ 81 static const struct ieee80211_channel ath9k_2ghz_chantable[] = { 82 CHAN2G(2412, 0), /* Channel 1 */ 83 CHAN2G(2417, 1), /* Channel 2 */ 84 CHAN2G(2422, 2), /* Channel 3 */ 85 CHAN2G(2427, 3), /* Channel 4 */ 86 CHAN2G(2432, 4), /* Channel 5 */ 87 CHAN2G(2437, 5), /* Channel 6 */ 88 CHAN2G(2442, 6), /* Channel 7 */ 89 CHAN2G(2447, 7), /* Channel 8 */ 90 CHAN2G(2452, 8), /* Channel 9 */ 91 CHAN2G(2457, 9), /* Channel 10 */ 92 CHAN2G(2462, 10), /* Channel 11 */ 93 CHAN2G(2467, 11), /* Channel 12 */ 94 CHAN2G(2472, 12), /* Channel 13 */ 95 CHAN2G(2484, 13), /* Channel 14 */ 96 }; 97 98 /* Some 5 GHz radios are actually tunable on XXXX-YYYY 99 * on 5 MHz steps, we support the channels which we know 100 * we have calibration data for all cards though to make 101 * this static */ 102 static const struct ieee80211_channel ath9k_5ghz_chantable[] = { 103 /* _We_ call this UNII 1 */ 104 CHAN5G(5180, 14), /* Channel 36 */ 105 CHAN5G(5200, 15), /* Channel 40 */ 106 CHAN5G(5220, 16), /* Channel 44 */ 107 CHAN5G(5240, 17), /* Channel 48 */ 108 /* _We_ call this UNII 2 */ 109 CHAN5G(5260, 18), /* Channel 52 */ 110 CHAN5G(5280, 19), /* Channel 56 */ 111 CHAN5G(5300, 20), /* Channel 60 */ 112 CHAN5G(5320, 21), /* Channel 64 */ 113 /* _We_ call this "Middle band" */ 114 CHAN5G(5500, 22), /* Channel 100 */ 115 CHAN5G(5520, 23), /* Channel 104 */ 116 CHAN5G(5540, 24), /* Channel 108 */ 117 CHAN5G(5560, 25), /* Channel 112 */ 118 CHAN5G(5580, 26), /* Channel 116 */ 119 CHAN5G(5600, 27), /* Channel 120 */ 120 CHAN5G(5620, 28), /* Channel 124 */ 121 CHAN5G(5640, 29), /* Channel 128 */ 122 CHAN5G(5660, 30), /* Channel 132 */ 123 CHAN5G(5680, 31), /* Channel 136 */ 124 CHAN5G(5700, 32), /* Channel 140 */ 125 /* _We_ call this UNII 3 */ 126 CHAN5G(5745, 33), /* Channel 149 */ 127 CHAN5G(5765, 34), /* Channel 153 */ 128 CHAN5G(5785, 35), /* Channel 157 */ 129 CHAN5G(5805, 36), /* Channel 161 */ 130 CHAN5G(5825, 37), /* Channel 165 */ 131 }; 132 133 /* Atheros hardware rate code addition for short premble */ 134 #define SHPCHECK(__hw_rate, __flags) \ 135 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) 136 137 #define RATE(_bitrate, _hw_rate, _flags) { \ 138 .bitrate = (_bitrate), \ 139 .flags = (_flags), \ 140 .hw_value = (_hw_rate), \ 141 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 142 } 143 144 static struct ieee80211_rate ath9k_legacy_rates[] = { 145 RATE(10, 0x1b, 0), 146 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), 147 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), 148 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), 149 RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ | 150 IEEE80211_RATE_SUPPORTS_10MHZ)), 151 RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ | 152 IEEE80211_RATE_SUPPORTS_10MHZ)), 153 RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ | 154 IEEE80211_RATE_SUPPORTS_10MHZ)), 155 RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ | 156 IEEE80211_RATE_SUPPORTS_10MHZ)), 157 RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ | 158 IEEE80211_RATE_SUPPORTS_10MHZ)), 159 RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ | 160 IEEE80211_RATE_SUPPORTS_10MHZ)), 161 RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ | 162 IEEE80211_RATE_SUPPORTS_10MHZ)), 163 RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ | 164 IEEE80211_RATE_SUPPORTS_10MHZ)), 165 }; 166 167 #ifdef CONFIG_MAC80211_LEDS 168 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 169 { .throughput = 0 * 1024, .blink_time = 334 }, 170 { .throughput = 1 * 1024, .blink_time = 260 }, 171 { .throughput = 5 * 1024, .blink_time = 220 }, 172 { .throughput = 10 * 1024, .blink_time = 190 }, 173 { .throughput = 20 * 1024, .blink_time = 170 }, 174 { .throughput = 50 * 1024, .blink_time = 150 }, 175 { .throughput = 70 * 1024, .blink_time = 130 }, 176 { .throughput = 100 * 1024, .blink_time = 110 }, 177 { .throughput = 200 * 1024, .blink_time = 80 }, 178 { .throughput = 300 * 1024, .blink_time = 50 }, 179 }; 180 #endif 181 182 static void ath9k_deinit_softc(struct ath_softc *sc); 183 184 /* 185 * Read and write, they both share the same lock. We do this to serialize 186 * reads and writes on Atheros 802.11n PCI devices only. This is required 187 * as the FIFO on these devices can only accept sanely 2 requests. 188 */ 189 190 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 191 { 192 struct ath_hw *ah = (struct ath_hw *) hw_priv; 193 struct ath_common *common = ath9k_hw_common(ah); 194 struct ath_softc *sc = (struct ath_softc *) common->priv; 195 196 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 197 unsigned long flags; 198 spin_lock_irqsave(&sc->sc_serial_rw, flags); 199 iowrite32(val, sc->mem + reg_offset); 200 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 201 } else 202 iowrite32(val, sc->mem + reg_offset); 203 } 204 205 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 206 { 207 struct ath_hw *ah = (struct ath_hw *) hw_priv; 208 struct ath_common *common = ath9k_hw_common(ah); 209 struct ath_softc *sc = (struct ath_softc *) common->priv; 210 u32 val; 211 212 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 213 unsigned long flags; 214 spin_lock_irqsave(&sc->sc_serial_rw, flags); 215 val = ioread32(sc->mem + reg_offset); 216 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 217 } else 218 val = ioread32(sc->mem + reg_offset); 219 return val; 220 } 221 222 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 223 u32 set, u32 clr) 224 { 225 u32 val; 226 227 val = ioread32(sc->mem + reg_offset); 228 val &= ~clr; 229 val |= set; 230 iowrite32(val, sc->mem + reg_offset); 231 232 return val; 233 } 234 235 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 236 { 237 struct ath_hw *ah = (struct ath_hw *) hw_priv; 238 struct ath_common *common = ath9k_hw_common(ah); 239 struct ath_softc *sc = (struct ath_softc *) common->priv; 240 unsigned long uninitialized_var(flags); 241 u32 val; 242 243 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 244 spin_lock_irqsave(&sc->sc_serial_rw, flags); 245 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 246 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 247 } else 248 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 249 250 return val; 251 } 252 253 /**************************/ 254 /* Initialization */ 255 /**************************/ 256 257 static void setup_ht_cap(struct ath_softc *sc, 258 struct ieee80211_sta_ht_cap *ht_info) 259 { 260 struct ath_hw *ah = sc->sc_ah; 261 struct ath_common *common = ath9k_hw_common(ah); 262 u8 tx_streams, rx_streams; 263 int i, max_streams; 264 265 ht_info->ht_supported = true; 266 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 267 IEEE80211_HT_CAP_SM_PS | 268 IEEE80211_HT_CAP_SGI_40 | 269 IEEE80211_HT_CAP_DSSSCCK40; 270 271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) 272 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; 273 274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 275 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 276 277 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 278 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 279 280 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) 281 max_streams = 1; 282 else if (AR_SREV_9462(ah)) 283 max_streams = 2; 284 else if (AR_SREV_9300_20_OR_LATER(ah)) 285 max_streams = 3; 286 else 287 max_streams = 2; 288 289 if (AR_SREV_9280_20_OR_LATER(ah)) { 290 if (max_streams >= 2) 291 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; 292 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 293 } 294 295 /* set up supported mcs set */ 296 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 297 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); 298 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); 299 300 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", 301 tx_streams, rx_streams); 302 303 if (tx_streams != rx_streams) { 304 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 305 ht_info->mcs.tx_params |= ((tx_streams - 1) << 306 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 307 } 308 309 for (i = 0; i < rx_streams; i++) 310 ht_info->mcs.rx_mask[i] = 0xff; 311 312 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 313 } 314 315 static void ath9k_reg_notifier(struct wiphy *wiphy, 316 struct regulatory_request *request) 317 { 318 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 319 struct ath_softc *sc = hw->priv; 320 struct ath_hw *ah = sc->sc_ah; 321 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 322 323 ath_reg_notifier_apply(wiphy, request, reg); 324 325 /* Set tx power */ 326 if (ah->curchan) { 327 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 328 ath9k_ps_wakeup(sc); 329 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 330 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 331 /* synchronize DFS detector if regulatory domain changed */ 332 if (sc->dfs_detector != NULL) 333 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 334 request->dfs_region); 335 ath9k_ps_restore(sc); 336 } 337 } 338 339 /* 340 * This function will allocate both the DMA descriptor structure, and the 341 * buffers it contains. These are used to contain the descriptors used 342 * by the system. 343 */ 344 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 345 struct list_head *head, const char *name, 346 int nbuf, int ndesc, bool is_tx) 347 { 348 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 349 u8 *ds; 350 struct ath_buf *bf; 351 int i, bsize, desc_len; 352 353 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 354 name, nbuf, ndesc); 355 356 INIT_LIST_HEAD(head); 357 358 if (is_tx) 359 desc_len = sc->sc_ah->caps.tx_desc_len; 360 else 361 desc_len = sizeof(struct ath_desc); 362 363 /* ath_desc must be a multiple of DWORDs */ 364 if ((desc_len % 4) != 0) { 365 ath_err(common, "ath_desc not DWORD aligned\n"); 366 BUG_ON((desc_len % 4) != 0); 367 return -ENOMEM; 368 } 369 370 dd->dd_desc_len = desc_len * nbuf * ndesc; 371 372 /* 373 * Need additional DMA memory because we can't use 374 * descriptors that cross the 4K page boundary. Assume 375 * one skipped descriptor per 4K page. 376 */ 377 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 378 u32 ndesc_skipped = 379 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 380 u32 dma_len; 381 382 while (ndesc_skipped) { 383 dma_len = ndesc_skipped * desc_len; 384 dd->dd_desc_len += dma_len; 385 386 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 387 } 388 } 389 390 /* allocate descriptors */ 391 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 392 &dd->dd_desc_paddr, GFP_KERNEL); 393 if (!dd->dd_desc) 394 return -ENOMEM; 395 396 ds = (u8 *) dd->dd_desc; 397 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 398 name, ds, (u32) dd->dd_desc_len, 399 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 400 401 /* allocate buffers */ 402 bsize = sizeof(struct ath_buf) * nbuf; 403 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 404 if (!bf) 405 return -ENOMEM; 406 407 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 408 bf->bf_desc = ds; 409 bf->bf_daddr = DS2PHYS(dd, ds); 410 411 if (!(sc->sc_ah->caps.hw_caps & 412 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 413 /* 414 * Skip descriptor addresses which can cause 4KB 415 * boundary crossing (addr + length) with a 32 dword 416 * descriptor fetch. 417 */ 418 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 419 BUG_ON((caddr_t) bf->bf_desc >= 420 ((caddr_t) dd->dd_desc + 421 dd->dd_desc_len)); 422 423 ds += (desc_len * ndesc); 424 bf->bf_desc = ds; 425 bf->bf_daddr = DS2PHYS(dd, ds); 426 } 427 } 428 list_add_tail(&bf->list, head); 429 } 430 return 0; 431 } 432 433 static int ath9k_init_queues(struct ath_softc *sc) 434 { 435 int i = 0; 436 437 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 438 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 439 440 sc->config.cabqReadytime = ATH_CABQ_READY_TIME; 441 ath_cabq_update(sc); 442 443 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 444 445 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 446 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 447 sc->tx.txq_map[i]->mac80211_qnum = i; 448 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 449 } 450 return 0; 451 } 452 453 static int ath9k_init_channels_rates(struct ath_softc *sc) 454 { 455 void *channels; 456 457 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + 458 ARRAY_SIZE(ath9k_5ghz_chantable) != 459 ATH9K_NUM_CHANNELS); 460 461 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 462 channels = devm_kzalloc(sc->dev, 463 sizeof(ath9k_2ghz_chantable), GFP_KERNEL); 464 if (!channels) 465 return -ENOMEM; 466 467 memcpy(channels, ath9k_2ghz_chantable, 468 sizeof(ath9k_2ghz_chantable)); 469 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; 470 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 471 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 472 ARRAY_SIZE(ath9k_2ghz_chantable); 473 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 474 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 475 ARRAY_SIZE(ath9k_legacy_rates); 476 } 477 478 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 479 channels = devm_kzalloc(sc->dev, 480 sizeof(ath9k_5ghz_chantable), GFP_KERNEL); 481 if (!channels) 482 return -ENOMEM; 483 484 memcpy(channels, ath9k_5ghz_chantable, 485 sizeof(ath9k_5ghz_chantable)); 486 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; 487 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 488 sc->sbands[IEEE80211_BAND_5GHZ].n_channels = 489 ARRAY_SIZE(ath9k_5ghz_chantable); 490 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 491 ath9k_legacy_rates + 4; 492 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 493 ARRAY_SIZE(ath9k_legacy_rates) - 4; 494 } 495 return 0; 496 } 497 498 static void ath9k_init_misc(struct ath_softc *sc) 499 { 500 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 501 int i = 0; 502 503 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 504 505 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 506 sc->config.txpowlimit = ATH_TXPOWER_MAX; 507 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 508 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 509 510 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 511 sc->beacon.bslot[i] = NULL; 512 513 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 514 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 515 516 sc->spec_config.enabled = 0; 517 sc->spec_config.short_repeat = true; 518 sc->spec_config.count = 8; 519 sc->spec_config.endless = false; 520 sc->spec_config.period = 0xFF; 521 sc->spec_config.fft_period = 0xF; 522 } 523 524 static void ath9k_init_platform(struct ath_softc *sc) 525 { 526 struct ath_hw *ah = sc->sc_ah; 527 struct ath9k_hw_capabilities *pCap = &ah->caps; 528 struct ath_common *common = ath9k_hw_common(ah); 529 530 if (common->bus_ops->ath_bus_type != ATH_PCI) 531 return; 532 533 if (sc->driver_data & (ATH9K_PCI_CUS198 | 534 ATH9K_PCI_CUS230)) { 535 ah->config.xlna_gpio = 9; 536 ah->config.xatten_margin_cfg = true; 537 ah->config.alt_mingainidx = true; 538 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 539 sc->ant_comb.low_rssi_thresh = 20; 540 sc->ant_comb.fast_div_bias = 3; 541 542 ath_info(common, "Set parameters for %s\n", 543 (sc->driver_data & ATH9K_PCI_CUS198) ? 544 "CUS198" : "CUS230"); 545 } 546 547 if (sc->driver_data & ATH9K_PCI_CUS217) 548 ath_info(common, "CUS217 card detected\n"); 549 550 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 551 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 552 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 553 } 554 555 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 556 ah->config.pcie_waen = 0x0040473b; 557 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 558 } 559 } 560 561 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 562 void *ctx) 563 { 564 struct ath9k_eeprom_ctx *ec = ctx; 565 566 if (eeprom_blob) 567 ec->ah->eeprom_blob = eeprom_blob; 568 569 complete(&ec->complete); 570 } 571 572 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 573 { 574 struct ath9k_eeprom_ctx ec; 575 struct ath_hw *ah = ah = sc->sc_ah; 576 int err; 577 578 /* try to load the EEPROM content asynchronously */ 579 init_completion(&ec.complete); 580 ec.ah = sc->sc_ah; 581 582 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 583 &ec, ath9k_eeprom_request_cb); 584 if (err < 0) { 585 ath_err(ath9k_hw_common(ah), 586 "EEPROM request failed\n"); 587 return err; 588 } 589 590 wait_for_completion(&ec.complete); 591 592 if (!ah->eeprom_blob) { 593 ath_err(ath9k_hw_common(ah), 594 "Unable to load EEPROM file %s\n", name); 595 return -EINVAL; 596 } 597 598 return 0; 599 } 600 601 static void ath9k_eeprom_release(struct ath_softc *sc) 602 { 603 release_firmware(sc->sc_ah->eeprom_blob); 604 } 605 606 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 607 const struct ath_bus_ops *bus_ops) 608 { 609 struct ath9k_platform_data *pdata = sc->dev->platform_data; 610 struct ath_hw *ah = NULL; 611 struct ath9k_hw_capabilities *pCap; 612 struct ath_common *common; 613 int ret = 0, i; 614 int csz = 0; 615 616 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 617 if (!ah) 618 return -ENOMEM; 619 620 ah->dev = sc->dev; 621 ah->hw = sc->hw; 622 ah->hw_version.devid = devid; 623 ah->reg_ops.read = ath9k_ioread32; 624 ah->reg_ops.write = ath9k_iowrite32; 625 ah->reg_ops.rmw = ath9k_reg_rmw; 626 atomic_set(&ah->intr_ref_cnt, -1); 627 sc->sc_ah = ah; 628 pCap = &ah->caps; 629 630 sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET); 631 632 if (!pdata) { 633 ah->ah_flags |= AH_USE_EEPROM; 634 sc->sc_ah->led_pin = -1; 635 } else { 636 sc->sc_ah->gpio_mask = pdata->gpio_mask; 637 sc->sc_ah->gpio_val = pdata->gpio_val; 638 sc->sc_ah->led_pin = pdata->led_pin; 639 ah->is_clk_25mhz = pdata->is_clk_25mhz; 640 ah->get_mac_revision = pdata->get_mac_revision; 641 ah->external_reset = pdata->external_reset; 642 } 643 644 common = ath9k_hw_common(ah); 645 common->ops = &ah->reg_ops; 646 common->bus_ops = bus_ops; 647 common->ah = ah; 648 common->hw = sc->hw; 649 common->priv = sc; 650 common->debug_mask = ath9k_debug; 651 common->btcoex_enabled = ath9k_btcoex_enable == 1; 652 common->disable_ani = false; 653 654 /* 655 * Platform quirks. 656 */ 657 ath9k_init_platform(sc); 658 659 /* 660 * Enable WLAN/BT RX Antenna diversity only when: 661 * 662 * - BTCOEX is disabled. 663 * - the user manually requests the feature. 664 * - the HW cap is set using the platform data. 665 */ 666 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 667 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 668 common->bt_ant_diversity = 1; 669 670 spin_lock_init(&common->cc_lock); 671 672 spin_lock_init(&sc->sc_serial_rw); 673 spin_lock_init(&sc->sc_pm_lock); 674 mutex_init(&sc->mutex); 675 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 676 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 677 (unsigned long)sc); 678 679 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 680 INIT_WORK(&sc->hw_check_work, ath_hw_check); 681 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 682 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 683 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); 684 685 /* 686 * Cache line size is used to size and align various 687 * structures used to communicate with the hardware. 688 */ 689 ath_read_cachesize(common, &csz); 690 common->cachelsz = csz << 2; /* convert to bytes */ 691 692 if (pdata && pdata->eeprom_name) { 693 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 694 if (ret) 695 return ret; 696 } 697 698 /* Initializes the hardware for all supported chipsets */ 699 ret = ath9k_hw_init(ah); 700 if (ret) 701 goto err_hw; 702 703 if (pdata && pdata->macaddr) 704 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 705 706 ret = ath9k_init_queues(sc); 707 if (ret) 708 goto err_queues; 709 710 ret = ath9k_init_btcoex(sc); 711 if (ret) 712 goto err_btcoex; 713 714 ret = ath9k_init_channels_rates(sc); 715 if (ret) 716 goto err_btcoex; 717 718 ath9k_cmn_init_crypto(sc->sc_ah); 719 ath9k_init_misc(sc); 720 ath_fill_led_pin(sc); 721 722 if (common->bus_ops->aspm_init) 723 common->bus_ops->aspm_init(common); 724 725 return 0; 726 727 err_btcoex: 728 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 729 if (ATH_TXQ_SETUP(sc, i)) 730 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 731 err_queues: 732 ath9k_hw_deinit(ah); 733 err_hw: 734 ath9k_eeprom_release(sc); 735 return ret; 736 } 737 738 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 739 { 740 struct ieee80211_supported_band *sband; 741 struct ieee80211_channel *chan; 742 struct ath_hw *ah = sc->sc_ah; 743 struct cfg80211_chan_def chandef; 744 int i; 745 746 sband = &sc->sbands[band]; 747 for (i = 0; i < sband->n_channels; i++) { 748 chan = &sband->channels[i]; 749 ah->curchan = &ah->channels[chan->hw_value]; 750 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 751 ath9k_cmn_update_ichannel(ah->curchan, &chandef); 752 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 753 } 754 } 755 756 static void ath9k_init_txpower_limits(struct ath_softc *sc) 757 { 758 struct ath_hw *ah = sc->sc_ah; 759 struct ath9k_channel *curchan = ah->curchan; 760 761 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 762 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 763 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 764 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 765 766 ah->curchan = curchan; 767 } 768 769 void ath9k_reload_chainmask_settings(struct ath_softc *sc) 770 { 771 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) 772 return; 773 774 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 775 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 776 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 777 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 778 } 779 780 static const struct ieee80211_iface_limit if_limits[] = { 781 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | 782 BIT(NL80211_IFTYPE_P2P_CLIENT) | 783 BIT(NL80211_IFTYPE_WDS) }, 784 { .max = 8, .types = 785 #ifdef CONFIG_MAC80211_MESH 786 BIT(NL80211_IFTYPE_MESH_POINT) | 787 #endif 788 BIT(NL80211_IFTYPE_AP) | 789 BIT(NL80211_IFTYPE_P2P_GO) }, 790 }; 791 792 793 static const struct ieee80211_iface_limit if_dfs_limits[] = { 794 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) }, 795 }; 796 797 static const struct ieee80211_iface_combination if_comb[] = { 798 { 799 .limits = if_limits, 800 .n_limits = ARRAY_SIZE(if_limits), 801 .max_interfaces = 2048, 802 .num_different_channels = 1, 803 .beacon_int_infra_match = true, 804 }, 805 { 806 .limits = if_dfs_limits, 807 .n_limits = ARRAY_SIZE(if_dfs_limits), 808 .max_interfaces = 1, 809 .num_different_channels = 1, 810 .beacon_int_infra_match = true, 811 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) | 812 BIT(NL80211_CHAN_HT20), 813 } 814 }; 815 816 #ifdef CONFIG_PM 817 static const struct wiphy_wowlan_support ath9k_wowlan_support = { 818 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 819 .n_patterns = MAX_NUM_USER_PATTERN, 820 .pattern_min_len = 1, 821 .pattern_max_len = MAX_PATTERN_SIZE, 822 }; 823 #endif 824 825 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 826 { 827 struct ath_hw *ah = sc->sc_ah; 828 struct ath_common *common = ath9k_hw_common(ah); 829 830 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 831 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 832 IEEE80211_HW_SIGNAL_DBM | 833 IEEE80211_HW_SUPPORTS_PS | 834 IEEE80211_HW_PS_NULLFUNC_STACK | 835 IEEE80211_HW_SPECTRUM_MGMT | 836 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 837 IEEE80211_HW_SUPPORTS_RC_TABLE | 838 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 839 840 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 841 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 842 843 if (AR_SREV_9280_20_OR_LATER(ah)) 844 hw->radiotap_mcs_details |= 845 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 846 } 847 848 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 849 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 850 851 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; 852 853 hw->wiphy->interface_modes = 854 BIT(NL80211_IFTYPE_P2P_GO) | 855 BIT(NL80211_IFTYPE_P2P_CLIENT) | 856 BIT(NL80211_IFTYPE_AP) | 857 BIT(NL80211_IFTYPE_WDS) | 858 BIT(NL80211_IFTYPE_STATION) | 859 BIT(NL80211_IFTYPE_ADHOC) | 860 BIT(NL80211_IFTYPE_MESH_POINT); 861 862 hw->wiphy->iface_combinations = if_comb; 863 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 864 865 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 866 867 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 868 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 869 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 870 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 871 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 872 873 #ifdef CONFIG_PM_SLEEP 874 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && 875 (sc->driver_data & ATH9K_PCI_WOW) && 876 device_can_wakeup(sc->dev)) 877 hw->wiphy->wowlan = &ath9k_wowlan_support; 878 879 atomic_set(&sc->wow_sleep_proc_intr, -1); 880 atomic_set(&sc->wow_got_bmiss_intr, -1); 881 #endif 882 883 hw->queues = 4; 884 hw->max_rates = 4; 885 hw->channel_change_time = 5000; 886 hw->max_listen_interval = 1; 887 hw->max_rate_tries = 10; 888 hw->sta_data_size = sizeof(struct ath_node); 889 hw->vif_data_size = sizeof(struct ath_vif); 890 891 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 892 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 893 894 /* single chain devices with rx diversity */ 895 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 896 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 897 898 sc->ant_rx = hw->wiphy->available_antennas_rx; 899 sc->ant_tx = hw->wiphy->available_antennas_tx; 900 901 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 902 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 903 &sc->sbands[IEEE80211_BAND_2GHZ]; 904 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 905 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 906 &sc->sbands[IEEE80211_BAND_5GHZ]; 907 908 ath9k_reload_chainmask_settings(sc); 909 910 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 911 } 912 913 int ath9k_init_device(u16 devid, struct ath_softc *sc, 914 const struct ath_bus_ops *bus_ops) 915 { 916 struct ieee80211_hw *hw = sc->hw; 917 struct ath_common *common; 918 struct ath_hw *ah; 919 int error = 0; 920 struct ath_regulatory *reg; 921 922 /* Bring up device */ 923 error = ath9k_init_softc(devid, sc, bus_ops); 924 if (error) 925 return error; 926 927 ah = sc->sc_ah; 928 common = ath9k_hw_common(ah); 929 ath9k_set_hw_capab(sc, hw); 930 931 /* Initialize regulatory */ 932 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 933 ath9k_reg_notifier); 934 if (error) 935 goto deinit; 936 937 reg = &common->regulatory; 938 939 /* Setup TX DMA */ 940 error = ath_tx_init(sc, ATH_TXBUF); 941 if (error != 0) 942 goto deinit; 943 944 /* Setup RX DMA */ 945 error = ath_rx_init(sc, ATH_RXBUF); 946 if (error != 0) 947 goto deinit; 948 949 ath9k_init_txpower_limits(sc); 950 951 #ifdef CONFIG_MAC80211_LEDS 952 /* must be initialized before ieee80211_register_hw */ 953 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 954 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 955 ARRAY_SIZE(ath9k_tpt_blink)); 956 #endif 957 958 /* Register with mac80211 */ 959 error = ieee80211_register_hw(hw); 960 if (error) 961 goto rx_cleanup; 962 963 error = ath9k_init_debug(ah); 964 if (error) { 965 ath_err(common, "Unable to create debugfs files\n"); 966 goto unregister; 967 } 968 969 /* Handle world regulatory */ 970 if (!ath_is_world_regd(reg)) { 971 error = regulatory_hint(hw->wiphy, reg->alpha2); 972 if (error) 973 goto debug_cleanup; 974 } 975 976 ath_init_leds(sc); 977 ath_start_rfkill_poll(sc); 978 979 return 0; 980 981 debug_cleanup: 982 ath9k_deinit_debug(sc); 983 unregister: 984 ieee80211_unregister_hw(hw); 985 rx_cleanup: 986 ath_rx_cleanup(sc); 987 deinit: 988 ath9k_deinit_softc(sc); 989 return error; 990 } 991 992 /*****************************/ 993 /* De-Initialization */ 994 /*****************************/ 995 996 static void ath9k_deinit_softc(struct ath_softc *sc) 997 { 998 int i = 0; 999 1000 ath9k_deinit_btcoex(sc); 1001 1002 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1003 if (ATH_TXQ_SETUP(sc, i)) 1004 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1005 1006 ath9k_hw_deinit(sc->sc_ah); 1007 if (sc->dfs_detector != NULL) 1008 sc->dfs_detector->exit(sc->dfs_detector); 1009 1010 ath9k_eeprom_release(sc); 1011 } 1012 1013 void ath9k_deinit_device(struct ath_softc *sc) 1014 { 1015 struct ieee80211_hw *hw = sc->hw; 1016 1017 ath9k_ps_wakeup(sc); 1018 1019 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1020 ath_deinit_leds(sc); 1021 1022 ath9k_ps_restore(sc); 1023 1024 ath9k_deinit_debug(sc); 1025 ieee80211_unregister_hw(hw); 1026 ath_rx_cleanup(sc); 1027 ath9k_deinit_softc(sc); 1028 } 1029 1030 /************************/ 1031 /* Module Hooks */ 1032 /************************/ 1033 1034 static int __init ath9k_init(void) 1035 { 1036 int error; 1037 1038 /* Register rate control algorithm */ 1039 error = ath_rate_control_register(); 1040 if (error != 0) { 1041 pr_err("Unable to register rate control algorithm: %d\n", 1042 error); 1043 goto err_out; 1044 } 1045 1046 error = ath_pci_init(); 1047 if (error < 0) { 1048 pr_err("No PCI devices found, driver not installed\n"); 1049 error = -ENODEV; 1050 goto err_rate_unregister; 1051 } 1052 1053 error = ath_ahb_init(); 1054 if (error < 0) { 1055 error = -ENODEV; 1056 goto err_pci_exit; 1057 } 1058 1059 return 0; 1060 1061 err_pci_exit: 1062 ath_pci_exit(); 1063 1064 err_rate_unregister: 1065 ath_rate_control_unregister(); 1066 err_out: 1067 return error; 1068 } 1069 module_init(ath9k_init); 1070 1071 static void __exit ath9k_exit(void) 1072 { 1073 is_ath9k_unloaded = true; 1074 ath_ahb_exit(); 1075 ath_pci_exit(); 1076 ath_rate_control_unregister(); 1077 pr_info("%s: Driver unloaded\n", dev_info); 1078 } 1079 module_exit(ath9k_exit); 1080