1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "phy.h" 31 #include "btcoex.h" 32 #include "dynack.h" 33 34 #include "../regd.h" 35 36 #define ATHEROS_VENDOR_ID 0x168c 37 38 #define AR5416_DEVID_PCI 0x0023 39 #define AR5416_DEVID_PCIE 0x0024 40 #define AR9160_DEVID_PCI 0x0027 41 #define AR9280_DEVID_PCI 0x0029 42 #define AR9280_DEVID_PCIE 0x002a 43 #define AR9285_DEVID_PCIE 0x002b 44 #define AR2427_DEVID_PCIE 0x002c 45 #define AR9287_DEVID_PCI 0x002d 46 #define AR9287_DEVID_PCIE 0x002e 47 #define AR9300_DEVID_PCIE 0x0030 48 #define AR9300_DEVID_AR9340 0x0031 49 #define AR9300_DEVID_AR9485_PCIE 0x0032 50 #define AR9300_DEVID_AR9580 0x0033 51 #define AR9300_DEVID_AR9462 0x0034 52 #define AR9300_DEVID_AR9330 0x0035 53 #define AR9300_DEVID_QCA955X 0x0038 54 #define AR9485_DEVID_AR1111 0x0037 55 #define AR9300_DEVID_AR9565 0x0036 56 #define AR9300_DEVID_AR953X 0x003d 57 58 #define AR5416_AR9100_DEVID 0x000b 59 60 #define AR_SUBVENDOR_ID_NOG 0x0e11 61 #define AR_SUBVENDOR_ID_NEW_A 0x7065 62 #define AR5416_MAGIC 0x19641014 63 64 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 65 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 66 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 67 68 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 69 70 #define ATH_DEFAULT_NOISE_FLOOR -95 71 72 #define ATH9K_RSSI_BAD -128 73 74 #define ATH9K_NUM_CHANNELS 38 75 76 /* Register read/write primitives */ 77 #define REG_WRITE(_ah, _reg, _val) \ 78 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 79 80 #define REG_READ(_ah, _reg) \ 81 (_ah)->reg_ops.read((_ah), (_reg)) 82 83 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 84 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 85 86 #define REG_RMW(_ah, _reg, _set, _clr) \ 87 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 88 89 #define ENABLE_REGWRITE_BUFFER(_ah) \ 90 do { \ 91 if ((_ah)->reg_ops.enable_write_buffer) \ 92 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 93 } while (0) 94 95 #define REGWRITE_BUFFER_FLUSH(_ah) \ 96 do { \ 97 if ((_ah)->reg_ops.write_flush) \ 98 (_ah)->reg_ops.write_flush((_ah)); \ 99 } while (0) 100 101 #define PR_EEP(_s, _val) \ 102 do { \ 103 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ 104 _s, (_val)); \ 105 } while (0) 106 107 #define SM(_v, _f) (((_v) << _f##_S) & _f) 108 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 109 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 110 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 111 #define REG_READ_FIELD(_a, _r, _f) \ 112 (((REG_READ(_a, _r) & _f) >> _f##_S)) 113 #define REG_SET_BIT(_a, _r, _f) \ 114 REG_RMW(_a, _r, (_f), 0) 115 #define REG_CLR_BIT(_a, _r, _f) \ 116 REG_RMW(_a, _r, 0, (_f)) 117 118 #define DO_DELAY(x) do { \ 119 if (((++(x) % 64) == 0) && \ 120 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 121 != ATH_USB)) \ 122 udelay(1); \ 123 } while (0) 124 125 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 126 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 127 128 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 129 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 130 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 131 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 132 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 133 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 134 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 139 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 140 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 141 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 142 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 143 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 144 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 145 146 #define AR_GPIOD_MASK 0x00001FFF 147 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 148 149 #define BASE_ACTIVATE_DELAY 100 150 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 151 #define COEF_SCALE_S 24 152 #define HT40_CHANNEL_CENTER_SHIFT 10 153 154 #define ATH9K_ANTENNA0_CHAINMASK 0x1 155 #define ATH9K_ANTENNA1_CHAINMASK 0x2 156 157 #define ATH9K_NUM_DMA_DEBUG_REGS 8 158 #define ATH9K_NUM_QUEUES 10 159 160 #define MAX_RATE_POWER 63 161 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 162 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 163 #define AH_TIME_QUANTUM 10 164 #define AR_KEYTABLE_SIZE 128 165 #define POWER_UP_TIME 10000 166 #define SPUR_RSSI_THRESH 40 167 #define UPPER_5G_SUB_BAND_START 5700 168 #define MID_5G_SUB_BAND_START 5400 169 170 #define CAB_TIMEOUT_VAL 10 171 #define BEACON_TIMEOUT_VAL 10 172 #define MIN_BEACON_TIMEOUT_VAL 1 173 #define SLEEP_SLOP TU_TO_USEC(3) 174 175 #define INIT_CONFIG_STATUS 0x00000000 176 #define INIT_RSSI_THR 0x00000700 177 #define INIT_BCON_CNTRL_REG 0x00000000 178 179 #define TU_TO_USEC(_tu) ((_tu) << 10) 180 181 #define ATH9K_HW_RX_HP_QDEPTH 16 182 #define ATH9K_HW_RX_LP_QDEPTH 128 183 184 #define PAPRD_GAIN_TABLE_ENTRIES 32 185 #define PAPRD_TABLE_SZ 24 186 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 187 188 /* 189 * Wake on Wireless 190 */ 191 192 /* Keep Alive Frame */ 193 #define KAL_FRAME_LEN 28 194 #define KAL_FRAME_TYPE 0x2 /* data frame */ 195 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 196 #define KAL_DURATION_ID 0x3d 197 #define KAL_NUM_DATA_WORDS 6 198 #define KAL_NUM_DESC_WORDS 12 199 #define KAL_ANTENNA_MODE 1 200 #define KAL_TO_DS 1 201 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ 202 #define KAL_TIMEOUT 900 203 204 #define MAX_PATTERN_SIZE 256 205 #define MAX_PATTERN_MASK_SIZE 32 206 #define MAX_NUM_PATTERN 8 207 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 208 deauthenticate packets */ 209 210 /* 211 * WoW trigger mapping to hardware code 212 */ 213 214 #define AH_WOW_USER_PATTERN_EN BIT(0) 215 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 216 #define AH_WOW_LINK_CHANGE BIT(2) 217 #define AH_WOW_BEACON_MISS BIT(3) 218 219 enum ath_hw_txq_subtype { 220 ATH_TXQ_AC_BK = 0, 221 ATH_TXQ_AC_BE = 1, 222 ATH_TXQ_AC_VI = 2, 223 ATH_TXQ_AC_VO = 3, 224 }; 225 226 enum ath_ini_subsys { 227 ATH_INI_PRE = 0, 228 ATH_INI_CORE, 229 ATH_INI_POST, 230 ATH_INI_NUM_SPLIT, 231 }; 232 233 enum ath9k_hw_caps { 234 ATH9K_HW_CAP_HT = BIT(0), 235 ATH9K_HW_CAP_RFSILENT = BIT(1), 236 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 237 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 238 ATH9K_HW_CAP_EDMA = BIT(4), 239 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 240 ATH9K_HW_CAP_LDPC = BIT(6), 241 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 242 ATH9K_HW_CAP_SGI_20 = BIT(8), 243 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 244 ATH9K_HW_CAP_2GHZ = BIT(11), 245 ATH9K_HW_CAP_5GHZ = BIT(12), 246 ATH9K_HW_CAP_APM = BIT(13), 247 #ifdef CONFIG_ATH9K_PCOEM 248 ATH9K_HW_CAP_RTT = BIT(14), 249 ATH9K_HW_CAP_MCI = BIT(15), 250 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(16), 251 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), 252 #else 253 ATH9K_HW_CAP_RTT = 0, 254 ATH9K_HW_CAP_MCI = 0, 255 ATH9K_HW_WOW_DEVICE_CAPABLE = 0, 256 ATH9K_HW_CAP_BT_ANT_DIV = 0, 257 #endif 258 ATH9K_HW_CAP_DFS = BIT(18), 259 ATH9K_HW_CAP_PAPRD = BIT(19), 260 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), 261 }; 262 263 /* 264 * WoW device capabilities 265 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 266 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 267 * an exact user defined pattern or de-authentication/disassoc pattern. 268 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 269 * bytes of the pattern for user defined pattern, de-authentication and 270 * disassociation patterns for all types of possible frames recieved 271 * of those types. 272 */ 273 274 struct ath9k_hw_capabilities { 275 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 276 u16 rts_aggr_limit; 277 u8 tx_chainmask; 278 u8 rx_chainmask; 279 u8 chip_chainmask; 280 u8 max_txchains; 281 u8 max_rxchains; 282 u8 num_gpio_pins; 283 u8 rx_hp_qdepth; 284 u8 rx_lp_qdepth; 285 u8 rx_status_len; 286 u8 tx_desc_len; 287 u8 txs_len; 288 }; 289 290 #define AR_NO_SPUR 0x8000 291 #define AR_BASE_FREQ_2GHZ 2300 292 #define AR_BASE_FREQ_5GHZ 4900 293 #define AR_SPUR_FEEQ_BOUND_HT40 19 294 #define AR_SPUR_FEEQ_BOUND_HT20 10 295 296 enum ath9k_hw_hang_checks { 297 HW_BB_WATCHDOG = BIT(0), 298 HW_PHYRESTART_CLC_WAR = BIT(1), 299 HW_BB_RIFS_HANG = BIT(2), 300 HW_BB_DFS_HANG = BIT(3), 301 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), 302 HW_MAC_HANG = BIT(5), 303 }; 304 305 struct ath9k_ops_config { 306 int dma_beacon_response_time; 307 int sw_beacon_response_time; 308 u32 cwm_ignore_extcca; 309 u32 pcie_waen; 310 u8 analog_shiftreg; 311 u32 ofdm_trig_low; 312 u32 ofdm_trig_high; 313 u32 cck_trig_high; 314 u32 cck_trig_low; 315 u32 enable_paprd; 316 int serialize_regmode; 317 bool rx_intr_mitigation; 318 bool tx_intr_mitigation; 319 u8 max_txtrig_level; 320 u16 ani_poll_interval; /* ANI poll interval in ms */ 321 u16 hw_hang_checks; 322 u16 rimt_first; 323 u16 rimt_last; 324 325 /* Platform specific config */ 326 u32 aspm_l1_fix; 327 u32 xlna_gpio; 328 u32 ant_ctrl_comm2g_switch_enable; 329 bool xatten_margin_cfg; 330 bool alt_mingainidx; 331 bool no_pll_pwrsave; 332 bool tx_gain_buffalo; 333 bool led_active_high; 334 }; 335 336 enum ath9k_int { 337 ATH9K_INT_RX = 0x00000001, 338 ATH9K_INT_RXDESC = 0x00000002, 339 ATH9K_INT_RXHP = 0x00000001, 340 ATH9K_INT_RXLP = 0x00000002, 341 ATH9K_INT_RXNOFRM = 0x00000008, 342 ATH9K_INT_RXEOL = 0x00000010, 343 ATH9K_INT_RXORN = 0x00000020, 344 ATH9K_INT_TX = 0x00000040, 345 ATH9K_INT_TXDESC = 0x00000080, 346 ATH9K_INT_TIM_TIMER = 0x00000100, 347 ATH9K_INT_MCI = 0x00000200, 348 ATH9K_INT_BB_WATCHDOG = 0x00000400, 349 ATH9K_INT_TXURN = 0x00000800, 350 ATH9K_INT_MIB = 0x00001000, 351 ATH9K_INT_RXPHY = 0x00004000, 352 ATH9K_INT_RXKCM = 0x00008000, 353 ATH9K_INT_SWBA = 0x00010000, 354 ATH9K_INT_BMISS = 0x00040000, 355 ATH9K_INT_BNR = 0x00100000, 356 ATH9K_INT_TIM = 0x00200000, 357 ATH9K_INT_DTIM = 0x00400000, 358 ATH9K_INT_DTIMSYNC = 0x00800000, 359 ATH9K_INT_GPIO = 0x01000000, 360 ATH9K_INT_CABEND = 0x02000000, 361 ATH9K_INT_TSFOOR = 0x04000000, 362 ATH9K_INT_GENTIMER = 0x08000000, 363 ATH9K_INT_CST = 0x10000000, 364 ATH9K_INT_GTT = 0x20000000, 365 ATH9K_INT_FATAL = 0x40000000, 366 ATH9K_INT_GLOBAL = 0x80000000, 367 ATH9K_INT_BMISC = ATH9K_INT_TIM | 368 ATH9K_INT_DTIM | 369 ATH9K_INT_DTIMSYNC | 370 ATH9K_INT_TSFOOR | 371 ATH9K_INT_CABEND, 372 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 373 ATH9K_INT_RXDESC | 374 ATH9K_INT_RXEOL | 375 ATH9K_INT_RXORN | 376 ATH9K_INT_TXURN | 377 ATH9K_INT_TXDESC | 378 ATH9K_INT_MIB | 379 ATH9K_INT_RXPHY | 380 ATH9K_INT_RXKCM | 381 ATH9K_INT_SWBA | 382 ATH9K_INT_BMISS | 383 ATH9K_INT_GPIO, 384 ATH9K_INT_NOCARD = 0xffffffff 385 }; 386 387 #define MAX_RTT_TABLE_ENTRY 6 388 #define MAX_IQCAL_MEASUREMENT 8 389 #define MAX_CL_TAB_ENTRY 16 390 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) 391 392 enum ath9k_cal_flags { 393 RTT_DONE, 394 PAPRD_PACKET_SENT, 395 PAPRD_DONE, 396 NFCAL_PENDING, 397 NFCAL_INTF, 398 TXIQCAL_DONE, 399 TXCLCAL_DONE, 400 SW_PKDET_DONE, 401 }; 402 403 struct ath9k_hw_cal_data { 404 u16 channel; 405 u16 channelFlags; 406 unsigned long cal_flags; 407 int32_t CalValid; 408 int8_t iCoff; 409 int8_t qCoff; 410 u8 caldac[2]; 411 u16 small_signal_gain[AR9300_MAX_CHAINS]; 412 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 413 u32 num_measures[AR9300_MAX_CHAINS]; 414 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 415 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 416 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 417 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 418 }; 419 420 struct ath9k_channel { 421 struct ieee80211_channel *chan; 422 u16 channel; 423 u16 channelFlags; 424 s16 noisefloor; 425 }; 426 427 #define CHANNEL_5GHZ BIT(0) 428 #define CHANNEL_HALF BIT(1) 429 #define CHANNEL_QUARTER BIT(2) 430 #define CHANNEL_HT BIT(3) 431 #define CHANNEL_HT40PLUS BIT(4) 432 #define CHANNEL_HT40MINUS BIT(5) 433 434 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) 435 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 436 437 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) 438 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) 439 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 440 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 441 442 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) 443 444 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) 445 446 #define IS_CHAN_HT40(_c) \ 447 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) 448 449 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) 450 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) 451 452 enum ath9k_power_mode { 453 ATH9K_PM_AWAKE = 0, 454 ATH9K_PM_FULL_SLEEP, 455 ATH9K_PM_NETWORK_SLEEP, 456 ATH9K_PM_UNDEFINED 457 }; 458 459 enum ser_reg_mode { 460 SER_REG_MODE_OFF = 0, 461 SER_REG_MODE_ON = 1, 462 SER_REG_MODE_AUTO = 2, 463 }; 464 465 enum ath9k_rx_qtype { 466 ATH9K_RX_QUEUE_HP, 467 ATH9K_RX_QUEUE_LP, 468 ATH9K_RX_QUEUE_MAX, 469 }; 470 471 struct ath9k_beacon_state { 472 u32 bs_nexttbtt; 473 u32 bs_nextdtim; 474 u32 bs_intval; 475 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 476 u32 bs_dtimperiod; 477 u16 bs_bmissthreshold; 478 u32 bs_sleepduration; 479 u32 bs_tsfoor_threshold; 480 }; 481 482 struct chan_centers { 483 u16 synth_center; 484 u16 ctl_center; 485 u16 ext_center; 486 }; 487 488 enum { 489 ATH9K_RESET_POWER_ON, 490 ATH9K_RESET_WARM, 491 ATH9K_RESET_COLD, 492 }; 493 494 struct ath9k_hw_version { 495 u32 magic; 496 u16 devid; 497 u16 subvendorid; 498 u32 macVersion; 499 u16 macRev; 500 u16 phyRev; 501 u16 analog5GhzRev; 502 u16 analog2GhzRev; 503 enum ath_usb_dev usbdev; 504 }; 505 506 /* Generic TSF timer definitions */ 507 508 #define ATH_MAX_GEN_TIMER 16 509 510 #define AR_GENTMR_BIT(_index) (1 << (_index)) 511 512 struct ath_gen_timer_configuration { 513 u32 next_addr; 514 u32 period_addr; 515 u32 mode_addr; 516 u32 mode_mask; 517 }; 518 519 struct ath_gen_timer { 520 void (*trigger)(void *arg); 521 void (*overflow)(void *arg); 522 void *arg; 523 u8 index; 524 }; 525 526 struct ath_gen_timer_table { 527 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 528 u16 timer_mask; 529 bool tsf2_enabled; 530 }; 531 532 struct ath_hw_antcomb_conf { 533 u8 main_lna_conf; 534 u8 alt_lna_conf; 535 u8 fast_div_bias; 536 u8 main_gaintb; 537 u8 alt_gaintb; 538 int lna1_lna2_delta; 539 int lna1_lna2_switch_delta; 540 u8 div_group; 541 }; 542 543 /** 544 * struct ath_hw_radar_conf - radar detection initialization parameters 545 * 546 * @pulse_inband: threshold for checking the ratio of in-band power 547 * to total power for short radar pulses (half dB steps) 548 * @pulse_inband_step: threshold for checking an in-band power to total 549 * power ratio increase for short radar pulses (half dB steps) 550 * @pulse_height: threshold for detecting the beginning of a short 551 * radar pulse (dB step) 552 * @pulse_rssi: threshold for detecting if a short radar pulse is 553 * gone (dB step) 554 * @pulse_maxlen: maximum pulse length (0.8 us steps) 555 * 556 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 557 * @radar_inband: threshold for checking the ratio of in-band power 558 * to total power for long radar pulses (half dB steps) 559 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 560 * 561 * @ext_channel: enable extension channel radar detection 562 */ 563 struct ath_hw_radar_conf { 564 unsigned int pulse_inband; 565 unsigned int pulse_inband_step; 566 unsigned int pulse_height; 567 unsigned int pulse_rssi; 568 unsigned int pulse_maxlen; 569 570 unsigned int radar_rssi; 571 unsigned int radar_inband; 572 int fir_power; 573 574 bool ext_channel; 575 }; 576 577 /** 578 * struct ath_hw_private_ops - callbacks used internally by hardware code 579 * 580 * This structure contains private callbacks designed to only be used internally 581 * by the hardware core. 582 * 583 * @init_cal_settings: setup types of calibrations supported 584 * @init_cal: starts actual calibration 585 * 586 * @init_mode_gain_regs: Initialize TX/RX gain registers 587 * 588 * @rf_set_freq: change frequency 589 * @spur_mitigate_freq: spur mitigation 590 * @set_rf_regs: 591 * @compute_pll_control: compute the PLL control value to use for 592 * AR_RTC_PLL_CONTROL for a given channel 593 * @setup_calibration: set up calibration 594 * @iscal_supported: used to query if a type of calibration is supported 595 * 596 * @ani_cache_ini_regs: cache the values for ANI from the initial 597 * register settings through the register initialization. 598 */ 599 struct ath_hw_private_ops { 600 void (*init_hang_checks)(struct ath_hw *ah); 601 bool (*detect_mac_hang)(struct ath_hw *ah); 602 bool (*detect_bb_hang)(struct ath_hw *ah); 603 604 /* Calibration ops */ 605 void (*init_cal_settings)(struct ath_hw *ah); 606 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 607 608 void (*init_mode_gain_regs)(struct ath_hw *ah); 609 void (*setup_calibration)(struct ath_hw *ah, 610 struct ath9k_cal_list *currCal); 611 612 /* PHY ops */ 613 int (*rf_set_freq)(struct ath_hw *ah, 614 struct ath9k_channel *chan); 615 void (*spur_mitigate_freq)(struct ath_hw *ah, 616 struct ath9k_channel *chan); 617 bool (*set_rf_regs)(struct ath_hw *ah, 618 struct ath9k_channel *chan, 619 u16 modesIndex); 620 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 621 void (*init_bb)(struct ath_hw *ah, 622 struct ath9k_channel *chan); 623 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 624 void (*olc_init)(struct ath_hw *ah); 625 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 626 void (*mark_phy_inactive)(struct ath_hw *ah); 627 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 628 bool (*rfbus_req)(struct ath_hw *ah); 629 void (*rfbus_done)(struct ath_hw *ah); 630 void (*restore_chainmask)(struct ath_hw *ah); 631 u32 (*compute_pll_control)(struct ath_hw *ah, 632 struct ath9k_channel *chan); 633 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 634 int param); 635 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 636 void (*set_radar_params)(struct ath_hw *ah, 637 struct ath_hw_radar_conf *conf); 638 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 639 u8 *ini_reloaded); 640 641 /* ANI */ 642 void (*ani_cache_ini_regs)(struct ath_hw *ah); 643 }; 644 645 /** 646 * struct ath_spec_scan - parameters for Atheros spectral scan 647 * 648 * @enabled: enable/disable spectral scan 649 * @short_repeat: controls whether the chip is in spectral scan mode 650 * for 4 usec (enabled) or 204 usec (disabled) 651 * @count: number of scan results requested. There are special meanings 652 * in some chip revisions: 653 * AR92xx: highest bit set (>=128) for endless mode 654 * (spectral scan won't stopped until explicitly disabled) 655 * AR9300 and newer: 0 for endless mode 656 * @endless: true if endless mode is intended. Otherwise, count value is 657 * corrected to the next possible value. 658 * @period: time duration between successive spectral scan entry points 659 * (period*256*Tclk). Tclk = ath_common->clockrate 660 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS 661 * 662 * Note: Tclk = 40MHz or 44MHz depending upon operating mode. 663 * Typically it's 44MHz in 2/5GHz on later chips, but there's 664 * a "fast clock" check for this in 5GHz. 665 * 666 */ 667 struct ath_spec_scan { 668 bool enabled; 669 bool short_repeat; 670 bool endless; 671 u8 count; 672 u8 period; 673 u8 fft_period; 674 }; 675 676 /** 677 * struct ath_hw_ops - callbacks used by hardware code and driver code 678 * 679 * This structure contains callbacks designed to to be used internally by 680 * hardware code and also by the lower level driver. 681 * 682 * @config_pci_powersave: 683 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 684 * 685 * @spectral_scan_config: set parameters for spectral scan and enable/disable it 686 * @spectral_scan_trigger: trigger a spectral scan run 687 * @spectral_scan_wait: wait for a spectral scan run to finish 688 */ 689 struct ath_hw_ops { 690 void (*config_pci_powersave)(struct ath_hw *ah, 691 bool power_off); 692 void (*rx_enable)(struct ath_hw *ah); 693 void (*set_desc_link)(void *ds, u32 link); 694 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, 695 u8 rxchainmask, bool longcal); 696 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, 697 u32 *sync_cause_p); 698 void (*set_txdesc)(struct ath_hw *ah, void *ds, 699 struct ath_tx_info *i); 700 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 701 struct ath_tx_status *ts); 702 int (*get_duration)(struct ath_hw *ah, const void *ds, int index); 703 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 704 struct ath_hw_antcomb_conf *antconf); 705 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 706 struct ath_hw_antcomb_conf *antconf); 707 void (*spectral_scan_config)(struct ath_hw *ah, 708 struct ath_spec_scan *param); 709 void (*spectral_scan_trigger)(struct ath_hw *ah); 710 void (*spectral_scan_wait)(struct ath_hw *ah); 711 712 void (*tx99_start)(struct ath_hw *ah, u32 qnum); 713 void (*tx99_stop)(struct ath_hw *ah); 714 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); 715 716 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 717 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); 718 #endif 719 }; 720 721 struct ath_nf_limits { 722 s16 max; 723 s16 min; 724 s16 nominal; 725 }; 726 727 enum ath_cal_list { 728 TX_IQ_CAL = BIT(0), 729 TX_IQ_ON_AGC_CAL = BIT(1), 730 TX_CL_CAL = BIT(2), 731 }; 732 733 /* ah_flags */ 734 #define AH_USE_EEPROM 0x1 735 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 736 #define AH_FASTCC 0x4 737 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */ 738 739 struct ath_hw { 740 struct ath_ops reg_ops; 741 742 struct device *dev; 743 struct ieee80211_hw *hw; 744 struct ath_common common; 745 struct ath9k_hw_version hw_version; 746 struct ath9k_ops_config config; 747 struct ath9k_hw_capabilities caps; 748 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 749 struct ath9k_channel *curchan; 750 751 union { 752 struct ar5416_eeprom_def def; 753 struct ar5416_eeprom_4k map4k; 754 struct ar9287_eeprom map9287; 755 struct ar9300_eeprom ar9300_eep; 756 } eeprom; 757 const struct eeprom_ops *eep_ops; 758 759 bool sw_mgmt_crypto_tx; 760 bool sw_mgmt_crypto_rx; 761 bool is_pciexpress; 762 bool aspm_enabled; 763 bool is_monitoring; 764 bool need_an_top2_fixup; 765 u16 tx_trig_level; 766 767 u32 nf_regs[6]; 768 struct ath_nf_limits nf_2g; 769 struct ath_nf_limits nf_5g; 770 u16 rfsilent; 771 u32 rfkill_gpio; 772 u32 rfkill_polarity; 773 u32 ah_flags; 774 775 bool reset_power_on; 776 bool htc_reset_init; 777 778 enum nl80211_iftype opmode; 779 enum ath9k_power_mode power_mode; 780 781 s8 noise; 782 struct ath9k_hw_cal_data *caldata; 783 struct ath9k_pacal_info pacal_info; 784 struct ar5416Stats stats; 785 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 786 787 enum ath9k_int imask; 788 u32 imrs2_reg; 789 u32 txok_interrupt_mask; 790 u32 txerr_interrupt_mask; 791 u32 txdesc_interrupt_mask; 792 u32 txeol_interrupt_mask; 793 u32 txurn_interrupt_mask; 794 atomic_t intr_ref_cnt; 795 bool chip_fullsleep; 796 u32 modes_index; 797 798 /* Calibration */ 799 u32 supp_cals; 800 struct ath9k_cal_list iq_caldata; 801 struct ath9k_cal_list adcgain_caldata; 802 struct ath9k_cal_list adcdc_caldata; 803 struct ath9k_cal_list *cal_list; 804 struct ath9k_cal_list *cal_list_last; 805 struct ath9k_cal_list *cal_list_curr; 806 #define totalPowerMeasI meas0.unsign 807 #define totalPowerMeasQ meas1.unsign 808 #define totalIqCorrMeas meas2.sign 809 #define totalAdcIOddPhase meas0.unsign 810 #define totalAdcIEvenPhase meas1.unsign 811 #define totalAdcQOddPhase meas2.unsign 812 #define totalAdcQEvenPhase meas3.unsign 813 #define totalAdcDcOffsetIOddPhase meas0.sign 814 #define totalAdcDcOffsetIEvenPhase meas1.sign 815 #define totalAdcDcOffsetQOddPhase meas2.sign 816 #define totalAdcDcOffsetQEvenPhase meas3.sign 817 union { 818 u32 unsign[AR5416_MAX_CHAINS]; 819 int32_t sign[AR5416_MAX_CHAINS]; 820 } meas0; 821 union { 822 u32 unsign[AR5416_MAX_CHAINS]; 823 int32_t sign[AR5416_MAX_CHAINS]; 824 } meas1; 825 union { 826 u32 unsign[AR5416_MAX_CHAINS]; 827 int32_t sign[AR5416_MAX_CHAINS]; 828 } meas2; 829 union { 830 u32 unsign[AR5416_MAX_CHAINS]; 831 int32_t sign[AR5416_MAX_CHAINS]; 832 } meas3; 833 u16 cal_samples; 834 u8 enabled_cals; 835 836 u32 sta_id1_defaults; 837 u32 misc_mode; 838 839 /* Private to hardware code */ 840 struct ath_hw_private_ops private_ops; 841 /* Accessed by the lower level driver */ 842 struct ath_hw_ops ops; 843 844 /* Used to program the radio on non single-chip devices */ 845 u32 *analogBank6Data; 846 847 int coverage_class; 848 u32 slottime; 849 u32 globaltxtimeout; 850 851 /* ANI */ 852 u32 aniperiod; 853 enum ath9k_ani_cmd ani_function; 854 u32 ani_skip_count; 855 struct ar5416AniState ani; 856 857 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 858 struct ath_btcoex_hw btcoex_hw; 859 #endif 860 861 u32 intr_txqs; 862 u8 txchainmask; 863 u8 rxchainmask; 864 865 struct ath_hw_radar_conf radar_conf; 866 867 u32 originalGain[22]; 868 int initPDADC; 869 int PDADCdelta; 870 int led_pin; 871 u32 gpio_mask; 872 u32 gpio_val; 873 874 struct ar5416IniArray ini_dfs; 875 struct ar5416IniArray iniModes; 876 struct ar5416IniArray iniCommon; 877 struct ar5416IniArray iniBB_RfGain; 878 struct ar5416IniArray iniBank6; 879 struct ar5416IniArray iniAddac; 880 struct ar5416IniArray iniPcieSerdes; 881 struct ar5416IniArray iniPcieSerdesLowPower; 882 struct ar5416IniArray iniModesFastClock; 883 struct ar5416IniArray iniAdditional; 884 struct ar5416IniArray iniModesRxGain; 885 struct ar5416IniArray ini_modes_rx_gain_bounds; 886 struct ar5416IniArray iniModesTxGain; 887 struct ar5416IniArray iniCckfirNormal; 888 struct ar5416IniArray iniCckfirJapan2484; 889 struct ar5416IniArray iniModes_9271_ANI_reg; 890 struct ar5416IniArray ini_radio_post_sys2ant; 891 struct ar5416IniArray ini_modes_rxgain_5g_xlna; 892 struct ar5416IniArray ini_modes_rxgain_bb_core; 893 struct ar5416IniArray ini_modes_rxgain_bb_postamble; 894 895 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 896 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 897 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 898 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 899 900 u32 intr_gen_timer_trigger; 901 u32 intr_gen_timer_thresh; 902 struct ath_gen_timer_table hw_gen_timers; 903 904 struct ar9003_txs *ts_ring; 905 u32 ts_paddr_start; 906 u32 ts_paddr_end; 907 u16 ts_tail; 908 u16 ts_size; 909 910 u32 bb_watchdog_last_status; 911 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 912 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 913 914 unsigned int paprd_target_power; 915 unsigned int paprd_training_power; 916 unsigned int paprd_ratemask; 917 unsigned int paprd_ratemask_ht40; 918 bool paprd_table_write_done; 919 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 920 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 921 /* 922 * Store the permanent value of Reg 0x4004in WARegVal 923 * so we dont have to R/M/W. We should not be reading 924 * this register when in sleep states. 925 */ 926 u32 WARegVal; 927 928 /* Enterprise mode cap */ 929 u32 ent_mode; 930 931 #ifdef CONFIG_ATH9K_WOW 932 u32 wow_event_mask; 933 #endif 934 bool is_clk_25mhz; 935 int (*get_mac_revision)(void); 936 int (*external_reset)(void); 937 bool disable_2ghz; 938 bool disable_5ghz; 939 940 const struct firmware *eeprom_blob; 941 942 struct ath_dynack dynack; 943 944 bool tpc_enabled; 945 u8 tx_power[Ar5416RateSize]; 946 u8 tx_power_stbc[Ar5416RateSize]; 947 }; 948 949 struct ath_bus_ops { 950 enum ath_bus_type ath_bus_type; 951 void (*read_cachesize)(struct ath_common *common, int *csz); 952 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 953 void (*bt_coex_prep)(struct ath_common *common); 954 void (*aspm_init)(struct ath_common *common); 955 }; 956 957 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 958 { 959 return &ah->common; 960 } 961 962 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 963 { 964 return &(ath9k_hw_common(ah)->regulatory); 965 } 966 967 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 968 { 969 return &ah->private_ops; 970 } 971 972 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 973 { 974 return &ah->ops; 975 } 976 977 static inline u8 get_streams(int mask) 978 { 979 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 980 } 981 982 /* Initialization, Detach, Reset */ 983 void ath9k_hw_deinit(struct ath_hw *ah); 984 int ath9k_hw_init(struct ath_hw *ah); 985 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 986 struct ath9k_hw_cal_data *caldata, bool fastcc); 987 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 988 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 989 990 /* GPIO / RFKILL / Antennae */ 991 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 992 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 993 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 994 u32 ah_signal_type); 995 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 996 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 997 998 /* General Operation */ 999 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 1000 int hw_delay); 1001 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 1002 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 1003 int column, unsigned int *writecnt); 1004 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1005 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 1006 u8 phy, int kbps, 1007 u32 frameLen, u16 rateix, bool shortPreamble); 1008 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 1009 struct ath9k_channel *chan, 1010 struct chan_centers *centers); 1011 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 1012 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 1013 bool ath9k_hw_phy_disable(struct ath_hw *ah); 1014 bool ath9k_hw_disable(struct ath_hw *ah); 1015 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 1016 void ath9k_hw_setopmode(struct ath_hw *ah); 1017 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 1018 void ath9k_hw_write_associd(struct ath_hw *ah); 1019 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1020 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1021 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1022 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1023 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur); 1024 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1025 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1026 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1027 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); 1028 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1029 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1030 const struct ath9k_beacon_state *bs); 1031 void ath9k_hw_check_nav(struct ath_hw *ah); 1032 bool ath9k_hw_check_alive(struct ath_hw *ah); 1033 1034 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1035 1036 /* Generic hw timer primitives */ 1037 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1038 void (*trigger)(void *), 1039 void (*overflow)(void *), 1040 void *arg, 1041 u8 timer_index); 1042 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1043 struct ath_gen_timer *timer, 1044 u32 timer_next, 1045 u32 timer_period); 1046 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah); 1047 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1048 1049 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1050 void ath_gen_timer_isr(struct ath_hw *hw); 1051 1052 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1053 1054 /* PHY */ 1055 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1056 u32 *coef_mantissa, u32 *coef_exponent); 1057 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1058 bool test); 1059 1060 /* 1061 * Code Specific to AR5008, AR9001 or AR9002, 1062 * we stuff these here to avoid callbacks for AR9003. 1063 */ 1064 int ar9002_hw_rf_claim(struct ath_hw *ah); 1065 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1066 1067 /* 1068 * Code specific to AR9003, we stuff these here to avoid callbacks 1069 * for older families 1070 */ 1071 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); 1072 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1073 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1074 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1075 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1076 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1077 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1078 struct ath9k_hw_cal_data *caldata, 1079 int chain); 1080 int ar9003_paprd_create_curve(struct ath_hw *ah, 1081 struct ath9k_hw_cal_data *caldata, int chain); 1082 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1083 int ar9003_paprd_init_table(struct ath_hw *ah); 1084 bool ar9003_paprd_is_done(struct ath_hw *ah); 1085 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1086 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1087 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, 1088 struct ath9k_channel *chan); 1089 1090 /* Hardware family op attach helpers */ 1091 int ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1092 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1093 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1094 1095 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1096 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1097 1098 int ar9002_hw_attach_ops(struct ath_hw *ah); 1099 void ar9003_hw_attach_ops(struct ath_hw *ah); 1100 1101 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1102 1103 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1104 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1105 1106 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); 1107 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); 1108 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); 1109 1110 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1111 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1112 { 1113 return ah->btcoex_hw.enabled; 1114 } 1115 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1116 { 1117 return ah->common.btcoex_enabled && 1118 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1119 1120 } 1121 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1122 static inline enum ath_btcoex_scheme 1123 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1124 { 1125 return ah->btcoex_hw.scheme; 1126 } 1127 #else 1128 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1129 { 1130 return false; 1131 } 1132 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1133 { 1134 return false; 1135 } 1136 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1137 { 1138 } 1139 static inline enum ath_btcoex_scheme 1140 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1141 { 1142 return ATH_BTCOEX_CFG_NONE; 1143 } 1144 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1145 1146 1147 #ifdef CONFIG_ATH9K_WOW 1148 const char *ath9k_hw_wow_event_to_string(u32 wow_event); 1149 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1150 u8 *user_mask, int pattern_count, 1151 int pattern_len); 1152 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1153 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1154 #else 1155 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) 1156 { 1157 return NULL; 1158 } 1159 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1160 u8 *user_pattern, 1161 u8 *user_mask, 1162 int pattern_count, 1163 int pattern_len) 1164 { 1165 } 1166 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1167 { 1168 return 0; 1169 } 1170 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1171 { 1172 } 1173 #endif 1174 1175 #define ATH9K_CLOCK_RATE_CCK 22 1176 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1177 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1178 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1179 1180 #endif 1181