1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "phy.h" 31 #include "btcoex.h" 32 #include "dynack.h" 33 34 #include "../regd.h" 35 36 #define ATHEROS_VENDOR_ID 0x168c 37 38 #define AR5416_DEVID_PCI 0x0023 39 #define AR5416_DEVID_PCIE 0x0024 40 #define AR9160_DEVID_PCI 0x0027 41 #define AR9280_DEVID_PCI 0x0029 42 #define AR9280_DEVID_PCIE 0x002a 43 #define AR9285_DEVID_PCIE 0x002b 44 #define AR2427_DEVID_PCIE 0x002c 45 #define AR9287_DEVID_PCI 0x002d 46 #define AR9287_DEVID_PCIE 0x002e 47 #define AR9300_DEVID_PCIE 0x0030 48 #define AR9300_DEVID_AR9340 0x0031 49 #define AR9300_DEVID_AR9485_PCIE 0x0032 50 #define AR9300_DEVID_AR9580 0x0033 51 #define AR9300_DEVID_AR9462 0x0034 52 #define AR9300_DEVID_AR9330 0x0035 53 #define AR9300_DEVID_QCA955X 0x0038 54 #define AR9485_DEVID_AR1111 0x0037 55 #define AR9300_DEVID_AR9565 0x0036 56 #define AR9300_DEVID_AR953X 0x003d 57 #define AR9300_DEVID_QCA956X 0x003f 58 59 #define AR5416_AR9100_DEVID 0x000b 60 61 #define AR_SUBVENDOR_ID_NOG 0x0e11 62 #define AR_SUBVENDOR_ID_NEW_A 0x7065 63 #define AR5416_MAGIC 0x19641014 64 65 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 66 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 67 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 68 69 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 70 71 #define ATH_DEFAULT_NOISE_FLOOR -95 72 73 #define ATH9K_RSSI_BAD -128 74 75 #define ATH9K_NUM_CHANNELS 38 76 77 /* Register read/write primitives */ 78 #define REG_WRITE(_ah, _reg, _val) \ 79 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 80 81 #define REG_READ(_ah, _reg) \ 82 (_ah)->reg_ops.read((_ah), (_reg)) 83 84 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 85 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 86 87 #define REG_RMW(_ah, _reg, _set, _clr) \ 88 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 89 90 #define ENABLE_REGWRITE_BUFFER(_ah) \ 91 do { \ 92 if ((_ah)->reg_ops.enable_write_buffer) \ 93 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 94 } while (0) 95 96 #define REGWRITE_BUFFER_FLUSH(_ah) \ 97 do { \ 98 if ((_ah)->reg_ops.write_flush) \ 99 (_ah)->reg_ops.write_flush((_ah)); \ 100 } while (0) 101 102 #define PR_EEP(_s, _val) \ 103 do { \ 104 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ 105 _s, (_val)); \ 106 } while (0) 107 108 #define SM(_v, _f) (((_v) << _f##_S) & _f) 109 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 110 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 111 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 112 #define REG_READ_FIELD(_a, _r, _f) \ 113 (((REG_READ(_a, _r) & _f) >> _f##_S)) 114 #define REG_SET_BIT(_a, _r, _f) \ 115 REG_RMW(_a, _r, (_f), 0) 116 #define REG_CLR_BIT(_a, _r, _f) \ 117 REG_RMW(_a, _r, 0, (_f)) 118 119 #define DO_DELAY(x) do { \ 120 if (((++(x) % 64) == 0) && \ 121 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 122 != ATH_USB)) \ 123 udelay(1); \ 124 } while (0) 125 126 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 127 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 128 129 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 130 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 131 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 132 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 133 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 134 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 135 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 139 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 140 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 141 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 142 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 143 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 144 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 145 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 146 147 #define AR_GPIOD_MASK 0x00001FFF 148 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 149 150 #define BASE_ACTIVATE_DELAY 100 151 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 152 #define COEF_SCALE_S 24 153 #define HT40_CHANNEL_CENTER_SHIFT 10 154 155 #define ATH9K_ANTENNA0_CHAINMASK 0x1 156 #define ATH9K_ANTENNA1_CHAINMASK 0x2 157 158 #define ATH9K_NUM_DMA_DEBUG_REGS 8 159 #define ATH9K_NUM_QUEUES 10 160 161 #define MAX_RATE_POWER 63 162 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 163 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 164 #define AH_TIME_QUANTUM 10 165 #define AR_KEYTABLE_SIZE 128 166 #define POWER_UP_TIME 10000 167 #define SPUR_RSSI_THRESH 40 168 #define UPPER_5G_SUB_BAND_START 5700 169 #define MID_5G_SUB_BAND_START 5400 170 171 #define CAB_TIMEOUT_VAL 10 172 #define BEACON_TIMEOUT_VAL 10 173 #define MIN_BEACON_TIMEOUT_VAL 1 174 #define SLEEP_SLOP TU_TO_USEC(3) 175 176 #define INIT_CONFIG_STATUS 0x00000000 177 #define INIT_RSSI_THR 0x00000700 178 #define INIT_BCON_CNTRL_REG 0x00000000 179 180 #define TU_TO_USEC(_tu) ((_tu) << 10) 181 182 #define ATH9K_HW_RX_HP_QDEPTH 16 183 #define ATH9K_HW_RX_LP_QDEPTH 128 184 185 #define PAPRD_GAIN_TABLE_ENTRIES 32 186 #define PAPRD_TABLE_SZ 24 187 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 188 189 /* 190 * Wake on Wireless 191 */ 192 193 /* Keep Alive Frame */ 194 #define KAL_FRAME_LEN 28 195 #define KAL_FRAME_TYPE 0x2 /* data frame */ 196 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 197 #define KAL_DURATION_ID 0x3d 198 #define KAL_NUM_DATA_WORDS 6 199 #define KAL_NUM_DESC_WORDS 12 200 #define KAL_ANTENNA_MODE 1 201 #define KAL_TO_DS 1 202 #define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */ 203 #define KAL_TIMEOUT 900 204 205 #define MAX_PATTERN_SIZE 256 206 #define MAX_PATTERN_MASK_SIZE 32 207 #define MAX_NUM_PATTERN 16 208 #define MAX_NUM_PATTERN_LEGACY 8 209 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 210 deauthenticate packets */ 211 212 /* 213 * WoW trigger mapping to hardware code 214 */ 215 216 #define AH_WOW_USER_PATTERN_EN BIT(0) 217 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 218 #define AH_WOW_LINK_CHANGE BIT(2) 219 #define AH_WOW_BEACON_MISS BIT(3) 220 221 enum ath_hw_txq_subtype { 222 ATH_TXQ_AC_BK = 0, 223 ATH_TXQ_AC_BE = 1, 224 ATH_TXQ_AC_VI = 2, 225 ATH_TXQ_AC_VO = 3, 226 }; 227 228 enum ath_ini_subsys { 229 ATH_INI_PRE = 0, 230 ATH_INI_CORE, 231 ATH_INI_POST, 232 ATH_INI_NUM_SPLIT, 233 }; 234 235 enum ath9k_hw_caps { 236 ATH9K_HW_CAP_HT = BIT(0), 237 ATH9K_HW_CAP_RFSILENT = BIT(1), 238 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 239 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 240 ATH9K_HW_CAP_EDMA = BIT(4), 241 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 242 ATH9K_HW_CAP_LDPC = BIT(6), 243 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 244 ATH9K_HW_CAP_SGI_20 = BIT(8), 245 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 246 ATH9K_HW_CAP_2GHZ = BIT(11), 247 ATH9K_HW_CAP_5GHZ = BIT(12), 248 ATH9K_HW_CAP_APM = BIT(13), 249 #ifdef CONFIG_ATH9K_PCOEM 250 ATH9K_HW_CAP_RTT = BIT(14), 251 ATH9K_HW_CAP_MCI = BIT(15), 252 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), 253 #else 254 ATH9K_HW_CAP_RTT = 0, 255 ATH9K_HW_CAP_MCI = 0, 256 ATH9K_HW_CAP_BT_ANT_DIV = 0, 257 #endif 258 ATH9K_HW_CAP_DFS = BIT(18), 259 ATH9K_HW_CAP_PAPRD = BIT(19), 260 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), 261 }; 262 263 /* 264 * WoW device capabilities 265 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 266 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 267 * an exact user defined pattern or de-authentication/disassoc pattern. 268 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 269 * bytes of the pattern for user defined pattern, de-authentication and 270 * disassociation patterns for all types of possible frames recieved 271 * of those types. 272 */ 273 274 struct ath9k_hw_wow { 275 u32 wow_event_mask; 276 u32 wow_event_mask2; 277 u8 max_patterns; 278 }; 279 280 struct ath9k_hw_capabilities { 281 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 282 u16 rts_aggr_limit; 283 u8 tx_chainmask; 284 u8 rx_chainmask; 285 u8 chip_chainmask; 286 u8 max_txchains; 287 u8 max_rxchains; 288 u8 num_gpio_pins; 289 u8 rx_hp_qdepth; 290 u8 rx_lp_qdepth; 291 u8 rx_status_len; 292 u8 tx_desc_len; 293 u8 txs_len; 294 }; 295 296 #define AR_NO_SPUR 0x8000 297 #define AR_BASE_FREQ_2GHZ 2300 298 #define AR_BASE_FREQ_5GHZ 4900 299 #define AR_SPUR_FEEQ_BOUND_HT40 19 300 #define AR_SPUR_FEEQ_BOUND_HT20 10 301 302 enum ath9k_hw_hang_checks { 303 HW_BB_WATCHDOG = BIT(0), 304 HW_PHYRESTART_CLC_WAR = BIT(1), 305 HW_BB_RIFS_HANG = BIT(2), 306 HW_BB_DFS_HANG = BIT(3), 307 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), 308 HW_MAC_HANG = BIT(5), 309 }; 310 311 struct ath9k_ops_config { 312 int dma_beacon_response_time; 313 int sw_beacon_response_time; 314 u32 cwm_ignore_extcca; 315 u32 pcie_waen; 316 u8 analog_shiftreg; 317 u32 ofdm_trig_low; 318 u32 ofdm_trig_high; 319 u32 cck_trig_high; 320 u32 cck_trig_low; 321 u32 enable_paprd; 322 int serialize_regmode; 323 bool rx_intr_mitigation; 324 bool tx_intr_mitigation; 325 u8 max_txtrig_level; 326 u16 ani_poll_interval; /* ANI poll interval in ms */ 327 u16 hw_hang_checks; 328 u16 rimt_first; 329 u16 rimt_last; 330 331 /* Platform specific config */ 332 u32 aspm_l1_fix; 333 u32 xlna_gpio; 334 u32 ant_ctrl_comm2g_switch_enable; 335 bool xatten_margin_cfg; 336 bool alt_mingainidx; 337 bool no_pll_pwrsave; 338 bool tx_gain_buffalo; 339 bool led_active_high; 340 }; 341 342 enum ath9k_int { 343 ATH9K_INT_RX = 0x00000001, 344 ATH9K_INT_RXDESC = 0x00000002, 345 ATH9K_INT_RXHP = 0x00000001, 346 ATH9K_INT_RXLP = 0x00000002, 347 ATH9K_INT_RXNOFRM = 0x00000008, 348 ATH9K_INT_RXEOL = 0x00000010, 349 ATH9K_INT_RXORN = 0x00000020, 350 ATH9K_INT_TX = 0x00000040, 351 ATH9K_INT_TXDESC = 0x00000080, 352 ATH9K_INT_TIM_TIMER = 0x00000100, 353 ATH9K_INT_MCI = 0x00000200, 354 ATH9K_INT_BB_WATCHDOG = 0x00000400, 355 ATH9K_INT_TXURN = 0x00000800, 356 ATH9K_INT_MIB = 0x00001000, 357 ATH9K_INT_RXPHY = 0x00004000, 358 ATH9K_INT_RXKCM = 0x00008000, 359 ATH9K_INT_SWBA = 0x00010000, 360 ATH9K_INT_BMISS = 0x00040000, 361 ATH9K_INT_BNR = 0x00100000, 362 ATH9K_INT_TIM = 0x00200000, 363 ATH9K_INT_DTIM = 0x00400000, 364 ATH9K_INT_DTIMSYNC = 0x00800000, 365 ATH9K_INT_GPIO = 0x01000000, 366 ATH9K_INT_CABEND = 0x02000000, 367 ATH9K_INT_TSFOOR = 0x04000000, 368 ATH9K_INT_GENTIMER = 0x08000000, 369 ATH9K_INT_CST = 0x10000000, 370 ATH9K_INT_GTT = 0x20000000, 371 ATH9K_INT_FATAL = 0x40000000, 372 ATH9K_INT_GLOBAL = 0x80000000, 373 ATH9K_INT_BMISC = ATH9K_INT_TIM | 374 ATH9K_INT_DTIM | 375 ATH9K_INT_DTIMSYNC | 376 ATH9K_INT_TSFOOR | 377 ATH9K_INT_CABEND, 378 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 379 ATH9K_INT_RXDESC | 380 ATH9K_INT_RXEOL | 381 ATH9K_INT_RXORN | 382 ATH9K_INT_TXURN | 383 ATH9K_INT_TXDESC | 384 ATH9K_INT_MIB | 385 ATH9K_INT_RXPHY | 386 ATH9K_INT_RXKCM | 387 ATH9K_INT_SWBA | 388 ATH9K_INT_BMISS | 389 ATH9K_INT_GPIO, 390 ATH9K_INT_NOCARD = 0xffffffff 391 }; 392 393 #define MAX_RTT_TABLE_ENTRY 6 394 #define MAX_IQCAL_MEASUREMENT 8 395 #define MAX_CL_TAB_ENTRY 16 396 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) 397 398 enum ath9k_cal_flags { 399 RTT_DONE, 400 PAPRD_PACKET_SENT, 401 PAPRD_DONE, 402 NFCAL_PENDING, 403 NFCAL_INTF, 404 TXIQCAL_DONE, 405 TXCLCAL_DONE, 406 SW_PKDET_DONE, 407 }; 408 409 struct ath9k_hw_cal_data { 410 u16 channel; 411 u16 channelFlags; 412 unsigned long cal_flags; 413 int32_t CalValid; 414 int8_t iCoff; 415 int8_t qCoff; 416 u8 caldac[2]; 417 u16 small_signal_gain[AR9300_MAX_CHAINS]; 418 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 419 u32 num_measures[AR9300_MAX_CHAINS]; 420 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 421 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 422 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 423 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 424 }; 425 426 struct ath9k_channel { 427 struct ieee80211_channel *chan; 428 u16 channel; 429 u16 channelFlags; 430 s16 noisefloor; 431 }; 432 433 #define CHANNEL_5GHZ BIT(0) 434 #define CHANNEL_HALF BIT(1) 435 #define CHANNEL_QUARTER BIT(2) 436 #define CHANNEL_HT BIT(3) 437 #define CHANNEL_HT40PLUS BIT(4) 438 #define CHANNEL_HT40MINUS BIT(5) 439 440 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) 441 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 442 443 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) 444 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) 445 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 446 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 447 448 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) 449 450 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) 451 452 #define IS_CHAN_HT40(_c) \ 453 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) 454 455 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) 456 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) 457 458 enum ath9k_power_mode { 459 ATH9K_PM_AWAKE = 0, 460 ATH9K_PM_FULL_SLEEP, 461 ATH9K_PM_NETWORK_SLEEP, 462 ATH9K_PM_UNDEFINED 463 }; 464 465 enum ser_reg_mode { 466 SER_REG_MODE_OFF = 0, 467 SER_REG_MODE_ON = 1, 468 SER_REG_MODE_AUTO = 2, 469 }; 470 471 enum ath9k_rx_qtype { 472 ATH9K_RX_QUEUE_HP, 473 ATH9K_RX_QUEUE_LP, 474 ATH9K_RX_QUEUE_MAX, 475 }; 476 477 struct ath9k_beacon_state { 478 u32 bs_nexttbtt; 479 u32 bs_nextdtim; 480 u32 bs_intval; 481 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 482 u32 bs_dtimperiod; 483 u16 bs_bmissthreshold; 484 u32 bs_sleepduration; 485 u32 bs_tsfoor_threshold; 486 }; 487 488 struct chan_centers { 489 u16 synth_center; 490 u16 ctl_center; 491 u16 ext_center; 492 }; 493 494 enum { 495 ATH9K_RESET_POWER_ON, 496 ATH9K_RESET_WARM, 497 ATH9K_RESET_COLD, 498 }; 499 500 struct ath9k_hw_version { 501 u32 magic; 502 u16 devid; 503 u16 subvendorid; 504 u32 macVersion; 505 u16 macRev; 506 u16 phyRev; 507 u16 analog5GhzRev; 508 u16 analog2GhzRev; 509 enum ath_usb_dev usbdev; 510 }; 511 512 /* Generic TSF timer definitions */ 513 514 #define ATH_MAX_GEN_TIMER 16 515 516 #define AR_GENTMR_BIT(_index) (1 << (_index)) 517 518 struct ath_gen_timer_configuration { 519 u32 next_addr; 520 u32 period_addr; 521 u32 mode_addr; 522 u32 mode_mask; 523 }; 524 525 struct ath_gen_timer { 526 void (*trigger)(void *arg); 527 void (*overflow)(void *arg); 528 void *arg; 529 u8 index; 530 }; 531 532 struct ath_gen_timer_table { 533 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 534 u16 timer_mask; 535 bool tsf2_enabled; 536 }; 537 538 struct ath_hw_antcomb_conf { 539 u8 main_lna_conf; 540 u8 alt_lna_conf; 541 u8 fast_div_bias; 542 u8 main_gaintb; 543 u8 alt_gaintb; 544 int lna1_lna2_delta; 545 int lna1_lna2_switch_delta; 546 u8 div_group; 547 }; 548 549 /** 550 * struct ath_hw_radar_conf - radar detection initialization parameters 551 * 552 * @pulse_inband: threshold for checking the ratio of in-band power 553 * to total power for short radar pulses (half dB steps) 554 * @pulse_inband_step: threshold for checking an in-band power to total 555 * power ratio increase for short radar pulses (half dB steps) 556 * @pulse_height: threshold for detecting the beginning of a short 557 * radar pulse (dB step) 558 * @pulse_rssi: threshold for detecting if a short radar pulse is 559 * gone (dB step) 560 * @pulse_maxlen: maximum pulse length (0.8 us steps) 561 * 562 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 563 * @radar_inband: threshold for checking the ratio of in-band power 564 * to total power for long radar pulses (half dB steps) 565 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 566 * 567 * @ext_channel: enable extension channel radar detection 568 */ 569 struct ath_hw_radar_conf { 570 unsigned int pulse_inband; 571 unsigned int pulse_inband_step; 572 unsigned int pulse_height; 573 unsigned int pulse_rssi; 574 unsigned int pulse_maxlen; 575 576 unsigned int radar_rssi; 577 unsigned int radar_inband; 578 int fir_power; 579 580 bool ext_channel; 581 }; 582 583 /** 584 * struct ath_hw_private_ops - callbacks used internally by hardware code 585 * 586 * This structure contains private callbacks designed to only be used internally 587 * by the hardware core. 588 * 589 * @init_cal_settings: setup types of calibrations supported 590 * @init_cal: starts actual calibration 591 * 592 * @init_mode_gain_regs: Initialize TX/RX gain registers 593 * 594 * @rf_set_freq: change frequency 595 * @spur_mitigate_freq: spur mitigation 596 * @set_rf_regs: 597 * @compute_pll_control: compute the PLL control value to use for 598 * AR_RTC_PLL_CONTROL for a given channel 599 * @setup_calibration: set up calibration 600 * @iscal_supported: used to query if a type of calibration is supported 601 * 602 * @ani_cache_ini_regs: cache the values for ANI from the initial 603 * register settings through the register initialization. 604 */ 605 struct ath_hw_private_ops { 606 void (*init_hang_checks)(struct ath_hw *ah); 607 bool (*detect_mac_hang)(struct ath_hw *ah); 608 bool (*detect_bb_hang)(struct ath_hw *ah); 609 610 /* Calibration ops */ 611 void (*init_cal_settings)(struct ath_hw *ah); 612 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 613 614 void (*init_mode_gain_regs)(struct ath_hw *ah); 615 void (*setup_calibration)(struct ath_hw *ah, 616 struct ath9k_cal_list *currCal); 617 618 /* PHY ops */ 619 int (*rf_set_freq)(struct ath_hw *ah, 620 struct ath9k_channel *chan); 621 void (*spur_mitigate_freq)(struct ath_hw *ah, 622 struct ath9k_channel *chan); 623 bool (*set_rf_regs)(struct ath_hw *ah, 624 struct ath9k_channel *chan, 625 u16 modesIndex); 626 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 627 void (*init_bb)(struct ath_hw *ah, 628 struct ath9k_channel *chan); 629 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 630 void (*olc_init)(struct ath_hw *ah); 631 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 632 void (*mark_phy_inactive)(struct ath_hw *ah); 633 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 634 bool (*rfbus_req)(struct ath_hw *ah); 635 void (*rfbus_done)(struct ath_hw *ah); 636 void (*restore_chainmask)(struct ath_hw *ah); 637 u32 (*compute_pll_control)(struct ath_hw *ah, 638 struct ath9k_channel *chan); 639 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 640 int param); 641 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 642 void (*set_radar_params)(struct ath_hw *ah, 643 struct ath_hw_radar_conf *conf); 644 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 645 u8 *ini_reloaded); 646 647 /* ANI */ 648 void (*ani_cache_ini_regs)(struct ath_hw *ah); 649 }; 650 651 /** 652 * struct ath_spec_scan - parameters for Atheros spectral scan 653 * 654 * @enabled: enable/disable spectral scan 655 * @short_repeat: controls whether the chip is in spectral scan mode 656 * for 4 usec (enabled) or 204 usec (disabled) 657 * @count: number of scan results requested. There are special meanings 658 * in some chip revisions: 659 * AR92xx: highest bit set (>=128) for endless mode 660 * (spectral scan won't stopped until explicitly disabled) 661 * AR9300 and newer: 0 for endless mode 662 * @endless: true if endless mode is intended. Otherwise, count value is 663 * corrected to the next possible value. 664 * @period: time duration between successive spectral scan entry points 665 * (period*256*Tclk). Tclk = ath_common->clockrate 666 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS 667 * 668 * Note: Tclk = 40MHz or 44MHz depending upon operating mode. 669 * Typically it's 44MHz in 2/5GHz on later chips, but there's 670 * a "fast clock" check for this in 5GHz. 671 * 672 */ 673 struct ath_spec_scan { 674 bool enabled; 675 bool short_repeat; 676 bool endless; 677 u8 count; 678 u8 period; 679 u8 fft_period; 680 }; 681 682 /** 683 * struct ath_hw_ops - callbacks used by hardware code and driver code 684 * 685 * This structure contains callbacks designed to to be used internally by 686 * hardware code and also by the lower level driver. 687 * 688 * @config_pci_powersave: 689 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 690 * 691 * @spectral_scan_config: set parameters for spectral scan and enable/disable it 692 * @spectral_scan_trigger: trigger a spectral scan run 693 * @spectral_scan_wait: wait for a spectral scan run to finish 694 */ 695 struct ath_hw_ops { 696 void (*config_pci_powersave)(struct ath_hw *ah, 697 bool power_off); 698 void (*rx_enable)(struct ath_hw *ah); 699 void (*set_desc_link)(void *ds, u32 link); 700 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, 701 u8 rxchainmask, bool longcal); 702 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, 703 u32 *sync_cause_p); 704 void (*set_txdesc)(struct ath_hw *ah, void *ds, 705 struct ath_tx_info *i); 706 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 707 struct ath_tx_status *ts); 708 int (*get_duration)(struct ath_hw *ah, const void *ds, int index); 709 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 710 struct ath_hw_antcomb_conf *antconf); 711 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 712 struct ath_hw_antcomb_conf *antconf); 713 void (*spectral_scan_config)(struct ath_hw *ah, 714 struct ath_spec_scan *param); 715 void (*spectral_scan_trigger)(struct ath_hw *ah); 716 void (*spectral_scan_wait)(struct ath_hw *ah); 717 718 void (*tx99_start)(struct ath_hw *ah, u32 qnum); 719 void (*tx99_stop)(struct ath_hw *ah); 720 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); 721 722 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 723 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); 724 #endif 725 }; 726 727 struct ath_nf_limits { 728 s16 max; 729 s16 min; 730 s16 nominal; 731 }; 732 733 enum ath_cal_list { 734 TX_IQ_CAL = BIT(0), 735 TX_IQ_ON_AGC_CAL = BIT(1), 736 TX_CL_CAL = BIT(2), 737 }; 738 739 /* ah_flags */ 740 #define AH_USE_EEPROM 0x1 741 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 742 #define AH_FASTCC 0x4 743 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */ 744 745 struct ath_hw { 746 struct ath_ops reg_ops; 747 748 struct device *dev; 749 struct ieee80211_hw *hw; 750 struct ath_common common; 751 struct ath9k_hw_version hw_version; 752 struct ath9k_ops_config config; 753 struct ath9k_hw_capabilities caps; 754 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 755 struct ath9k_channel *curchan; 756 757 union { 758 struct ar5416_eeprom_def def; 759 struct ar5416_eeprom_4k map4k; 760 struct ar9287_eeprom map9287; 761 struct ar9300_eeprom ar9300_eep; 762 } eeprom; 763 const struct eeprom_ops *eep_ops; 764 765 bool sw_mgmt_crypto_tx; 766 bool sw_mgmt_crypto_rx; 767 bool is_pciexpress; 768 bool aspm_enabled; 769 bool is_monitoring; 770 bool need_an_top2_fixup; 771 u16 tx_trig_level; 772 773 u32 nf_regs[6]; 774 struct ath_nf_limits nf_2g; 775 struct ath_nf_limits nf_5g; 776 u16 rfsilent; 777 u32 rfkill_gpio; 778 u32 rfkill_polarity; 779 u32 ah_flags; 780 781 bool reset_power_on; 782 bool htc_reset_init; 783 784 enum nl80211_iftype opmode; 785 enum ath9k_power_mode power_mode; 786 787 s8 noise; 788 struct ath9k_hw_cal_data *caldata; 789 struct ath9k_pacal_info pacal_info; 790 struct ar5416Stats stats; 791 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 792 793 enum ath9k_int imask; 794 u32 imrs2_reg; 795 u32 txok_interrupt_mask; 796 u32 txerr_interrupt_mask; 797 u32 txdesc_interrupt_mask; 798 u32 txeol_interrupt_mask; 799 u32 txurn_interrupt_mask; 800 atomic_t intr_ref_cnt; 801 bool chip_fullsleep; 802 u32 modes_index; 803 804 /* Calibration */ 805 u32 supp_cals; 806 struct ath9k_cal_list iq_caldata; 807 struct ath9k_cal_list adcgain_caldata; 808 struct ath9k_cal_list adcdc_caldata; 809 struct ath9k_cal_list *cal_list; 810 struct ath9k_cal_list *cal_list_last; 811 struct ath9k_cal_list *cal_list_curr; 812 #define totalPowerMeasI meas0.unsign 813 #define totalPowerMeasQ meas1.unsign 814 #define totalIqCorrMeas meas2.sign 815 #define totalAdcIOddPhase meas0.unsign 816 #define totalAdcIEvenPhase meas1.unsign 817 #define totalAdcQOddPhase meas2.unsign 818 #define totalAdcQEvenPhase meas3.unsign 819 #define totalAdcDcOffsetIOddPhase meas0.sign 820 #define totalAdcDcOffsetIEvenPhase meas1.sign 821 #define totalAdcDcOffsetQOddPhase meas2.sign 822 #define totalAdcDcOffsetQEvenPhase meas3.sign 823 union { 824 u32 unsign[AR5416_MAX_CHAINS]; 825 int32_t sign[AR5416_MAX_CHAINS]; 826 } meas0; 827 union { 828 u32 unsign[AR5416_MAX_CHAINS]; 829 int32_t sign[AR5416_MAX_CHAINS]; 830 } meas1; 831 union { 832 u32 unsign[AR5416_MAX_CHAINS]; 833 int32_t sign[AR5416_MAX_CHAINS]; 834 } meas2; 835 union { 836 u32 unsign[AR5416_MAX_CHAINS]; 837 int32_t sign[AR5416_MAX_CHAINS]; 838 } meas3; 839 u16 cal_samples; 840 u8 enabled_cals; 841 842 u32 sta_id1_defaults; 843 u32 misc_mode; 844 845 /* Private to hardware code */ 846 struct ath_hw_private_ops private_ops; 847 /* Accessed by the lower level driver */ 848 struct ath_hw_ops ops; 849 850 /* Used to program the radio on non single-chip devices */ 851 u32 *analogBank6Data; 852 853 int coverage_class; 854 u32 slottime; 855 u32 globaltxtimeout; 856 857 /* ANI */ 858 u32 aniperiod; 859 enum ath9k_ani_cmd ani_function; 860 u32 ani_skip_count; 861 struct ar5416AniState ani; 862 863 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 864 struct ath_btcoex_hw btcoex_hw; 865 #endif 866 867 u32 intr_txqs; 868 u8 txchainmask; 869 u8 rxchainmask; 870 871 struct ath_hw_radar_conf radar_conf; 872 873 u32 originalGain[22]; 874 int initPDADC; 875 int PDADCdelta; 876 int led_pin; 877 u32 gpio_mask; 878 u32 gpio_val; 879 880 struct ar5416IniArray ini_dfs; 881 struct ar5416IniArray iniModes; 882 struct ar5416IniArray iniCommon; 883 struct ar5416IniArray iniBB_RfGain; 884 struct ar5416IniArray iniBank6; 885 struct ar5416IniArray iniAddac; 886 struct ar5416IniArray iniPcieSerdes; 887 struct ar5416IniArray iniPcieSerdesLowPower; 888 struct ar5416IniArray iniModesFastClock; 889 struct ar5416IniArray iniAdditional; 890 struct ar5416IniArray iniModesRxGain; 891 struct ar5416IniArray ini_modes_rx_gain_bounds; 892 struct ar5416IniArray iniModesTxGain; 893 struct ar5416IniArray iniCckfirNormal; 894 struct ar5416IniArray iniCckfirJapan2484; 895 struct ar5416IniArray iniModes_9271_ANI_reg; 896 struct ar5416IniArray ini_radio_post_sys2ant; 897 struct ar5416IniArray ini_modes_rxgain_5g_xlna; 898 struct ar5416IniArray ini_modes_rxgain_bb_core; 899 struct ar5416IniArray ini_modes_rxgain_bb_postamble; 900 901 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 902 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 903 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 904 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 905 906 u32 intr_gen_timer_trigger; 907 u32 intr_gen_timer_thresh; 908 struct ath_gen_timer_table hw_gen_timers; 909 910 struct ar9003_txs *ts_ring; 911 u32 ts_paddr_start; 912 u32 ts_paddr_end; 913 u16 ts_tail; 914 u16 ts_size; 915 916 u32 bb_watchdog_last_status; 917 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 918 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 919 920 unsigned int paprd_target_power; 921 unsigned int paprd_training_power; 922 unsigned int paprd_ratemask; 923 unsigned int paprd_ratemask_ht40; 924 bool paprd_table_write_done; 925 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 926 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 927 /* 928 * Store the permanent value of Reg 0x4004in WARegVal 929 * so we dont have to R/M/W. We should not be reading 930 * this register when in sleep states. 931 */ 932 u32 WARegVal; 933 934 /* Enterprise mode cap */ 935 u32 ent_mode; 936 937 #ifdef CONFIG_ATH9K_WOW 938 struct ath9k_hw_wow wow; 939 #endif 940 bool is_clk_25mhz; 941 int (*get_mac_revision)(void); 942 int (*external_reset)(void); 943 bool disable_2ghz; 944 bool disable_5ghz; 945 946 const struct firmware *eeprom_blob; 947 948 struct ath_dynack dynack; 949 950 bool tpc_enabled; 951 u8 tx_power[Ar5416RateSize]; 952 u8 tx_power_stbc[Ar5416RateSize]; 953 }; 954 955 struct ath_bus_ops { 956 enum ath_bus_type ath_bus_type; 957 void (*read_cachesize)(struct ath_common *common, int *csz); 958 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 959 void (*bt_coex_prep)(struct ath_common *common); 960 void (*aspm_init)(struct ath_common *common); 961 }; 962 963 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 964 { 965 return &ah->common; 966 } 967 968 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 969 { 970 return &(ath9k_hw_common(ah)->regulatory); 971 } 972 973 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 974 { 975 return &ah->private_ops; 976 } 977 978 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 979 { 980 return &ah->ops; 981 } 982 983 static inline u8 get_streams(int mask) 984 { 985 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 986 } 987 988 /* Initialization, Detach, Reset */ 989 void ath9k_hw_deinit(struct ath_hw *ah); 990 int ath9k_hw_init(struct ath_hw *ah); 991 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 992 struct ath9k_hw_cal_data *caldata, bool fastcc); 993 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 994 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 995 996 /* GPIO / RFKILL / Antennae */ 997 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 998 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 999 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 1000 u32 ah_signal_type); 1001 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 1002 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 1003 1004 /* General Operation */ 1005 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 1006 int hw_delay); 1007 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 1008 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 1009 int column, unsigned int *writecnt); 1010 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1011 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 1012 u8 phy, int kbps, 1013 u32 frameLen, u16 rateix, bool shortPreamble); 1014 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 1015 struct ath9k_channel *chan, 1016 struct chan_centers *centers); 1017 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 1018 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 1019 bool ath9k_hw_phy_disable(struct ath_hw *ah); 1020 bool ath9k_hw_disable(struct ath_hw *ah); 1021 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 1022 void ath9k_hw_setopmode(struct ath_hw *ah); 1023 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 1024 void ath9k_hw_write_associd(struct ath_hw *ah); 1025 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1026 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1027 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1028 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1029 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur); 1030 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1031 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1032 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1033 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); 1034 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1035 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1036 const struct ath9k_beacon_state *bs); 1037 void ath9k_hw_check_nav(struct ath_hw *ah); 1038 bool ath9k_hw_check_alive(struct ath_hw *ah); 1039 1040 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1041 1042 /* Generic hw timer primitives */ 1043 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1044 void (*trigger)(void *), 1045 void (*overflow)(void *), 1046 void *arg, 1047 u8 timer_index); 1048 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1049 struct ath_gen_timer *timer, 1050 u32 timer_next, 1051 u32 timer_period); 1052 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah); 1053 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1054 1055 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1056 void ath_gen_timer_isr(struct ath_hw *hw); 1057 1058 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1059 1060 /* PHY */ 1061 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1062 u32 *coef_mantissa, u32 *coef_exponent); 1063 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1064 bool test); 1065 1066 /* 1067 * Code Specific to AR5008, AR9001 or AR9002, 1068 * we stuff these here to avoid callbacks for AR9003. 1069 */ 1070 int ar9002_hw_rf_claim(struct ath_hw *ah); 1071 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1072 1073 /* 1074 * Code specific to AR9003, we stuff these here to avoid callbacks 1075 * for older families 1076 */ 1077 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); 1078 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1079 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1080 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1081 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1082 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1083 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1084 struct ath9k_hw_cal_data *caldata, 1085 int chain); 1086 int ar9003_paprd_create_curve(struct ath_hw *ah, 1087 struct ath9k_hw_cal_data *caldata, int chain); 1088 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1089 int ar9003_paprd_init_table(struct ath_hw *ah); 1090 bool ar9003_paprd_is_done(struct ath_hw *ah); 1091 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1092 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1093 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, 1094 struct ath9k_channel *chan); 1095 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1096 struct ath9k_channel *chan, int ht40_delta); 1097 1098 /* Hardware family op attach helpers */ 1099 int ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1100 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1101 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1102 1103 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1104 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1105 1106 int ar9002_hw_attach_ops(struct ath_hw *ah); 1107 void ar9003_hw_attach_ops(struct ath_hw *ah); 1108 1109 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1110 1111 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1112 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1113 1114 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); 1115 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); 1116 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); 1117 1118 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1119 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1120 { 1121 return ah->btcoex_hw.enabled; 1122 } 1123 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1124 { 1125 return ah->common.btcoex_enabled && 1126 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1127 1128 } 1129 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1130 static inline enum ath_btcoex_scheme 1131 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1132 { 1133 return ah->btcoex_hw.scheme; 1134 } 1135 #else 1136 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1137 { 1138 return false; 1139 } 1140 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1141 { 1142 return false; 1143 } 1144 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1145 { 1146 } 1147 static inline enum ath_btcoex_scheme 1148 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1149 { 1150 return ATH_BTCOEX_CFG_NONE; 1151 } 1152 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1153 1154 1155 #ifdef CONFIG_ATH9K_WOW 1156 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1157 u8 *user_mask, int pattern_count, 1158 int pattern_len); 1159 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1160 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1161 #else 1162 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1163 u8 *user_pattern, 1164 u8 *user_mask, 1165 int pattern_count, 1166 int pattern_len) 1167 { 1168 return 0; 1169 } 1170 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1171 { 1172 return 0; 1173 } 1174 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1175 { 1176 } 1177 #endif 1178 1179 #define ATH9K_CLOCK_RATE_CCK 22 1180 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1181 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1182 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1183 1184 #endif 1185