1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "reg_mci.h" 31 #include "phy.h" 32 #include "btcoex.h" 33 #include "dynack.h" 34 35 #include "../regd.h" 36 37 #define ATHEROS_VENDOR_ID 0x168c 38 39 #define AR5416_DEVID_PCI 0x0023 40 #define AR5416_DEVID_PCIE 0x0024 41 #define AR9160_DEVID_PCI 0x0027 42 #define AR9280_DEVID_PCI 0x0029 43 #define AR9280_DEVID_PCIE 0x002a 44 #define AR9285_DEVID_PCIE 0x002b 45 #define AR2427_DEVID_PCIE 0x002c 46 #define AR9287_DEVID_PCI 0x002d 47 #define AR9287_DEVID_PCIE 0x002e 48 #define AR9300_DEVID_PCIE 0x0030 49 #define AR9300_DEVID_AR9340 0x0031 50 #define AR9300_DEVID_AR9485_PCIE 0x0032 51 #define AR9300_DEVID_AR9580 0x0033 52 #define AR9300_DEVID_AR9462 0x0034 53 #define AR9300_DEVID_AR9330 0x0035 54 #define AR9300_DEVID_QCA955X 0x0038 55 #define AR9485_DEVID_AR1111 0x0037 56 #define AR9300_DEVID_AR9565 0x0036 57 #define AR9300_DEVID_AR953X 0x003d 58 #define AR9300_DEVID_QCA956X 0x003f 59 60 #define AR5416_AR9100_DEVID 0x000b 61 62 #define AR_SUBVENDOR_ID_NOG 0x0e11 63 #define AR_SUBVENDOR_ID_NEW_A 0x7065 64 #define AR5416_MAGIC 0x19641014 65 66 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 67 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 68 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 69 70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 71 72 #define ATH_DEFAULT_NOISE_FLOOR -95 73 74 #define ATH9K_RSSI_BAD -128 75 76 #define ATH9K_NUM_CHANNELS 38 77 78 /* Register read/write primitives */ 79 #define REG_WRITE(_ah, _reg, _val) \ 80 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 81 82 #define REG_READ(_ah, _reg) \ 83 (_ah)->reg_ops.read((_ah), (_reg)) 84 85 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 87 88 #define REG_RMW(_ah, _reg, _set, _clr) \ 89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 90 91 #define ENABLE_REGWRITE_BUFFER(_ah) \ 92 do { \ 93 if ((_ah)->reg_ops.enable_write_buffer) \ 94 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 95 } while (0) 96 97 #define REGWRITE_BUFFER_FLUSH(_ah) \ 98 do { \ 99 if ((_ah)->reg_ops.write_flush) \ 100 (_ah)->reg_ops.write_flush((_ah)); \ 101 } while (0) 102 103 #define PR_EEP(_s, _val) \ 104 do { \ 105 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ 106 _s, (_val)); \ 107 } while (0) 108 109 #define SM(_v, _f) (((_v) << _f##_S) & _f) 110 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 111 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 112 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 113 #define REG_READ_FIELD(_a, _r, _f) \ 114 (((REG_READ(_a, _r) & _f) >> _f##_S)) 115 #define REG_SET_BIT(_a, _r, _f) \ 116 REG_RMW(_a, _r, (_f), 0) 117 #define REG_CLR_BIT(_a, _r, _f) \ 118 REG_RMW(_a, _r, 0, (_f)) 119 120 #define DO_DELAY(x) do { \ 121 if (((++(x) % 64) == 0) && \ 122 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 123 != ATH_USB)) \ 124 udelay(1); \ 125 } while (0) 126 127 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 128 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 129 130 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 131 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 132 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 133 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 134 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 135 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 136 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 139 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 140 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 141 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 142 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 143 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 144 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 145 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 146 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 147 148 #define AR_GPIOD_MASK 0x00001FFF 149 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 150 151 #define BASE_ACTIVATE_DELAY 100 152 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 153 #define COEF_SCALE_S 24 154 #define HT40_CHANNEL_CENTER_SHIFT 10 155 156 #define ATH9K_ANTENNA0_CHAINMASK 0x1 157 #define ATH9K_ANTENNA1_CHAINMASK 0x2 158 159 #define ATH9K_NUM_DMA_DEBUG_REGS 8 160 #define ATH9K_NUM_QUEUES 10 161 162 #define MAX_RATE_POWER 63 163 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 164 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 165 #define AH_TIME_QUANTUM 10 166 #define AR_KEYTABLE_SIZE 128 167 #define POWER_UP_TIME 10000 168 #define SPUR_RSSI_THRESH 40 169 #define UPPER_5G_SUB_BAND_START 5700 170 #define MID_5G_SUB_BAND_START 5400 171 172 #define CAB_TIMEOUT_VAL 10 173 #define BEACON_TIMEOUT_VAL 10 174 #define MIN_BEACON_TIMEOUT_VAL 1 175 #define SLEEP_SLOP TU_TO_USEC(3) 176 177 #define INIT_CONFIG_STATUS 0x00000000 178 #define INIT_RSSI_THR 0x00000700 179 #define INIT_BCON_CNTRL_REG 0x00000000 180 181 #define TU_TO_USEC(_tu) ((_tu) << 10) 182 183 #define ATH9K_HW_RX_HP_QDEPTH 16 184 #define ATH9K_HW_RX_LP_QDEPTH 128 185 186 #define PAPRD_GAIN_TABLE_ENTRIES 32 187 #define PAPRD_TABLE_SZ 24 188 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 189 190 /* 191 * Wake on Wireless 192 */ 193 194 /* Keep Alive Frame */ 195 #define KAL_FRAME_LEN 28 196 #define KAL_FRAME_TYPE 0x2 /* data frame */ 197 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 198 #define KAL_DURATION_ID 0x3d 199 #define KAL_NUM_DATA_WORDS 6 200 #define KAL_NUM_DESC_WORDS 12 201 #define KAL_ANTENNA_MODE 1 202 #define KAL_TO_DS 1 203 #define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */ 204 #define KAL_TIMEOUT 900 205 206 #define MAX_PATTERN_SIZE 256 207 #define MAX_PATTERN_MASK_SIZE 32 208 #define MAX_NUM_PATTERN 16 209 #define MAX_NUM_PATTERN_LEGACY 8 210 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 211 deauthenticate packets */ 212 213 /* 214 * WoW trigger mapping to hardware code 215 */ 216 217 #define AH_WOW_USER_PATTERN_EN BIT(0) 218 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 219 #define AH_WOW_LINK_CHANGE BIT(2) 220 #define AH_WOW_BEACON_MISS BIT(3) 221 222 enum ath_hw_txq_subtype { 223 ATH_TXQ_AC_BK = 0, 224 ATH_TXQ_AC_BE = 1, 225 ATH_TXQ_AC_VI = 2, 226 ATH_TXQ_AC_VO = 3, 227 }; 228 229 enum ath_ini_subsys { 230 ATH_INI_PRE = 0, 231 ATH_INI_CORE, 232 ATH_INI_POST, 233 ATH_INI_NUM_SPLIT, 234 }; 235 236 enum ath9k_hw_caps { 237 ATH9K_HW_CAP_HT = BIT(0), 238 ATH9K_HW_CAP_RFSILENT = BIT(1), 239 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 240 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 241 ATH9K_HW_CAP_EDMA = BIT(4), 242 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 243 ATH9K_HW_CAP_LDPC = BIT(6), 244 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 245 ATH9K_HW_CAP_SGI_20 = BIT(8), 246 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 247 ATH9K_HW_CAP_2GHZ = BIT(11), 248 ATH9K_HW_CAP_5GHZ = BIT(12), 249 ATH9K_HW_CAP_APM = BIT(13), 250 #ifdef CONFIG_ATH9K_PCOEM 251 ATH9K_HW_CAP_RTT = BIT(14), 252 ATH9K_HW_CAP_MCI = BIT(15), 253 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), 254 #else 255 ATH9K_HW_CAP_RTT = 0, 256 ATH9K_HW_CAP_MCI = 0, 257 ATH9K_HW_CAP_BT_ANT_DIV = 0, 258 #endif 259 ATH9K_HW_CAP_DFS = BIT(18), 260 ATH9K_HW_CAP_PAPRD = BIT(19), 261 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), 262 }; 263 264 /* 265 * WoW device capabilities 266 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 267 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 268 * an exact user defined pattern or de-authentication/disassoc pattern. 269 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 270 * bytes of the pattern for user defined pattern, de-authentication and 271 * disassociation patterns for all types of possible frames recieved 272 * of those types. 273 */ 274 275 struct ath9k_hw_wow { 276 u32 wow_event_mask; 277 u32 wow_event_mask2; 278 u8 max_patterns; 279 }; 280 281 struct ath9k_hw_capabilities { 282 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 283 u16 rts_aggr_limit; 284 u8 tx_chainmask; 285 u8 rx_chainmask; 286 u8 chip_chainmask; 287 u8 max_txchains; 288 u8 max_rxchains; 289 u8 num_gpio_pins; 290 u8 rx_hp_qdepth; 291 u8 rx_lp_qdepth; 292 u8 rx_status_len; 293 u8 tx_desc_len; 294 u8 txs_len; 295 }; 296 297 #define AR_NO_SPUR 0x8000 298 #define AR_BASE_FREQ_2GHZ 2300 299 #define AR_BASE_FREQ_5GHZ 4900 300 #define AR_SPUR_FEEQ_BOUND_HT40 19 301 #define AR_SPUR_FEEQ_BOUND_HT20 10 302 303 enum ath9k_hw_hang_checks { 304 HW_BB_WATCHDOG = BIT(0), 305 HW_PHYRESTART_CLC_WAR = BIT(1), 306 HW_BB_RIFS_HANG = BIT(2), 307 HW_BB_DFS_HANG = BIT(3), 308 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), 309 HW_MAC_HANG = BIT(5), 310 }; 311 312 struct ath9k_ops_config { 313 int dma_beacon_response_time; 314 int sw_beacon_response_time; 315 u32 cwm_ignore_extcca; 316 u32 pcie_waen; 317 u8 analog_shiftreg; 318 u32 ofdm_trig_low; 319 u32 ofdm_trig_high; 320 u32 cck_trig_high; 321 u32 cck_trig_low; 322 u32 enable_paprd; 323 int serialize_regmode; 324 bool rx_intr_mitigation; 325 bool tx_intr_mitigation; 326 u8 max_txtrig_level; 327 u16 ani_poll_interval; /* ANI poll interval in ms */ 328 u16 hw_hang_checks; 329 u16 rimt_first; 330 u16 rimt_last; 331 332 /* Platform specific config */ 333 u32 aspm_l1_fix; 334 u32 xlna_gpio; 335 u32 ant_ctrl_comm2g_switch_enable; 336 bool xatten_margin_cfg; 337 bool alt_mingainidx; 338 bool no_pll_pwrsave; 339 bool tx_gain_buffalo; 340 bool led_active_high; 341 }; 342 343 enum ath9k_int { 344 ATH9K_INT_RX = 0x00000001, 345 ATH9K_INT_RXDESC = 0x00000002, 346 ATH9K_INT_RXHP = 0x00000001, 347 ATH9K_INT_RXLP = 0x00000002, 348 ATH9K_INT_RXNOFRM = 0x00000008, 349 ATH9K_INT_RXEOL = 0x00000010, 350 ATH9K_INT_RXORN = 0x00000020, 351 ATH9K_INT_TX = 0x00000040, 352 ATH9K_INT_TXDESC = 0x00000080, 353 ATH9K_INT_TIM_TIMER = 0x00000100, 354 ATH9K_INT_MCI = 0x00000200, 355 ATH9K_INT_BB_WATCHDOG = 0x00000400, 356 ATH9K_INT_TXURN = 0x00000800, 357 ATH9K_INT_MIB = 0x00001000, 358 ATH9K_INT_RXPHY = 0x00004000, 359 ATH9K_INT_RXKCM = 0x00008000, 360 ATH9K_INT_SWBA = 0x00010000, 361 ATH9K_INT_BMISS = 0x00040000, 362 ATH9K_INT_BNR = 0x00100000, 363 ATH9K_INT_TIM = 0x00200000, 364 ATH9K_INT_DTIM = 0x00400000, 365 ATH9K_INT_DTIMSYNC = 0x00800000, 366 ATH9K_INT_GPIO = 0x01000000, 367 ATH9K_INT_CABEND = 0x02000000, 368 ATH9K_INT_TSFOOR = 0x04000000, 369 ATH9K_INT_GENTIMER = 0x08000000, 370 ATH9K_INT_CST = 0x10000000, 371 ATH9K_INT_GTT = 0x20000000, 372 ATH9K_INT_FATAL = 0x40000000, 373 ATH9K_INT_GLOBAL = 0x80000000, 374 ATH9K_INT_BMISC = ATH9K_INT_TIM | 375 ATH9K_INT_DTIM | 376 ATH9K_INT_DTIMSYNC | 377 ATH9K_INT_TSFOOR | 378 ATH9K_INT_CABEND, 379 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 380 ATH9K_INT_RXDESC | 381 ATH9K_INT_RXEOL | 382 ATH9K_INT_RXORN | 383 ATH9K_INT_TXURN | 384 ATH9K_INT_TXDESC | 385 ATH9K_INT_MIB | 386 ATH9K_INT_RXPHY | 387 ATH9K_INT_RXKCM | 388 ATH9K_INT_SWBA | 389 ATH9K_INT_BMISS | 390 ATH9K_INT_GPIO, 391 ATH9K_INT_NOCARD = 0xffffffff 392 }; 393 394 #define MAX_RTT_TABLE_ENTRY 6 395 #define MAX_IQCAL_MEASUREMENT 8 396 #define MAX_CL_TAB_ENTRY 16 397 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) 398 399 enum ath9k_cal_flags { 400 RTT_DONE, 401 PAPRD_PACKET_SENT, 402 PAPRD_DONE, 403 NFCAL_PENDING, 404 NFCAL_INTF, 405 TXIQCAL_DONE, 406 TXCLCAL_DONE, 407 SW_PKDET_DONE, 408 }; 409 410 struct ath9k_hw_cal_data { 411 u16 channel; 412 u16 channelFlags; 413 unsigned long cal_flags; 414 int32_t CalValid; 415 int8_t iCoff; 416 int8_t qCoff; 417 u8 caldac[2]; 418 u16 small_signal_gain[AR9300_MAX_CHAINS]; 419 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 420 u32 num_measures[AR9300_MAX_CHAINS]; 421 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 422 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 423 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 424 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 425 }; 426 427 struct ath9k_channel { 428 struct ieee80211_channel *chan; 429 u16 channel; 430 u16 channelFlags; 431 s16 noisefloor; 432 }; 433 434 #define CHANNEL_5GHZ BIT(0) 435 #define CHANNEL_HALF BIT(1) 436 #define CHANNEL_QUARTER BIT(2) 437 #define CHANNEL_HT BIT(3) 438 #define CHANNEL_HT40PLUS BIT(4) 439 #define CHANNEL_HT40MINUS BIT(5) 440 441 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) 442 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 443 444 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) 445 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) 446 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 447 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 448 449 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) 450 451 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) 452 453 #define IS_CHAN_HT40(_c) \ 454 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) 455 456 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) 457 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) 458 459 enum ath9k_power_mode { 460 ATH9K_PM_AWAKE = 0, 461 ATH9K_PM_FULL_SLEEP, 462 ATH9K_PM_NETWORK_SLEEP, 463 ATH9K_PM_UNDEFINED 464 }; 465 466 enum ser_reg_mode { 467 SER_REG_MODE_OFF = 0, 468 SER_REG_MODE_ON = 1, 469 SER_REG_MODE_AUTO = 2, 470 }; 471 472 enum ath9k_rx_qtype { 473 ATH9K_RX_QUEUE_HP, 474 ATH9K_RX_QUEUE_LP, 475 ATH9K_RX_QUEUE_MAX, 476 }; 477 478 struct ath9k_beacon_state { 479 u32 bs_nexttbtt; 480 u32 bs_nextdtim; 481 u32 bs_intval; 482 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 483 u32 bs_dtimperiod; 484 u16 bs_bmissthreshold; 485 u32 bs_sleepduration; 486 u32 bs_tsfoor_threshold; 487 }; 488 489 struct chan_centers { 490 u16 synth_center; 491 u16 ctl_center; 492 u16 ext_center; 493 }; 494 495 enum { 496 ATH9K_RESET_POWER_ON, 497 ATH9K_RESET_WARM, 498 ATH9K_RESET_COLD, 499 }; 500 501 struct ath9k_hw_version { 502 u32 magic; 503 u16 devid; 504 u16 subvendorid; 505 u32 macVersion; 506 u16 macRev; 507 u16 phyRev; 508 u16 analog5GhzRev; 509 u16 analog2GhzRev; 510 enum ath_usb_dev usbdev; 511 }; 512 513 /* Generic TSF timer definitions */ 514 515 #define ATH_MAX_GEN_TIMER 16 516 517 #define AR_GENTMR_BIT(_index) (1 << (_index)) 518 519 struct ath_gen_timer_configuration { 520 u32 next_addr; 521 u32 period_addr; 522 u32 mode_addr; 523 u32 mode_mask; 524 }; 525 526 struct ath_gen_timer { 527 void (*trigger)(void *arg); 528 void (*overflow)(void *arg); 529 void *arg; 530 u8 index; 531 }; 532 533 struct ath_gen_timer_table { 534 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 535 u16 timer_mask; 536 bool tsf2_enabled; 537 }; 538 539 struct ath_hw_antcomb_conf { 540 u8 main_lna_conf; 541 u8 alt_lna_conf; 542 u8 fast_div_bias; 543 u8 main_gaintb; 544 u8 alt_gaintb; 545 int lna1_lna2_delta; 546 int lna1_lna2_switch_delta; 547 u8 div_group; 548 }; 549 550 /** 551 * struct ath_hw_radar_conf - radar detection initialization parameters 552 * 553 * @pulse_inband: threshold for checking the ratio of in-band power 554 * to total power for short radar pulses (half dB steps) 555 * @pulse_inband_step: threshold for checking an in-band power to total 556 * power ratio increase for short radar pulses (half dB steps) 557 * @pulse_height: threshold for detecting the beginning of a short 558 * radar pulse (dB step) 559 * @pulse_rssi: threshold for detecting if a short radar pulse is 560 * gone (dB step) 561 * @pulse_maxlen: maximum pulse length (0.8 us steps) 562 * 563 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 564 * @radar_inband: threshold for checking the ratio of in-band power 565 * to total power for long radar pulses (half dB steps) 566 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 567 * 568 * @ext_channel: enable extension channel radar detection 569 */ 570 struct ath_hw_radar_conf { 571 unsigned int pulse_inband; 572 unsigned int pulse_inband_step; 573 unsigned int pulse_height; 574 unsigned int pulse_rssi; 575 unsigned int pulse_maxlen; 576 577 unsigned int radar_rssi; 578 unsigned int radar_inband; 579 int fir_power; 580 581 bool ext_channel; 582 }; 583 584 /** 585 * struct ath_hw_private_ops - callbacks used internally by hardware code 586 * 587 * This structure contains private callbacks designed to only be used internally 588 * by the hardware core. 589 * 590 * @init_cal_settings: setup types of calibrations supported 591 * @init_cal: starts actual calibration 592 * 593 * @init_mode_gain_regs: Initialize TX/RX gain registers 594 * 595 * @rf_set_freq: change frequency 596 * @spur_mitigate_freq: spur mitigation 597 * @set_rf_regs: 598 * @compute_pll_control: compute the PLL control value to use for 599 * AR_RTC_PLL_CONTROL for a given channel 600 * @setup_calibration: set up calibration 601 * @iscal_supported: used to query if a type of calibration is supported 602 * 603 * @ani_cache_ini_regs: cache the values for ANI from the initial 604 * register settings through the register initialization. 605 */ 606 struct ath_hw_private_ops { 607 void (*init_hang_checks)(struct ath_hw *ah); 608 bool (*detect_mac_hang)(struct ath_hw *ah); 609 bool (*detect_bb_hang)(struct ath_hw *ah); 610 611 /* Calibration ops */ 612 void (*init_cal_settings)(struct ath_hw *ah); 613 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 614 615 void (*init_mode_gain_regs)(struct ath_hw *ah); 616 void (*setup_calibration)(struct ath_hw *ah, 617 struct ath9k_cal_list *currCal); 618 619 /* PHY ops */ 620 int (*rf_set_freq)(struct ath_hw *ah, 621 struct ath9k_channel *chan); 622 void (*spur_mitigate_freq)(struct ath_hw *ah, 623 struct ath9k_channel *chan); 624 bool (*set_rf_regs)(struct ath_hw *ah, 625 struct ath9k_channel *chan, 626 u16 modesIndex); 627 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 628 void (*init_bb)(struct ath_hw *ah, 629 struct ath9k_channel *chan); 630 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 631 void (*olc_init)(struct ath_hw *ah); 632 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 633 void (*mark_phy_inactive)(struct ath_hw *ah); 634 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 635 bool (*rfbus_req)(struct ath_hw *ah); 636 void (*rfbus_done)(struct ath_hw *ah); 637 void (*restore_chainmask)(struct ath_hw *ah); 638 u32 (*compute_pll_control)(struct ath_hw *ah, 639 struct ath9k_channel *chan); 640 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 641 int param); 642 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 643 void (*set_radar_params)(struct ath_hw *ah, 644 struct ath_hw_radar_conf *conf); 645 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 646 u8 *ini_reloaded); 647 648 /* ANI */ 649 void (*ani_cache_ini_regs)(struct ath_hw *ah); 650 }; 651 652 /** 653 * struct ath_spec_scan - parameters for Atheros spectral scan 654 * 655 * @enabled: enable/disable spectral scan 656 * @short_repeat: controls whether the chip is in spectral scan mode 657 * for 4 usec (enabled) or 204 usec (disabled) 658 * @count: number of scan results requested. There are special meanings 659 * in some chip revisions: 660 * AR92xx: highest bit set (>=128) for endless mode 661 * (spectral scan won't stopped until explicitly disabled) 662 * AR9300 and newer: 0 for endless mode 663 * @endless: true if endless mode is intended. Otherwise, count value is 664 * corrected to the next possible value. 665 * @period: time duration between successive spectral scan entry points 666 * (period*256*Tclk). Tclk = ath_common->clockrate 667 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS 668 * 669 * Note: Tclk = 40MHz or 44MHz depending upon operating mode. 670 * Typically it's 44MHz in 2/5GHz on later chips, but there's 671 * a "fast clock" check for this in 5GHz. 672 * 673 */ 674 struct ath_spec_scan { 675 bool enabled; 676 bool short_repeat; 677 bool endless; 678 u8 count; 679 u8 period; 680 u8 fft_period; 681 }; 682 683 /** 684 * struct ath_hw_ops - callbacks used by hardware code and driver code 685 * 686 * This structure contains callbacks designed to to be used internally by 687 * hardware code and also by the lower level driver. 688 * 689 * @config_pci_powersave: 690 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 691 * 692 * @spectral_scan_config: set parameters for spectral scan and enable/disable it 693 * @spectral_scan_trigger: trigger a spectral scan run 694 * @spectral_scan_wait: wait for a spectral scan run to finish 695 */ 696 struct ath_hw_ops { 697 void (*config_pci_powersave)(struct ath_hw *ah, 698 bool power_off); 699 void (*rx_enable)(struct ath_hw *ah); 700 void (*set_desc_link)(void *ds, u32 link); 701 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, 702 u8 rxchainmask, bool longcal); 703 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, 704 u32 *sync_cause_p); 705 void (*set_txdesc)(struct ath_hw *ah, void *ds, 706 struct ath_tx_info *i); 707 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 708 struct ath_tx_status *ts); 709 int (*get_duration)(struct ath_hw *ah, const void *ds, int index); 710 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 711 struct ath_hw_antcomb_conf *antconf); 712 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 713 struct ath_hw_antcomb_conf *antconf); 714 void (*spectral_scan_config)(struct ath_hw *ah, 715 struct ath_spec_scan *param); 716 void (*spectral_scan_trigger)(struct ath_hw *ah); 717 void (*spectral_scan_wait)(struct ath_hw *ah); 718 719 void (*tx99_start)(struct ath_hw *ah, u32 qnum); 720 void (*tx99_stop)(struct ath_hw *ah); 721 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); 722 723 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 724 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); 725 #endif 726 }; 727 728 struct ath_nf_limits { 729 s16 max; 730 s16 min; 731 s16 nominal; 732 }; 733 734 enum ath_cal_list { 735 TX_IQ_CAL = BIT(0), 736 TX_IQ_ON_AGC_CAL = BIT(1), 737 TX_CL_CAL = BIT(2), 738 }; 739 740 /* ah_flags */ 741 #define AH_USE_EEPROM 0x1 742 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 743 #define AH_FASTCC 0x4 744 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */ 745 746 struct ath_hw { 747 struct ath_ops reg_ops; 748 749 struct device *dev; 750 struct ieee80211_hw *hw; 751 struct ath_common common; 752 struct ath9k_hw_version hw_version; 753 struct ath9k_ops_config config; 754 struct ath9k_hw_capabilities caps; 755 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 756 struct ath9k_channel *curchan; 757 758 union { 759 struct ar5416_eeprom_def def; 760 struct ar5416_eeprom_4k map4k; 761 struct ar9287_eeprom map9287; 762 struct ar9300_eeprom ar9300_eep; 763 } eeprom; 764 const struct eeprom_ops *eep_ops; 765 766 bool sw_mgmt_crypto_tx; 767 bool sw_mgmt_crypto_rx; 768 bool is_pciexpress; 769 bool aspm_enabled; 770 bool is_monitoring; 771 bool need_an_top2_fixup; 772 u16 tx_trig_level; 773 774 u32 nf_regs[6]; 775 struct ath_nf_limits nf_2g; 776 struct ath_nf_limits nf_5g; 777 u16 rfsilent; 778 u32 rfkill_gpio; 779 u32 rfkill_polarity; 780 u32 ah_flags; 781 782 bool reset_power_on; 783 bool htc_reset_init; 784 785 enum nl80211_iftype opmode; 786 enum ath9k_power_mode power_mode; 787 788 s8 noise; 789 struct ath9k_hw_cal_data *caldata; 790 struct ath9k_pacal_info pacal_info; 791 struct ar5416Stats stats; 792 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 793 794 enum ath9k_int imask; 795 u32 imrs2_reg; 796 u32 txok_interrupt_mask; 797 u32 txerr_interrupt_mask; 798 u32 txdesc_interrupt_mask; 799 u32 txeol_interrupt_mask; 800 u32 txurn_interrupt_mask; 801 atomic_t intr_ref_cnt; 802 bool chip_fullsleep; 803 u32 modes_index; 804 805 /* Calibration */ 806 u32 supp_cals; 807 struct ath9k_cal_list iq_caldata; 808 struct ath9k_cal_list adcgain_caldata; 809 struct ath9k_cal_list adcdc_caldata; 810 struct ath9k_cal_list *cal_list; 811 struct ath9k_cal_list *cal_list_last; 812 struct ath9k_cal_list *cal_list_curr; 813 #define totalPowerMeasI meas0.unsign 814 #define totalPowerMeasQ meas1.unsign 815 #define totalIqCorrMeas meas2.sign 816 #define totalAdcIOddPhase meas0.unsign 817 #define totalAdcIEvenPhase meas1.unsign 818 #define totalAdcQOddPhase meas2.unsign 819 #define totalAdcQEvenPhase meas3.unsign 820 #define totalAdcDcOffsetIOddPhase meas0.sign 821 #define totalAdcDcOffsetIEvenPhase meas1.sign 822 #define totalAdcDcOffsetQOddPhase meas2.sign 823 #define totalAdcDcOffsetQEvenPhase meas3.sign 824 union { 825 u32 unsign[AR5416_MAX_CHAINS]; 826 int32_t sign[AR5416_MAX_CHAINS]; 827 } meas0; 828 union { 829 u32 unsign[AR5416_MAX_CHAINS]; 830 int32_t sign[AR5416_MAX_CHAINS]; 831 } meas1; 832 union { 833 u32 unsign[AR5416_MAX_CHAINS]; 834 int32_t sign[AR5416_MAX_CHAINS]; 835 } meas2; 836 union { 837 u32 unsign[AR5416_MAX_CHAINS]; 838 int32_t sign[AR5416_MAX_CHAINS]; 839 } meas3; 840 u16 cal_samples; 841 u8 enabled_cals; 842 843 u32 sta_id1_defaults; 844 u32 misc_mode; 845 846 /* Private to hardware code */ 847 struct ath_hw_private_ops private_ops; 848 /* Accessed by the lower level driver */ 849 struct ath_hw_ops ops; 850 851 /* Used to program the radio on non single-chip devices */ 852 u32 *analogBank6Data; 853 854 int coverage_class; 855 u32 slottime; 856 u32 globaltxtimeout; 857 858 /* ANI */ 859 u32 aniperiod; 860 enum ath9k_ani_cmd ani_function; 861 u32 ani_skip_count; 862 struct ar5416AniState ani; 863 864 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 865 struct ath_btcoex_hw btcoex_hw; 866 #endif 867 868 u32 intr_txqs; 869 u8 txchainmask; 870 u8 rxchainmask; 871 872 struct ath_hw_radar_conf radar_conf; 873 874 u32 originalGain[22]; 875 int initPDADC; 876 int PDADCdelta; 877 int led_pin; 878 u32 gpio_mask; 879 u32 gpio_val; 880 881 struct ar5416IniArray ini_dfs; 882 struct ar5416IniArray iniModes; 883 struct ar5416IniArray iniCommon; 884 struct ar5416IniArray iniBB_RfGain; 885 struct ar5416IniArray iniBank6; 886 struct ar5416IniArray iniAddac; 887 struct ar5416IniArray iniPcieSerdes; 888 struct ar5416IniArray iniPcieSerdesLowPower; 889 struct ar5416IniArray iniModesFastClock; 890 struct ar5416IniArray iniAdditional; 891 struct ar5416IniArray iniModesRxGain; 892 struct ar5416IniArray ini_modes_rx_gain_bounds; 893 struct ar5416IniArray iniModesTxGain; 894 struct ar5416IniArray iniCckfirNormal; 895 struct ar5416IniArray iniCckfirJapan2484; 896 struct ar5416IniArray iniModes_9271_ANI_reg; 897 struct ar5416IniArray ini_radio_post_sys2ant; 898 struct ar5416IniArray ini_modes_rxgain_5g_xlna; 899 struct ar5416IniArray ini_modes_rxgain_bb_core; 900 struct ar5416IniArray ini_modes_rxgain_bb_postamble; 901 902 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 903 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 904 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 905 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 906 907 u32 intr_gen_timer_trigger; 908 u32 intr_gen_timer_thresh; 909 struct ath_gen_timer_table hw_gen_timers; 910 911 struct ar9003_txs *ts_ring; 912 u32 ts_paddr_start; 913 u32 ts_paddr_end; 914 u16 ts_tail; 915 u16 ts_size; 916 917 u32 bb_watchdog_last_status; 918 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 919 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 920 921 unsigned int paprd_target_power; 922 unsigned int paprd_training_power; 923 unsigned int paprd_ratemask; 924 unsigned int paprd_ratemask_ht40; 925 bool paprd_table_write_done; 926 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 927 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 928 /* 929 * Store the permanent value of Reg 0x4004in WARegVal 930 * so we dont have to R/M/W. We should not be reading 931 * this register when in sleep states. 932 */ 933 u32 WARegVal; 934 935 /* Enterprise mode cap */ 936 u32 ent_mode; 937 938 #ifdef CONFIG_ATH9K_WOW 939 struct ath9k_hw_wow wow; 940 #endif 941 bool is_clk_25mhz; 942 int (*get_mac_revision)(void); 943 int (*external_reset)(void); 944 bool disable_2ghz; 945 bool disable_5ghz; 946 947 const struct firmware *eeprom_blob; 948 949 struct ath_dynack dynack; 950 951 bool tpc_enabled; 952 u8 tx_power[Ar5416RateSize]; 953 u8 tx_power_stbc[Ar5416RateSize]; 954 }; 955 956 struct ath_bus_ops { 957 enum ath_bus_type ath_bus_type; 958 void (*read_cachesize)(struct ath_common *common, int *csz); 959 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 960 void (*bt_coex_prep)(struct ath_common *common); 961 void (*aspm_init)(struct ath_common *common); 962 }; 963 964 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 965 { 966 return &ah->common; 967 } 968 969 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 970 { 971 return &(ath9k_hw_common(ah)->regulatory); 972 } 973 974 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 975 { 976 return &ah->private_ops; 977 } 978 979 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 980 { 981 return &ah->ops; 982 } 983 984 static inline u8 get_streams(int mask) 985 { 986 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 987 } 988 989 /* Initialization, Detach, Reset */ 990 void ath9k_hw_deinit(struct ath_hw *ah); 991 int ath9k_hw_init(struct ath_hw *ah); 992 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 993 struct ath9k_hw_cal_data *caldata, bool fastcc); 994 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 995 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 996 997 /* GPIO / RFKILL / Antennae */ 998 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 999 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 1000 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 1001 u32 ah_signal_type); 1002 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 1003 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 1004 1005 /* General Operation */ 1006 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 1007 int hw_delay); 1008 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 1009 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 1010 int column, unsigned int *writecnt); 1011 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1012 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 1013 u8 phy, int kbps, 1014 u32 frameLen, u16 rateix, bool shortPreamble); 1015 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 1016 struct ath9k_channel *chan, 1017 struct chan_centers *centers); 1018 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 1019 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 1020 bool ath9k_hw_phy_disable(struct ath_hw *ah); 1021 bool ath9k_hw_disable(struct ath_hw *ah); 1022 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 1023 void ath9k_hw_setopmode(struct ath_hw *ah); 1024 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 1025 void ath9k_hw_write_associd(struct ath_hw *ah); 1026 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1027 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1028 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1029 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1030 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur); 1031 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1032 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1033 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1034 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); 1035 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1036 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1037 const struct ath9k_beacon_state *bs); 1038 void ath9k_hw_check_nav(struct ath_hw *ah); 1039 bool ath9k_hw_check_alive(struct ath_hw *ah); 1040 1041 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1042 1043 /* Generic hw timer primitives */ 1044 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1045 void (*trigger)(void *), 1046 void (*overflow)(void *), 1047 void *arg, 1048 u8 timer_index); 1049 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1050 struct ath_gen_timer *timer, 1051 u32 timer_next, 1052 u32 timer_period); 1053 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah); 1054 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1055 1056 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1057 void ath_gen_timer_isr(struct ath_hw *hw); 1058 1059 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1060 1061 /* PHY */ 1062 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1063 u32 *coef_mantissa, u32 *coef_exponent); 1064 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1065 bool test); 1066 1067 /* 1068 * Code Specific to AR5008, AR9001 or AR9002, 1069 * we stuff these here to avoid callbacks for AR9003. 1070 */ 1071 int ar9002_hw_rf_claim(struct ath_hw *ah); 1072 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1073 1074 /* 1075 * Code specific to AR9003, we stuff these here to avoid callbacks 1076 * for older families 1077 */ 1078 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); 1079 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1080 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1081 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1082 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1083 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1084 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1085 struct ath9k_hw_cal_data *caldata, 1086 int chain); 1087 int ar9003_paprd_create_curve(struct ath_hw *ah, 1088 struct ath9k_hw_cal_data *caldata, int chain); 1089 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1090 int ar9003_paprd_init_table(struct ath_hw *ah); 1091 bool ar9003_paprd_is_done(struct ath_hw *ah); 1092 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1093 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1094 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, 1095 struct ath9k_channel *chan); 1096 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1097 struct ath9k_channel *chan, int ht40_delta); 1098 1099 /* Hardware family op attach helpers */ 1100 int ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1101 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1102 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1103 1104 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1105 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1106 1107 int ar9002_hw_attach_ops(struct ath_hw *ah); 1108 void ar9003_hw_attach_ops(struct ath_hw *ah); 1109 1110 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1111 1112 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1113 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1114 1115 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); 1116 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); 1117 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); 1118 1119 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1120 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1121 { 1122 return ah->btcoex_hw.enabled; 1123 } 1124 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1125 { 1126 return ah->common.btcoex_enabled && 1127 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1128 1129 } 1130 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1131 static inline enum ath_btcoex_scheme 1132 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1133 { 1134 return ah->btcoex_hw.scheme; 1135 } 1136 #else 1137 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1138 { 1139 return false; 1140 } 1141 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1142 { 1143 return false; 1144 } 1145 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1146 { 1147 } 1148 static inline enum ath_btcoex_scheme 1149 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1150 { 1151 return ATH_BTCOEX_CFG_NONE; 1152 } 1153 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1154 1155 1156 #ifdef CONFIG_ATH9K_WOW 1157 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1158 u8 *user_mask, int pattern_count, 1159 int pattern_len); 1160 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1161 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1162 #else 1163 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1164 u8 *user_pattern, 1165 u8 *user_mask, 1166 int pattern_count, 1167 int pattern_len) 1168 { 1169 return 0; 1170 } 1171 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1172 { 1173 return 0; 1174 } 1175 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1176 { 1177 } 1178 #endif 1179 1180 #define ATH9K_CLOCK_RATE_CCK 22 1181 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1182 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1183 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1184 1185 #endif 1186