1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 34 #define ATHEROS_VENDOR_ID 0x168c 35 36 #define AR5416_DEVID_PCI 0x0023 37 #define AR5416_DEVID_PCIE 0x0024 38 #define AR9160_DEVID_PCI 0x0027 39 #define AR9280_DEVID_PCI 0x0029 40 #define AR9280_DEVID_PCIE 0x002a 41 #define AR9285_DEVID_PCIE 0x002b 42 #define AR2427_DEVID_PCIE 0x002c 43 #define AR9287_DEVID_PCI 0x002d 44 #define AR9287_DEVID_PCIE 0x002e 45 #define AR9300_DEVID_PCIE 0x0030 46 #define AR9300_DEVID_AR9340 0x0031 47 #define AR9300_DEVID_AR9485_PCIE 0x0032 48 #define AR9300_DEVID_AR9580 0x0033 49 #define AR9300_DEVID_AR9462 0x0034 50 #define AR9300_DEVID_AR9330 0x0035 51 52 #define AR5416_AR9100_DEVID 0x000b 53 54 #define AR_SUBVENDOR_ID_NOG 0x0e11 55 #define AR_SUBVENDOR_ID_NEW_A 0x7065 56 #define AR5416_MAGIC 0x19641014 57 58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 61 62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 63 64 #define ATH_DEFAULT_NOISE_FLOOR -95 65 66 #define ATH9K_RSSI_BAD -128 67 68 #define ATH9K_NUM_CHANNELS 38 69 70 /* Register read/write primitives */ 71 #define REG_WRITE(_ah, _reg, _val) \ 72 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 73 74 #define REG_READ(_ah, _reg) \ 75 (_ah)->reg_ops.read((_ah), (_reg)) 76 77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 79 80 #define REG_RMW(_ah, _reg, _set, _clr) \ 81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 82 83 #define ENABLE_REGWRITE_BUFFER(_ah) \ 84 do { \ 85 if ((_ah)->reg_ops.enable_write_buffer) \ 86 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 87 } while (0) 88 89 #define REGWRITE_BUFFER_FLUSH(_ah) \ 90 do { \ 91 if ((_ah)->reg_ops.write_flush) \ 92 (_ah)->reg_ops.write_flush((_ah)); \ 93 } while (0) 94 95 #define PR_EEP(_s, _val) \ 96 do { \ 97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \ 98 _s, (_val)); \ 99 } while (0) 100 101 #define SM(_v, _f) (((_v) << _f##_S) & _f) 102 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 103 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 105 #define REG_READ_FIELD(_a, _r, _f) \ 106 (((REG_READ(_a, _r) & _f) >> _f##_S)) 107 #define REG_SET_BIT(_a, _r, _f) \ 108 REG_RMW(_a, _r, (_f), 0) 109 #define REG_CLR_BIT(_a, _r, _f) \ 110 REG_RMW(_a, _r, 0, (_f)) 111 112 #define DO_DELAY(x) do { \ 113 if (((++(x) % 64) == 0) && \ 114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 115 != ATH_USB)) \ 116 udelay(1); \ 117 } while (0) 118 119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 120 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 121 122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 129 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 130 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 133 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 134 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 135 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 136 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 137 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 138 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 139 140 #define AR_GPIOD_MASK 0x00001FFF 141 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 142 143 #define BASE_ACTIVATE_DELAY 100 144 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 145 #define COEF_SCALE_S 24 146 #define HT40_CHANNEL_CENTER_SHIFT 10 147 148 #define ATH9K_ANTENNA0_CHAINMASK 0x1 149 #define ATH9K_ANTENNA1_CHAINMASK 0x2 150 151 #define ATH9K_NUM_DMA_DEBUG_REGS 8 152 #define ATH9K_NUM_QUEUES 10 153 154 #define MAX_RATE_POWER 63 155 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 156 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 157 #define AH_TIME_QUANTUM 10 158 #define AR_KEYTABLE_SIZE 128 159 #define POWER_UP_TIME 10000 160 #define SPUR_RSSI_THRESH 40 161 #define UPPER_5G_SUB_BAND_START 5700 162 #define MID_5G_SUB_BAND_START 5400 163 164 #define CAB_TIMEOUT_VAL 10 165 #define BEACON_TIMEOUT_VAL 10 166 #define MIN_BEACON_TIMEOUT_VAL 1 167 #define SLEEP_SLOP 3 168 169 #define INIT_CONFIG_STATUS 0x00000000 170 #define INIT_RSSI_THR 0x00000700 171 #define INIT_BCON_CNTRL_REG 0x00000000 172 173 #define TU_TO_USEC(_tu) ((_tu) << 10) 174 175 #define ATH9K_HW_RX_HP_QDEPTH 16 176 #define ATH9K_HW_RX_LP_QDEPTH 128 177 178 #define PAPRD_GAIN_TABLE_ENTRIES 32 179 #define PAPRD_TABLE_SZ 24 180 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 181 182 enum ath_hw_txq_subtype { 183 ATH_TXQ_AC_BE = 0, 184 ATH_TXQ_AC_BK = 1, 185 ATH_TXQ_AC_VI = 2, 186 ATH_TXQ_AC_VO = 3, 187 }; 188 189 enum ath_ini_subsys { 190 ATH_INI_PRE = 0, 191 ATH_INI_CORE, 192 ATH_INI_POST, 193 ATH_INI_NUM_SPLIT, 194 }; 195 196 enum ath9k_hw_caps { 197 ATH9K_HW_CAP_HT = BIT(0), 198 ATH9K_HW_CAP_RFSILENT = BIT(1), 199 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 200 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 201 ATH9K_HW_CAP_EDMA = BIT(4), 202 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 203 ATH9K_HW_CAP_LDPC = BIT(6), 204 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 205 ATH9K_HW_CAP_SGI_20 = BIT(8), 206 ATH9K_HW_CAP_PAPRD = BIT(9), 207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 208 ATH9K_HW_CAP_2GHZ = BIT(11), 209 ATH9K_HW_CAP_5GHZ = BIT(12), 210 ATH9K_HW_CAP_APM = BIT(13), 211 ATH9K_HW_CAP_RTT = BIT(14), 212 ATH9K_HW_CAP_MCI = BIT(15), 213 ATH9K_HW_CAP_DFS = BIT(16), 214 }; 215 216 struct ath9k_hw_capabilities { 217 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 218 u16 rts_aggr_limit; 219 u8 tx_chainmask; 220 u8 rx_chainmask; 221 u8 max_txchains; 222 u8 max_rxchains; 223 u8 num_gpio_pins; 224 u8 rx_hp_qdepth; 225 u8 rx_lp_qdepth; 226 u8 rx_status_len; 227 u8 tx_desc_len; 228 u8 txs_len; 229 u16 pcie_lcr_offset; 230 bool pcie_lcr_extsync_en; 231 }; 232 233 struct ath9k_ops_config { 234 int dma_beacon_response_time; 235 int sw_beacon_response_time; 236 int additional_swba_backoff; 237 int ack_6mb; 238 u32 cwm_ignore_extcca; 239 bool pcieSerDesWrite; 240 u8 pcie_clock_req; 241 u32 pcie_waen; 242 u8 analog_shiftreg; 243 u8 paprd_disable; 244 u32 ofdm_trig_low; 245 u32 ofdm_trig_high; 246 u32 cck_trig_high; 247 u32 cck_trig_low; 248 u32 enable_ani; 249 int serialize_regmode; 250 bool rx_intr_mitigation; 251 bool tx_intr_mitigation; 252 #define SPUR_DISABLE 0 253 #define SPUR_ENABLE_IOCTL 1 254 #define SPUR_ENABLE_EEPROM 2 255 #define AR_SPUR_5413_1 1640 256 #define AR_SPUR_5413_2 1200 257 #define AR_NO_SPUR 0x8000 258 #define AR_BASE_FREQ_2GHZ 2300 259 #define AR_BASE_FREQ_5GHZ 4900 260 #define AR_SPUR_FEEQ_BOUND_HT40 19 261 #define AR_SPUR_FEEQ_BOUND_HT20 10 262 int spurmode; 263 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 264 u8 max_txtrig_level; 265 u16 ani_poll_interval; /* ANI poll interval in ms */ 266 }; 267 268 enum ath9k_int { 269 ATH9K_INT_RX = 0x00000001, 270 ATH9K_INT_RXDESC = 0x00000002, 271 ATH9K_INT_RXHP = 0x00000001, 272 ATH9K_INT_RXLP = 0x00000002, 273 ATH9K_INT_RXNOFRM = 0x00000008, 274 ATH9K_INT_RXEOL = 0x00000010, 275 ATH9K_INT_RXORN = 0x00000020, 276 ATH9K_INT_TX = 0x00000040, 277 ATH9K_INT_TXDESC = 0x00000080, 278 ATH9K_INT_TIM_TIMER = 0x00000100, 279 ATH9K_INT_MCI = 0x00000200, 280 ATH9K_INT_BB_WATCHDOG = 0x00000400, 281 ATH9K_INT_TXURN = 0x00000800, 282 ATH9K_INT_MIB = 0x00001000, 283 ATH9K_INT_RXPHY = 0x00004000, 284 ATH9K_INT_RXKCM = 0x00008000, 285 ATH9K_INT_SWBA = 0x00010000, 286 ATH9K_INT_BMISS = 0x00040000, 287 ATH9K_INT_BNR = 0x00100000, 288 ATH9K_INT_TIM = 0x00200000, 289 ATH9K_INT_DTIM = 0x00400000, 290 ATH9K_INT_DTIMSYNC = 0x00800000, 291 ATH9K_INT_GPIO = 0x01000000, 292 ATH9K_INT_CABEND = 0x02000000, 293 ATH9K_INT_TSFOOR = 0x04000000, 294 ATH9K_INT_GENTIMER = 0x08000000, 295 ATH9K_INT_CST = 0x10000000, 296 ATH9K_INT_GTT = 0x20000000, 297 ATH9K_INT_FATAL = 0x40000000, 298 ATH9K_INT_GLOBAL = 0x80000000, 299 ATH9K_INT_BMISC = ATH9K_INT_TIM | 300 ATH9K_INT_DTIM | 301 ATH9K_INT_DTIMSYNC | 302 ATH9K_INT_TSFOOR | 303 ATH9K_INT_CABEND, 304 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 305 ATH9K_INT_RXDESC | 306 ATH9K_INT_RXEOL | 307 ATH9K_INT_RXORN | 308 ATH9K_INT_TXURN | 309 ATH9K_INT_TXDESC | 310 ATH9K_INT_MIB | 311 ATH9K_INT_RXPHY | 312 ATH9K_INT_RXKCM | 313 ATH9K_INT_SWBA | 314 ATH9K_INT_BMISS | 315 ATH9K_INT_GPIO, 316 ATH9K_INT_NOCARD = 0xffffffff 317 }; 318 319 #define CHANNEL_CW_INT 0x00002 320 #define CHANNEL_CCK 0x00020 321 #define CHANNEL_OFDM 0x00040 322 #define CHANNEL_2GHZ 0x00080 323 #define CHANNEL_5GHZ 0x00100 324 #define CHANNEL_PASSIVE 0x00200 325 #define CHANNEL_DYN 0x00400 326 #define CHANNEL_HALF 0x04000 327 #define CHANNEL_QUARTER 0x08000 328 #define CHANNEL_HT20 0x10000 329 #define CHANNEL_HT40PLUS 0x20000 330 #define CHANNEL_HT40MINUS 0x40000 331 332 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 333 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 334 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 335 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 336 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 337 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 338 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 339 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 340 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 341 #define CHANNEL_ALL \ 342 (CHANNEL_OFDM| \ 343 CHANNEL_CCK| \ 344 CHANNEL_2GHZ | \ 345 CHANNEL_5GHZ | \ 346 CHANNEL_HT20 | \ 347 CHANNEL_HT40PLUS | \ 348 CHANNEL_HT40MINUS) 349 350 #define MAX_RTT_TABLE_ENTRY 6 351 #define MAX_IQCAL_MEASUREMENT 8 352 #define MAX_CL_TAB_ENTRY 16 353 354 struct ath9k_hw_cal_data { 355 u16 channel; 356 u32 channelFlags; 357 int32_t CalValid; 358 int8_t iCoff; 359 int8_t qCoff; 360 bool rtt_done; 361 bool paprd_done; 362 bool nfcal_pending; 363 bool nfcal_interference; 364 bool done_txiqcal_once; 365 bool done_txclcal_once; 366 u16 small_signal_gain[AR9300_MAX_CHAINS]; 367 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 368 u32 num_measures[AR9300_MAX_CHAINS]; 369 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 370 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 371 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 372 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 373 }; 374 375 struct ath9k_channel { 376 struct ieee80211_channel *chan; 377 struct ar5416AniState ani; 378 u16 channel; 379 u32 channelFlags; 380 u32 chanmode; 381 s16 noisefloor; 382 }; 383 384 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 385 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 386 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 387 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 388 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 389 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 390 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 391 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 392 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 393 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 394 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 395 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 396 397 /* These macros check chanmode and not channelFlags */ 398 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 399 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 400 ((_c)->chanmode == CHANNEL_G_HT20)) 401 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 402 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 403 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 404 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 405 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 406 407 enum ath9k_power_mode { 408 ATH9K_PM_AWAKE = 0, 409 ATH9K_PM_FULL_SLEEP, 410 ATH9K_PM_NETWORK_SLEEP, 411 ATH9K_PM_UNDEFINED 412 }; 413 414 enum ser_reg_mode { 415 SER_REG_MODE_OFF = 0, 416 SER_REG_MODE_ON = 1, 417 SER_REG_MODE_AUTO = 2, 418 }; 419 420 enum ath9k_rx_qtype { 421 ATH9K_RX_QUEUE_HP, 422 ATH9K_RX_QUEUE_LP, 423 ATH9K_RX_QUEUE_MAX, 424 }; 425 426 struct ath9k_beacon_state { 427 u32 bs_nexttbtt; 428 u32 bs_nextdtim; 429 u32 bs_intval; 430 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 431 u32 bs_dtimperiod; 432 u16 bs_cfpperiod; 433 u16 bs_cfpmaxduration; 434 u32 bs_cfpnext; 435 u16 bs_timoffset; 436 u16 bs_bmissthreshold; 437 u32 bs_sleepduration; 438 u32 bs_tsfoor_threshold; 439 }; 440 441 struct chan_centers { 442 u16 synth_center; 443 u16 ctl_center; 444 u16 ext_center; 445 }; 446 447 enum { 448 ATH9K_RESET_POWER_ON, 449 ATH9K_RESET_WARM, 450 ATH9K_RESET_COLD, 451 }; 452 453 struct ath9k_hw_version { 454 u32 magic; 455 u16 devid; 456 u16 subvendorid; 457 u32 macVersion; 458 u16 macRev; 459 u16 phyRev; 460 u16 analog5GhzRev; 461 u16 analog2GhzRev; 462 enum ath_usb_dev usbdev; 463 }; 464 465 /* Generic TSF timer definitions */ 466 467 #define ATH_MAX_GEN_TIMER 16 468 469 #define AR_GENTMR_BIT(_index) (1 << (_index)) 470 471 /* 472 * Using de Bruijin sequence to look up 1's index in a 32 bit number 473 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 474 */ 475 #define debruijn32 0x077CB531U 476 477 struct ath_gen_timer_configuration { 478 u32 next_addr; 479 u32 period_addr; 480 u32 mode_addr; 481 u32 mode_mask; 482 }; 483 484 struct ath_gen_timer { 485 void (*trigger)(void *arg); 486 void (*overflow)(void *arg); 487 void *arg; 488 u8 index; 489 }; 490 491 struct ath_gen_timer_table { 492 u32 gen_timer_index[32]; 493 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 494 union { 495 unsigned long timer_bits; 496 u16 val; 497 } timer_mask; 498 }; 499 500 struct ath_hw_antcomb_conf { 501 u8 main_lna_conf; 502 u8 alt_lna_conf; 503 u8 fast_div_bias; 504 u8 main_gaintb; 505 u8 alt_gaintb; 506 int lna1_lna2_delta; 507 u8 div_group; 508 }; 509 510 /** 511 * struct ath_hw_radar_conf - radar detection initialization parameters 512 * 513 * @pulse_inband: threshold for checking the ratio of in-band power 514 * to total power for short radar pulses (half dB steps) 515 * @pulse_inband_step: threshold for checking an in-band power to total 516 * power ratio increase for short radar pulses (half dB steps) 517 * @pulse_height: threshold for detecting the beginning of a short 518 * radar pulse (dB step) 519 * @pulse_rssi: threshold for detecting if a short radar pulse is 520 * gone (dB step) 521 * @pulse_maxlen: maximum pulse length (0.8 us steps) 522 * 523 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 524 * @radar_inband: threshold for checking the ratio of in-band power 525 * to total power for long radar pulses (half dB steps) 526 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 527 * 528 * @ext_channel: enable extension channel radar detection 529 */ 530 struct ath_hw_radar_conf { 531 unsigned int pulse_inband; 532 unsigned int pulse_inband_step; 533 unsigned int pulse_height; 534 unsigned int pulse_rssi; 535 unsigned int pulse_maxlen; 536 537 unsigned int radar_rssi; 538 unsigned int radar_inband; 539 int fir_power; 540 541 bool ext_channel; 542 }; 543 544 /** 545 * struct ath_hw_private_ops - callbacks used internally by hardware code 546 * 547 * This structure contains private callbacks designed to only be used internally 548 * by the hardware core. 549 * 550 * @init_cal_settings: setup types of calibrations supported 551 * @init_cal: starts actual calibration 552 * 553 * @init_mode_regs: Initializes mode registers 554 * @init_mode_gain_regs: Initialize TX/RX gain registers 555 * 556 * @rf_set_freq: change frequency 557 * @spur_mitigate_freq: spur mitigation 558 * @rf_alloc_ext_banks: 559 * @rf_free_ext_banks: 560 * @set_rf_regs: 561 * @compute_pll_control: compute the PLL control value to use for 562 * AR_RTC_PLL_CONTROL for a given channel 563 * @setup_calibration: set up calibration 564 * @iscal_supported: used to query if a type of calibration is supported 565 * 566 * @ani_cache_ini_regs: cache the values for ANI from the initial 567 * register settings through the register initialization. 568 */ 569 struct ath_hw_private_ops { 570 /* Calibration ops */ 571 void (*init_cal_settings)(struct ath_hw *ah); 572 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 573 574 void (*init_mode_regs)(struct ath_hw *ah); 575 void (*init_mode_gain_regs)(struct ath_hw *ah); 576 void (*setup_calibration)(struct ath_hw *ah, 577 struct ath9k_cal_list *currCal); 578 579 /* PHY ops */ 580 int (*rf_set_freq)(struct ath_hw *ah, 581 struct ath9k_channel *chan); 582 void (*spur_mitigate_freq)(struct ath_hw *ah, 583 struct ath9k_channel *chan); 584 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 585 void (*rf_free_ext_banks)(struct ath_hw *ah); 586 bool (*set_rf_regs)(struct ath_hw *ah, 587 struct ath9k_channel *chan, 588 u16 modesIndex); 589 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 590 void (*init_bb)(struct ath_hw *ah, 591 struct ath9k_channel *chan); 592 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 593 void (*olc_init)(struct ath_hw *ah); 594 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 595 void (*mark_phy_inactive)(struct ath_hw *ah); 596 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 597 bool (*rfbus_req)(struct ath_hw *ah); 598 void (*rfbus_done)(struct ath_hw *ah); 599 void (*restore_chainmask)(struct ath_hw *ah); 600 u32 (*compute_pll_control)(struct ath_hw *ah, 601 struct ath9k_channel *chan); 602 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 603 int param); 604 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 605 void (*set_radar_params)(struct ath_hw *ah, 606 struct ath_hw_radar_conf *conf); 607 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 608 u8 *ini_reloaded); 609 610 /* ANI */ 611 void (*ani_cache_ini_regs)(struct ath_hw *ah); 612 }; 613 614 /** 615 * struct ath_hw_ops - callbacks used by hardware code and driver code 616 * 617 * This structure contains callbacks designed to to be used internally by 618 * hardware code and also by the lower level driver. 619 * 620 * @config_pci_powersave: 621 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 622 */ 623 struct ath_hw_ops { 624 void (*config_pci_powersave)(struct ath_hw *ah, 625 bool power_off); 626 void (*rx_enable)(struct ath_hw *ah); 627 void (*set_desc_link)(void *ds, u32 link); 628 bool (*calibrate)(struct ath_hw *ah, 629 struct ath9k_channel *chan, 630 u8 rxchainmask, 631 bool longcal); 632 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 633 void (*set_txdesc)(struct ath_hw *ah, void *ds, 634 struct ath_tx_info *i); 635 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 636 struct ath_tx_status *ts); 637 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 638 struct ath_hw_antcomb_conf *antconf); 639 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 640 struct ath_hw_antcomb_conf *antconf); 641 642 }; 643 644 struct ath_nf_limits { 645 s16 max; 646 s16 min; 647 s16 nominal; 648 }; 649 650 enum ath_cal_list { 651 TX_IQ_CAL = BIT(0), 652 TX_IQ_ON_AGC_CAL = BIT(1), 653 TX_CL_CAL = BIT(2), 654 }; 655 656 /* ah_flags */ 657 #define AH_USE_EEPROM 0x1 658 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 659 #define AH_FASTCC 0x4 660 661 struct ath_hw { 662 struct ath_ops reg_ops; 663 664 struct ieee80211_hw *hw; 665 struct ath_common common; 666 struct ath9k_hw_version hw_version; 667 struct ath9k_ops_config config; 668 struct ath9k_hw_capabilities caps; 669 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 670 struct ath9k_channel *curchan; 671 672 union { 673 struct ar5416_eeprom_def def; 674 struct ar5416_eeprom_4k map4k; 675 struct ar9287_eeprom map9287; 676 struct ar9300_eeprom ar9300_eep; 677 } eeprom; 678 const struct eeprom_ops *eep_ops; 679 680 bool sw_mgmt_crypto; 681 bool is_pciexpress; 682 bool aspm_enabled; 683 bool is_monitoring; 684 bool need_an_top2_fixup; 685 u16 tx_trig_level; 686 687 u32 nf_regs[6]; 688 struct ath_nf_limits nf_2g; 689 struct ath_nf_limits nf_5g; 690 u16 rfsilent; 691 u32 rfkill_gpio; 692 u32 rfkill_polarity; 693 u32 ah_flags; 694 695 bool htc_reset_init; 696 697 enum nl80211_iftype opmode; 698 enum ath9k_power_mode power_mode; 699 700 s8 noise; 701 struct ath9k_hw_cal_data *caldata; 702 struct ath9k_pacal_info pacal_info; 703 struct ar5416Stats stats; 704 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 705 706 enum ath9k_int imask; 707 u32 imrs2_reg; 708 u32 txok_interrupt_mask; 709 u32 txerr_interrupt_mask; 710 u32 txdesc_interrupt_mask; 711 u32 txeol_interrupt_mask; 712 u32 txurn_interrupt_mask; 713 atomic_t intr_ref_cnt; 714 bool chip_fullsleep; 715 u32 atim_window; 716 u32 modes_index; 717 718 /* Calibration */ 719 u32 supp_cals; 720 struct ath9k_cal_list iq_caldata; 721 struct ath9k_cal_list adcgain_caldata; 722 struct ath9k_cal_list adcdc_caldata; 723 struct ath9k_cal_list tempCompCalData; 724 struct ath9k_cal_list *cal_list; 725 struct ath9k_cal_list *cal_list_last; 726 struct ath9k_cal_list *cal_list_curr; 727 #define totalPowerMeasI meas0.unsign 728 #define totalPowerMeasQ meas1.unsign 729 #define totalIqCorrMeas meas2.sign 730 #define totalAdcIOddPhase meas0.unsign 731 #define totalAdcIEvenPhase meas1.unsign 732 #define totalAdcQOddPhase meas2.unsign 733 #define totalAdcQEvenPhase meas3.unsign 734 #define totalAdcDcOffsetIOddPhase meas0.sign 735 #define totalAdcDcOffsetIEvenPhase meas1.sign 736 #define totalAdcDcOffsetQOddPhase meas2.sign 737 #define totalAdcDcOffsetQEvenPhase meas3.sign 738 union { 739 u32 unsign[AR5416_MAX_CHAINS]; 740 int32_t sign[AR5416_MAX_CHAINS]; 741 } meas0; 742 union { 743 u32 unsign[AR5416_MAX_CHAINS]; 744 int32_t sign[AR5416_MAX_CHAINS]; 745 } meas1; 746 union { 747 u32 unsign[AR5416_MAX_CHAINS]; 748 int32_t sign[AR5416_MAX_CHAINS]; 749 } meas2; 750 union { 751 u32 unsign[AR5416_MAX_CHAINS]; 752 int32_t sign[AR5416_MAX_CHAINS]; 753 } meas3; 754 u16 cal_samples; 755 u8 enabled_cals; 756 757 u32 sta_id1_defaults; 758 u32 misc_mode; 759 760 /* Private to hardware code */ 761 struct ath_hw_private_ops private_ops; 762 /* Accessed by the lower level driver */ 763 struct ath_hw_ops ops; 764 765 /* Used to program the radio on non single-chip devices */ 766 u32 *analogBank0Data; 767 u32 *analogBank1Data; 768 u32 *analogBank2Data; 769 u32 *analogBank3Data; 770 u32 *analogBank6Data; 771 u32 *analogBank6TPCData; 772 u32 *analogBank7Data; 773 u32 *bank6Temp; 774 775 int coverage_class; 776 u32 slottime; 777 u32 globaltxtimeout; 778 779 /* ANI */ 780 u32 proc_phyerr; 781 u32 aniperiod; 782 int totalSizeDesired[5]; 783 int coarse_high[5]; 784 int coarse_low[5]; 785 int firpwr[5]; 786 enum ath9k_ani_cmd ani_function; 787 788 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 789 struct ath_btcoex_hw btcoex_hw; 790 #endif 791 792 u32 intr_txqs; 793 u8 txchainmask; 794 u8 rxchainmask; 795 796 struct ath_hw_radar_conf radar_conf; 797 798 u32 originalGain[22]; 799 int initPDADC; 800 int PDADCdelta; 801 int led_pin; 802 u32 gpio_mask; 803 u32 gpio_val; 804 805 struct ar5416IniArray iniModes; 806 struct ar5416IniArray iniCommon; 807 struct ar5416IniArray iniBank0; 808 struct ar5416IniArray iniBB_RfGain; 809 struct ar5416IniArray iniBank1; 810 struct ar5416IniArray iniBank2; 811 struct ar5416IniArray iniBank3; 812 struct ar5416IniArray iniBank6; 813 struct ar5416IniArray iniBank6TPC; 814 struct ar5416IniArray iniBank7; 815 struct ar5416IniArray iniAddac; 816 struct ar5416IniArray iniPcieSerdes; 817 struct ar5416IniArray iniPcieSerdesLowPower; 818 struct ar5416IniArray iniModesFastClock; 819 struct ar5416IniArray iniAdditional; 820 struct ar5416IniArray iniModesRxGain; 821 struct ar5416IniArray iniModesTxGain; 822 struct ar5416IniArray iniCckfirNormal; 823 struct ar5416IniArray iniCckfirJapan2484; 824 struct ar5416IniArray ini_japan2484; 825 struct ar5416IniArray iniModes_9271_ANI_reg; 826 struct ar5416IniArray ini_radio_post_sys2ant; 827 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR; 828 829 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 830 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 831 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 832 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 833 834 u32 intr_gen_timer_trigger; 835 u32 intr_gen_timer_thresh; 836 struct ath_gen_timer_table hw_gen_timers; 837 838 struct ar9003_txs *ts_ring; 839 u32 ts_paddr_start; 840 u32 ts_paddr_end; 841 u16 ts_tail; 842 u16 ts_size; 843 844 u32 bb_watchdog_last_status; 845 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 846 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 847 848 unsigned int paprd_target_power; 849 unsigned int paprd_training_power; 850 unsigned int paprd_ratemask; 851 unsigned int paprd_ratemask_ht40; 852 bool paprd_table_write_done; 853 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 854 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 855 /* 856 * Store the permanent value of Reg 0x4004in WARegVal 857 * so we dont have to R/M/W. We should not be reading 858 * this register when in sleep states. 859 */ 860 u32 WARegVal; 861 862 /* Enterprise mode cap */ 863 u32 ent_mode; 864 865 bool is_clk_25mhz; 866 int (*get_mac_revision)(void); 867 int (*external_reset)(void); 868 }; 869 870 struct ath_bus_ops { 871 enum ath_bus_type ath_bus_type; 872 void (*read_cachesize)(struct ath_common *common, int *csz); 873 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 874 void (*bt_coex_prep)(struct ath_common *common); 875 void (*extn_synch_en)(struct ath_common *common); 876 void (*aspm_init)(struct ath_common *common); 877 }; 878 879 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 880 { 881 return &ah->common; 882 } 883 884 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 885 { 886 return &(ath9k_hw_common(ah)->regulatory); 887 } 888 889 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 890 { 891 return &ah->private_ops; 892 } 893 894 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 895 { 896 return &ah->ops; 897 } 898 899 static inline u8 get_streams(int mask) 900 { 901 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 902 } 903 904 /* Initialization, Detach, Reset */ 905 void ath9k_hw_deinit(struct ath_hw *ah); 906 int ath9k_hw_init(struct ath_hw *ah); 907 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 908 struct ath9k_hw_cal_data *caldata, bool fastcc); 909 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 910 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 911 912 /* GPIO / RFKILL / Antennae */ 913 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 914 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 915 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 916 u32 ah_signal_type); 917 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 918 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 919 920 /* General Operation */ 921 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 922 int hw_delay); 923 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 924 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 925 int column, unsigned int *writecnt); 926 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 927 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 928 u8 phy, int kbps, 929 u32 frameLen, u16 rateix, bool shortPreamble); 930 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 931 struct ath9k_channel *chan, 932 struct chan_centers *centers); 933 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 934 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 935 bool ath9k_hw_phy_disable(struct ath_hw *ah); 936 bool ath9k_hw_disable(struct ath_hw *ah); 937 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 938 void ath9k_hw_setopmode(struct ath_hw *ah); 939 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 940 void ath9k_hw_write_associd(struct ath_hw *ah); 941 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 942 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 943 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 944 void ath9k_hw_reset_tsf(struct ath_hw *ah); 945 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 946 void ath9k_hw_init_global_settings(struct ath_hw *ah); 947 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 948 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 949 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 950 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 951 const struct ath9k_beacon_state *bs); 952 bool ath9k_hw_check_alive(struct ath_hw *ah); 953 954 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 955 956 #ifdef CONFIG_ATH9K_DEBUGFS 957 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause); 958 #else 959 static inline void ath9k_debug_sync_cause(struct ath_common *common, 960 u32 sync_cause) {} 961 #endif 962 963 /* Generic hw timer primitives */ 964 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 965 void (*trigger)(void *), 966 void (*overflow)(void *), 967 void *arg, 968 u8 timer_index); 969 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 970 struct ath_gen_timer *timer, 971 u32 timer_next, 972 u32 timer_period); 973 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 974 975 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 976 void ath_gen_timer_isr(struct ath_hw *hw); 977 978 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 979 980 /* PHY */ 981 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 982 u32 *coef_mantissa, u32 *coef_exponent); 983 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 984 bool test); 985 986 /* 987 * Code Specific to AR5008, AR9001 or AR9002, 988 * we stuff these here to avoid callbacks for AR9003. 989 */ 990 int ar9002_hw_rf_claim(struct ath_hw *ah); 991 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 992 993 /* 994 * Code specific to AR9003, we stuff these here to avoid callbacks 995 * for older families 996 */ 997 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 998 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 999 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1000 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1001 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1002 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1003 struct ath9k_hw_cal_data *caldata, 1004 int chain); 1005 int ar9003_paprd_create_curve(struct ath_hw *ah, 1006 struct ath9k_hw_cal_data *caldata, int chain); 1007 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1008 int ar9003_paprd_init_table(struct ath_hw *ah); 1009 bool ar9003_paprd_is_done(struct ath_hw *ah); 1010 1011 /* Hardware family op attach helpers */ 1012 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1013 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1014 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1015 1016 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1017 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1018 1019 void ar9002_hw_attach_ops(struct ath_hw *ah); 1020 void ar9003_hw_attach_ops(struct ath_hw *ah); 1021 1022 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1023 /* 1024 * ANI work can be shared between all families but a next 1025 * generation implementation of ANI will be used only for AR9003 only 1026 * for now as the other families still need to be tested with the same 1027 * next generation ANI. Feel free to start testing it though for the 1028 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. 1029 */ 1030 extern int modparam_force_new_ani; 1031 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1032 void ath9k_hw_proc_mib_event(struct ath_hw *ah); 1033 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1034 1035 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1036 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1037 { 1038 return ah->btcoex_hw.enabled; 1039 } 1040 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1041 static inline enum ath_btcoex_scheme 1042 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1043 { 1044 return ah->btcoex_hw.scheme; 1045 } 1046 #else 1047 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1048 { 1049 return false; 1050 } 1051 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1052 { 1053 } 1054 static inline enum ath_btcoex_scheme 1055 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1056 { 1057 return ATH_BTCOEX_CFG_NONE; 1058 } 1059 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1060 1061 #define ATH9K_CLOCK_RATE_CCK 22 1062 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1063 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1064 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1065 1066 #endif 1067