1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 34 #define ATHEROS_VENDOR_ID 0x168c 35 36 #define AR5416_DEVID_PCI 0x0023 37 #define AR5416_DEVID_PCIE 0x0024 38 #define AR9160_DEVID_PCI 0x0027 39 #define AR9280_DEVID_PCI 0x0029 40 #define AR9280_DEVID_PCIE 0x002a 41 #define AR9285_DEVID_PCIE 0x002b 42 #define AR2427_DEVID_PCIE 0x002c 43 #define AR9287_DEVID_PCI 0x002d 44 #define AR9287_DEVID_PCIE 0x002e 45 #define AR9300_DEVID_PCIE 0x0030 46 #define AR9300_DEVID_AR9340 0x0031 47 #define AR9300_DEVID_AR9485_PCIE 0x0032 48 #define AR9300_DEVID_AR9330 0x0035 49 50 #define AR5416_AR9100_DEVID 0x000b 51 52 #define AR_SUBVENDOR_ID_NOG 0x0e11 53 #define AR_SUBVENDOR_ID_NEW_A 0x7065 54 #define AR5416_MAGIC 0x19641014 55 56 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 57 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 58 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 59 60 #define AR9300_NUM_BT_WEIGHTS 4 61 #define AR9300_NUM_WLAN_WEIGHTS 4 62 63 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 64 65 #define ATH_DEFAULT_NOISE_FLOOR -95 66 67 #define ATH9K_RSSI_BAD -128 68 69 #define ATH9K_NUM_CHANNELS 38 70 71 /* Register read/write primitives */ 72 #define REG_WRITE(_ah, _reg, _val) \ 73 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 74 75 #define REG_READ(_ah, _reg) \ 76 (_ah)->reg_ops.read((_ah), (_reg)) 77 78 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 79 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 80 81 #define REG_RMW(_ah, _reg, _set, _clr) \ 82 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 83 84 #define ENABLE_REGWRITE_BUFFER(_ah) \ 85 do { \ 86 if ((_ah)->reg_ops.enable_write_buffer) \ 87 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 88 } while (0) 89 90 #define REGWRITE_BUFFER_FLUSH(_ah) \ 91 do { \ 92 if ((_ah)->reg_ops.write_flush) \ 93 (_ah)->reg_ops.write_flush((_ah)); \ 94 } while (0) 95 96 #define SM(_v, _f) (((_v) << _f##_S) & _f) 97 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 98 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 99 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 100 #define REG_READ_FIELD(_a, _r, _f) \ 101 (((REG_READ(_a, _r) & _f) >> _f##_S)) 102 #define REG_SET_BIT(_a, _r, _f) \ 103 REG_RMW(_a, _r, (_f), 0) 104 #define REG_CLR_BIT(_a, _r, _f) \ 105 REG_RMW(_a, _r, 0, (_f)) 106 107 #define DO_DELAY(x) do { \ 108 if (((++(x) % 64) == 0) && \ 109 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 110 != ATH_USB)) \ 111 udelay(1); \ 112 } while (0) 113 114 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 115 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 116 117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 124 125 #define AR_GPIOD_MASK 0x00001FFF 126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 127 128 #define BASE_ACTIVATE_DELAY 100 129 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 130 #define COEF_SCALE_S 24 131 #define HT40_CHANNEL_CENTER_SHIFT 10 132 133 #define ATH9K_ANTENNA0_CHAINMASK 0x1 134 #define ATH9K_ANTENNA1_CHAINMASK 0x2 135 136 #define ATH9K_NUM_DMA_DEBUG_REGS 8 137 #define ATH9K_NUM_QUEUES 10 138 139 #define MAX_RATE_POWER 63 140 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 142 #define AH_TIME_QUANTUM 10 143 #define AR_KEYTABLE_SIZE 128 144 #define POWER_UP_TIME 10000 145 #define SPUR_RSSI_THRESH 40 146 #define UPPER_5G_SUB_BAND_START 5700 147 #define MID_5G_SUB_BAND_START 5400 148 149 #define CAB_TIMEOUT_VAL 10 150 #define BEACON_TIMEOUT_VAL 10 151 #define MIN_BEACON_TIMEOUT_VAL 1 152 #define SLEEP_SLOP 3 153 154 #define INIT_CONFIG_STATUS 0x00000000 155 #define INIT_RSSI_THR 0x00000700 156 #define INIT_BCON_CNTRL_REG 0x00000000 157 158 #define TU_TO_USEC(_tu) ((_tu) << 10) 159 160 #define ATH9K_HW_RX_HP_QDEPTH 16 161 #define ATH9K_HW_RX_LP_QDEPTH 128 162 163 #define PAPRD_GAIN_TABLE_ENTRIES 32 164 #define PAPRD_TABLE_SZ 24 165 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 166 167 enum ath_hw_txq_subtype { 168 ATH_TXQ_AC_BE = 0, 169 ATH_TXQ_AC_BK = 1, 170 ATH_TXQ_AC_VI = 2, 171 ATH_TXQ_AC_VO = 3, 172 }; 173 174 enum ath_ini_subsys { 175 ATH_INI_PRE = 0, 176 ATH_INI_CORE, 177 ATH_INI_POST, 178 ATH_INI_NUM_SPLIT, 179 }; 180 181 enum ath9k_hw_caps { 182 ATH9K_HW_CAP_HT = BIT(0), 183 ATH9K_HW_CAP_RFSILENT = BIT(1), 184 ATH9K_HW_CAP_CST = BIT(2), 185 ATH9K_HW_CAP_AUTOSLEEP = BIT(4), 186 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), 187 ATH9K_HW_CAP_EDMA = BIT(6), 188 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), 189 ATH9K_HW_CAP_LDPC = BIT(8), 190 ATH9K_HW_CAP_FASTCLOCK = BIT(9), 191 ATH9K_HW_CAP_SGI_20 = BIT(10), 192 ATH9K_HW_CAP_PAPRD = BIT(11), 193 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12), 194 ATH9K_HW_CAP_2GHZ = BIT(13), 195 ATH9K_HW_CAP_5GHZ = BIT(14), 196 ATH9K_HW_CAP_APM = BIT(15), 197 }; 198 199 struct ath9k_hw_capabilities { 200 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 201 u16 rts_aggr_limit; 202 u8 tx_chainmask; 203 u8 rx_chainmask; 204 u8 max_txchains; 205 u8 max_rxchains; 206 u8 num_gpio_pins; 207 u8 rx_hp_qdepth; 208 u8 rx_lp_qdepth; 209 u8 rx_status_len; 210 u8 tx_desc_len; 211 u8 txs_len; 212 u16 pcie_lcr_offset; 213 bool pcie_lcr_extsync_en; 214 }; 215 216 struct ath9k_ops_config { 217 int dma_beacon_response_time; 218 int sw_beacon_response_time; 219 int additional_swba_backoff; 220 int ack_6mb; 221 u32 cwm_ignore_extcca; 222 u8 pcie_powersave_enable; 223 bool pcieSerDesWrite; 224 u8 pcie_clock_req; 225 u32 pcie_waen; 226 u8 analog_shiftreg; 227 u8 paprd_disable; 228 u32 ofdm_trig_low; 229 u32 ofdm_trig_high; 230 u32 cck_trig_high; 231 u32 cck_trig_low; 232 u32 enable_ani; 233 int serialize_regmode; 234 bool rx_intr_mitigation; 235 bool tx_intr_mitigation; 236 #define SPUR_DISABLE 0 237 #define SPUR_ENABLE_IOCTL 1 238 #define SPUR_ENABLE_EEPROM 2 239 #define AR_SPUR_5413_1 1640 240 #define AR_SPUR_5413_2 1200 241 #define AR_NO_SPUR 0x8000 242 #define AR_BASE_FREQ_2GHZ 2300 243 #define AR_BASE_FREQ_5GHZ 4900 244 #define AR_SPUR_FEEQ_BOUND_HT40 19 245 #define AR_SPUR_FEEQ_BOUND_HT20 10 246 int spurmode; 247 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 248 u8 max_txtrig_level; 249 u16 ani_poll_interval; /* ANI poll interval in ms */ 250 }; 251 252 enum ath9k_int { 253 ATH9K_INT_RX = 0x00000001, 254 ATH9K_INT_RXDESC = 0x00000002, 255 ATH9K_INT_RXHP = 0x00000001, 256 ATH9K_INT_RXLP = 0x00000002, 257 ATH9K_INT_RXNOFRM = 0x00000008, 258 ATH9K_INT_RXEOL = 0x00000010, 259 ATH9K_INT_RXORN = 0x00000020, 260 ATH9K_INT_TX = 0x00000040, 261 ATH9K_INT_TXDESC = 0x00000080, 262 ATH9K_INT_TIM_TIMER = 0x00000100, 263 ATH9K_INT_BB_WATCHDOG = 0x00000400, 264 ATH9K_INT_TXURN = 0x00000800, 265 ATH9K_INT_MIB = 0x00001000, 266 ATH9K_INT_RXPHY = 0x00004000, 267 ATH9K_INT_RXKCM = 0x00008000, 268 ATH9K_INT_SWBA = 0x00010000, 269 ATH9K_INT_BMISS = 0x00040000, 270 ATH9K_INT_BNR = 0x00100000, 271 ATH9K_INT_TIM = 0x00200000, 272 ATH9K_INT_DTIM = 0x00400000, 273 ATH9K_INT_DTIMSYNC = 0x00800000, 274 ATH9K_INT_GPIO = 0x01000000, 275 ATH9K_INT_CABEND = 0x02000000, 276 ATH9K_INT_TSFOOR = 0x04000000, 277 ATH9K_INT_GENTIMER = 0x08000000, 278 ATH9K_INT_CST = 0x10000000, 279 ATH9K_INT_GTT = 0x20000000, 280 ATH9K_INT_FATAL = 0x40000000, 281 ATH9K_INT_GLOBAL = 0x80000000, 282 ATH9K_INT_BMISC = ATH9K_INT_TIM | 283 ATH9K_INT_DTIM | 284 ATH9K_INT_DTIMSYNC | 285 ATH9K_INT_TSFOOR | 286 ATH9K_INT_CABEND, 287 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 288 ATH9K_INT_RXDESC | 289 ATH9K_INT_RXEOL | 290 ATH9K_INT_RXORN | 291 ATH9K_INT_TXURN | 292 ATH9K_INT_TXDESC | 293 ATH9K_INT_MIB | 294 ATH9K_INT_RXPHY | 295 ATH9K_INT_RXKCM | 296 ATH9K_INT_SWBA | 297 ATH9K_INT_BMISS | 298 ATH9K_INT_GPIO, 299 ATH9K_INT_NOCARD = 0xffffffff 300 }; 301 302 #define CHANNEL_CW_INT 0x00002 303 #define CHANNEL_CCK 0x00020 304 #define CHANNEL_OFDM 0x00040 305 #define CHANNEL_2GHZ 0x00080 306 #define CHANNEL_5GHZ 0x00100 307 #define CHANNEL_PASSIVE 0x00200 308 #define CHANNEL_DYN 0x00400 309 #define CHANNEL_HALF 0x04000 310 #define CHANNEL_QUARTER 0x08000 311 #define CHANNEL_HT20 0x10000 312 #define CHANNEL_HT40PLUS 0x20000 313 #define CHANNEL_HT40MINUS 0x40000 314 315 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 316 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 317 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 318 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 319 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 320 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 321 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 322 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 323 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 324 #define CHANNEL_ALL \ 325 (CHANNEL_OFDM| \ 326 CHANNEL_CCK| \ 327 CHANNEL_2GHZ | \ 328 CHANNEL_5GHZ | \ 329 CHANNEL_HT20 | \ 330 CHANNEL_HT40PLUS | \ 331 CHANNEL_HT40MINUS) 332 333 struct ath9k_hw_cal_data { 334 u16 channel; 335 u32 channelFlags; 336 int32_t CalValid; 337 int8_t iCoff; 338 int8_t qCoff; 339 bool paprd_done; 340 bool nfcal_pending; 341 bool nfcal_interference; 342 u16 small_signal_gain[AR9300_MAX_CHAINS]; 343 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 344 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 345 }; 346 347 struct ath9k_channel { 348 struct ieee80211_channel *chan; 349 struct ar5416AniState ani; 350 u16 channel; 351 u32 channelFlags; 352 u32 chanmode; 353 s16 noisefloor; 354 }; 355 356 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 357 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 358 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 359 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 360 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 361 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 362 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 363 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 364 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 365 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 366 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 367 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 368 369 /* These macros check chanmode and not channelFlags */ 370 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 371 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 372 ((_c)->chanmode == CHANNEL_G_HT20)) 373 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 374 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 375 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 376 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 377 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 378 379 enum ath9k_power_mode { 380 ATH9K_PM_AWAKE = 0, 381 ATH9K_PM_FULL_SLEEP, 382 ATH9K_PM_NETWORK_SLEEP, 383 ATH9K_PM_UNDEFINED 384 }; 385 386 enum ath9k_tp_scale { 387 ATH9K_TP_SCALE_MAX = 0, 388 ATH9K_TP_SCALE_50, 389 ATH9K_TP_SCALE_25, 390 ATH9K_TP_SCALE_12, 391 ATH9K_TP_SCALE_MIN 392 }; 393 394 enum ser_reg_mode { 395 SER_REG_MODE_OFF = 0, 396 SER_REG_MODE_ON = 1, 397 SER_REG_MODE_AUTO = 2, 398 }; 399 400 enum ath9k_rx_qtype { 401 ATH9K_RX_QUEUE_HP, 402 ATH9K_RX_QUEUE_LP, 403 ATH9K_RX_QUEUE_MAX, 404 }; 405 406 struct ath9k_beacon_state { 407 u32 bs_nexttbtt; 408 u32 bs_nextdtim; 409 u32 bs_intval; 410 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 411 u32 bs_dtimperiod; 412 u16 bs_cfpperiod; 413 u16 bs_cfpmaxduration; 414 u32 bs_cfpnext; 415 u16 bs_timoffset; 416 u16 bs_bmissthreshold; 417 u32 bs_sleepduration; 418 u32 bs_tsfoor_threshold; 419 }; 420 421 struct chan_centers { 422 u16 synth_center; 423 u16 ctl_center; 424 u16 ext_center; 425 }; 426 427 enum { 428 ATH9K_RESET_POWER_ON, 429 ATH9K_RESET_WARM, 430 ATH9K_RESET_COLD, 431 }; 432 433 struct ath9k_hw_version { 434 u32 magic; 435 u16 devid; 436 u16 subvendorid; 437 u32 macVersion; 438 u16 macRev; 439 u16 phyRev; 440 u16 analog5GhzRev; 441 u16 analog2GhzRev; 442 u16 subsysid; 443 enum ath_usb_dev usbdev; 444 }; 445 446 /* Generic TSF timer definitions */ 447 448 #define ATH_MAX_GEN_TIMER 16 449 450 #define AR_GENTMR_BIT(_index) (1 << (_index)) 451 452 /* 453 * Using de Bruijin sequence to look up 1's index in a 32 bit number 454 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 455 */ 456 #define debruijn32 0x077CB531U 457 458 struct ath_gen_timer_configuration { 459 u32 next_addr; 460 u32 period_addr; 461 u32 mode_addr; 462 u32 mode_mask; 463 }; 464 465 struct ath_gen_timer { 466 void (*trigger)(void *arg); 467 void (*overflow)(void *arg); 468 void *arg; 469 u8 index; 470 }; 471 472 struct ath_gen_timer_table { 473 u32 gen_timer_index[32]; 474 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 475 union { 476 unsigned long timer_bits; 477 u16 val; 478 } timer_mask; 479 }; 480 481 struct ath_hw_antcomb_conf { 482 u8 main_lna_conf; 483 u8 alt_lna_conf; 484 u8 fast_div_bias; 485 u8 main_gaintb; 486 u8 alt_gaintb; 487 int lna1_lna2_delta; 488 u8 div_group; 489 }; 490 491 /** 492 * struct ath_hw_radar_conf - radar detection initialization parameters 493 * 494 * @pulse_inband: threshold for checking the ratio of in-band power 495 * to total power for short radar pulses (half dB steps) 496 * @pulse_inband_step: threshold for checking an in-band power to total 497 * power ratio increase for short radar pulses (half dB steps) 498 * @pulse_height: threshold for detecting the beginning of a short 499 * radar pulse (dB step) 500 * @pulse_rssi: threshold for detecting if a short radar pulse is 501 * gone (dB step) 502 * @pulse_maxlen: maximum pulse length (0.8 us steps) 503 * 504 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 505 * @radar_inband: threshold for checking the ratio of in-band power 506 * to total power for long radar pulses (half dB steps) 507 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 508 * 509 * @ext_channel: enable extension channel radar detection 510 */ 511 struct ath_hw_radar_conf { 512 unsigned int pulse_inband; 513 unsigned int pulse_inband_step; 514 unsigned int pulse_height; 515 unsigned int pulse_rssi; 516 unsigned int pulse_maxlen; 517 518 unsigned int radar_rssi; 519 unsigned int radar_inband; 520 int fir_power; 521 522 bool ext_channel; 523 }; 524 525 /** 526 * struct ath_hw_private_ops - callbacks used internally by hardware code 527 * 528 * This structure contains private callbacks designed to only be used internally 529 * by the hardware core. 530 * 531 * @init_cal_settings: setup types of calibrations supported 532 * @init_cal: starts actual calibration 533 * 534 * @init_mode_regs: Initializes mode registers 535 * @init_mode_gain_regs: Initialize TX/RX gain registers 536 * 537 * @rf_set_freq: change frequency 538 * @spur_mitigate_freq: spur mitigation 539 * @rf_alloc_ext_banks: 540 * @rf_free_ext_banks: 541 * @set_rf_regs: 542 * @compute_pll_control: compute the PLL control value to use for 543 * AR_RTC_PLL_CONTROL for a given channel 544 * @setup_calibration: set up calibration 545 * @iscal_supported: used to query if a type of calibration is supported 546 * 547 * @ani_cache_ini_regs: cache the values for ANI from the initial 548 * register settings through the register initialization. 549 */ 550 struct ath_hw_private_ops { 551 /* Calibration ops */ 552 void (*init_cal_settings)(struct ath_hw *ah); 553 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 554 555 void (*init_mode_regs)(struct ath_hw *ah); 556 void (*init_mode_gain_regs)(struct ath_hw *ah); 557 void (*setup_calibration)(struct ath_hw *ah, 558 struct ath9k_cal_list *currCal); 559 560 /* PHY ops */ 561 int (*rf_set_freq)(struct ath_hw *ah, 562 struct ath9k_channel *chan); 563 void (*spur_mitigate_freq)(struct ath_hw *ah, 564 struct ath9k_channel *chan); 565 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 566 void (*rf_free_ext_banks)(struct ath_hw *ah); 567 bool (*set_rf_regs)(struct ath_hw *ah, 568 struct ath9k_channel *chan, 569 u16 modesIndex); 570 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 571 void (*init_bb)(struct ath_hw *ah, 572 struct ath9k_channel *chan); 573 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 574 void (*olc_init)(struct ath_hw *ah); 575 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 576 void (*mark_phy_inactive)(struct ath_hw *ah); 577 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 578 bool (*rfbus_req)(struct ath_hw *ah); 579 void (*rfbus_done)(struct ath_hw *ah); 580 void (*restore_chainmask)(struct ath_hw *ah); 581 void (*set_diversity)(struct ath_hw *ah, bool value); 582 u32 (*compute_pll_control)(struct ath_hw *ah, 583 struct ath9k_channel *chan); 584 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 585 int param); 586 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 587 void (*set_radar_params)(struct ath_hw *ah, 588 struct ath_hw_radar_conf *conf); 589 590 /* ANI */ 591 void (*ani_cache_ini_regs)(struct ath_hw *ah); 592 }; 593 594 /** 595 * struct ath_hw_ops - callbacks used by hardware code and driver code 596 * 597 * This structure contains callbacks designed to to be used internally by 598 * hardware code and also by the lower level driver. 599 * 600 * @config_pci_powersave: 601 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 602 */ 603 struct ath_hw_ops { 604 void (*config_pci_powersave)(struct ath_hw *ah, 605 int restore, 606 int power_off); 607 void (*rx_enable)(struct ath_hw *ah); 608 void (*set_desc_link)(void *ds, u32 link); 609 bool (*calibrate)(struct ath_hw *ah, 610 struct ath9k_channel *chan, 611 u8 rxchainmask, 612 bool longcal); 613 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 614 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, 615 bool is_firstseg, bool is_is_lastseg, 616 const void *ds0, dma_addr_t buf_addr, 617 unsigned int qcu); 618 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 619 struct ath_tx_status *ts); 620 void (*set11n_txdesc)(struct ath_hw *ah, void *ds, 621 u32 pktLen, enum ath9k_pkt_type type, 622 u32 txPower, u32 keyIx, 623 enum ath9k_key_type keyType, 624 u32 flags); 625 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, 626 void *lastds, 627 u32 durUpdateEn, u32 rtsctsRate, 628 u32 rtsctsDuration, 629 struct ath9k_11n_rate_series series[], 630 u32 nseries, u32 flags); 631 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, 632 u32 aggrLen); 633 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, 634 u32 numDelims); 635 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); 636 void (*clr11n_aggr)(struct ath_hw *ah, void *ds); 637 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val); 638 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 639 struct ath_hw_antcomb_conf *antconf); 640 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 641 struct ath_hw_antcomb_conf *antconf); 642 643 }; 644 645 struct ath_nf_limits { 646 s16 max; 647 s16 min; 648 s16 nominal; 649 }; 650 651 /* ah_flags */ 652 #define AH_USE_EEPROM 0x1 653 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 654 655 struct ath_hw { 656 struct ath_ops reg_ops; 657 658 struct ieee80211_hw *hw; 659 struct ath_common common; 660 struct ath9k_hw_version hw_version; 661 struct ath9k_ops_config config; 662 struct ath9k_hw_capabilities caps; 663 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 664 struct ath9k_channel *curchan; 665 666 union { 667 struct ar5416_eeprom_def def; 668 struct ar5416_eeprom_4k map4k; 669 struct ar9287_eeprom map9287; 670 struct ar9300_eeprom ar9300_eep; 671 } eeprom; 672 const struct eeprom_ops *eep_ops; 673 674 bool sw_mgmt_crypto; 675 bool is_pciexpress; 676 bool is_monitoring; 677 bool need_an_top2_fixup; 678 u16 tx_trig_level; 679 680 u32 nf_regs[6]; 681 struct ath_nf_limits nf_2g; 682 struct ath_nf_limits nf_5g; 683 u16 rfsilent; 684 u32 rfkill_gpio; 685 u32 rfkill_polarity; 686 u32 ah_flags; 687 688 bool htc_reset_init; 689 690 enum nl80211_iftype opmode; 691 enum ath9k_power_mode power_mode; 692 693 struct ath9k_hw_cal_data *caldata; 694 struct ath9k_pacal_info pacal_info; 695 struct ar5416Stats stats; 696 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 697 698 int16_t curchan_rad_index; 699 enum ath9k_int imask; 700 u32 imrs2_reg; 701 u32 txok_interrupt_mask; 702 u32 txerr_interrupt_mask; 703 u32 txdesc_interrupt_mask; 704 u32 txeol_interrupt_mask; 705 u32 txurn_interrupt_mask; 706 bool chip_fullsleep; 707 u32 atim_window; 708 709 /* Calibration */ 710 u32 supp_cals; 711 struct ath9k_cal_list iq_caldata; 712 struct ath9k_cal_list adcgain_caldata; 713 struct ath9k_cal_list adcdc_caldata; 714 struct ath9k_cal_list tempCompCalData; 715 struct ath9k_cal_list *cal_list; 716 struct ath9k_cal_list *cal_list_last; 717 struct ath9k_cal_list *cal_list_curr; 718 #define totalPowerMeasI meas0.unsign 719 #define totalPowerMeasQ meas1.unsign 720 #define totalIqCorrMeas meas2.sign 721 #define totalAdcIOddPhase meas0.unsign 722 #define totalAdcIEvenPhase meas1.unsign 723 #define totalAdcQOddPhase meas2.unsign 724 #define totalAdcQEvenPhase meas3.unsign 725 #define totalAdcDcOffsetIOddPhase meas0.sign 726 #define totalAdcDcOffsetIEvenPhase meas1.sign 727 #define totalAdcDcOffsetQOddPhase meas2.sign 728 #define totalAdcDcOffsetQEvenPhase meas3.sign 729 union { 730 u32 unsign[AR5416_MAX_CHAINS]; 731 int32_t sign[AR5416_MAX_CHAINS]; 732 } meas0; 733 union { 734 u32 unsign[AR5416_MAX_CHAINS]; 735 int32_t sign[AR5416_MAX_CHAINS]; 736 } meas1; 737 union { 738 u32 unsign[AR5416_MAX_CHAINS]; 739 int32_t sign[AR5416_MAX_CHAINS]; 740 } meas2; 741 union { 742 u32 unsign[AR5416_MAX_CHAINS]; 743 int32_t sign[AR5416_MAX_CHAINS]; 744 } meas3; 745 u16 cal_samples; 746 747 u32 sta_id1_defaults; 748 u32 misc_mode; 749 enum { 750 AUTO_32KHZ, 751 USE_32KHZ, 752 DONT_USE_32KHZ, 753 } enable_32kHz_clock; 754 755 /* Private to hardware code */ 756 struct ath_hw_private_ops private_ops; 757 /* Accessed by the lower level driver */ 758 struct ath_hw_ops ops; 759 760 /* Used to program the radio on non single-chip devices */ 761 u32 *analogBank0Data; 762 u32 *analogBank1Data; 763 u32 *analogBank2Data; 764 u32 *analogBank3Data; 765 u32 *analogBank6Data; 766 u32 *analogBank6TPCData; 767 u32 *analogBank7Data; 768 u32 *addac5416_21; 769 u32 *bank6Temp; 770 771 u8 txpower_limit; 772 int coverage_class; 773 u32 slottime; 774 u32 globaltxtimeout; 775 776 /* ANI */ 777 u32 proc_phyerr; 778 u32 aniperiod; 779 int totalSizeDesired[5]; 780 int coarse_high[5]; 781 int coarse_low[5]; 782 int firpwr[5]; 783 enum ath9k_ani_cmd ani_function; 784 785 /* Bluetooth coexistance */ 786 struct ath_btcoex_hw btcoex_hw; 787 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; 788 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; 789 790 u32 intr_txqs; 791 u8 txchainmask; 792 u8 rxchainmask; 793 794 struct ath_hw_radar_conf radar_conf; 795 796 u32 originalGain[22]; 797 int initPDADC; 798 int PDADCdelta; 799 int led_pin; 800 u32 gpio_mask; 801 u32 gpio_val; 802 803 struct ar5416IniArray iniModes; 804 struct ar5416IniArray iniCommon; 805 struct ar5416IniArray iniBank0; 806 struct ar5416IniArray iniBB_RfGain; 807 struct ar5416IniArray iniBank1; 808 struct ar5416IniArray iniBank2; 809 struct ar5416IniArray iniBank3; 810 struct ar5416IniArray iniBank6; 811 struct ar5416IniArray iniBank6TPC; 812 struct ar5416IniArray iniBank7; 813 struct ar5416IniArray iniAddac; 814 struct ar5416IniArray iniPcieSerdes; 815 struct ar5416IniArray iniPcieSerdesLowPower; 816 struct ar5416IniArray iniModesAdditional; 817 struct ar5416IniArray iniModesAdditional_40M; 818 struct ar5416IniArray iniModesRxGain; 819 struct ar5416IniArray iniModesTxGain; 820 struct ar5416IniArray iniModes_9271_1_0_only; 821 struct ar5416IniArray iniCckfirNormal; 822 struct ar5416IniArray iniCckfirJapan2484; 823 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; 824 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; 825 struct ar5416IniArray iniModes_9271_ANI_reg; 826 struct ar5416IniArray iniModes_high_power_tx_gain_9271; 827 struct ar5416IniArray iniModes_normal_power_tx_gain_9271; 828 829 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 830 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 831 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 832 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 833 834 u32 intr_gen_timer_trigger; 835 u32 intr_gen_timer_thresh; 836 struct ath_gen_timer_table hw_gen_timers; 837 838 struct ar9003_txs *ts_ring; 839 void *ts_start; 840 u32 ts_paddr_start; 841 u32 ts_paddr_end; 842 u16 ts_tail; 843 u8 ts_size; 844 845 u32 bb_watchdog_last_status; 846 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 847 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 848 849 unsigned int paprd_target_power; 850 unsigned int paprd_training_power; 851 unsigned int paprd_ratemask; 852 unsigned int paprd_ratemask_ht40; 853 bool paprd_table_write_done; 854 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 855 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 856 /* 857 * Store the permanent value of Reg 0x4004in WARegVal 858 * so we dont have to R/M/W. We should not be reading 859 * this register when in sleep states. 860 */ 861 u32 WARegVal; 862 863 /* Enterprise mode cap */ 864 u32 ent_mode; 865 866 bool is_clk_25mhz; 867 int (*get_mac_revision)(void); 868 int (*external_reset)(void); 869 }; 870 871 struct ath_bus_ops { 872 enum ath_bus_type ath_bus_type; 873 void (*read_cachesize)(struct ath_common *common, int *csz); 874 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 875 void (*bt_coex_prep)(struct ath_common *common); 876 void (*extn_synch_en)(struct ath_common *common); 877 }; 878 879 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 880 { 881 return &ah->common; 882 } 883 884 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 885 { 886 return &(ath9k_hw_common(ah)->regulatory); 887 } 888 889 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 890 { 891 return &ah->private_ops; 892 } 893 894 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 895 { 896 return &ah->ops; 897 } 898 899 static inline u8 get_streams(int mask) 900 { 901 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 902 } 903 904 /* Initialization, Detach, Reset */ 905 const char *ath9k_hw_probe(u16 vendorid, u16 devid); 906 void ath9k_hw_deinit(struct ath_hw *ah); 907 int ath9k_hw_init(struct ath_hw *ah); 908 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 909 struct ath9k_hw_cal_data *caldata, bool bChannelChange); 910 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 911 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 912 913 /* GPIO / RFKILL / Antennae */ 914 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 915 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 916 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 917 u32 ah_signal_type); 918 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 919 u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 920 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 921 922 /* General Operation */ 923 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 924 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 925 int column, unsigned int *writecnt); 926 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 927 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 928 u8 phy, int kbps, 929 u32 frameLen, u16 rateix, bool shortPreamble); 930 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 931 struct ath9k_channel *chan, 932 struct chan_centers *centers); 933 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 934 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 935 bool ath9k_hw_phy_disable(struct ath_hw *ah); 936 bool ath9k_hw_disable(struct ath_hw *ah); 937 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 938 void ath9k_hw_setopmode(struct ath_hw *ah); 939 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 940 void ath9k_hw_setbssidmask(struct ath_hw *ah); 941 void ath9k_hw_write_associd(struct ath_hw *ah); 942 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 943 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 944 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 945 void ath9k_hw_reset_tsf(struct ath_hw *ah); 946 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 947 void ath9k_hw_init_global_settings(struct ath_hw *ah); 948 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 949 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 950 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 951 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 952 const struct ath9k_beacon_state *bs); 953 bool ath9k_hw_check_alive(struct ath_hw *ah); 954 955 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 956 957 /* Generic hw timer primitives */ 958 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 959 void (*trigger)(void *), 960 void (*overflow)(void *), 961 void *arg, 962 u8 timer_index); 963 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 964 struct ath_gen_timer *timer, 965 u32 timer_next, 966 u32 timer_period); 967 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 968 969 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 970 void ath_gen_timer_isr(struct ath_hw *hw); 971 972 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 973 974 /* HTC */ 975 void ath9k_hw_htc_resetinit(struct ath_hw *ah); 976 977 /* PHY */ 978 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 979 u32 *coef_mantissa, u32 *coef_exponent); 980 981 /* 982 * Code Specific to AR5008, AR9001 or AR9002, 983 * we stuff these here to avoid callbacks for AR9003. 984 */ 985 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); 986 int ar9002_hw_rf_claim(struct ath_hw *ah); 987 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 988 989 /* 990 * Code specific to AR9003, we stuff these here to avoid callbacks 991 * for older families 992 */ 993 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 994 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 995 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 996 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 997 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 998 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 999 struct ath9k_hw_cal_data *caldata, 1000 int chain); 1001 int ar9003_paprd_create_curve(struct ath_hw *ah, 1002 struct ath9k_hw_cal_data *caldata, int chain); 1003 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1004 int ar9003_paprd_init_table(struct ath_hw *ah); 1005 bool ar9003_paprd_is_done(struct ath_hw *ah); 1006 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); 1007 1008 /* Hardware family op attach helpers */ 1009 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1010 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1011 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1012 1013 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1014 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1015 1016 void ar9002_hw_attach_ops(struct ath_hw *ah); 1017 void ar9003_hw_attach_ops(struct ath_hw *ah); 1018 1019 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1020 /* 1021 * ANI work can be shared between all families but a next 1022 * generation implementation of ANI will be used only for AR9003 only 1023 * for now as the other families still need to be tested with the same 1024 * next generation ANI. Feel free to start testing it though for the 1025 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. 1026 */ 1027 extern int modparam_force_new_ani; 1028 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1029 void ath9k_hw_proc_mib_event(struct ath_hw *ah); 1030 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1031 1032 #define ATH_PCIE_CAP_LINK_CTRL 0x70 1033 #define ATH_PCIE_CAP_LINK_L0S 1 1034 #define ATH_PCIE_CAP_LINK_L1 2 1035 1036 #define ATH9K_CLOCK_RATE_CCK 22 1037 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1038 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1039 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1040 1041 #endif 1042