1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "phy.h" 31 #include "btcoex.h" 32 33 #include "../regd.h" 34 35 #define ATHEROS_VENDOR_ID 0x168c 36 37 #define AR5416_DEVID_PCI 0x0023 38 #define AR5416_DEVID_PCIE 0x0024 39 #define AR9160_DEVID_PCI 0x0027 40 #define AR9280_DEVID_PCI 0x0029 41 #define AR9280_DEVID_PCIE 0x002a 42 #define AR9285_DEVID_PCIE 0x002b 43 #define AR2427_DEVID_PCIE 0x002c 44 #define AR9287_DEVID_PCI 0x002d 45 #define AR9287_DEVID_PCIE 0x002e 46 #define AR9300_DEVID_PCIE 0x0030 47 #define AR9300_DEVID_AR9340 0x0031 48 #define AR9300_DEVID_AR9485_PCIE 0x0032 49 #define AR9300_DEVID_AR9580 0x0033 50 #define AR9300_DEVID_AR9462 0x0034 51 #define AR9300_DEVID_AR9330 0x0035 52 #define AR9300_DEVID_QCA955X 0x0038 53 #define AR9485_DEVID_AR1111 0x0037 54 #define AR9300_DEVID_AR9565 0x0036 55 #define AR9300_DEVID_AR953X 0x003d 56 57 #define AR5416_AR9100_DEVID 0x000b 58 59 #define AR_SUBVENDOR_ID_NOG 0x0e11 60 #define AR_SUBVENDOR_ID_NEW_A 0x7065 61 #define AR5416_MAGIC 0x19641014 62 63 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 64 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 65 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 66 67 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 68 69 #define ATH_DEFAULT_NOISE_FLOOR -95 70 71 #define ATH9K_RSSI_BAD -128 72 73 #define ATH9K_NUM_CHANNELS 38 74 75 /* Register read/write primitives */ 76 #define REG_WRITE(_ah, _reg, _val) \ 77 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 78 79 #define REG_READ(_ah, _reg) \ 80 (_ah)->reg_ops.read((_ah), (_reg)) 81 82 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 83 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 84 85 #define REG_RMW(_ah, _reg, _set, _clr) \ 86 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 87 88 #define ENABLE_REGWRITE_BUFFER(_ah) \ 89 do { \ 90 if ((_ah)->reg_ops.enable_write_buffer) \ 91 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 92 } while (0) 93 94 #define REGWRITE_BUFFER_FLUSH(_ah) \ 95 do { \ 96 if ((_ah)->reg_ops.write_flush) \ 97 (_ah)->reg_ops.write_flush((_ah)); \ 98 } while (0) 99 100 #define PR_EEP(_s, _val) \ 101 do { \ 102 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ 103 _s, (_val)); \ 104 } while (0) 105 106 #define SM(_v, _f) (((_v) << _f##_S) & _f) 107 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 108 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 109 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 110 #define REG_READ_FIELD(_a, _r, _f) \ 111 (((REG_READ(_a, _r) & _f) >> _f##_S)) 112 #define REG_SET_BIT(_a, _r, _f) \ 113 REG_RMW(_a, _r, (_f), 0) 114 #define REG_CLR_BIT(_a, _r, _f) \ 115 REG_RMW(_a, _r, 0, (_f)) 116 117 #define DO_DELAY(x) do { \ 118 if (((++(x) % 64) == 0) && \ 119 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 120 != ATH_USB)) \ 121 udelay(1); \ 122 } while (0) 123 124 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 125 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 126 127 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 129 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 130 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 131 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 133 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 139 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 141 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 143 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 144 145 #define AR_GPIOD_MASK 0x00001FFF 146 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 147 148 #define BASE_ACTIVATE_DELAY 100 149 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 150 #define COEF_SCALE_S 24 151 #define HT40_CHANNEL_CENTER_SHIFT 10 152 153 #define ATH9K_ANTENNA0_CHAINMASK 0x1 154 #define ATH9K_ANTENNA1_CHAINMASK 0x2 155 156 #define ATH9K_NUM_DMA_DEBUG_REGS 8 157 #define ATH9K_NUM_QUEUES 10 158 159 #define MAX_RATE_POWER 63 160 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 161 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 162 #define AH_TIME_QUANTUM 10 163 #define AR_KEYTABLE_SIZE 128 164 #define POWER_UP_TIME 10000 165 #define SPUR_RSSI_THRESH 40 166 #define UPPER_5G_SUB_BAND_START 5700 167 #define MID_5G_SUB_BAND_START 5400 168 169 #define CAB_TIMEOUT_VAL 10 170 #define BEACON_TIMEOUT_VAL 10 171 #define MIN_BEACON_TIMEOUT_VAL 1 172 #define SLEEP_SLOP TU_TO_USEC(3) 173 174 #define INIT_CONFIG_STATUS 0x00000000 175 #define INIT_RSSI_THR 0x00000700 176 #define INIT_BCON_CNTRL_REG 0x00000000 177 178 #define TU_TO_USEC(_tu) ((_tu) << 10) 179 180 #define ATH9K_HW_RX_HP_QDEPTH 16 181 #define ATH9K_HW_RX_LP_QDEPTH 128 182 183 #define PAPRD_GAIN_TABLE_ENTRIES 32 184 #define PAPRD_TABLE_SZ 24 185 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 186 187 /* 188 * Wake on Wireless 189 */ 190 191 /* Keep Alive Frame */ 192 #define KAL_FRAME_LEN 28 193 #define KAL_FRAME_TYPE 0x2 /* data frame */ 194 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 195 #define KAL_DURATION_ID 0x3d 196 #define KAL_NUM_DATA_WORDS 6 197 #define KAL_NUM_DESC_WORDS 12 198 #define KAL_ANTENNA_MODE 1 199 #define KAL_TO_DS 1 200 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ 201 #define KAL_TIMEOUT 900 202 203 #define MAX_PATTERN_SIZE 256 204 #define MAX_PATTERN_MASK_SIZE 32 205 #define MAX_NUM_PATTERN 8 206 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 207 deauthenticate packets */ 208 209 /* 210 * WoW trigger mapping to hardware code 211 */ 212 213 #define AH_WOW_USER_PATTERN_EN BIT(0) 214 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 215 #define AH_WOW_LINK_CHANGE BIT(2) 216 #define AH_WOW_BEACON_MISS BIT(3) 217 218 enum ath_hw_txq_subtype { 219 ATH_TXQ_AC_BE = 0, 220 ATH_TXQ_AC_BK = 1, 221 ATH_TXQ_AC_VI = 2, 222 ATH_TXQ_AC_VO = 3, 223 }; 224 225 enum ath_ini_subsys { 226 ATH_INI_PRE = 0, 227 ATH_INI_CORE, 228 ATH_INI_POST, 229 ATH_INI_NUM_SPLIT, 230 }; 231 232 enum ath9k_hw_caps { 233 ATH9K_HW_CAP_HT = BIT(0), 234 ATH9K_HW_CAP_RFSILENT = BIT(1), 235 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 236 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 237 ATH9K_HW_CAP_EDMA = BIT(4), 238 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 239 ATH9K_HW_CAP_LDPC = BIT(6), 240 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 241 ATH9K_HW_CAP_SGI_20 = BIT(8), 242 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 243 ATH9K_HW_CAP_2GHZ = BIT(11), 244 ATH9K_HW_CAP_5GHZ = BIT(12), 245 ATH9K_HW_CAP_APM = BIT(13), 246 ATH9K_HW_CAP_RTT = BIT(14), 247 ATH9K_HW_CAP_MCI = BIT(15), 248 ATH9K_HW_CAP_DFS = BIT(16), 249 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17), 250 ATH9K_HW_CAP_PAPRD = BIT(18), 251 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19), 252 ATH9K_HW_CAP_BT_ANT_DIV = BIT(20), 253 }; 254 255 /* 256 * WoW device capabilities 257 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 258 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 259 * an exact user defined pattern or de-authentication/disassoc pattern. 260 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 261 * bytes of the pattern for user defined pattern, de-authentication and 262 * disassociation patterns for all types of possible frames recieved 263 * of those types. 264 */ 265 266 struct ath9k_hw_capabilities { 267 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 268 u16 rts_aggr_limit; 269 u8 tx_chainmask; 270 u8 rx_chainmask; 271 u8 max_txchains; 272 u8 max_rxchains; 273 u8 num_gpio_pins; 274 u8 rx_hp_qdepth; 275 u8 rx_lp_qdepth; 276 u8 rx_status_len; 277 u8 tx_desc_len; 278 u8 txs_len; 279 }; 280 281 #define AR_NO_SPUR 0x8000 282 #define AR_BASE_FREQ_2GHZ 2300 283 #define AR_BASE_FREQ_5GHZ 4900 284 #define AR_SPUR_FEEQ_BOUND_HT40 19 285 #define AR_SPUR_FEEQ_BOUND_HT20 10 286 287 enum ath9k_hw_hang_checks { 288 HW_BB_WATCHDOG = BIT(0), 289 HW_PHYRESTART_CLC_WAR = BIT(1), 290 HW_BB_RIFS_HANG = BIT(2), 291 HW_BB_DFS_HANG = BIT(3), 292 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), 293 HW_MAC_HANG = BIT(5), 294 }; 295 296 struct ath9k_ops_config { 297 int dma_beacon_response_time; 298 int sw_beacon_response_time; 299 u32 cwm_ignore_extcca; 300 u32 pcie_waen; 301 u8 analog_shiftreg; 302 u32 ofdm_trig_low; 303 u32 ofdm_trig_high; 304 u32 cck_trig_high; 305 u32 cck_trig_low; 306 u32 enable_paprd; 307 int serialize_regmode; 308 bool rx_intr_mitigation; 309 bool tx_intr_mitigation; 310 u8 max_txtrig_level; 311 u16 ani_poll_interval; /* ANI poll interval in ms */ 312 u16 hw_hang_checks; 313 u16 rimt_first; 314 u16 rimt_last; 315 316 /* Platform specific config */ 317 u32 aspm_l1_fix; 318 u32 xlna_gpio; 319 u32 ant_ctrl_comm2g_switch_enable; 320 bool xatten_margin_cfg; 321 bool alt_mingainidx; 322 bool no_pll_pwrsave; 323 bool tx_gain_buffalo; 324 }; 325 326 enum ath9k_int { 327 ATH9K_INT_RX = 0x00000001, 328 ATH9K_INT_RXDESC = 0x00000002, 329 ATH9K_INT_RXHP = 0x00000001, 330 ATH9K_INT_RXLP = 0x00000002, 331 ATH9K_INT_RXNOFRM = 0x00000008, 332 ATH9K_INT_RXEOL = 0x00000010, 333 ATH9K_INT_RXORN = 0x00000020, 334 ATH9K_INT_TX = 0x00000040, 335 ATH9K_INT_TXDESC = 0x00000080, 336 ATH9K_INT_TIM_TIMER = 0x00000100, 337 ATH9K_INT_MCI = 0x00000200, 338 ATH9K_INT_BB_WATCHDOG = 0x00000400, 339 ATH9K_INT_TXURN = 0x00000800, 340 ATH9K_INT_MIB = 0x00001000, 341 ATH9K_INT_RXPHY = 0x00004000, 342 ATH9K_INT_RXKCM = 0x00008000, 343 ATH9K_INT_SWBA = 0x00010000, 344 ATH9K_INT_BMISS = 0x00040000, 345 ATH9K_INT_BNR = 0x00100000, 346 ATH9K_INT_TIM = 0x00200000, 347 ATH9K_INT_DTIM = 0x00400000, 348 ATH9K_INT_DTIMSYNC = 0x00800000, 349 ATH9K_INT_GPIO = 0x01000000, 350 ATH9K_INT_CABEND = 0x02000000, 351 ATH9K_INT_TSFOOR = 0x04000000, 352 ATH9K_INT_GENTIMER = 0x08000000, 353 ATH9K_INT_CST = 0x10000000, 354 ATH9K_INT_GTT = 0x20000000, 355 ATH9K_INT_FATAL = 0x40000000, 356 ATH9K_INT_GLOBAL = 0x80000000, 357 ATH9K_INT_BMISC = ATH9K_INT_TIM | 358 ATH9K_INT_DTIM | 359 ATH9K_INT_DTIMSYNC | 360 ATH9K_INT_TSFOOR | 361 ATH9K_INT_CABEND, 362 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 363 ATH9K_INT_RXDESC | 364 ATH9K_INT_RXEOL | 365 ATH9K_INT_RXORN | 366 ATH9K_INT_TXURN | 367 ATH9K_INT_TXDESC | 368 ATH9K_INT_MIB | 369 ATH9K_INT_RXPHY | 370 ATH9K_INT_RXKCM | 371 ATH9K_INT_SWBA | 372 ATH9K_INT_BMISS | 373 ATH9K_INT_GPIO, 374 ATH9K_INT_NOCARD = 0xffffffff 375 }; 376 377 #define MAX_RTT_TABLE_ENTRY 6 378 #define MAX_IQCAL_MEASUREMENT 8 379 #define MAX_CL_TAB_ENTRY 16 380 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) 381 382 enum ath9k_cal_flags { 383 RTT_DONE, 384 PAPRD_PACKET_SENT, 385 PAPRD_DONE, 386 NFCAL_PENDING, 387 NFCAL_INTF, 388 TXIQCAL_DONE, 389 TXCLCAL_DONE, 390 SW_PKDET_DONE, 391 }; 392 393 struct ath9k_hw_cal_data { 394 u16 channel; 395 u16 channelFlags; 396 unsigned long cal_flags; 397 int32_t CalValid; 398 int8_t iCoff; 399 int8_t qCoff; 400 u8 caldac[2]; 401 u16 small_signal_gain[AR9300_MAX_CHAINS]; 402 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 403 u32 num_measures[AR9300_MAX_CHAINS]; 404 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 405 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 406 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 407 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 408 }; 409 410 struct ath9k_channel { 411 struct ieee80211_channel *chan; 412 u16 channel; 413 u16 channelFlags; 414 s16 noisefloor; 415 }; 416 417 #define CHANNEL_5GHZ BIT(0) 418 #define CHANNEL_HALF BIT(1) 419 #define CHANNEL_QUARTER BIT(2) 420 #define CHANNEL_HT BIT(3) 421 #define CHANNEL_HT40PLUS BIT(4) 422 #define CHANNEL_HT40MINUS BIT(5) 423 424 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) 425 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 426 427 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) 428 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) 429 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 430 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 431 432 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) 433 434 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) 435 436 #define IS_CHAN_HT40(_c) \ 437 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) 438 439 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) 440 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) 441 442 enum ath9k_power_mode { 443 ATH9K_PM_AWAKE = 0, 444 ATH9K_PM_FULL_SLEEP, 445 ATH9K_PM_NETWORK_SLEEP, 446 ATH9K_PM_UNDEFINED 447 }; 448 449 enum ser_reg_mode { 450 SER_REG_MODE_OFF = 0, 451 SER_REG_MODE_ON = 1, 452 SER_REG_MODE_AUTO = 2, 453 }; 454 455 enum ath9k_rx_qtype { 456 ATH9K_RX_QUEUE_HP, 457 ATH9K_RX_QUEUE_LP, 458 ATH9K_RX_QUEUE_MAX, 459 }; 460 461 struct ath9k_beacon_state { 462 u32 bs_nexttbtt; 463 u32 bs_nextdtim; 464 u32 bs_intval; 465 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 466 u32 bs_dtimperiod; 467 u16 bs_bmissthreshold; 468 u32 bs_sleepduration; 469 u32 bs_tsfoor_threshold; 470 }; 471 472 struct chan_centers { 473 u16 synth_center; 474 u16 ctl_center; 475 u16 ext_center; 476 }; 477 478 enum { 479 ATH9K_RESET_POWER_ON, 480 ATH9K_RESET_WARM, 481 ATH9K_RESET_COLD, 482 }; 483 484 struct ath9k_hw_version { 485 u32 magic; 486 u16 devid; 487 u16 subvendorid; 488 u32 macVersion; 489 u16 macRev; 490 u16 phyRev; 491 u16 analog5GhzRev; 492 u16 analog2GhzRev; 493 enum ath_usb_dev usbdev; 494 }; 495 496 /* Generic TSF timer definitions */ 497 498 #define ATH_MAX_GEN_TIMER 16 499 500 #define AR_GENTMR_BIT(_index) (1 << (_index)) 501 502 struct ath_gen_timer_configuration { 503 u32 next_addr; 504 u32 period_addr; 505 u32 mode_addr; 506 u32 mode_mask; 507 }; 508 509 struct ath_gen_timer { 510 void (*trigger)(void *arg); 511 void (*overflow)(void *arg); 512 void *arg; 513 u8 index; 514 }; 515 516 struct ath_gen_timer_table { 517 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 518 u16 timer_mask; 519 }; 520 521 struct ath_hw_antcomb_conf { 522 u8 main_lna_conf; 523 u8 alt_lna_conf; 524 u8 fast_div_bias; 525 u8 main_gaintb; 526 u8 alt_gaintb; 527 int lna1_lna2_delta; 528 int lna1_lna2_switch_delta; 529 u8 div_group; 530 }; 531 532 /** 533 * struct ath_hw_radar_conf - radar detection initialization parameters 534 * 535 * @pulse_inband: threshold for checking the ratio of in-band power 536 * to total power for short radar pulses (half dB steps) 537 * @pulse_inband_step: threshold for checking an in-band power to total 538 * power ratio increase for short radar pulses (half dB steps) 539 * @pulse_height: threshold for detecting the beginning of a short 540 * radar pulse (dB step) 541 * @pulse_rssi: threshold for detecting if a short radar pulse is 542 * gone (dB step) 543 * @pulse_maxlen: maximum pulse length (0.8 us steps) 544 * 545 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 546 * @radar_inband: threshold for checking the ratio of in-band power 547 * to total power for long radar pulses (half dB steps) 548 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 549 * 550 * @ext_channel: enable extension channel radar detection 551 */ 552 struct ath_hw_radar_conf { 553 unsigned int pulse_inband; 554 unsigned int pulse_inband_step; 555 unsigned int pulse_height; 556 unsigned int pulse_rssi; 557 unsigned int pulse_maxlen; 558 559 unsigned int radar_rssi; 560 unsigned int radar_inband; 561 int fir_power; 562 563 bool ext_channel; 564 }; 565 566 /** 567 * struct ath_hw_private_ops - callbacks used internally by hardware code 568 * 569 * This structure contains private callbacks designed to only be used internally 570 * by the hardware core. 571 * 572 * @init_cal_settings: setup types of calibrations supported 573 * @init_cal: starts actual calibration 574 * 575 * @init_mode_gain_regs: Initialize TX/RX gain registers 576 * 577 * @rf_set_freq: change frequency 578 * @spur_mitigate_freq: spur mitigation 579 * @set_rf_regs: 580 * @compute_pll_control: compute the PLL control value to use for 581 * AR_RTC_PLL_CONTROL for a given channel 582 * @setup_calibration: set up calibration 583 * @iscal_supported: used to query if a type of calibration is supported 584 * 585 * @ani_cache_ini_regs: cache the values for ANI from the initial 586 * register settings through the register initialization. 587 */ 588 struct ath_hw_private_ops { 589 void (*init_hang_checks)(struct ath_hw *ah); 590 bool (*detect_mac_hang)(struct ath_hw *ah); 591 bool (*detect_bb_hang)(struct ath_hw *ah); 592 593 /* Calibration ops */ 594 void (*init_cal_settings)(struct ath_hw *ah); 595 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 596 597 void (*init_mode_gain_regs)(struct ath_hw *ah); 598 void (*setup_calibration)(struct ath_hw *ah, 599 struct ath9k_cal_list *currCal); 600 601 /* PHY ops */ 602 int (*rf_set_freq)(struct ath_hw *ah, 603 struct ath9k_channel *chan); 604 void (*spur_mitigate_freq)(struct ath_hw *ah, 605 struct ath9k_channel *chan); 606 bool (*set_rf_regs)(struct ath_hw *ah, 607 struct ath9k_channel *chan, 608 u16 modesIndex); 609 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 610 void (*init_bb)(struct ath_hw *ah, 611 struct ath9k_channel *chan); 612 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 613 void (*olc_init)(struct ath_hw *ah); 614 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 615 void (*mark_phy_inactive)(struct ath_hw *ah); 616 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 617 bool (*rfbus_req)(struct ath_hw *ah); 618 void (*rfbus_done)(struct ath_hw *ah); 619 void (*restore_chainmask)(struct ath_hw *ah); 620 u32 (*compute_pll_control)(struct ath_hw *ah, 621 struct ath9k_channel *chan); 622 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 623 int param); 624 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 625 void (*set_radar_params)(struct ath_hw *ah, 626 struct ath_hw_radar_conf *conf); 627 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 628 u8 *ini_reloaded); 629 630 /* ANI */ 631 void (*ani_cache_ini_regs)(struct ath_hw *ah); 632 }; 633 634 /** 635 * struct ath_spec_scan - parameters for Atheros spectral scan 636 * 637 * @enabled: enable/disable spectral scan 638 * @short_repeat: controls whether the chip is in spectral scan mode 639 * for 4 usec (enabled) or 204 usec (disabled) 640 * @count: number of scan results requested. There are special meanings 641 * in some chip revisions: 642 * AR92xx: highest bit set (>=128) for endless mode 643 * (spectral scan won't stopped until explicitly disabled) 644 * AR9300 and newer: 0 for endless mode 645 * @endless: true if endless mode is intended. Otherwise, count value is 646 * corrected to the next possible value. 647 * @period: time duration between successive spectral scan entry points 648 * (period*256*Tclk). Tclk = ath_common->clockrate 649 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS 650 * 651 * Note: Tclk = 40MHz or 44MHz depending upon operating mode. 652 * Typically it's 44MHz in 2/5GHz on later chips, but there's 653 * a "fast clock" check for this in 5GHz. 654 * 655 */ 656 struct ath_spec_scan { 657 bool enabled; 658 bool short_repeat; 659 bool endless; 660 u8 count; 661 u8 period; 662 u8 fft_period; 663 }; 664 665 /** 666 * struct ath_hw_ops - callbacks used by hardware code and driver code 667 * 668 * This structure contains callbacks designed to to be used internally by 669 * hardware code and also by the lower level driver. 670 * 671 * @config_pci_powersave: 672 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 673 * 674 * @spectral_scan_config: set parameters for spectral scan and enable/disable it 675 * @spectral_scan_trigger: trigger a spectral scan run 676 * @spectral_scan_wait: wait for a spectral scan run to finish 677 */ 678 struct ath_hw_ops { 679 void (*config_pci_powersave)(struct ath_hw *ah, 680 bool power_off); 681 void (*rx_enable)(struct ath_hw *ah); 682 void (*set_desc_link)(void *ds, u32 link); 683 bool (*calibrate)(struct ath_hw *ah, 684 struct ath9k_channel *chan, 685 u8 rxchainmask, 686 bool longcal); 687 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, 688 u32 *sync_cause_p); 689 void (*set_txdesc)(struct ath_hw *ah, void *ds, 690 struct ath_tx_info *i); 691 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 692 struct ath_tx_status *ts); 693 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 694 struct ath_hw_antcomb_conf *antconf); 695 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 696 struct ath_hw_antcomb_conf *antconf); 697 void (*spectral_scan_config)(struct ath_hw *ah, 698 struct ath_spec_scan *param); 699 void (*spectral_scan_trigger)(struct ath_hw *ah); 700 void (*spectral_scan_wait)(struct ath_hw *ah); 701 702 void (*tx99_start)(struct ath_hw *ah, u32 qnum); 703 void (*tx99_stop)(struct ath_hw *ah); 704 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); 705 706 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 707 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); 708 #endif 709 }; 710 711 struct ath_nf_limits { 712 s16 max; 713 s16 min; 714 s16 nominal; 715 }; 716 717 enum ath_cal_list { 718 TX_IQ_CAL = BIT(0), 719 TX_IQ_ON_AGC_CAL = BIT(1), 720 TX_CL_CAL = BIT(2), 721 }; 722 723 /* ah_flags */ 724 #define AH_USE_EEPROM 0x1 725 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 726 #define AH_FASTCC 0x4 727 728 struct ath_hw { 729 struct ath_ops reg_ops; 730 731 struct device *dev; 732 struct ieee80211_hw *hw; 733 struct ath_common common; 734 struct ath9k_hw_version hw_version; 735 struct ath9k_ops_config config; 736 struct ath9k_hw_capabilities caps; 737 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 738 struct ath9k_channel *curchan; 739 740 union { 741 struct ar5416_eeprom_def def; 742 struct ar5416_eeprom_4k map4k; 743 struct ar9287_eeprom map9287; 744 struct ar9300_eeprom ar9300_eep; 745 } eeprom; 746 const struct eeprom_ops *eep_ops; 747 748 bool sw_mgmt_crypto; 749 bool is_pciexpress; 750 bool aspm_enabled; 751 bool is_monitoring; 752 bool need_an_top2_fixup; 753 u16 tx_trig_level; 754 755 u32 nf_regs[6]; 756 struct ath_nf_limits nf_2g; 757 struct ath_nf_limits nf_5g; 758 u16 rfsilent; 759 u32 rfkill_gpio; 760 u32 rfkill_polarity; 761 u32 ah_flags; 762 763 bool reset_power_on; 764 bool htc_reset_init; 765 766 enum nl80211_iftype opmode; 767 enum ath9k_power_mode power_mode; 768 769 s8 noise; 770 struct ath9k_hw_cal_data *caldata; 771 struct ath9k_pacal_info pacal_info; 772 struct ar5416Stats stats; 773 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 774 775 enum ath9k_int imask; 776 u32 imrs2_reg; 777 u32 txok_interrupt_mask; 778 u32 txerr_interrupt_mask; 779 u32 txdesc_interrupt_mask; 780 u32 txeol_interrupt_mask; 781 u32 txurn_interrupt_mask; 782 atomic_t intr_ref_cnt; 783 bool chip_fullsleep; 784 u32 modes_index; 785 786 /* Calibration */ 787 u32 supp_cals; 788 struct ath9k_cal_list iq_caldata; 789 struct ath9k_cal_list adcgain_caldata; 790 struct ath9k_cal_list adcdc_caldata; 791 struct ath9k_cal_list *cal_list; 792 struct ath9k_cal_list *cal_list_last; 793 struct ath9k_cal_list *cal_list_curr; 794 #define totalPowerMeasI meas0.unsign 795 #define totalPowerMeasQ meas1.unsign 796 #define totalIqCorrMeas meas2.sign 797 #define totalAdcIOddPhase meas0.unsign 798 #define totalAdcIEvenPhase meas1.unsign 799 #define totalAdcQOddPhase meas2.unsign 800 #define totalAdcQEvenPhase meas3.unsign 801 #define totalAdcDcOffsetIOddPhase meas0.sign 802 #define totalAdcDcOffsetIEvenPhase meas1.sign 803 #define totalAdcDcOffsetQOddPhase meas2.sign 804 #define totalAdcDcOffsetQEvenPhase meas3.sign 805 union { 806 u32 unsign[AR5416_MAX_CHAINS]; 807 int32_t sign[AR5416_MAX_CHAINS]; 808 } meas0; 809 union { 810 u32 unsign[AR5416_MAX_CHAINS]; 811 int32_t sign[AR5416_MAX_CHAINS]; 812 } meas1; 813 union { 814 u32 unsign[AR5416_MAX_CHAINS]; 815 int32_t sign[AR5416_MAX_CHAINS]; 816 } meas2; 817 union { 818 u32 unsign[AR5416_MAX_CHAINS]; 819 int32_t sign[AR5416_MAX_CHAINS]; 820 } meas3; 821 u16 cal_samples; 822 u8 enabled_cals; 823 824 u32 sta_id1_defaults; 825 u32 misc_mode; 826 827 /* Private to hardware code */ 828 struct ath_hw_private_ops private_ops; 829 /* Accessed by the lower level driver */ 830 struct ath_hw_ops ops; 831 832 /* Used to program the radio on non single-chip devices */ 833 u32 *analogBank6Data; 834 835 int coverage_class; 836 u32 slottime; 837 u32 globaltxtimeout; 838 839 /* ANI */ 840 u32 aniperiod; 841 enum ath9k_ani_cmd ani_function; 842 u32 ani_skip_count; 843 struct ar5416AniState ani; 844 845 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 846 struct ath_btcoex_hw btcoex_hw; 847 #endif 848 849 u32 intr_txqs; 850 u8 txchainmask; 851 u8 rxchainmask; 852 853 struct ath_hw_radar_conf radar_conf; 854 855 u32 originalGain[22]; 856 int initPDADC; 857 int PDADCdelta; 858 int led_pin; 859 u32 gpio_mask; 860 u32 gpio_val; 861 862 struct ar5416IniArray ini_dfs; 863 struct ar5416IniArray iniModes; 864 struct ar5416IniArray iniCommon; 865 struct ar5416IniArray iniBB_RfGain; 866 struct ar5416IniArray iniBank6; 867 struct ar5416IniArray iniAddac; 868 struct ar5416IniArray iniPcieSerdes; 869 struct ar5416IniArray iniPcieSerdesLowPower; 870 struct ar5416IniArray iniModesFastClock; 871 struct ar5416IniArray iniAdditional; 872 struct ar5416IniArray iniModesRxGain; 873 struct ar5416IniArray ini_modes_rx_gain_bounds; 874 struct ar5416IniArray iniModesTxGain; 875 struct ar5416IniArray iniCckfirNormal; 876 struct ar5416IniArray iniCckfirJapan2484; 877 struct ar5416IniArray iniModes_9271_ANI_reg; 878 struct ar5416IniArray ini_radio_post_sys2ant; 879 struct ar5416IniArray ini_modes_rxgain_5g_xlna; 880 struct ar5416IniArray ini_modes_rxgain_bb_core; 881 struct ar5416IniArray ini_modes_rxgain_bb_postamble; 882 883 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 884 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 885 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 886 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 887 888 u32 intr_gen_timer_trigger; 889 u32 intr_gen_timer_thresh; 890 struct ath_gen_timer_table hw_gen_timers; 891 892 struct ar9003_txs *ts_ring; 893 u32 ts_paddr_start; 894 u32 ts_paddr_end; 895 u16 ts_tail; 896 u16 ts_size; 897 898 u32 bb_watchdog_last_status; 899 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 900 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 901 902 unsigned int paprd_target_power; 903 unsigned int paprd_training_power; 904 unsigned int paprd_ratemask; 905 unsigned int paprd_ratemask_ht40; 906 bool paprd_table_write_done; 907 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 908 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 909 /* 910 * Store the permanent value of Reg 0x4004in WARegVal 911 * so we dont have to R/M/W. We should not be reading 912 * this register when in sleep states. 913 */ 914 u32 WARegVal; 915 916 /* Enterprise mode cap */ 917 u32 ent_mode; 918 919 #ifdef CONFIG_ATH9K_WOW 920 u32 wow_event_mask; 921 #endif 922 bool is_clk_25mhz; 923 int (*get_mac_revision)(void); 924 int (*external_reset)(void); 925 926 const struct firmware *eeprom_blob; 927 }; 928 929 struct ath_bus_ops { 930 enum ath_bus_type ath_bus_type; 931 void (*read_cachesize)(struct ath_common *common, int *csz); 932 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 933 void (*bt_coex_prep)(struct ath_common *common); 934 void (*aspm_init)(struct ath_common *common); 935 }; 936 937 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 938 { 939 return &ah->common; 940 } 941 942 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 943 { 944 return &(ath9k_hw_common(ah)->regulatory); 945 } 946 947 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 948 { 949 return &ah->private_ops; 950 } 951 952 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 953 { 954 return &ah->ops; 955 } 956 957 static inline u8 get_streams(int mask) 958 { 959 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 960 } 961 962 /* Initialization, Detach, Reset */ 963 void ath9k_hw_deinit(struct ath_hw *ah); 964 int ath9k_hw_init(struct ath_hw *ah); 965 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 966 struct ath9k_hw_cal_data *caldata, bool fastcc); 967 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 968 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 969 970 /* GPIO / RFKILL / Antennae */ 971 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 972 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 973 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 974 u32 ah_signal_type); 975 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 976 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 977 978 /* General Operation */ 979 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 980 int hw_delay); 981 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 982 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 983 int column, unsigned int *writecnt); 984 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 985 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 986 u8 phy, int kbps, 987 u32 frameLen, u16 rateix, bool shortPreamble); 988 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 989 struct ath9k_channel *chan, 990 struct chan_centers *centers); 991 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 992 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 993 bool ath9k_hw_phy_disable(struct ath_hw *ah); 994 bool ath9k_hw_disable(struct ath_hw *ah); 995 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 996 void ath9k_hw_setopmode(struct ath_hw *ah); 997 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 998 void ath9k_hw_write_associd(struct ath_hw *ah); 999 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1000 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1001 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1002 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1003 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur); 1004 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1005 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1006 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1007 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); 1008 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1009 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1010 const struct ath9k_beacon_state *bs); 1011 void ath9k_hw_check_nav(struct ath_hw *ah); 1012 bool ath9k_hw_check_alive(struct ath_hw *ah); 1013 1014 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1015 1016 /* Generic hw timer primitives */ 1017 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1018 void (*trigger)(void *), 1019 void (*overflow)(void *), 1020 void *arg, 1021 u8 timer_index); 1022 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1023 struct ath_gen_timer *timer, 1024 u32 timer_next, 1025 u32 timer_period); 1026 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1027 1028 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1029 void ath_gen_timer_isr(struct ath_hw *hw); 1030 1031 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1032 1033 /* PHY */ 1034 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1035 u32 *coef_mantissa, u32 *coef_exponent); 1036 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1037 bool test); 1038 1039 /* 1040 * Code Specific to AR5008, AR9001 or AR9002, 1041 * we stuff these here to avoid callbacks for AR9003. 1042 */ 1043 int ar9002_hw_rf_claim(struct ath_hw *ah); 1044 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1045 1046 /* 1047 * Code specific to AR9003, we stuff these here to avoid callbacks 1048 * for older families 1049 */ 1050 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); 1051 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1052 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1053 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1054 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1055 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1056 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1057 struct ath9k_hw_cal_data *caldata, 1058 int chain); 1059 int ar9003_paprd_create_curve(struct ath_hw *ah, 1060 struct ath9k_hw_cal_data *caldata, int chain); 1061 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1062 int ar9003_paprd_init_table(struct ath_hw *ah); 1063 bool ar9003_paprd_is_done(struct ath_hw *ah); 1064 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1065 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1066 1067 /* Hardware family op attach helpers */ 1068 int ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1069 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1070 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1071 1072 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1073 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1074 1075 int ar9002_hw_attach_ops(struct ath_hw *ah); 1076 void ar9003_hw_attach_ops(struct ath_hw *ah); 1077 1078 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1079 1080 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1081 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1082 1083 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1084 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1085 { 1086 return ah->btcoex_hw.enabled; 1087 } 1088 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1089 { 1090 return ah->common.btcoex_enabled && 1091 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1092 1093 } 1094 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1095 static inline enum ath_btcoex_scheme 1096 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1097 { 1098 return ah->btcoex_hw.scheme; 1099 } 1100 #else 1101 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1102 { 1103 return false; 1104 } 1105 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1106 { 1107 return false; 1108 } 1109 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1110 { 1111 } 1112 static inline enum ath_btcoex_scheme 1113 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1114 { 1115 return ATH_BTCOEX_CFG_NONE; 1116 } 1117 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1118 1119 1120 #ifdef CONFIG_ATH9K_WOW 1121 const char *ath9k_hw_wow_event_to_string(u32 wow_event); 1122 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1123 u8 *user_mask, int pattern_count, 1124 int pattern_len); 1125 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1126 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1127 #else 1128 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) 1129 { 1130 return NULL; 1131 } 1132 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1133 u8 *user_pattern, 1134 u8 *user_mask, 1135 int pattern_count, 1136 int pattern_len) 1137 { 1138 } 1139 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1140 { 1141 return 0; 1142 } 1143 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1144 { 1145 } 1146 #endif 1147 1148 #define ATH9K_CLOCK_RATE_CCK 22 1149 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1150 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1151 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1152 1153 #endif 1154