xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/hw.h (revision 4800cd83)
1 /*
2  * Copyright (c) 2008-2010 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef HW_H
18 #define HW_H
19 
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31 
32 #include "../regd.h"
33 
34 #define ATHEROS_VENDOR_ID	0x168c
35 
36 #define AR5416_DEVID_PCI	0x0023
37 #define AR5416_DEVID_PCIE	0x0024
38 #define AR9160_DEVID_PCI	0x0027
39 #define AR9280_DEVID_PCI	0x0029
40 #define AR9280_DEVID_PCIE	0x002a
41 #define AR9285_DEVID_PCIE	0x002b
42 #define AR2427_DEVID_PCIE	0x002c
43 #define AR9287_DEVID_PCI	0x002d
44 #define AR9287_DEVID_PCIE	0x002e
45 #define AR9300_DEVID_PCIE	0x0030
46 #define AR9300_DEVID_AR9485_PCIE 0x0032
47 
48 #define AR5416_AR9100_DEVID	0x000b
49 
50 #define	AR_SUBVENDOR_ID_NOG	0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A	0x7065
52 #define AR5416_MAGIC		0x19641014
53 
54 #define AR9280_COEX2WIRE_SUBSYSID	0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID	0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID	0x30ab
57 
58 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
59 
60 #define	ATH_DEFAULT_NOISE_FLOOR -95
61 
62 #define ATH9K_RSSI_BAD			-128
63 
64 #define ATH9K_NUM_CHANNELS	38
65 
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 	ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69 
70 #define REG_READ(_ah, _reg) \
71 	ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
72 
73 #define ENABLE_REGWRITE_BUFFER(_ah)					\
74 	do {								\
75 		if (ath9k_hw_common(_ah)->ops->enable_write_buffer)	\
76 			ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 	} while (0)
78 
79 #define REGWRITE_BUFFER_FLUSH(_ah)					\
80 	do {								\
81 		if (ath9k_hw_common(_ah)->ops->write_flush)		\
82 			ath9k_hw_common(_ah)->ops->write_flush((_ah));	\
83 	} while (0)
84 
85 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
86 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
87 #define REG_RMW(_a, _r, _set, _clr)    \
88 	REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
89 #define REG_RMW_FIELD(_a, _r, _f, _v) \
90 	REG_WRITE(_a, _r, \
91 	(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
92 #define REG_READ_FIELD(_a, _r, _f) \
93 	(((REG_READ(_a, _r) & _f) >> _f##_S))
94 #define REG_SET_BIT(_a, _r, _f) \
95 	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
96 #define REG_CLR_BIT(_a, _r, _f) \
97 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
98 
99 #define DO_DELAY(x) do {			\
100 		if ((++(x) % 64) == 0)          \
101 			udelay(1);		\
102 	} while (0)
103 
104 #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
105 		int r;							\
106 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
107 			REG_WRITE(ah, INI_RA((iniarray), (r), 0),	\
108 				  INI_RA((iniarray), r, (column)));	\
109 			DO_DELAY(regWr);				\
110 		}							\
111 	} while (0)
112 
113 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
114 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
115 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
116 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
117 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
118 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
119 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
120 
121 #define AR_GPIOD_MASK               0x00001FFF
122 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
123 
124 #define BASE_ACTIVATE_DELAY         100
125 #define RTC_PLL_SETTLE_DELAY        100
126 #define COEF_SCALE_S                24
127 #define HT40_CHANNEL_CENTER_SHIFT   10
128 
129 #define ATH9K_ANTENNA0_CHAINMASK    0x1
130 #define ATH9K_ANTENNA1_CHAINMASK    0x2
131 
132 #define ATH9K_NUM_DMA_DEBUG_REGS    8
133 #define ATH9K_NUM_QUEUES            10
134 
135 #define MAX_RATE_POWER              63
136 #define AH_WAIT_TIMEOUT             100000 /* (us) */
137 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
138 #define AH_TIME_QUANTUM             10
139 #define AR_KEYTABLE_SIZE            128
140 #define POWER_UP_TIME               10000
141 #define SPUR_RSSI_THRESH            40
142 
143 #define CAB_TIMEOUT_VAL             10
144 #define BEACON_TIMEOUT_VAL          10
145 #define MIN_BEACON_TIMEOUT_VAL      1
146 #define SLEEP_SLOP                  3
147 
148 #define INIT_CONFIG_STATUS          0x00000000
149 #define INIT_RSSI_THR               0x00000700
150 #define INIT_BCON_CNTRL_REG         0x00000000
151 
152 #define TU_TO_USEC(_tu)             ((_tu) << 10)
153 
154 #define ATH9K_HW_RX_HP_QDEPTH	16
155 #define ATH9K_HW_RX_LP_QDEPTH	128
156 
157 #define PAPRD_GAIN_TABLE_ENTRIES    32
158 #define PAPRD_TABLE_SZ              24
159 
160 enum ath_hw_txq_subtype {
161 	ATH_TXQ_AC_BE = 0,
162 	ATH_TXQ_AC_BK = 1,
163 	ATH_TXQ_AC_VI = 2,
164 	ATH_TXQ_AC_VO = 3,
165 };
166 
167 enum ath_ini_subsys {
168 	ATH_INI_PRE = 0,
169 	ATH_INI_CORE,
170 	ATH_INI_POST,
171 	ATH_INI_NUM_SPLIT,
172 };
173 
174 enum ath9k_hw_caps {
175 	ATH9K_HW_CAP_HT                         = BIT(0),
176 	ATH9K_HW_CAP_RFSILENT                   = BIT(1),
177 	ATH9K_HW_CAP_CST                        = BIT(2),
178 	ATH9K_HW_CAP_ENHANCEDPM                 = BIT(3),
179 	ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
180 	ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
181 	ATH9K_HW_CAP_EDMA			= BIT(6),
182 	ATH9K_HW_CAP_RAC_SUPPORTED		= BIT(7),
183 	ATH9K_HW_CAP_LDPC			= BIT(8),
184 	ATH9K_HW_CAP_FASTCLOCK			= BIT(9),
185 	ATH9K_HW_CAP_SGI_20			= BIT(10),
186 	ATH9K_HW_CAP_PAPRD			= BIT(11),
187 	ATH9K_HW_CAP_ANT_DIV_COMB		= BIT(12),
188 	ATH9K_HW_CAP_2GHZ			= BIT(13),
189 	ATH9K_HW_CAP_5GHZ			= BIT(14),
190 	ATH9K_HW_CAP_APM			= BIT(15),
191 };
192 
193 struct ath9k_hw_capabilities {
194 	u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
195 	u16 total_queues;
196 	u16 keycache_size;
197 	u16 low_5ghz_chan, high_5ghz_chan;
198 	u16 low_2ghz_chan, high_2ghz_chan;
199 	u16 rts_aggr_limit;
200 	u8 tx_chainmask;
201 	u8 rx_chainmask;
202 	u8 max_txchains;
203 	u8 max_rxchains;
204 	u16 tx_triglevel_max;
205 	u16 reg_cap;
206 	u8 num_gpio_pins;
207 	u8 rx_hp_qdepth;
208 	u8 rx_lp_qdepth;
209 	u8 rx_status_len;
210 	u8 tx_desc_len;
211 	u8 txs_len;
212 	u16 pcie_lcr_offset;
213 	bool pcie_lcr_extsync_en;
214 };
215 
216 struct ath9k_ops_config {
217 	int dma_beacon_response_time;
218 	int sw_beacon_response_time;
219 	int additional_swba_backoff;
220 	int ack_6mb;
221 	u32 cwm_ignore_extcca;
222 	u8 pcie_powersave_enable;
223 	bool pcieSerDesWrite;
224 	u8 pcie_clock_req;
225 	u32 pcie_waen;
226 	u8 analog_shiftreg;
227 	u8 ht_enable;
228 	u8 paprd_disable;
229 	u32 ofdm_trig_low;
230 	u32 ofdm_trig_high;
231 	u32 cck_trig_high;
232 	u32 cck_trig_low;
233 	u32 enable_ani;
234 	int serialize_regmode;
235 	bool rx_intr_mitigation;
236 	bool tx_intr_mitigation;
237 #define SPUR_DISABLE        	0
238 #define SPUR_ENABLE_IOCTL   	1
239 #define SPUR_ENABLE_EEPROM  	2
240 #define AR_SPUR_5413_1      	1640
241 #define AR_SPUR_5413_2      	1200
242 #define AR_NO_SPUR      	0x8000
243 #define AR_BASE_FREQ_2GHZ   	2300
244 #define AR_BASE_FREQ_5GHZ   	4900
245 #define AR_SPUR_FEEQ_BOUND_HT40 19
246 #define AR_SPUR_FEEQ_BOUND_HT20 10
247 	int spurmode;
248 	u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
249 	u8 max_txtrig_level;
250 	u16 ani_poll_interval; /* ANI poll interval in ms */
251 };
252 
253 enum ath9k_int {
254 	ATH9K_INT_RX = 0x00000001,
255 	ATH9K_INT_RXDESC = 0x00000002,
256 	ATH9K_INT_RXHP = 0x00000001,
257 	ATH9K_INT_RXLP = 0x00000002,
258 	ATH9K_INT_RXNOFRM = 0x00000008,
259 	ATH9K_INT_RXEOL = 0x00000010,
260 	ATH9K_INT_RXORN = 0x00000020,
261 	ATH9K_INT_TX = 0x00000040,
262 	ATH9K_INT_TXDESC = 0x00000080,
263 	ATH9K_INT_TIM_TIMER = 0x00000100,
264 	ATH9K_INT_BB_WATCHDOG = 0x00000400,
265 	ATH9K_INT_TXURN = 0x00000800,
266 	ATH9K_INT_MIB = 0x00001000,
267 	ATH9K_INT_RXPHY = 0x00004000,
268 	ATH9K_INT_RXKCM = 0x00008000,
269 	ATH9K_INT_SWBA = 0x00010000,
270 	ATH9K_INT_BMISS = 0x00040000,
271 	ATH9K_INT_BNR = 0x00100000,
272 	ATH9K_INT_TIM = 0x00200000,
273 	ATH9K_INT_DTIM = 0x00400000,
274 	ATH9K_INT_DTIMSYNC = 0x00800000,
275 	ATH9K_INT_GPIO = 0x01000000,
276 	ATH9K_INT_CABEND = 0x02000000,
277 	ATH9K_INT_TSFOOR = 0x04000000,
278 	ATH9K_INT_GENTIMER = 0x08000000,
279 	ATH9K_INT_CST = 0x10000000,
280 	ATH9K_INT_GTT = 0x20000000,
281 	ATH9K_INT_FATAL = 0x40000000,
282 	ATH9K_INT_GLOBAL = 0x80000000,
283 	ATH9K_INT_BMISC = ATH9K_INT_TIM |
284 		ATH9K_INT_DTIM |
285 		ATH9K_INT_DTIMSYNC |
286 		ATH9K_INT_TSFOOR |
287 		ATH9K_INT_CABEND,
288 	ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
289 		ATH9K_INT_RXDESC |
290 		ATH9K_INT_RXEOL |
291 		ATH9K_INT_RXORN |
292 		ATH9K_INT_TXURN |
293 		ATH9K_INT_TXDESC |
294 		ATH9K_INT_MIB |
295 		ATH9K_INT_RXPHY |
296 		ATH9K_INT_RXKCM |
297 		ATH9K_INT_SWBA |
298 		ATH9K_INT_BMISS |
299 		ATH9K_INT_GPIO,
300 	ATH9K_INT_NOCARD = 0xffffffff
301 };
302 
303 #define CHANNEL_CW_INT    0x00002
304 #define CHANNEL_CCK       0x00020
305 #define CHANNEL_OFDM      0x00040
306 #define CHANNEL_2GHZ      0x00080
307 #define CHANNEL_5GHZ      0x00100
308 #define CHANNEL_PASSIVE   0x00200
309 #define CHANNEL_DYN       0x00400
310 #define CHANNEL_HALF      0x04000
311 #define CHANNEL_QUARTER   0x08000
312 #define CHANNEL_HT20      0x10000
313 #define CHANNEL_HT40PLUS  0x20000
314 #define CHANNEL_HT40MINUS 0x40000
315 
316 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
317 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
318 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
319 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
320 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
321 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
322 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
323 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
324 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
325 #define CHANNEL_ALL				\
326 	(CHANNEL_OFDM|				\
327 	 CHANNEL_CCK|				\
328 	 CHANNEL_2GHZ |				\
329 	 CHANNEL_5GHZ |				\
330 	 CHANNEL_HT20 |				\
331 	 CHANNEL_HT40PLUS |			\
332 	 CHANNEL_HT40MINUS)
333 
334 struct ath9k_hw_cal_data {
335 	u16 channel;
336 	u32 channelFlags;
337 	int32_t CalValid;
338 	int8_t iCoff;
339 	int8_t qCoff;
340 	bool paprd_done;
341 	bool nfcal_pending;
342 	bool nfcal_interference;
343 	u16 small_signal_gain[AR9300_MAX_CHAINS];
344 	u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
345 	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
346 };
347 
348 struct ath9k_channel {
349 	struct ieee80211_channel *chan;
350 	struct ar5416AniState ani;
351 	u16 channel;
352 	u32 channelFlags;
353 	u32 chanmode;
354 	s16 noisefloor;
355 };
356 
357 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
358        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
359        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
360        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
361 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
362 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
363 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
364 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
365 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
366 #define IS_CHAN_A_FAST_CLOCK(_ah, _c)			\
367 	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&	\
368 	 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
369 
370 /* These macros check chanmode and not channelFlags */
371 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
372 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) ||	\
373 			  ((_c)->chanmode == CHANNEL_G_HT20))
374 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||	\
375 			  ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||	\
376 			  ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||	\
377 			  ((_c)->chanmode == CHANNEL_G_HT40MINUS))
378 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
379 
380 enum ath9k_power_mode {
381 	ATH9K_PM_AWAKE = 0,
382 	ATH9K_PM_FULL_SLEEP,
383 	ATH9K_PM_NETWORK_SLEEP,
384 	ATH9K_PM_UNDEFINED
385 };
386 
387 enum ath9k_tp_scale {
388 	ATH9K_TP_SCALE_MAX = 0,
389 	ATH9K_TP_SCALE_50,
390 	ATH9K_TP_SCALE_25,
391 	ATH9K_TP_SCALE_12,
392 	ATH9K_TP_SCALE_MIN
393 };
394 
395 enum ser_reg_mode {
396 	SER_REG_MODE_OFF = 0,
397 	SER_REG_MODE_ON = 1,
398 	SER_REG_MODE_AUTO = 2,
399 };
400 
401 enum ath9k_rx_qtype {
402 	ATH9K_RX_QUEUE_HP,
403 	ATH9K_RX_QUEUE_LP,
404 	ATH9K_RX_QUEUE_MAX,
405 };
406 
407 struct ath9k_beacon_state {
408 	u32 bs_nexttbtt;
409 	u32 bs_nextdtim;
410 	u32 bs_intval;
411 #define ATH9K_BEACON_PERIOD       0x0000ffff
412 #define ATH9K_BEACON_ENA          0x00800000
413 #define ATH9K_BEACON_RESET_TSF    0x01000000
414 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
415 	u32 bs_dtimperiod;
416 	u16 bs_cfpperiod;
417 	u16 bs_cfpmaxduration;
418 	u32 bs_cfpnext;
419 	u16 bs_timoffset;
420 	u16 bs_bmissthreshold;
421 	u32 bs_sleepduration;
422 	u32 bs_tsfoor_threshold;
423 };
424 
425 struct chan_centers {
426 	u16 synth_center;
427 	u16 ctl_center;
428 	u16 ext_center;
429 };
430 
431 enum {
432 	ATH9K_RESET_POWER_ON,
433 	ATH9K_RESET_WARM,
434 	ATH9K_RESET_COLD,
435 };
436 
437 struct ath9k_hw_version {
438 	u32 magic;
439 	u16 devid;
440 	u16 subvendorid;
441 	u32 macVersion;
442 	u16 macRev;
443 	u16 phyRev;
444 	u16 analog5GhzRev;
445 	u16 analog2GhzRev;
446 	u16 subsysid;
447 	enum ath_usb_dev usbdev;
448 };
449 
450 /* Generic TSF timer definitions */
451 
452 #define ATH_MAX_GEN_TIMER	16
453 
454 #define AR_GENTMR_BIT(_index)	(1 << (_index))
455 
456 /*
457  * Using de Bruijin sequence to look up 1's index in a 32 bit number
458  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
459  */
460 #define debruijn32 0x077CB531U
461 
462 struct ath_gen_timer_configuration {
463 	u32 next_addr;
464 	u32 period_addr;
465 	u32 mode_addr;
466 	u32 mode_mask;
467 };
468 
469 struct ath_gen_timer {
470 	void (*trigger)(void *arg);
471 	void (*overflow)(void *arg);
472 	void *arg;
473 	u8 index;
474 };
475 
476 struct ath_gen_timer_table {
477 	u32 gen_timer_index[32];
478 	struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
479 	union {
480 		unsigned long timer_bits;
481 		u16 val;
482 	} timer_mask;
483 };
484 
485 struct ath_hw_antcomb_conf {
486 	u8 main_lna_conf;
487 	u8 alt_lna_conf;
488 	u8 fast_div_bias;
489 };
490 
491 /**
492  * struct ath_hw_radar_conf - radar detection initialization parameters
493  *
494  * @pulse_inband: threshold for checking the ratio of in-band power
495  *	to total power for short radar pulses (half dB steps)
496  * @pulse_inband_step: threshold for checking an in-band power to total
497  *	power ratio increase for short radar pulses (half dB steps)
498  * @pulse_height: threshold for detecting the beginning of a short
499  *	radar pulse (dB step)
500  * @pulse_rssi: threshold for detecting if a short radar pulse is
501  *	gone (dB step)
502  * @pulse_maxlen: maximum pulse length (0.8 us steps)
503  *
504  * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
505  * @radar_inband: threshold for checking the ratio of in-band power
506  *	to total power for long radar pulses (half dB steps)
507  * @fir_power: threshold for detecting the end of a long radar pulse (dB)
508  *
509  * @ext_channel: enable extension channel radar detection
510  */
511 struct ath_hw_radar_conf {
512 	unsigned int pulse_inband;
513 	unsigned int pulse_inband_step;
514 	unsigned int pulse_height;
515 	unsigned int pulse_rssi;
516 	unsigned int pulse_maxlen;
517 
518 	unsigned int radar_rssi;
519 	unsigned int radar_inband;
520 	int fir_power;
521 
522 	bool ext_channel;
523 };
524 
525 /**
526  * struct ath_hw_private_ops - callbacks used internally by hardware code
527  *
528  * This structure contains private callbacks designed to only be used internally
529  * by the hardware core.
530  *
531  * @init_cal_settings: setup types of calibrations supported
532  * @init_cal: starts actual calibration
533  *
534  * @init_mode_regs: Initializes mode registers
535  * @init_mode_gain_regs: Initialize TX/RX gain registers
536  *
537  * @rf_set_freq: change frequency
538  * @spur_mitigate_freq: spur mitigation
539  * @rf_alloc_ext_banks:
540  * @rf_free_ext_banks:
541  * @set_rf_regs:
542  * @compute_pll_control: compute the PLL control value to use for
543  *	AR_RTC_PLL_CONTROL for a given channel
544  * @setup_calibration: set up calibration
545  * @iscal_supported: used to query if a type of calibration is supported
546  *
547  * @ani_cache_ini_regs: cache the values for ANI from the initial
548  *	register settings through the register initialization.
549  */
550 struct ath_hw_private_ops {
551 	/* Calibration ops */
552 	void (*init_cal_settings)(struct ath_hw *ah);
553 	bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
554 
555 	void (*init_mode_regs)(struct ath_hw *ah);
556 	void (*init_mode_gain_regs)(struct ath_hw *ah);
557 	void (*setup_calibration)(struct ath_hw *ah,
558 				  struct ath9k_cal_list *currCal);
559 
560 	/* PHY ops */
561 	int (*rf_set_freq)(struct ath_hw *ah,
562 			   struct ath9k_channel *chan);
563 	void (*spur_mitigate_freq)(struct ath_hw *ah,
564 				   struct ath9k_channel *chan);
565 	int (*rf_alloc_ext_banks)(struct ath_hw *ah);
566 	void (*rf_free_ext_banks)(struct ath_hw *ah);
567 	bool (*set_rf_regs)(struct ath_hw *ah,
568 			    struct ath9k_channel *chan,
569 			    u16 modesIndex);
570 	void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
571 	void (*init_bb)(struct ath_hw *ah,
572 			struct ath9k_channel *chan);
573 	int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
574 	void (*olc_init)(struct ath_hw *ah);
575 	void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
576 	void (*mark_phy_inactive)(struct ath_hw *ah);
577 	void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
578 	bool (*rfbus_req)(struct ath_hw *ah);
579 	void (*rfbus_done)(struct ath_hw *ah);
580 	void (*restore_chainmask)(struct ath_hw *ah);
581 	void (*set_diversity)(struct ath_hw *ah, bool value);
582 	u32 (*compute_pll_control)(struct ath_hw *ah,
583 				   struct ath9k_channel *chan);
584 	bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
585 			    int param);
586 	void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
587 	void (*set_radar_params)(struct ath_hw *ah,
588 				 struct ath_hw_radar_conf *conf);
589 
590 	/* ANI */
591 	void (*ani_cache_ini_regs)(struct ath_hw *ah);
592 };
593 
594 /**
595  * struct ath_hw_ops - callbacks used by hardware code and driver code
596  *
597  * This structure contains callbacks designed to to be used internally by
598  * hardware code and also by the lower level driver.
599  *
600  * @config_pci_powersave:
601  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
602  */
603 struct ath_hw_ops {
604 	void (*config_pci_powersave)(struct ath_hw *ah,
605 				     int restore,
606 				     int power_off);
607 	void (*rx_enable)(struct ath_hw *ah);
608 	void (*set_desc_link)(void *ds, u32 link);
609 	void (*get_desc_link)(void *ds, u32 **link);
610 	bool (*calibrate)(struct ath_hw *ah,
611 			  struct ath9k_channel *chan,
612 			  u8 rxchainmask,
613 			  bool longcal);
614 	bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
615 	void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
616 			    bool is_firstseg, bool is_is_lastseg,
617 			    const void *ds0, dma_addr_t buf_addr,
618 			    unsigned int qcu);
619 	int (*proc_txdesc)(struct ath_hw *ah, void *ds,
620 			   struct ath_tx_status *ts);
621 	void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
622 			      u32 pktLen, enum ath9k_pkt_type type,
623 			      u32 txPower, u32 keyIx,
624 			      enum ath9k_key_type keyType,
625 			      u32 flags);
626 	void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
627 				void *lastds,
628 				u32 durUpdateEn, u32 rtsctsRate,
629 				u32 rtsctsDuration,
630 				struct ath9k_11n_rate_series series[],
631 				u32 nseries, u32 flags);
632 	void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
633 				  u32 aggrLen);
634 	void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
635 				   u32 numDelims);
636 	void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
637 	void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
638 	void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
639 				     u32 burstDuration);
640 	void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
641 				       u32 vmf);
642 };
643 
644 struct ath_nf_limits {
645 	s16 max;
646 	s16 min;
647 	s16 nominal;
648 };
649 
650 /* ah_flags */
651 #define AH_USE_EEPROM   0x1
652 #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
653 
654 struct ath_hw {
655 	struct ieee80211_hw *hw;
656 	struct ath_common common;
657 	struct ath9k_hw_version hw_version;
658 	struct ath9k_ops_config config;
659 	struct ath9k_hw_capabilities caps;
660 	struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
661 	struct ath9k_channel *curchan;
662 
663 	union {
664 		struct ar5416_eeprom_def def;
665 		struct ar5416_eeprom_4k map4k;
666 		struct ar9287_eeprom map9287;
667 		struct ar9300_eeprom ar9300_eep;
668 	} eeprom;
669 	const struct eeprom_ops *eep_ops;
670 
671 	bool sw_mgmt_crypto;
672 	bool is_pciexpress;
673 	bool is_monitoring;
674 	bool need_an_top2_fixup;
675 	u16 tx_trig_level;
676 
677 	u32 nf_regs[6];
678 	struct ath_nf_limits nf_2g;
679 	struct ath_nf_limits nf_5g;
680 	u16 rfsilent;
681 	u32 rfkill_gpio;
682 	u32 rfkill_polarity;
683 	u32 ah_flags;
684 
685 	bool htc_reset_init;
686 
687 	enum nl80211_iftype opmode;
688 	enum ath9k_power_mode power_mode;
689 
690 	struct ath9k_hw_cal_data *caldata;
691 	struct ath9k_pacal_info pacal_info;
692 	struct ar5416Stats stats;
693 	struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
694 
695 	int16_t curchan_rad_index;
696 	enum ath9k_int imask;
697 	u32 imrs2_reg;
698 	u32 txok_interrupt_mask;
699 	u32 txerr_interrupt_mask;
700 	u32 txdesc_interrupt_mask;
701 	u32 txeol_interrupt_mask;
702 	u32 txurn_interrupt_mask;
703 	bool chip_fullsleep;
704 	u32 atim_window;
705 
706 	/* Calibration */
707 	u32 supp_cals;
708 	struct ath9k_cal_list iq_caldata;
709 	struct ath9k_cal_list adcgain_caldata;
710 	struct ath9k_cal_list adcdc_caldata;
711 	struct ath9k_cal_list tempCompCalData;
712 	struct ath9k_cal_list *cal_list;
713 	struct ath9k_cal_list *cal_list_last;
714 	struct ath9k_cal_list *cal_list_curr;
715 #define totalPowerMeasI meas0.unsign
716 #define totalPowerMeasQ meas1.unsign
717 #define totalIqCorrMeas meas2.sign
718 #define totalAdcIOddPhase  meas0.unsign
719 #define totalAdcIEvenPhase meas1.unsign
720 #define totalAdcQOddPhase  meas2.unsign
721 #define totalAdcQEvenPhase meas3.unsign
722 #define totalAdcDcOffsetIOddPhase  meas0.sign
723 #define totalAdcDcOffsetIEvenPhase meas1.sign
724 #define totalAdcDcOffsetQOddPhase  meas2.sign
725 #define totalAdcDcOffsetQEvenPhase meas3.sign
726 	union {
727 		u32 unsign[AR5416_MAX_CHAINS];
728 		int32_t sign[AR5416_MAX_CHAINS];
729 	} meas0;
730 	union {
731 		u32 unsign[AR5416_MAX_CHAINS];
732 		int32_t sign[AR5416_MAX_CHAINS];
733 	} meas1;
734 	union {
735 		u32 unsign[AR5416_MAX_CHAINS];
736 		int32_t sign[AR5416_MAX_CHAINS];
737 	} meas2;
738 	union {
739 		u32 unsign[AR5416_MAX_CHAINS];
740 		int32_t sign[AR5416_MAX_CHAINS];
741 	} meas3;
742 	u16 cal_samples;
743 
744 	u32 sta_id1_defaults;
745 	u32 misc_mode;
746 	enum {
747 		AUTO_32KHZ,
748 		USE_32KHZ,
749 		DONT_USE_32KHZ,
750 	} enable_32kHz_clock;
751 
752 	/* Private to hardware code */
753 	struct ath_hw_private_ops private_ops;
754 	/* Accessed by the lower level driver */
755 	struct ath_hw_ops ops;
756 
757 	/* Used to program the radio on non single-chip devices */
758 	u32 *analogBank0Data;
759 	u32 *analogBank1Data;
760 	u32 *analogBank2Data;
761 	u32 *analogBank3Data;
762 	u32 *analogBank6Data;
763 	u32 *analogBank6TPCData;
764 	u32 *analogBank7Data;
765 	u32 *addac5416_21;
766 	u32 *bank6Temp;
767 
768 	u8 txpower_limit;
769 	int coverage_class;
770 	u32 slottime;
771 	u32 globaltxtimeout;
772 
773 	/* ANI */
774 	u32 proc_phyerr;
775 	u32 aniperiod;
776 	int totalSizeDesired[5];
777 	int coarse_high[5];
778 	int coarse_low[5];
779 	int firpwr[5];
780 	enum ath9k_ani_cmd ani_function;
781 
782 	/* Bluetooth coexistance */
783 	struct ath_btcoex_hw btcoex_hw;
784 
785 	u32 intr_txqs;
786 	u8 txchainmask;
787 	u8 rxchainmask;
788 
789 	struct ath_hw_radar_conf radar_conf;
790 
791 	u32 originalGain[22];
792 	int initPDADC;
793 	int PDADCdelta;
794 	u8 led_pin;
795 
796 	struct ar5416IniArray iniModes;
797 	struct ar5416IniArray iniCommon;
798 	struct ar5416IniArray iniBank0;
799 	struct ar5416IniArray iniBB_RfGain;
800 	struct ar5416IniArray iniBank1;
801 	struct ar5416IniArray iniBank2;
802 	struct ar5416IniArray iniBank3;
803 	struct ar5416IniArray iniBank6;
804 	struct ar5416IniArray iniBank6TPC;
805 	struct ar5416IniArray iniBank7;
806 	struct ar5416IniArray iniAddac;
807 	struct ar5416IniArray iniPcieSerdes;
808 	struct ar5416IniArray iniPcieSerdesLowPower;
809 	struct ar5416IniArray iniModesAdditional;
810 	struct ar5416IniArray iniModesRxGain;
811 	struct ar5416IniArray iniModesTxGain;
812 	struct ar5416IniArray iniModes_9271_1_0_only;
813 	struct ar5416IniArray iniCckfirNormal;
814 	struct ar5416IniArray iniCckfirJapan2484;
815 	struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
816 	struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
817 	struct ar5416IniArray iniModes_9271_ANI_reg;
818 	struct ar5416IniArray iniModes_high_power_tx_gain_9271;
819 	struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
820 
821 	struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
822 	struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
823 	struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
824 	struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
825 
826 	u32 intr_gen_timer_trigger;
827 	u32 intr_gen_timer_thresh;
828 	struct ath_gen_timer_table hw_gen_timers;
829 
830 	struct ar9003_txs *ts_ring;
831 	void *ts_start;
832 	u32 ts_paddr_start;
833 	u32 ts_paddr_end;
834 	u16 ts_tail;
835 	u8 ts_size;
836 
837 	u32 bb_watchdog_last_status;
838 	u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
839 
840 	unsigned int paprd_target_power;
841 	unsigned int paprd_training_power;
842 	unsigned int paprd_ratemask;
843 	unsigned int paprd_ratemask_ht40;
844 	bool paprd_table_write_done;
845 	u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
846 	u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
847 	/*
848 	 * Store the permanent value of Reg 0x4004in WARegVal
849 	 * so we dont have to R/M/W. We should not be reading
850 	 * this register when in sleep states.
851 	 */
852 	u32 WARegVal;
853 
854 	/* Enterprise mode cap */
855 	u32 ent_mode;
856 };
857 
858 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
859 {
860 	return &ah->common;
861 }
862 
863 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
864 {
865 	return &(ath9k_hw_common(ah)->regulatory);
866 }
867 
868 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
869 {
870 	return &ah->private_ops;
871 }
872 
873 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
874 {
875 	return &ah->ops;
876 }
877 
878 static inline u8 get_streams(int mask)
879 {
880 	return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
881 }
882 
883 /* Initialization, Detach, Reset */
884 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
885 void ath9k_hw_deinit(struct ath_hw *ah);
886 int ath9k_hw_init(struct ath_hw *ah);
887 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
888 		   struct ath9k_hw_cal_data *caldata, bool bChannelChange);
889 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
890 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
891 
892 /* GPIO / RFKILL / Antennae */
893 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
894 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
895 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
896 			 u32 ah_signal_type);
897 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
898 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
899 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
900 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
901 				   struct ath_hw_antcomb_conf *antconf);
902 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
903 				   struct ath_hw_antcomb_conf *antconf);
904 
905 /* General Operation */
906 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
907 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
908 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
909 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
910 			   u8 phy, int kbps,
911 			   u32 frameLen, u16 rateix, bool shortPreamble);
912 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
913 				  struct ath9k_channel *chan,
914 				  struct chan_centers *centers);
915 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
916 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
917 bool ath9k_hw_phy_disable(struct ath_hw *ah);
918 bool ath9k_hw_disable(struct ath_hw *ah);
919 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
920 void ath9k_hw_setopmode(struct ath_hw *ah);
921 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
922 void ath9k_hw_setbssidmask(struct ath_hw *ah);
923 void ath9k_hw_write_associd(struct ath_hw *ah);
924 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
925 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
926 void ath9k_hw_reset_tsf(struct ath_hw *ah);
927 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
928 void ath9k_hw_init_global_settings(struct ath_hw *ah);
929 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
930 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
931 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
932 				    const struct ath9k_beacon_state *bs);
933 bool ath9k_hw_check_alive(struct ath_hw *ah);
934 
935 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
936 
937 /* Generic hw timer primitives */
938 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
939 					  void (*trigger)(void *),
940 					  void (*overflow)(void *),
941 					  void *arg,
942 					  u8 timer_index);
943 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
944 			      struct ath_gen_timer *timer,
945 			      u32 timer_next,
946 			      u32 timer_period);
947 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
948 
949 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
950 void ath_gen_timer_isr(struct ath_hw *hw);
951 
952 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
953 
954 /* HTC */
955 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
956 
957 /* PHY */
958 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
959 				   u32 *coef_mantissa, u32 *coef_exponent);
960 
961 /*
962  * Code Specific to AR5008, AR9001 or AR9002,
963  * we stuff these here to avoid callbacks for AR9003.
964  */
965 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
966 int ar9002_hw_rf_claim(struct ath_hw *ah);
967 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
968 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
969 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
970 
971 /*
972  * Code specific to AR9003, we stuff these here to avoid callbacks
973  * for older families
974  */
975 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
976 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
977 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
978 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
979 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
980 					struct ath9k_hw_cal_data *caldata,
981 					int chain);
982 int ar9003_paprd_create_curve(struct ath_hw *ah,
983 			      struct ath9k_hw_cal_data *caldata, int chain);
984 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
985 int ar9003_paprd_init_table(struct ath_hw *ah);
986 bool ar9003_paprd_is_done(struct ath_hw *ah);
987 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
988 
989 /* Hardware family op attach helpers */
990 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
991 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
992 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
993 
994 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
995 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
996 
997 void ar9002_hw_attach_ops(struct ath_hw *ah);
998 void ar9003_hw_attach_ops(struct ath_hw *ah);
999 
1000 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1001 /*
1002  * ANI work can be shared between all families but a next
1003  * generation implementation of ANI will be used only for AR9003 only
1004  * for now as the other families still need to be tested with the same
1005  * next generation ANI. Feel free to start testing it though for the
1006  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1007  */
1008 extern int modparam_force_new_ani;
1009 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1010 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1011 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1012 
1013 #define ATH_PCIE_CAP_LINK_CTRL	0x70
1014 #define ATH_PCIE_CAP_LINK_L0S	1
1015 #define ATH_PCIE_CAP_LINK_L1	2
1016 
1017 #define ATH9K_CLOCK_RATE_CCK		22
1018 #define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
1019 #define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
1020 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1021 
1022 #endif
1023