1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "ar9003_phy.h" 28 #include "debug.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static int __init ath9k_init(void) 39 { 40 return 0; 41 } 42 module_init(ath9k_init); 43 44 static void __exit ath9k_exit(void) 45 { 46 return; 47 } 48 module_exit(ath9k_exit); 49 50 /* Private hardware callbacks */ 51 52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 55 } 56 57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59 { 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61 } 62 63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64 { 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69 } 70 71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72 { 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78 } 79 80 /********************/ 81 /* Helper Functions */ 82 /********************/ 83 84 #ifdef CONFIG_ATH9K_DEBUGFS 85 86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 87 { 88 struct ath_softc *sc = common->priv; 89 if (sync_cause) 90 sc->debug.stats.istats.sync_cause_all++; 91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 92 sc->debug.stats.istats.sync_rtc_irq++; 93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 94 sc->debug.stats.istats.sync_mac_irq++; 95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 96 sc->debug.stats.istats.eeprom_illegal_access++; 97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 98 sc->debug.stats.istats.apb_timeout++; 99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 100 sc->debug.stats.istats.pci_mode_conflict++; 101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 102 sc->debug.stats.istats.host1_fatal++; 103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 104 sc->debug.stats.istats.host1_perr++; 105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 106 sc->debug.stats.istats.trcv_fifo_perr++; 107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 108 sc->debug.stats.istats.radm_cpl_ep++; 109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 110 sc->debug.stats.istats.radm_cpl_dllp_abort++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 112 sc->debug.stats.istats.radm_cpl_tlp_abort++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 114 sc->debug.stats.istats.radm_cpl_ecrc_err++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 116 sc->debug.stats.istats.radm_cpl_timeout++; 117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 118 sc->debug.stats.istats.local_timeout++; 119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 120 sc->debug.stats.istats.pm_access++; 121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 122 sc->debug.stats.istats.mac_awake++; 123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 124 sc->debug.stats.istats.mac_asleep++; 125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 126 sc->debug.stats.istats.mac_sleep_access++; 127 } 128 #endif 129 130 131 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 132 { 133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 134 struct ath_common *common = ath9k_hw_common(ah); 135 unsigned int clockrate; 136 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 139 clockrate = 117; 140 else if (!ah->curchan) /* should really check for CCK instead */ 141 clockrate = ATH9K_CLOCK_RATE_CCK; 142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 146 else 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 148 149 if (conf_is_ht40(conf)) 150 clockrate *= 2; 151 152 if (ah->curchan) { 153 if (IS_CHAN_HALF_RATE(ah->curchan)) 154 clockrate /= 2; 155 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 156 clockrate /= 4; 157 } 158 159 common->clockrate = clockrate; 160 } 161 162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 163 { 164 struct ath_common *common = ath9k_hw_common(ah); 165 166 return usecs * common->clockrate; 167 } 168 169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 170 { 171 int i; 172 173 BUG_ON(timeout < AH_TIME_QUANTUM); 174 175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 176 if ((REG_READ(ah, reg) & mask) == val) 177 return true; 178 179 udelay(AH_TIME_QUANTUM); 180 } 181 182 ath_dbg(ath9k_hw_common(ah), ANY, 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 184 timeout, reg, REG_READ(ah, reg), mask, val); 185 186 return false; 187 } 188 EXPORT_SYMBOL(ath9k_hw_wait); 189 190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 191 int hw_delay) 192 { 193 if (IS_CHAN_B(chan)) 194 hw_delay = (4 * hw_delay) / 22; 195 else 196 hw_delay /= 10; 197 198 if (IS_CHAN_HALF_RATE(chan)) 199 hw_delay *= 2; 200 else if (IS_CHAN_QUARTER_RATE(chan)) 201 hw_delay *= 4; 202 203 udelay(hw_delay + BASE_ACTIVATE_DELAY); 204 } 205 206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 207 int column, unsigned int *writecnt) 208 { 209 int r; 210 211 ENABLE_REGWRITE_BUFFER(ah); 212 for (r = 0; r < array->ia_rows; r++) { 213 REG_WRITE(ah, INI_RA(array, r, 0), 214 INI_RA(array, r, column)); 215 DO_DELAY(*writecnt); 216 } 217 REGWRITE_BUFFER_FLUSH(ah); 218 } 219 220 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 221 { 222 u32 retval; 223 int i; 224 225 for (i = 0, retval = 0; i < n; i++) { 226 retval = (retval << 1) | (val & 1); 227 val >>= 1; 228 } 229 return retval; 230 } 231 232 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 233 u8 phy, int kbps, 234 u32 frameLen, u16 rateix, 235 bool shortPreamble) 236 { 237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 238 239 if (kbps == 0) 240 return 0; 241 242 switch (phy) { 243 case WLAN_RC_PHY_CCK: 244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 245 if (shortPreamble) 246 phyTime >>= 1; 247 numBits = frameLen << 3; 248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 249 break; 250 case WLAN_RC_PHY_OFDM: 251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 253 numBits = OFDM_PLCP_BITS + (frameLen << 3); 254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 255 txTime = OFDM_SIFS_TIME_QUARTER 256 + OFDM_PREAMBLE_TIME_QUARTER 257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 258 } else if (ah->curchan && 259 IS_CHAN_HALF_RATE(ah->curchan)) { 260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 261 numBits = OFDM_PLCP_BITS + (frameLen << 3); 262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 263 txTime = OFDM_SIFS_TIME_HALF + 264 OFDM_PREAMBLE_TIME_HALF 265 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 266 } else { 267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 268 numBits = OFDM_PLCP_BITS + (frameLen << 3); 269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 271 + (numSymbols * OFDM_SYMBOL_TIME); 272 } 273 break; 274 default: 275 ath_err(ath9k_hw_common(ah), 276 "Unknown phy %u (rate ix %u)\n", phy, rateix); 277 txTime = 0; 278 break; 279 } 280 281 return txTime; 282 } 283 EXPORT_SYMBOL(ath9k_hw_computetxtime); 284 285 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 286 struct ath9k_channel *chan, 287 struct chan_centers *centers) 288 { 289 int8_t extoff; 290 291 if (!IS_CHAN_HT40(chan)) { 292 centers->ctl_center = centers->ext_center = 293 centers->synth_center = chan->channel; 294 return; 295 } 296 297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 298 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 299 centers->synth_center = 300 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 301 extoff = 1; 302 } else { 303 centers->synth_center = 304 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 305 extoff = -1; 306 } 307 308 centers->ctl_center = 309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 310 /* 25 MHz spacing is supported by hw but not on upper layers */ 311 centers->ext_center = 312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 313 } 314 315 /******************/ 316 /* Chip Revisions */ 317 /******************/ 318 319 static void ath9k_hw_read_revisions(struct ath_hw *ah) 320 { 321 u32 val; 322 323 switch (ah->hw_version.devid) { 324 case AR5416_AR9100_DEVID: 325 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 326 break; 327 case AR9300_DEVID_AR9330: 328 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 329 if (ah->get_mac_revision) { 330 ah->hw_version.macRev = ah->get_mac_revision(); 331 } else { 332 val = REG_READ(ah, AR_SREV); 333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 334 } 335 return; 336 case AR9300_DEVID_AR9340: 337 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 338 val = REG_READ(ah, AR_SREV); 339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 340 return; 341 case AR9300_DEVID_QCA955X: 342 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 343 return; 344 } 345 346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 347 348 if (val == 0xFF) { 349 val = REG_READ(ah, AR_SREV); 350 ah->hw_version.macVersion = 351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 353 354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 355 ah->is_pciexpress = true; 356 else 357 ah->is_pciexpress = (val & 358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 359 } else { 360 if (!AR_SREV_9100(ah)) 361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 362 363 ah->hw_version.macRev = val & AR_SREV_REVISION; 364 365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 366 ah->is_pciexpress = true; 367 } 368 } 369 370 /************************************/ 371 /* HW Attach, Detach, Init Routines */ 372 /************************************/ 373 374 static void ath9k_hw_disablepcie(struct ath_hw *ah) 375 { 376 if (!AR_SREV_5416(ah)) 377 return; 378 379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 388 389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 390 } 391 392 /* This should work for all families including legacy */ 393 static bool ath9k_hw_chip_test(struct ath_hw *ah) 394 { 395 struct ath_common *common = ath9k_hw_common(ah); 396 u32 regAddr[2] = { AR_STA_ID0 }; 397 u32 regHold[2]; 398 static const u32 patternData[4] = { 399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 400 }; 401 int i, j, loop_max; 402 403 if (!AR_SREV_9300_20_OR_LATER(ah)) { 404 loop_max = 2; 405 regAddr[1] = AR_PHY_BASE + (8 << 2); 406 } else 407 loop_max = 1; 408 409 for (i = 0; i < loop_max; i++) { 410 u32 addr = regAddr[i]; 411 u32 wrData, rdData; 412 413 regHold[i] = REG_READ(ah, addr); 414 for (j = 0; j < 0x100; j++) { 415 wrData = (j << 16) | j; 416 REG_WRITE(ah, addr, wrData); 417 rdData = REG_READ(ah, addr); 418 if (rdData != wrData) { 419 ath_err(common, 420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 421 addr, wrData, rdData); 422 return false; 423 } 424 } 425 for (j = 0; j < 4; j++) { 426 wrData = patternData[j]; 427 REG_WRITE(ah, addr, wrData); 428 rdData = REG_READ(ah, addr); 429 if (wrData != rdData) { 430 ath_err(common, 431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 432 addr, wrData, rdData); 433 return false; 434 } 435 } 436 REG_WRITE(ah, regAddr[i], regHold[i]); 437 } 438 udelay(100); 439 440 return true; 441 } 442 443 static void ath9k_hw_init_config(struct ath_hw *ah) 444 { 445 int i; 446 447 ah->config.dma_beacon_response_time = 1; 448 ah->config.sw_beacon_response_time = 6; 449 ah->config.additional_swba_backoff = 0; 450 ah->config.ack_6mb = 0x0; 451 ah->config.cwm_ignore_extcca = 0; 452 ah->config.pcie_clock_req = 0; 453 ah->config.pcie_waen = 0; 454 ah->config.analog_shiftreg = 1; 455 ah->config.enable_ani = true; 456 457 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 458 ah->config.spurchans[i][0] = AR_NO_SPUR; 459 ah->config.spurchans[i][1] = AR_NO_SPUR; 460 } 461 462 ah->config.rx_intr_mitigation = true; 463 ah->config.pcieSerDesWrite = true; 464 465 /* 466 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 467 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 468 * This means we use it for all AR5416 devices, and the few 469 * minor PCI AR9280 devices out there. 470 * 471 * Serialization is required because these devices do not handle 472 * well the case of two concurrent reads/writes due to the latency 473 * involved. During one read/write another read/write can be issued 474 * on another CPU while the previous read/write may still be working 475 * on our hardware, if we hit this case the hardware poops in a loop. 476 * We prevent this by serializing reads and writes. 477 * 478 * This issue is not present on PCI-Express devices or pre-AR5416 479 * devices (legacy, 802.11abg). 480 */ 481 if (num_possible_cpus() > 1) 482 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 483 } 484 485 static void ath9k_hw_init_defaults(struct ath_hw *ah) 486 { 487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 488 489 regulatory->country_code = CTRY_DEFAULT; 490 regulatory->power_limit = MAX_RATE_POWER; 491 492 ah->hw_version.magic = AR5416_MAGIC; 493 ah->hw_version.subvendorid = 0; 494 495 ah->atim_window = 0; 496 ah->sta_id1_defaults = 497 AR_STA_ID1_CRPT_MIC_ENABLE | 498 AR_STA_ID1_MCAST_KSRCH; 499 if (AR_SREV_9100(ah)) 500 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 501 ah->slottime = ATH9K_SLOT_TIME_9; 502 ah->globaltxtimeout = (u32) -1; 503 ah->power_mode = ATH9K_PM_UNDEFINED; 504 ah->htc_reset_init = true; 505 } 506 507 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 508 { 509 struct ath_common *common = ath9k_hw_common(ah); 510 u32 sum; 511 int i; 512 u16 eeval; 513 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 514 515 sum = 0; 516 for (i = 0; i < 3; i++) { 517 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 518 sum += eeval; 519 common->macaddr[2 * i] = eeval >> 8; 520 common->macaddr[2 * i + 1] = eeval & 0xff; 521 } 522 if (sum == 0 || sum == 0xffff * 3) 523 return -EADDRNOTAVAIL; 524 525 return 0; 526 } 527 528 static int ath9k_hw_post_init(struct ath_hw *ah) 529 { 530 struct ath_common *common = ath9k_hw_common(ah); 531 int ecode; 532 533 if (common->bus_ops->ath_bus_type != ATH_USB) { 534 if (!ath9k_hw_chip_test(ah)) 535 return -ENODEV; 536 } 537 538 if (!AR_SREV_9300_20_OR_LATER(ah)) { 539 ecode = ar9002_hw_rf_claim(ah); 540 if (ecode != 0) 541 return ecode; 542 } 543 544 ecode = ath9k_hw_eeprom_init(ah); 545 if (ecode != 0) 546 return ecode; 547 548 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 549 ah->eep_ops->get_eeprom_ver(ah), 550 ah->eep_ops->get_eeprom_rev(ah)); 551 552 if (ah->config.enable_ani) 553 ath9k_hw_ani_init(ah); 554 555 return 0; 556 } 557 558 static int ath9k_hw_attach_ops(struct ath_hw *ah) 559 { 560 if (!AR_SREV_9300_20_OR_LATER(ah)) 561 return ar9002_hw_attach_ops(ah); 562 563 ar9003_hw_attach_ops(ah); 564 return 0; 565 } 566 567 /* Called for all hardware families */ 568 static int __ath9k_hw_init(struct ath_hw *ah) 569 { 570 struct ath_common *common = ath9k_hw_common(ah); 571 int r = 0; 572 573 ath9k_hw_read_revisions(ah); 574 575 /* 576 * Read back AR_WA into a permanent copy and set bits 14 and 17. 577 * We need to do this to avoid RMW of this register. We cannot 578 * read the reg when chip is asleep. 579 */ 580 ah->WARegVal = REG_READ(ah, AR_WA); 581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 582 AR_WA_ASPM_TIMER_BASED_DISABLE); 583 584 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 585 ath_err(common, "Couldn't reset chip\n"); 586 return -EIO; 587 } 588 589 if (AR_SREV_9462(ah)) 590 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 591 592 if (AR_SREV_9565(ah)) { 593 ah->WARegVal |= AR_WA_BIT22; 594 REG_WRITE(ah, AR_WA, ah->WARegVal); 595 } 596 597 ath9k_hw_init_defaults(ah); 598 ath9k_hw_init_config(ah); 599 600 r = ath9k_hw_attach_ops(ah); 601 if (r) 602 return r; 603 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 605 ath_err(common, "Couldn't wakeup chip\n"); 606 return -EIO; 607 } 608 609 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 610 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 611 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 612 !ah->is_pciexpress)) { 613 ah->config.serialize_regmode = 614 SER_REG_MODE_ON; 615 } else { 616 ah->config.serialize_regmode = 617 SER_REG_MODE_OFF; 618 } 619 } 620 621 ath_dbg(common, RESET, "serialize_regmode is %d\n", 622 ah->config.serialize_regmode); 623 624 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 625 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 626 else 627 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 628 629 switch (ah->hw_version.macVersion) { 630 case AR_SREV_VERSION_5416_PCI: 631 case AR_SREV_VERSION_5416_PCIE: 632 case AR_SREV_VERSION_9160: 633 case AR_SREV_VERSION_9100: 634 case AR_SREV_VERSION_9280: 635 case AR_SREV_VERSION_9285: 636 case AR_SREV_VERSION_9287: 637 case AR_SREV_VERSION_9271: 638 case AR_SREV_VERSION_9300: 639 case AR_SREV_VERSION_9330: 640 case AR_SREV_VERSION_9485: 641 case AR_SREV_VERSION_9340: 642 case AR_SREV_VERSION_9462: 643 case AR_SREV_VERSION_9550: 644 case AR_SREV_VERSION_9565: 645 break; 646 default: 647 ath_err(common, 648 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 649 ah->hw_version.macVersion, ah->hw_version.macRev); 650 return -EOPNOTSUPP; 651 } 652 653 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 654 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 655 ah->is_pciexpress = false; 656 657 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 658 ath9k_hw_init_cal_settings(ah); 659 660 ah->ani_function = ATH9K_ANI_ALL; 661 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 662 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 663 if (!AR_SREV_9300_20_OR_LATER(ah)) 664 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 665 666 if (!ah->is_pciexpress) 667 ath9k_hw_disablepcie(ah); 668 669 r = ath9k_hw_post_init(ah); 670 if (r) 671 return r; 672 673 ath9k_hw_init_mode_gain_regs(ah); 674 r = ath9k_hw_fill_cap_info(ah); 675 if (r) 676 return r; 677 678 r = ath9k_hw_init_macaddr(ah); 679 if (r) { 680 ath_err(common, "Failed to initialize MAC address\n"); 681 return r; 682 } 683 684 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 685 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 686 else 687 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 688 689 if (AR_SREV_9330(ah)) 690 ah->bb_watchdog_timeout_ms = 85; 691 else 692 ah->bb_watchdog_timeout_ms = 25; 693 694 common->state = ATH_HW_INITIALIZED; 695 696 return 0; 697 } 698 699 int ath9k_hw_init(struct ath_hw *ah) 700 { 701 int ret; 702 struct ath_common *common = ath9k_hw_common(ah); 703 704 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 705 switch (ah->hw_version.devid) { 706 case AR5416_DEVID_PCI: 707 case AR5416_DEVID_PCIE: 708 case AR5416_AR9100_DEVID: 709 case AR9160_DEVID_PCI: 710 case AR9280_DEVID_PCI: 711 case AR9280_DEVID_PCIE: 712 case AR9285_DEVID_PCIE: 713 case AR9287_DEVID_PCI: 714 case AR9287_DEVID_PCIE: 715 case AR2427_DEVID_PCIE: 716 case AR9300_DEVID_PCIE: 717 case AR9300_DEVID_AR9485_PCIE: 718 case AR9300_DEVID_AR9330: 719 case AR9300_DEVID_AR9340: 720 case AR9300_DEVID_QCA955X: 721 case AR9300_DEVID_AR9580: 722 case AR9300_DEVID_AR9462: 723 case AR9485_DEVID_AR1111: 724 case AR9300_DEVID_AR9565: 725 break; 726 default: 727 if (common->bus_ops->ath_bus_type == ATH_USB) 728 break; 729 ath_err(common, "Hardware device ID 0x%04x not supported\n", 730 ah->hw_version.devid); 731 return -EOPNOTSUPP; 732 } 733 734 ret = __ath9k_hw_init(ah); 735 if (ret) { 736 ath_err(common, 737 "Unable to initialize hardware; initialization status: %d\n", 738 ret); 739 return ret; 740 } 741 742 return 0; 743 } 744 EXPORT_SYMBOL(ath9k_hw_init); 745 746 static void ath9k_hw_init_qos(struct ath_hw *ah) 747 { 748 ENABLE_REGWRITE_BUFFER(ah); 749 750 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 751 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 752 753 REG_WRITE(ah, AR_QOS_NO_ACK, 754 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 755 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 756 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 757 758 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 759 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 760 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 761 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 762 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 763 764 REGWRITE_BUFFER_FLUSH(ah); 765 } 766 767 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 768 { 769 struct ath_common *common = ath9k_hw_common(ah); 770 int i = 0; 771 772 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 773 udelay(100); 774 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 775 776 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 777 778 udelay(100); 779 780 if (WARN_ON_ONCE(i >= 100)) { 781 ath_err(common, "PLL4 meaurement not done\n"); 782 break; 783 } 784 785 i++; 786 } 787 788 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 789 } 790 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 791 792 static void ath9k_hw_init_pll(struct ath_hw *ah, 793 struct ath9k_channel *chan) 794 { 795 u32 pll; 796 797 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 798 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 800 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 802 AR_CH0_DPLL2_KD, 0x40); 803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 804 AR_CH0_DPLL2_KI, 0x4); 805 806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 807 AR_CH0_BB_DPLL1_REFDIV, 0x5); 808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 809 AR_CH0_BB_DPLL1_NINI, 0x58); 810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 811 AR_CH0_BB_DPLL1_NFRAC, 0x0); 812 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 814 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 816 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 818 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 819 820 /* program BB PLL phase_shift to 0x6 */ 821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 822 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 823 824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 825 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 826 udelay(1000); 827 } else if (AR_SREV_9330(ah)) { 828 u32 ddr_dpll2, pll_control2, kd; 829 830 if (ah->is_clk_25mhz) { 831 ddr_dpll2 = 0x18e82f01; 832 pll_control2 = 0xe04a3d; 833 kd = 0x1d; 834 } else { 835 ddr_dpll2 = 0x19e82f01; 836 pll_control2 = 0x886666; 837 kd = 0x3d; 838 } 839 840 /* program DDR PLL ki and kd value */ 841 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 842 843 /* program DDR PLL phase_shift */ 844 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 845 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 846 847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 848 udelay(1000); 849 850 /* program refdiv, nint, frac to RTC register */ 851 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 852 853 /* program BB PLL kd and ki value */ 854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 856 857 /* program BB PLL phase_shift */ 858 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 859 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 860 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 861 u32 regval, pll2_divint, pll2_divfrac, refdiv; 862 863 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 864 udelay(1000); 865 866 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 867 udelay(100); 868 869 if (ah->is_clk_25mhz) { 870 pll2_divint = 0x54; 871 pll2_divfrac = 0x1eb85; 872 refdiv = 3; 873 } else { 874 if (AR_SREV_9340(ah)) { 875 pll2_divint = 88; 876 pll2_divfrac = 0; 877 refdiv = 5; 878 } else { 879 pll2_divint = 0x11; 880 pll2_divfrac = 0x26666; 881 refdiv = 1; 882 } 883 } 884 885 regval = REG_READ(ah, AR_PHY_PLL_MODE); 886 regval |= (0x1 << 16); 887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 888 udelay(100); 889 890 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 891 (pll2_divint << 18) | pll2_divfrac); 892 udelay(100); 893 894 regval = REG_READ(ah, AR_PHY_PLL_MODE); 895 if (AR_SREV_9340(ah)) 896 regval = (regval & 0x80071fff) | (0x1 << 30) | 897 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 898 else 899 regval = (regval & 0x80071fff) | (0x3 << 30) | 900 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 902 REG_WRITE(ah, AR_PHY_PLL_MODE, 903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 904 udelay(1000); 905 } 906 907 pll = ath9k_hw_compute_pll_control(ah, chan); 908 if (AR_SREV_9565(ah)) 909 pll |= 0x40000; 910 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 911 912 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 913 AR_SREV_9550(ah)) 914 udelay(1000); 915 916 /* Switch the core clock for ar9271 to 117Mhz */ 917 if (AR_SREV_9271(ah)) { 918 udelay(500); 919 REG_WRITE(ah, 0x50040, 0x304); 920 } 921 922 udelay(RTC_PLL_SETTLE_DELAY); 923 924 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 925 926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 927 if (ah->is_clk_25mhz) { 928 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 929 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 930 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 931 } else { 932 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 933 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 934 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 935 } 936 udelay(100); 937 } 938 } 939 940 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 941 enum nl80211_iftype opmode) 942 { 943 u32 sync_default = AR_INTR_SYNC_DEFAULT; 944 u32 imr_reg = AR_IMR_TXERR | 945 AR_IMR_TXURN | 946 AR_IMR_RXERR | 947 AR_IMR_RXORN | 948 AR_IMR_BCNMISC; 949 950 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 951 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 952 953 if (AR_SREV_9300_20_OR_LATER(ah)) { 954 imr_reg |= AR_IMR_RXOK_HP; 955 if (ah->config.rx_intr_mitigation) 956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 957 else 958 imr_reg |= AR_IMR_RXOK_LP; 959 960 } else { 961 if (ah->config.rx_intr_mitigation) 962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 963 else 964 imr_reg |= AR_IMR_RXOK; 965 } 966 967 if (ah->config.tx_intr_mitigation) 968 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 969 else 970 imr_reg |= AR_IMR_TXOK; 971 972 ENABLE_REGWRITE_BUFFER(ah); 973 974 REG_WRITE(ah, AR_IMR, imr_reg); 975 ah->imrs2_reg |= AR_IMR_S2_GTT; 976 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 977 978 if (!AR_SREV_9100(ah)) { 979 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 980 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 981 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 982 } 983 984 REGWRITE_BUFFER_FLUSH(ah); 985 986 if (AR_SREV_9300_20_OR_LATER(ah)) { 987 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 989 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 991 } 992 } 993 994 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 995 { 996 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 997 val = min(val, (u32) 0xFFFF); 998 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 999 } 1000 1001 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1002 { 1003 u32 val = ath9k_hw_mac_to_clks(ah, us); 1004 val = min(val, (u32) 0xFFFF); 1005 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1006 } 1007 1008 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1009 { 1010 u32 val = ath9k_hw_mac_to_clks(ah, us); 1011 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1012 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1013 } 1014 1015 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1016 { 1017 u32 val = ath9k_hw_mac_to_clks(ah, us); 1018 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1019 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1020 } 1021 1022 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1023 { 1024 if (tu > 0xFFFF) { 1025 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1026 tu); 1027 ah->globaltxtimeout = (u32) -1; 1028 return false; 1029 } else { 1030 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1031 ah->globaltxtimeout = tu; 1032 return true; 1033 } 1034 } 1035 1036 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1037 { 1038 struct ath_common *common = ath9k_hw_common(ah); 1039 struct ieee80211_conf *conf = &common->hw->conf; 1040 const struct ath9k_channel *chan = ah->curchan; 1041 int acktimeout, ctstimeout, ack_offset = 0; 1042 int slottime; 1043 int sifstime; 1044 int rx_lat = 0, tx_lat = 0, eifs = 0; 1045 u32 reg; 1046 1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1048 ah->misc_mode); 1049 1050 if (!chan) 1051 return; 1052 1053 if (ah->misc_mode != 0) 1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1055 1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1057 rx_lat = 41; 1058 else 1059 rx_lat = 37; 1060 tx_lat = 54; 1061 1062 if (IS_CHAN_5GHZ(chan)) 1063 sifstime = 16; 1064 else 1065 sifstime = 10; 1066 1067 if (IS_CHAN_HALF_RATE(chan)) { 1068 eifs = 175; 1069 rx_lat *= 2; 1070 tx_lat *= 2; 1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1072 tx_lat += 11; 1073 1074 sifstime *= 2; 1075 ack_offset = 16; 1076 slottime = 13; 1077 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1078 eifs = 340; 1079 rx_lat = (rx_lat * 4) - 1; 1080 tx_lat *= 4; 1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1082 tx_lat += 22; 1083 1084 sifstime *= 4; 1085 ack_offset = 32; 1086 slottime = 21; 1087 } else { 1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1090 reg = AR_USEC_ASYNC_FIFO; 1091 } else { 1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1093 common->clockrate; 1094 reg = REG_READ(ah, AR_USEC); 1095 } 1096 rx_lat = MS(reg, AR_USEC_RX_LAT); 1097 tx_lat = MS(reg, AR_USEC_TX_LAT); 1098 1099 slottime = ah->slottime; 1100 } 1101 1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1103 slottime += 3 * ah->coverage_class; 1104 acktimeout = slottime + sifstime + ack_offset; 1105 ctstimeout = acktimeout; 1106 1107 /* 1108 * Workaround for early ACK timeouts, add an offset to match the 1109 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1110 * This was initially only meant to work around an issue with delayed 1111 * BA frames in some implementations, but it has been found to fix ACK 1112 * timeout issues in other cases as well. 1113 */ 1114 if (conf->chandef.chan && 1115 conf->chandef.chan->band == IEEE80211_BAND_2GHZ && 1116 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1117 acktimeout += 64 - sifstime - ah->slottime; 1118 ctstimeout += 48 - sifstime - ah->slottime; 1119 } 1120 1121 1122 ath9k_hw_set_sifs_time(ah, sifstime); 1123 ath9k_hw_setslottime(ah, slottime); 1124 ath9k_hw_set_ack_timeout(ah, acktimeout); 1125 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1126 if (ah->globaltxtimeout != (u32) -1) 1127 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1128 1129 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1130 REG_RMW(ah, AR_USEC, 1131 (common->clockrate - 1) | 1132 SM(rx_lat, AR_USEC_RX_LAT) | 1133 SM(tx_lat, AR_USEC_TX_LAT), 1134 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1135 1136 } 1137 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1138 1139 void ath9k_hw_deinit(struct ath_hw *ah) 1140 { 1141 struct ath_common *common = ath9k_hw_common(ah); 1142 1143 if (common->state < ATH_HW_INITIALIZED) 1144 return; 1145 1146 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1147 } 1148 EXPORT_SYMBOL(ath9k_hw_deinit); 1149 1150 /*******/ 1151 /* INI */ 1152 /*******/ 1153 1154 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1155 { 1156 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1157 1158 if (IS_CHAN_B(chan)) 1159 ctl |= CTL_11B; 1160 else if (IS_CHAN_G(chan)) 1161 ctl |= CTL_11G; 1162 else 1163 ctl |= CTL_11A; 1164 1165 return ctl; 1166 } 1167 1168 /****************************************/ 1169 /* Reset and Channel Switching Routines */ 1170 /****************************************/ 1171 1172 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1173 { 1174 struct ath_common *common = ath9k_hw_common(ah); 1175 int txbuf_size; 1176 1177 ENABLE_REGWRITE_BUFFER(ah); 1178 1179 /* 1180 * set AHB_MODE not to do cacheline prefetches 1181 */ 1182 if (!AR_SREV_9300_20_OR_LATER(ah)) 1183 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1184 1185 /* 1186 * let mac dma reads be in 128 byte chunks 1187 */ 1188 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1189 1190 REGWRITE_BUFFER_FLUSH(ah); 1191 1192 /* 1193 * Restore TX Trigger Level to its pre-reset value. 1194 * The initial value depends on whether aggregation is enabled, and is 1195 * adjusted whenever underruns are detected. 1196 */ 1197 if (!AR_SREV_9300_20_OR_LATER(ah)) 1198 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1199 1200 ENABLE_REGWRITE_BUFFER(ah); 1201 1202 /* 1203 * let mac dma writes be in 128 byte chunks 1204 */ 1205 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1206 1207 /* 1208 * Setup receive FIFO threshold to hold off TX activities 1209 */ 1210 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1211 1212 if (AR_SREV_9300_20_OR_LATER(ah)) { 1213 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1214 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1215 1216 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1217 ah->caps.rx_status_len); 1218 } 1219 1220 /* 1221 * reduce the number of usable entries in PCU TXBUF to avoid 1222 * wrap around issues. 1223 */ 1224 if (AR_SREV_9285(ah)) { 1225 /* For AR9285 the number of Fifos are reduced to half. 1226 * So set the usable tx buf size also to half to 1227 * avoid data/delimiter underruns 1228 */ 1229 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1230 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1231 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1232 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1233 } else { 1234 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1235 } 1236 1237 if (!AR_SREV_9271(ah)) 1238 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1239 1240 REGWRITE_BUFFER_FLUSH(ah); 1241 1242 if (AR_SREV_9300_20_OR_LATER(ah)) 1243 ath9k_hw_reset_txstatus_ring(ah); 1244 } 1245 1246 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1247 { 1248 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1249 u32 set = AR_STA_ID1_KSRCH_MODE; 1250 1251 switch (opmode) { 1252 case NL80211_IFTYPE_ADHOC: 1253 case NL80211_IFTYPE_MESH_POINT: 1254 set |= AR_STA_ID1_ADHOC; 1255 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1256 break; 1257 case NL80211_IFTYPE_AP: 1258 set |= AR_STA_ID1_STA_AP; 1259 /* fall through */ 1260 case NL80211_IFTYPE_STATION: 1261 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1262 break; 1263 default: 1264 if (!ah->is_monitoring) 1265 set = 0; 1266 break; 1267 } 1268 REG_RMW(ah, AR_STA_ID1, set, mask); 1269 } 1270 1271 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1272 u32 *coef_mantissa, u32 *coef_exponent) 1273 { 1274 u32 coef_exp, coef_man; 1275 1276 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1277 if ((coef_scaled >> coef_exp) & 0x1) 1278 break; 1279 1280 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1281 1282 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1283 1284 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1285 *coef_exponent = coef_exp - 16; 1286 } 1287 1288 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1289 { 1290 u32 rst_flags; 1291 u32 tmpReg; 1292 1293 if (AR_SREV_9100(ah)) { 1294 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1295 AR_RTC_DERIVED_CLK_PERIOD, 1); 1296 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1297 } 1298 1299 ENABLE_REGWRITE_BUFFER(ah); 1300 1301 if (AR_SREV_9300_20_OR_LATER(ah)) { 1302 REG_WRITE(ah, AR_WA, ah->WARegVal); 1303 udelay(10); 1304 } 1305 1306 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1307 AR_RTC_FORCE_WAKE_ON_INT); 1308 1309 if (AR_SREV_9100(ah)) { 1310 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1311 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1312 } else { 1313 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1314 if (AR_SREV_9340(ah)) 1315 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1316 else 1317 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1318 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1319 1320 if (tmpReg) { 1321 u32 val; 1322 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1323 1324 val = AR_RC_HOSTIF; 1325 if (!AR_SREV_9300_20_OR_LATER(ah)) 1326 val |= AR_RC_AHB; 1327 REG_WRITE(ah, AR_RC, val); 1328 1329 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1330 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1331 1332 rst_flags = AR_RTC_RC_MAC_WARM; 1333 if (type == ATH9K_RESET_COLD) 1334 rst_flags |= AR_RTC_RC_MAC_COLD; 1335 } 1336 1337 if (AR_SREV_9330(ah)) { 1338 int npend = 0; 1339 int i; 1340 1341 /* AR9330 WAR: 1342 * call external reset function to reset WMAC if: 1343 * - doing a cold reset 1344 * - we have pending frames in the TX queues 1345 */ 1346 1347 for (i = 0; i < AR_NUM_QCU; i++) { 1348 npend = ath9k_hw_numtxpending(ah, i); 1349 if (npend) 1350 break; 1351 } 1352 1353 if (ah->external_reset && 1354 (npend || type == ATH9K_RESET_COLD)) { 1355 int reset_err = 0; 1356 1357 ath_dbg(ath9k_hw_common(ah), RESET, 1358 "reset MAC via external reset\n"); 1359 1360 reset_err = ah->external_reset(); 1361 if (reset_err) { 1362 ath_err(ath9k_hw_common(ah), 1363 "External reset failed, err=%d\n", 1364 reset_err); 1365 return false; 1366 } 1367 1368 REG_WRITE(ah, AR_RTC_RESET, 1); 1369 } 1370 } 1371 1372 if (ath9k_hw_mci_is_enabled(ah)) 1373 ar9003_mci_check_gpm_offset(ah); 1374 1375 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1376 1377 REGWRITE_BUFFER_FLUSH(ah); 1378 1379 udelay(50); 1380 1381 REG_WRITE(ah, AR_RTC_RC, 0); 1382 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1383 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1384 return false; 1385 } 1386 1387 if (!AR_SREV_9100(ah)) 1388 REG_WRITE(ah, AR_RC, 0); 1389 1390 if (AR_SREV_9100(ah)) 1391 udelay(50); 1392 1393 return true; 1394 } 1395 1396 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1397 { 1398 ENABLE_REGWRITE_BUFFER(ah); 1399 1400 if (AR_SREV_9300_20_OR_LATER(ah)) { 1401 REG_WRITE(ah, AR_WA, ah->WARegVal); 1402 udelay(10); 1403 } 1404 1405 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1406 AR_RTC_FORCE_WAKE_ON_INT); 1407 1408 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1409 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1410 1411 REG_WRITE(ah, AR_RTC_RESET, 0); 1412 1413 REGWRITE_BUFFER_FLUSH(ah); 1414 1415 if (!AR_SREV_9300_20_OR_LATER(ah)) 1416 udelay(2); 1417 1418 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1419 REG_WRITE(ah, AR_RC, 0); 1420 1421 REG_WRITE(ah, AR_RTC_RESET, 1); 1422 1423 if (!ath9k_hw_wait(ah, 1424 AR_RTC_STATUS, 1425 AR_RTC_STATUS_M, 1426 AR_RTC_STATUS_ON, 1427 AH_WAIT_TIMEOUT)) { 1428 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1429 return false; 1430 } 1431 1432 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1433 } 1434 1435 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1436 { 1437 bool ret = false; 1438 1439 if (AR_SREV_9300_20_OR_LATER(ah)) { 1440 REG_WRITE(ah, AR_WA, ah->WARegVal); 1441 udelay(10); 1442 } 1443 1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1445 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1446 1447 if (!ah->reset_power_on) 1448 type = ATH9K_RESET_POWER_ON; 1449 1450 switch (type) { 1451 case ATH9K_RESET_POWER_ON: 1452 ret = ath9k_hw_set_reset_power_on(ah); 1453 if (ret) 1454 ah->reset_power_on = true; 1455 break; 1456 case ATH9K_RESET_WARM: 1457 case ATH9K_RESET_COLD: 1458 ret = ath9k_hw_set_reset(ah, type); 1459 break; 1460 default: 1461 break; 1462 } 1463 1464 return ret; 1465 } 1466 1467 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1468 struct ath9k_channel *chan) 1469 { 1470 int reset_type = ATH9K_RESET_WARM; 1471 1472 if (AR_SREV_9280(ah)) { 1473 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1474 reset_type = ATH9K_RESET_POWER_ON; 1475 else 1476 reset_type = ATH9K_RESET_COLD; 1477 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1478 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1479 reset_type = ATH9K_RESET_COLD; 1480 1481 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1482 return false; 1483 1484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1485 return false; 1486 1487 ah->chip_fullsleep = false; 1488 1489 if (AR_SREV_9330(ah)) 1490 ar9003_hw_internal_regulator_apply(ah); 1491 ath9k_hw_init_pll(ah, chan); 1492 ath9k_hw_set_rfmode(ah, chan); 1493 1494 return true; 1495 } 1496 1497 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1498 struct ath9k_channel *chan) 1499 { 1500 struct ath_common *common = ath9k_hw_common(ah); 1501 u32 qnum; 1502 int r; 1503 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1504 bool band_switch, mode_diff; 1505 u8 ini_reloaded; 1506 1507 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1508 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1509 CHANNEL_5GHZ)); 1510 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1511 1512 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1513 if (ath9k_hw_numtxpending(ah, qnum)) { 1514 ath_dbg(common, QUEUE, 1515 "Transmit frames pending on queue %d\n", qnum); 1516 return false; 1517 } 1518 } 1519 1520 if (!ath9k_hw_rfbus_req(ah)) { 1521 ath_err(common, "Could not kill baseband RX\n"); 1522 return false; 1523 } 1524 1525 if (edma && (band_switch || mode_diff)) { 1526 ath9k_hw_mark_phy_inactive(ah); 1527 udelay(5); 1528 1529 ath9k_hw_init_pll(ah, NULL); 1530 1531 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1532 ath_err(common, "Failed to do fast channel change\n"); 1533 return false; 1534 } 1535 } 1536 1537 ath9k_hw_set_channel_regs(ah, chan); 1538 1539 r = ath9k_hw_rf_set_freq(ah, chan); 1540 if (r) { 1541 ath_err(common, "Failed to set channel\n"); 1542 return false; 1543 } 1544 ath9k_hw_set_clockrate(ah); 1545 ath9k_hw_apply_txpower(ah, chan, false); 1546 ath9k_hw_rfbus_done(ah); 1547 1548 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1549 ath9k_hw_set_delta_slope(ah, chan); 1550 1551 ath9k_hw_spur_mitigate_freq(ah, chan); 1552 1553 if (edma && (band_switch || mode_diff)) { 1554 ah->ah_flags |= AH_FASTCC; 1555 if (band_switch || ini_reloaded) 1556 ah->eep_ops->set_board_values(ah, chan); 1557 1558 ath9k_hw_init_bb(ah, chan); 1559 1560 if (band_switch || ini_reloaded) 1561 ath9k_hw_init_cal(ah, chan); 1562 ah->ah_flags &= ~AH_FASTCC; 1563 } 1564 1565 return true; 1566 } 1567 1568 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1569 { 1570 u32 gpio_mask = ah->gpio_mask; 1571 int i; 1572 1573 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1574 if (!(gpio_mask & 1)) 1575 continue; 1576 1577 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1578 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1579 } 1580 } 1581 1582 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1583 int *hang_state, int *hang_pos) 1584 { 1585 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1586 u32 chain_state, dcs_pos, i; 1587 1588 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1589 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1590 for (i = 0; i < 3; i++) { 1591 if (chain_state == dcu_chain_state[i]) { 1592 *hang_state = chain_state; 1593 *hang_pos = dcs_pos; 1594 return true; 1595 } 1596 } 1597 } 1598 return false; 1599 } 1600 1601 #define DCU_COMPLETE_STATE 1 1602 #define DCU_COMPLETE_STATE_MASK 0x3 1603 #define NUM_STATUS_READS 50 1604 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1605 { 1606 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1607 u32 i, hang_pos, hang_state, num_state = 6; 1608 1609 comp_state = REG_READ(ah, AR_DMADBG_6); 1610 1611 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1612 ath_dbg(ath9k_hw_common(ah), RESET, 1613 "MAC Hang signature not found at DCU complete\n"); 1614 return false; 1615 } 1616 1617 chain_state = REG_READ(ah, dcs_reg); 1618 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1619 goto hang_check_iter; 1620 1621 dcs_reg = AR_DMADBG_5; 1622 num_state = 4; 1623 chain_state = REG_READ(ah, dcs_reg); 1624 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1625 goto hang_check_iter; 1626 1627 ath_dbg(ath9k_hw_common(ah), RESET, 1628 "MAC Hang signature 1 not found\n"); 1629 return false; 1630 1631 hang_check_iter: 1632 ath_dbg(ath9k_hw_common(ah), RESET, 1633 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1634 chain_state, comp_state, hang_state, hang_pos); 1635 1636 for (i = 0; i < NUM_STATUS_READS; i++) { 1637 chain_state = REG_READ(ah, dcs_reg); 1638 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1639 comp_state = REG_READ(ah, AR_DMADBG_6); 1640 1641 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1642 DCU_COMPLETE_STATE) || 1643 (chain_state != hang_state)) 1644 return false; 1645 } 1646 1647 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1648 1649 return true; 1650 } 1651 1652 bool ath9k_hw_check_alive(struct ath_hw *ah) 1653 { 1654 int count = 50; 1655 u32 reg; 1656 1657 if (AR_SREV_9300(ah)) 1658 return !ath9k_hw_detect_mac_hang(ah); 1659 1660 if (AR_SREV_9285_12_OR_LATER(ah)) 1661 return true; 1662 1663 do { 1664 reg = REG_READ(ah, AR_OBS_BUS_1); 1665 1666 if ((reg & 0x7E7FFFEF) == 0x00702400) 1667 continue; 1668 1669 switch (reg & 0x7E000B00) { 1670 case 0x1E000000: 1671 case 0x52000B00: 1672 case 0x18000B00: 1673 continue; 1674 default: 1675 return true; 1676 } 1677 } while (count-- > 0); 1678 1679 return false; 1680 } 1681 EXPORT_SYMBOL(ath9k_hw_check_alive); 1682 1683 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1684 { 1685 /* Setup MFP options for CCMP */ 1686 if (AR_SREV_9280_20_OR_LATER(ah)) { 1687 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1688 * frames when constructing CCMP AAD. */ 1689 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1690 0xc7ff); 1691 ah->sw_mgmt_crypto = false; 1692 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1693 /* Disable hardware crypto for management frames */ 1694 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1695 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1696 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1697 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1698 ah->sw_mgmt_crypto = true; 1699 } else { 1700 ah->sw_mgmt_crypto = true; 1701 } 1702 } 1703 1704 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1705 u32 macStaId1, u32 saveDefAntenna) 1706 { 1707 struct ath_common *common = ath9k_hw_common(ah); 1708 1709 ENABLE_REGWRITE_BUFFER(ah); 1710 1711 REG_RMW(ah, AR_STA_ID1, macStaId1 1712 | AR_STA_ID1_RTS_USE_DEF 1713 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1714 | ah->sta_id1_defaults, 1715 ~AR_STA_ID1_SADH_MASK); 1716 ath_hw_setbssidmask(common); 1717 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1718 ath9k_hw_write_associd(ah); 1719 REG_WRITE(ah, AR_ISR, ~0); 1720 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1721 1722 REGWRITE_BUFFER_FLUSH(ah); 1723 1724 ath9k_hw_set_operating_mode(ah, ah->opmode); 1725 } 1726 1727 static void ath9k_hw_init_queues(struct ath_hw *ah) 1728 { 1729 int i; 1730 1731 ENABLE_REGWRITE_BUFFER(ah); 1732 1733 for (i = 0; i < AR_NUM_DCU; i++) 1734 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1735 1736 REGWRITE_BUFFER_FLUSH(ah); 1737 1738 ah->intr_txqs = 0; 1739 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1740 ath9k_hw_resettxqueue(ah, i); 1741 } 1742 1743 /* 1744 * For big endian systems turn on swapping for descriptors 1745 */ 1746 static void ath9k_hw_init_desc(struct ath_hw *ah) 1747 { 1748 struct ath_common *common = ath9k_hw_common(ah); 1749 1750 if (AR_SREV_9100(ah)) { 1751 u32 mask; 1752 mask = REG_READ(ah, AR_CFG); 1753 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1754 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1755 mask); 1756 } else { 1757 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1758 REG_WRITE(ah, AR_CFG, mask); 1759 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1760 REG_READ(ah, AR_CFG)); 1761 } 1762 } else { 1763 if (common->bus_ops->ath_bus_type == ATH_USB) { 1764 /* Configure AR9271 target WLAN */ 1765 if (AR_SREV_9271(ah)) 1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1767 else 1768 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1769 } 1770 #ifdef __BIG_ENDIAN 1771 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1772 AR_SREV_9550(ah)) 1773 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1774 else 1775 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1776 #endif 1777 } 1778 } 1779 1780 /* 1781 * Fast channel change: 1782 * (Change synthesizer based on channel freq without resetting chip) 1783 * 1784 * Don't do FCC when 1785 * - Flag is not set 1786 * - Chip is just coming out of full sleep 1787 * - Channel to be set is same as current channel 1788 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1789 */ 1790 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1791 { 1792 struct ath_common *common = ath9k_hw_common(ah); 1793 int ret; 1794 1795 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1796 goto fail; 1797 1798 if (ah->chip_fullsleep) 1799 goto fail; 1800 1801 if (!ah->curchan) 1802 goto fail; 1803 1804 if (chan->channel == ah->curchan->channel) 1805 goto fail; 1806 1807 if ((ah->curchan->channelFlags | chan->channelFlags) & 1808 (CHANNEL_HALF | CHANNEL_QUARTER)) 1809 goto fail; 1810 1811 if ((chan->channelFlags & CHANNEL_ALL) != 1812 (ah->curchan->channelFlags & CHANNEL_ALL)) 1813 goto fail; 1814 1815 if (!ath9k_hw_check_alive(ah)) 1816 goto fail; 1817 1818 /* 1819 * For AR9462, make sure that calibration data for 1820 * re-using are present. 1821 */ 1822 if (AR_SREV_9462(ah) && (ah->caldata && 1823 (!ah->caldata->done_txiqcal_once || 1824 !ah->caldata->done_txclcal_once || 1825 !ah->caldata->rtt_done))) 1826 goto fail; 1827 1828 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1829 ah->curchan->channel, chan->channel); 1830 1831 ret = ath9k_hw_channel_change(ah, chan); 1832 if (!ret) 1833 goto fail; 1834 1835 if (ath9k_hw_mci_is_enabled(ah)) 1836 ar9003_mci_2g5g_switch(ah, false); 1837 1838 ath9k_hw_loadnf(ah, ah->curchan); 1839 ath9k_hw_start_nfcal(ah, true); 1840 1841 if (AR_SREV_9271(ah)) 1842 ar9002_hw_load_ani_reg(ah, chan); 1843 1844 return 0; 1845 fail: 1846 return -EINVAL; 1847 } 1848 1849 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1850 struct ath9k_hw_cal_data *caldata, bool fastcc) 1851 { 1852 struct ath_common *common = ath9k_hw_common(ah); 1853 u32 saveLedState; 1854 u32 saveDefAntenna; 1855 u32 macStaId1; 1856 u64 tsf = 0; 1857 int r; 1858 bool start_mci_reset = false; 1859 bool save_fullsleep = ah->chip_fullsleep; 1860 1861 if (ath9k_hw_mci_is_enabled(ah)) { 1862 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1863 if (start_mci_reset) 1864 return 0; 1865 } 1866 1867 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1868 return -EIO; 1869 1870 if (ah->curchan && !ah->chip_fullsleep) 1871 ath9k_hw_getnf(ah, ah->curchan); 1872 1873 ah->caldata = caldata; 1874 if (caldata && (chan->channel != caldata->channel || 1875 chan->channelFlags != caldata->channelFlags)) { 1876 /* Operating channel changed, reset channel calibration data */ 1877 memset(caldata, 0, sizeof(*caldata)); 1878 ath9k_init_nfcal_hist_buffer(ah, chan); 1879 } else if (caldata) { 1880 caldata->paprd_packet_sent = false; 1881 } 1882 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1883 1884 if (fastcc) { 1885 r = ath9k_hw_do_fastcc(ah, chan); 1886 if (!r) 1887 return r; 1888 } 1889 1890 if (ath9k_hw_mci_is_enabled(ah)) 1891 ar9003_mci_stop_bt(ah, save_fullsleep); 1892 1893 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1894 if (saveDefAntenna == 0) 1895 saveDefAntenna = 1; 1896 1897 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1898 1899 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1900 if (AR_SREV_9100(ah) || 1901 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1902 tsf = ath9k_hw_gettsf64(ah); 1903 1904 saveLedState = REG_READ(ah, AR_CFG_LED) & 1905 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1906 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1907 1908 ath9k_hw_mark_phy_inactive(ah); 1909 1910 ah->paprd_table_write_done = false; 1911 1912 /* Only required on the first reset */ 1913 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1914 REG_WRITE(ah, 1915 AR9271_RESET_POWER_DOWN_CONTROL, 1916 AR9271_RADIO_RF_RST); 1917 udelay(50); 1918 } 1919 1920 if (!ath9k_hw_chip_reset(ah, chan)) { 1921 ath_err(common, "Chip reset failed\n"); 1922 return -EINVAL; 1923 } 1924 1925 /* Only required on the first reset */ 1926 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1927 ah->htc_reset_init = false; 1928 REG_WRITE(ah, 1929 AR9271_RESET_POWER_DOWN_CONTROL, 1930 AR9271_GATE_MAC_CTL); 1931 udelay(50); 1932 } 1933 1934 /* Restore TSF */ 1935 if (tsf) 1936 ath9k_hw_settsf64(ah, tsf); 1937 1938 if (AR_SREV_9280_20_OR_LATER(ah)) 1939 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1940 1941 if (!AR_SREV_9300_20_OR_LATER(ah)) 1942 ar9002_hw_enable_async_fifo(ah); 1943 1944 r = ath9k_hw_process_ini(ah, chan); 1945 if (r) 1946 return r; 1947 1948 if (ath9k_hw_mci_is_enabled(ah)) 1949 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1950 1951 /* 1952 * Some AR91xx SoC devices frequently fail to accept TSF writes 1953 * right after the chip reset. When that happens, write a new 1954 * value after the initvals have been applied, with an offset 1955 * based on measured time difference 1956 */ 1957 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1958 tsf += 1500; 1959 ath9k_hw_settsf64(ah, tsf); 1960 } 1961 1962 ath9k_hw_init_mfp(ah); 1963 1964 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1965 ath9k_hw_set_delta_slope(ah, chan); 1966 1967 ath9k_hw_spur_mitigate_freq(ah, chan); 1968 ah->eep_ops->set_board_values(ah, chan); 1969 1970 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1971 1972 r = ath9k_hw_rf_set_freq(ah, chan); 1973 if (r) 1974 return r; 1975 1976 ath9k_hw_set_clockrate(ah); 1977 1978 ath9k_hw_init_queues(ah); 1979 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1980 ath9k_hw_ani_cache_ini_regs(ah); 1981 ath9k_hw_init_qos(ah); 1982 1983 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1984 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1985 1986 ath9k_hw_init_global_settings(ah); 1987 1988 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1989 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1990 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1991 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1992 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1993 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1994 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1995 } 1996 1997 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1998 1999 ath9k_hw_set_dma(ah); 2000 2001 if (!ath9k_hw_mci_is_enabled(ah)) 2002 REG_WRITE(ah, AR_OBS, 8); 2003 2004 if (ah->config.rx_intr_mitigation) { 2005 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2006 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2007 } 2008 2009 if (ah->config.tx_intr_mitigation) { 2010 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2011 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2012 } 2013 2014 ath9k_hw_init_bb(ah, chan); 2015 2016 if (caldata) { 2017 caldata->done_txiqcal_once = false; 2018 caldata->done_txclcal_once = false; 2019 } 2020 if (!ath9k_hw_init_cal(ah, chan)) 2021 return -EIO; 2022 2023 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2024 return -EIO; 2025 2026 ENABLE_REGWRITE_BUFFER(ah); 2027 2028 ath9k_hw_restore_chainmask(ah); 2029 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2030 2031 REGWRITE_BUFFER_FLUSH(ah); 2032 2033 ath9k_hw_init_desc(ah); 2034 2035 if (ath9k_hw_btcoex_is_enabled(ah)) 2036 ath9k_hw_btcoex_enable(ah); 2037 2038 if (ath9k_hw_mci_is_enabled(ah)) 2039 ar9003_mci_check_bt(ah); 2040 2041 ath9k_hw_loadnf(ah, chan); 2042 ath9k_hw_start_nfcal(ah, true); 2043 2044 if (AR_SREV_9300_20_OR_LATER(ah)) { 2045 ar9003_hw_bb_watchdog_config(ah); 2046 ar9003_hw_disable_phy_restart(ah); 2047 } 2048 2049 ath9k_hw_apply_gpio_override(ah); 2050 2051 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv) 2052 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2053 2054 return 0; 2055 } 2056 EXPORT_SYMBOL(ath9k_hw_reset); 2057 2058 /******************************/ 2059 /* Power Management (Chipset) */ 2060 /******************************/ 2061 2062 /* 2063 * Notify Power Mgt is disabled in self-generated frames. 2064 * If requested, force chip to sleep. 2065 */ 2066 static void ath9k_set_power_sleep(struct ath_hw *ah) 2067 { 2068 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2069 2070 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2071 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2072 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2073 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2074 /* xxx Required for WLAN only case ? */ 2075 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2076 udelay(100); 2077 } 2078 2079 /* 2080 * Clear the RTC force wake bit to allow the 2081 * mac to go to sleep. 2082 */ 2083 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2084 2085 if (ath9k_hw_mci_is_enabled(ah)) 2086 udelay(100); 2087 2088 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2089 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2090 2091 /* Shutdown chip. Active low */ 2092 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2093 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2094 udelay(2); 2095 } 2096 2097 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2098 if (AR_SREV_9300_20_OR_LATER(ah)) 2099 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2100 } 2101 2102 /* 2103 * Notify Power Management is enabled in self-generating 2104 * frames. If request, set power mode of chip to 2105 * auto/normal. Duration in units of 128us (1/8 TU). 2106 */ 2107 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2108 { 2109 struct ath9k_hw_capabilities *pCap = &ah->caps; 2110 2111 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2112 2113 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2114 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2115 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2116 AR_RTC_FORCE_WAKE_ON_INT); 2117 } else { 2118 2119 /* When chip goes into network sleep, it could be waken 2120 * up by MCI_INT interrupt caused by BT's HW messages 2121 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2122 * rate (~100us). This will cause chip to leave and 2123 * re-enter network sleep mode frequently, which in 2124 * consequence will have WLAN MCI HW to generate lots of 2125 * SYS_WAKING and SYS_SLEEPING messages which will make 2126 * BT CPU to busy to process. 2127 */ 2128 if (ath9k_hw_mci_is_enabled(ah)) 2129 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2130 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2131 /* 2132 * Clear the RTC force wake bit to allow the 2133 * mac to go to sleep. 2134 */ 2135 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2136 2137 if (ath9k_hw_mci_is_enabled(ah)) 2138 udelay(30); 2139 } 2140 2141 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2142 if (AR_SREV_9300_20_OR_LATER(ah)) 2143 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2144 } 2145 2146 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2147 { 2148 u32 val; 2149 int i; 2150 2151 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2152 if (AR_SREV_9300_20_OR_LATER(ah)) { 2153 REG_WRITE(ah, AR_WA, ah->WARegVal); 2154 udelay(10); 2155 } 2156 2157 if ((REG_READ(ah, AR_RTC_STATUS) & 2158 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2159 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2160 return false; 2161 } 2162 if (!AR_SREV_9300_20_OR_LATER(ah)) 2163 ath9k_hw_init_pll(ah, NULL); 2164 } 2165 if (AR_SREV_9100(ah)) 2166 REG_SET_BIT(ah, AR_RTC_RESET, 2167 AR_RTC_RESET_EN); 2168 2169 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2170 AR_RTC_FORCE_WAKE_EN); 2171 udelay(50); 2172 2173 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2174 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2175 if (val == AR_RTC_STATUS_ON) 2176 break; 2177 udelay(50); 2178 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2179 AR_RTC_FORCE_WAKE_EN); 2180 } 2181 if (i == 0) { 2182 ath_err(ath9k_hw_common(ah), 2183 "Failed to wakeup in %uus\n", 2184 POWER_UP_TIME / 20); 2185 return false; 2186 } 2187 2188 if (ath9k_hw_mci_is_enabled(ah)) 2189 ar9003_mci_set_power_awake(ah); 2190 2191 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2192 2193 return true; 2194 } 2195 2196 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2197 { 2198 struct ath_common *common = ath9k_hw_common(ah); 2199 int status = true; 2200 static const char *modes[] = { 2201 "AWAKE", 2202 "FULL-SLEEP", 2203 "NETWORK SLEEP", 2204 "UNDEFINED" 2205 }; 2206 2207 if (ah->power_mode == mode) 2208 return status; 2209 2210 ath_dbg(common, RESET, "%s -> %s\n", 2211 modes[ah->power_mode], modes[mode]); 2212 2213 switch (mode) { 2214 case ATH9K_PM_AWAKE: 2215 status = ath9k_hw_set_power_awake(ah); 2216 break; 2217 case ATH9K_PM_FULL_SLEEP: 2218 if (ath9k_hw_mci_is_enabled(ah)) 2219 ar9003_mci_set_full_sleep(ah); 2220 2221 ath9k_set_power_sleep(ah); 2222 ah->chip_fullsleep = true; 2223 break; 2224 case ATH9K_PM_NETWORK_SLEEP: 2225 ath9k_set_power_network_sleep(ah); 2226 break; 2227 default: 2228 ath_err(common, "Unknown power mode %u\n", mode); 2229 return false; 2230 } 2231 ah->power_mode = mode; 2232 2233 /* 2234 * XXX: If this warning never comes up after a while then 2235 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2236 * ath9k_hw_setpower() return type void. 2237 */ 2238 2239 if (!(ah->ah_flags & AH_UNPLUGGED)) 2240 ATH_DBG_WARN_ON_ONCE(!status); 2241 2242 return status; 2243 } 2244 EXPORT_SYMBOL(ath9k_hw_setpower); 2245 2246 /*******************/ 2247 /* Beacon Handling */ 2248 /*******************/ 2249 2250 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2251 { 2252 int flags = 0; 2253 2254 ENABLE_REGWRITE_BUFFER(ah); 2255 2256 switch (ah->opmode) { 2257 case NL80211_IFTYPE_ADHOC: 2258 case NL80211_IFTYPE_MESH_POINT: 2259 REG_SET_BIT(ah, AR_TXCFG, 2260 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2261 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2262 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2263 flags |= AR_NDP_TIMER_EN; 2264 case NL80211_IFTYPE_AP: 2265 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2266 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2267 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2268 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2269 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2270 flags |= 2271 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2272 break; 2273 default: 2274 ath_dbg(ath9k_hw_common(ah), BEACON, 2275 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2276 return; 2277 break; 2278 } 2279 2280 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2281 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2282 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2283 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2284 2285 REGWRITE_BUFFER_FLUSH(ah); 2286 2287 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2288 } 2289 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2290 2291 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2292 const struct ath9k_beacon_state *bs) 2293 { 2294 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2295 struct ath9k_hw_capabilities *pCap = &ah->caps; 2296 struct ath_common *common = ath9k_hw_common(ah); 2297 2298 ENABLE_REGWRITE_BUFFER(ah); 2299 2300 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2301 2302 REG_WRITE(ah, AR_BEACON_PERIOD, 2303 TU_TO_USEC(bs->bs_intval)); 2304 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2305 TU_TO_USEC(bs->bs_intval)); 2306 2307 REGWRITE_BUFFER_FLUSH(ah); 2308 2309 REG_RMW_FIELD(ah, AR_RSSI_THR, 2310 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2311 2312 beaconintval = bs->bs_intval; 2313 2314 if (bs->bs_sleepduration > beaconintval) 2315 beaconintval = bs->bs_sleepduration; 2316 2317 dtimperiod = bs->bs_dtimperiod; 2318 if (bs->bs_sleepduration > dtimperiod) 2319 dtimperiod = bs->bs_sleepduration; 2320 2321 if (beaconintval == dtimperiod) 2322 nextTbtt = bs->bs_nextdtim; 2323 else 2324 nextTbtt = bs->bs_nexttbtt; 2325 2326 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2327 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2328 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2329 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2330 2331 ENABLE_REGWRITE_BUFFER(ah); 2332 2333 REG_WRITE(ah, AR_NEXT_DTIM, 2334 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2335 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2336 2337 REG_WRITE(ah, AR_SLEEP1, 2338 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2339 | AR_SLEEP1_ASSUME_DTIM); 2340 2341 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2342 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2343 else 2344 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2345 2346 REG_WRITE(ah, AR_SLEEP2, 2347 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2348 2349 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2350 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2351 2352 REGWRITE_BUFFER_FLUSH(ah); 2353 2354 REG_SET_BIT(ah, AR_TIMER_MODE, 2355 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2356 AR_DTIM_TIMER_EN); 2357 2358 /* TSF Out of Range Threshold */ 2359 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2360 } 2361 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2362 2363 /*******************/ 2364 /* HW Capabilities */ 2365 /*******************/ 2366 2367 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2368 { 2369 eeprom_chainmask &= chip_chainmask; 2370 if (eeprom_chainmask) 2371 return eeprom_chainmask; 2372 else 2373 return chip_chainmask; 2374 } 2375 2376 /** 2377 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2378 * @ah: the atheros hardware data structure 2379 * 2380 * We enable DFS support upstream on chipsets which have passed a series 2381 * of tests. The testing requirements are going to be documented. Desired 2382 * test requirements are documented at: 2383 * 2384 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2385 * 2386 * Once a new chipset gets properly tested an individual commit can be used 2387 * to document the testing for DFS for that chipset. 2388 */ 2389 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2390 { 2391 2392 switch (ah->hw_version.macVersion) { 2393 /* for temporary testing DFS with 9280 */ 2394 case AR_SREV_VERSION_9280: 2395 /* AR9580 will likely be our first target to get testing on */ 2396 case AR_SREV_VERSION_9580: 2397 return true; 2398 default: 2399 return false; 2400 } 2401 } 2402 2403 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2404 { 2405 struct ath9k_hw_capabilities *pCap = &ah->caps; 2406 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2407 struct ath_common *common = ath9k_hw_common(ah); 2408 unsigned int chip_chainmask; 2409 2410 u16 eeval; 2411 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2412 2413 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2414 regulatory->current_rd = eeval; 2415 2416 if (ah->opmode != NL80211_IFTYPE_AP && 2417 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2418 if (regulatory->current_rd == 0x64 || 2419 regulatory->current_rd == 0x65) 2420 regulatory->current_rd += 5; 2421 else if (regulatory->current_rd == 0x41) 2422 regulatory->current_rd = 0x43; 2423 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2424 regulatory->current_rd); 2425 } 2426 2427 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2428 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2429 ath_err(common, 2430 "no band has been marked as supported in EEPROM\n"); 2431 return -EINVAL; 2432 } 2433 2434 if (eeval & AR5416_OPFLAGS_11A) 2435 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2436 2437 if (eeval & AR5416_OPFLAGS_11G) 2438 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2439 2440 if (AR_SREV_9485(ah) || 2441 AR_SREV_9285(ah) || 2442 AR_SREV_9330(ah) || 2443 AR_SREV_9565(ah)) 2444 chip_chainmask = 1; 2445 else if (AR_SREV_9462(ah)) 2446 chip_chainmask = 3; 2447 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2448 chip_chainmask = 7; 2449 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2450 chip_chainmask = 3; 2451 else 2452 chip_chainmask = 7; 2453 2454 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2455 /* 2456 * For AR9271 we will temporarilly uses the rx chainmax as read from 2457 * the EEPROM. 2458 */ 2459 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2460 !(eeval & AR5416_OPFLAGS_11A) && 2461 !(AR_SREV_9271(ah))) 2462 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2463 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2464 else if (AR_SREV_9100(ah)) 2465 pCap->rx_chainmask = 0x7; 2466 else 2467 /* Use rx_chainmask from EEPROM. */ 2468 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2469 2470 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2471 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2472 ah->txchainmask = pCap->tx_chainmask; 2473 ah->rxchainmask = pCap->rx_chainmask; 2474 2475 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2476 2477 /* enable key search for every frame in an aggregate */ 2478 if (AR_SREV_9300_20_OR_LATER(ah)) 2479 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2480 2481 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2482 2483 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2484 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2485 else 2486 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2487 2488 if (AR_SREV_9271(ah)) 2489 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2490 else if (AR_DEVID_7010(ah)) 2491 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2492 else if (AR_SREV_9300_20_OR_LATER(ah)) 2493 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2494 else if (AR_SREV_9287_11_OR_LATER(ah)) 2495 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2496 else if (AR_SREV_9285_12_OR_LATER(ah)) 2497 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2498 else if (AR_SREV_9280_20_OR_LATER(ah)) 2499 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2500 else 2501 pCap->num_gpio_pins = AR_NUM_GPIO; 2502 2503 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2504 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2505 else 2506 pCap->rts_aggr_limit = (8 * 1024); 2507 2508 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2509 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2510 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2511 ah->rfkill_gpio = 2512 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2513 ah->rfkill_polarity = 2514 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2515 2516 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2517 } 2518 #endif 2519 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2520 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2521 else 2522 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2523 2524 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2525 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2526 else 2527 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2528 2529 if (AR_SREV_9300_20_OR_LATER(ah)) { 2530 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2531 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2532 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2533 2534 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2535 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2536 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2537 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2538 pCap->txs_len = sizeof(struct ar9003_txs); 2539 } else { 2540 pCap->tx_desc_len = sizeof(struct ath_desc); 2541 if (AR_SREV_9280_20(ah)) 2542 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2543 } 2544 2545 if (AR_SREV_9300_20_OR_LATER(ah)) 2546 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2547 2548 if (AR_SREV_9300_20_OR_LATER(ah)) 2549 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2550 2551 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2552 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2553 2554 if (AR_SREV_9285(ah)) 2555 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2556 ant_div_ctl1 = 2557 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2558 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2559 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2560 } 2561 if (AR_SREV_9300_20_OR_LATER(ah)) { 2562 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2563 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2564 } 2565 2566 2567 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2568 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2569 /* 2570 * enable the diversity-combining algorithm only when 2571 * both enable_lna_div and enable_fast_div are set 2572 * Table for Diversity 2573 * ant_div_alt_lnaconf bit 0-1 2574 * ant_div_main_lnaconf bit 2-3 2575 * ant_div_alt_gaintb bit 4 2576 * ant_div_main_gaintb bit 5 2577 * enable_ant_div_lnadiv bit 6 2578 * enable_ant_fast_div bit 7 2579 */ 2580 if ((ant_div_ctl1 >> 0x6) == 0x3) 2581 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2582 } 2583 2584 if (ath9k_hw_dfs_tested(ah)) 2585 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2586 2587 tx_chainmask = pCap->tx_chainmask; 2588 rx_chainmask = pCap->rx_chainmask; 2589 while (tx_chainmask || rx_chainmask) { 2590 if (tx_chainmask & BIT(0)) 2591 pCap->max_txchains++; 2592 if (rx_chainmask & BIT(0)) 2593 pCap->max_rxchains++; 2594 2595 tx_chainmask >>= 1; 2596 rx_chainmask >>= 1; 2597 } 2598 2599 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2600 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2601 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2602 2603 if (AR_SREV_9462_20(ah)) 2604 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2605 } 2606 2607 if (AR_SREV_9280_20_OR_LATER(ah)) { 2608 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE | 2609 ATH9K_HW_WOW_PATTERN_MATCH_EXACT; 2610 2611 if (AR_SREV_9280(ah)) 2612 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD; 2613 } 2614 2615 if (AR_SREV_9300_20_OR_LATER(ah) && 2616 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2617 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2618 2619 return 0; 2620 } 2621 2622 /****************************/ 2623 /* GPIO / RFKILL / Antennae */ 2624 /****************************/ 2625 2626 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2627 u32 gpio, u32 type) 2628 { 2629 int addr; 2630 u32 gpio_shift, tmp; 2631 2632 if (gpio > 11) 2633 addr = AR_GPIO_OUTPUT_MUX3; 2634 else if (gpio > 5) 2635 addr = AR_GPIO_OUTPUT_MUX2; 2636 else 2637 addr = AR_GPIO_OUTPUT_MUX1; 2638 2639 gpio_shift = (gpio % 6) * 5; 2640 2641 if (AR_SREV_9280_20_OR_LATER(ah) 2642 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2643 REG_RMW(ah, addr, (type << gpio_shift), 2644 (0x1f << gpio_shift)); 2645 } else { 2646 tmp = REG_READ(ah, addr); 2647 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2648 tmp &= ~(0x1f << gpio_shift); 2649 tmp |= (type << gpio_shift); 2650 REG_WRITE(ah, addr, tmp); 2651 } 2652 } 2653 2654 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2655 { 2656 u32 gpio_shift; 2657 2658 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2659 2660 if (AR_DEVID_7010(ah)) { 2661 gpio_shift = gpio; 2662 REG_RMW(ah, AR7010_GPIO_OE, 2663 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2664 (AR7010_GPIO_OE_MASK << gpio_shift)); 2665 return; 2666 } 2667 2668 gpio_shift = gpio << 1; 2669 REG_RMW(ah, 2670 AR_GPIO_OE_OUT, 2671 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2672 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2673 } 2674 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2675 2676 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2677 { 2678 #define MS_REG_READ(x, y) \ 2679 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2680 2681 if (gpio >= ah->caps.num_gpio_pins) 2682 return 0xffffffff; 2683 2684 if (AR_DEVID_7010(ah)) { 2685 u32 val; 2686 val = REG_READ(ah, AR7010_GPIO_IN); 2687 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2688 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2689 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2690 AR_GPIO_BIT(gpio)) != 0; 2691 else if (AR_SREV_9271(ah)) 2692 return MS_REG_READ(AR9271, gpio) != 0; 2693 else if (AR_SREV_9287_11_OR_LATER(ah)) 2694 return MS_REG_READ(AR9287, gpio) != 0; 2695 else if (AR_SREV_9285_12_OR_LATER(ah)) 2696 return MS_REG_READ(AR9285, gpio) != 0; 2697 else if (AR_SREV_9280_20_OR_LATER(ah)) 2698 return MS_REG_READ(AR928X, gpio) != 0; 2699 else 2700 return MS_REG_READ(AR, gpio) != 0; 2701 } 2702 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2703 2704 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2705 u32 ah_signal_type) 2706 { 2707 u32 gpio_shift; 2708 2709 if (AR_DEVID_7010(ah)) { 2710 gpio_shift = gpio; 2711 REG_RMW(ah, AR7010_GPIO_OE, 2712 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2713 (AR7010_GPIO_OE_MASK << gpio_shift)); 2714 return; 2715 } 2716 2717 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2718 gpio_shift = 2 * gpio; 2719 REG_RMW(ah, 2720 AR_GPIO_OE_OUT, 2721 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2722 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2723 } 2724 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2725 2726 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2727 { 2728 if (AR_DEVID_7010(ah)) { 2729 val = val ? 0 : 1; 2730 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2731 AR_GPIO_BIT(gpio)); 2732 return; 2733 } 2734 2735 if (AR_SREV_9271(ah)) 2736 val = ~val; 2737 2738 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2739 AR_GPIO_BIT(gpio)); 2740 } 2741 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2742 2743 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2744 { 2745 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2746 } 2747 EXPORT_SYMBOL(ath9k_hw_setantenna); 2748 2749 /*********************/ 2750 /* General Operation */ 2751 /*********************/ 2752 2753 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2754 { 2755 u32 bits = REG_READ(ah, AR_RX_FILTER); 2756 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2757 2758 if (phybits & AR_PHY_ERR_RADAR) 2759 bits |= ATH9K_RX_FILTER_PHYRADAR; 2760 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2761 bits |= ATH9K_RX_FILTER_PHYERR; 2762 2763 return bits; 2764 } 2765 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2766 2767 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2768 { 2769 u32 phybits; 2770 2771 ENABLE_REGWRITE_BUFFER(ah); 2772 2773 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2774 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2775 2776 REG_WRITE(ah, AR_RX_FILTER, bits); 2777 2778 phybits = 0; 2779 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2780 phybits |= AR_PHY_ERR_RADAR; 2781 if (bits & ATH9K_RX_FILTER_PHYERR) 2782 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2783 REG_WRITE(ah, AR_PHY_ERR, phybits); 2784 2785 if (phybits) 2786 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2787 else 2788 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2789 2790 REGWRITE_BUFFER_FLUSH(ah); 2791 } 2792 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2793 2794 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2795 { 2796 if (ath9k_hw_mci_is_enabled(ah)) 2797 ar9003_mci_bt_gain_ctrl(ah); 2798 2799 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2800 return false; 2801 2802 ath9k_hw_init_pll(ah, NULL); 2803 ah->htc_reset_init = true; 2804 return true; 2805 } 2806 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2807 2808 bool ath9k_hw_disable(struct ath_hw *ah) 2809 { 2810 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2811 return false; 2812 2813 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2814 return false; 2815 2816 ath9k_hw_init_pll(ah, NULL); 2817 return true; 2818 } 2819 EXPORT_SYMBOL(ath9k_hw_disable); 2820 2821 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2822 { 2823 enum eeprom_param gain_param; 2824 2825 if (IS_CHAN_2GHZ(chan)) 2826 gain_param = EEP_ANTENNA_GAIN_2G; 2827 else 2828 gain_param = EEP_ANTENNA_GAIN_5G; 2829 2830 return ah->eep_ops->get_eeprom(ah, gain_param); 2831 } 2832 2833 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2834 bool test) 2835 { 2836 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2837 struct ieee80211_channel *channel; 2838 int chan_pwr, new_pwr, max_gain; 2839 int ant_gain, ant_reduction = 0; 2840 2841 if (!chan) 2842 return; 2843 2844 channel = chan->chan; 2845 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2846 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2847 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2848 2849 ant_gain = get_antenna_gain(ah, chan); 2850 if (ant_gain > max_gain) 2851 ant_reduction = ant_gain - max_gain; 2852 2853 ah->eep_ops->set_txpower(ah, chan, 2854 ath9k_regd_get_ctl(reg, chan), 2855 ant_reduction, new_pwr, test); 2856 } 2857 2858 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2859 { 2860 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2861 struct ath9k_channel *chan = ah->curchan; 2862 struct ieee80211_channel *channel = chan->chan; 2863 2864 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2865 if (test) 2866 channel->max_power = MAX_RATE_POWER / 2; 2867 2868 ath9k_hw_apply_txpower(ah, chan, test); 2869 2870 if (test) 2871 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2872 } 2873 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2874 2875 void ath9k_hw_setopmode(struct ath_hw *ah) 2876 { 2877 ath9k_hw_set_operating_mode(ah, ah->opmode); 2878 } 2879 EXPORT_SYMBOL(ath9k_hw_setopmode); 2880 2881 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2882 { 2883 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2884 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2885 } 2886 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2887 2888 void ath9k_hw_write_associd(struct ath_hw *ah) 2889 { 2890 struct ath_common *common = ath9k_hw_common(ah); 2891 2892 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2893 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2894 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2895 } 2896 EXPORT_SYMBOL(ath9k_hw_write_associd); 2897 2898 #define ATH9K_MAX_TSF_READ 10 2899 2900 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2901 { 2902 u32 tsf_lower, tsf_upper1, tsf_upper2; 2903 int i; 2904 2905 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2906 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2907 tsf_lower = REG_READ(ah, AR_TSF_L32); 2908 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2909 if (tsf_upper2 == tsf_upper1) 2910 break; 2911 tsf_upper1 = tsf_upper2; 2912 } 2913 2914 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2915 2916 return (((u64)tsf_upper1 << 32) | tsf_lower); 2917 } 2918 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2919 2920 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2921 { 2922 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2923 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2924 } 2925 EXPORT_SYMBOL(ath9k_hw_settsf64); 2926 2927 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2928 { 2929 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2930 AH_TSF_WRITE_TIMEOUT)) 2931 ath_dbg(ath9k_hw_common(ah), RESET, 2932 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2933 2934 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2935 } 2936 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2937 2938 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2939 { 2940 if (set) 2941 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2942 else 2943 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2944 } 2945 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2946 2947 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2948 { 2949 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2950 u32 macmode; 2951 2952 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2953 macmode = AR_2040_JOINED_RX_CLEAR; 2954 else 2955 macmode = 0; 2956 2957 REG_WRITE(ah, AR_2040_MODE, macmode); 2958 } 2959 2960 /* HW Generic timers configuration */ 2961 2962 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2963 { 2964 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2965 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2970 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2971 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2972 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2973 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2974 AR_NDP2_TIMER_MODE, 0x0002}, 2975 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2976 AR_NDP2_TIMER_MODE, 0x0004}, 2977 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2978 AR_NDP2_TIMER_MODE, 0x0008}, 2979 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2980 AR_NDP2_TIMER_MODE, 0x0010}, 2981 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2982 AR_NDP2_TIMER_MODE, 0x0020}, 2983 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2984 AR_NDP2_TIMER_MODE, 0x0040}, 2985 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2986 AR_NDP2_TIMER_MODE, 0x0080} 2987 }; 2988 2989 /* HW generic timer primitives */ 2990 2991 /* compute and clear index of rightmost 1 */ 2992 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2993 { 2994 u32 b; 2995 2996 b = *mask; 2997 b &= (0-b); 2998 *mask &= ~b; 2999 b *= debruijn32; 3000 b >>= 27; 3001 3002 return timer_table->gen_timer_index[b]; 3003 } 3004 3005 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3006 { 3007 return REG_READ(ah, AR_TSF_L32); 3008 } 3009 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3010 3011 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3012 void (*trigger)(void *), 3013 void (*overflow)(void *), 3014 void *arg, 3015 u8 timer_index) 3016 { 3017 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3018 struct ath_gen_timer *timer; 3019 3020 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3021 if (timer == NULL) 3022 return NULL; 3023 3024 /* allocate a hardware generic timer slot */ 3025 timer_table->timers[timer_index] = timer; 3026 timer->index = timer_index; 3027 timer->trigger = trigger; 3028 timer->overflow = overflow; 3029 timer->arg = arg; 3030 3031 return timer; 3032 } 3033 EXPORT_SYMBOL(ath_gen_timer_alloc); 3034 3035 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3036 struct ath_gen_timer *timer, 3037 u32 trig_timeout, 3038 u32 timer_period) 3039 { 3040 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3041 u32 tsf, timer_next; 3042 3043 BUG_ON(!timer_period); 3044 3045 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3046 3047 tsf = ath9k_hw_gettsf32(ah); 3048 3049 timer_next = tsf + trig_timeout; 3050 3051 ath_dbg(ath9k_hw_common(ah), HWTIMER, 3052 "current tsf %x period %x timer_next %x\n", 3053 tsf, timer_period, timer_next); 3054 3055 /* 3056 * Program generic timer registers 3057 */ 3058 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3059 timer_next); 3060 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3061 timer_period); 3062 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3063 gen_tmr_configuration[timer->index].mode_mask); 3064 3065 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3066 /* 3067 * Starting from AR9462, each generic timer can select which tsf 3068 * to use. But we still follow the old rule, 0 - 7 use tsf and 3069 * 8 - 15 use tsf2. 3070 */ 3071 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3072 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3073 (1 << timer->index)); 3074 else 3075 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3076 (1 << timer->index)); 3077 } 3078 3079 /* Enable both trigger and thresh interrupt masks */ 3080 REG_SET_BIT(ah, AR_IMR_S5, 3081 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3082 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3083 } 3084 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3085 3086 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3087 { 3088 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3089 3090 if ((timer->index < AR_FIRST_NDP_TIMER) || 3091 (timer->index >= ATH_MAX_GEN_TIMER)) { 3092 return; 3093 } 3094 3095 /* Clear generic timer enable bits. */ 3096 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3097 gen_tmr_configuration[timer->index].mode_mask); 3098 3099 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3100 /* 3101 * Need to switch back to TSF if it was using TSF2. 3102 */ 3103 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3104 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3105 (1 << timer->index)); 3106 } 3107 } 3108 3109 /* Disable both trigger and thresh interrupt masks */ 3110 REG_CLR_BIT(ah, AR_IMR_S5, 3111 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3112 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3113 3114 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3115 } 3116 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3117 3118 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3119 { 3120 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3121 3122 /* free the hardware generic timer slot */ 3123 timer_table->timers[timer->index] = NULL; 3124 kfree(timer); 3125 } 3126 EXPORT_SYMBOL(ath_gen_timer_free); 3127 3128 /* 3129 * Generic Timer Interrupts handling 3130 */ 3131 void ath_gen_timer_isr(struct ath_hw *ah) 3132 { 3133 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3134 struct ath_gen_timer *timer; 3135 struct ath_common *common = ath9k_hw_common(ah); 3136 u32 trigger_mask, thresh_mask, index; 3137 3138 /* get hardware generic timer interrupt status */ 3139 trigger_mask = ah->intr_gen_timer_trigger; 3140 thresh_mask = ah->intr_gen_timer_thresh; 3141 trigger_mask &= timer_table->timer_mask.val; 3142 thresh_mask &= timer_table->timer_mask.val; 3143 3144 trigger_mask &= ~thresh_mask; 3145 3146 while (thresh_mask) { 3147 index = rightmost_index(timer_table, &thresh_mask); 3148 timer = timer_table->timers[index]; 3149 BUG_ON(!timer); 3150 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3151 index); 3152 timer->overflow(timer->arg); 3153 } 3154 3155 while (trigger_mask) { 3156 index = rightmost_index(timer_table, &trigger_mask); 3157 timer = timer_table->timers[index]; 3158 BUG_ON(!timer); 3159 ath_dbg(common, HWTIMER, 3160 "Gen timer[%d] trigger\n", index); 3161 timer->trigger(timer->arg); 3162 } 3163 } 3164 EXPORT_SYMBOL(ath_gen_timer_isr); 3165 3166 /********/ 3167 /* HTC */ 3168 /********/ 3169 3170 static struct { 3171 u32 version; 3172 const char * name; 3173 } ath_mac_bb_names[] = { 3174 /* Devices with external radios */ 3175 { AR_SREV_VERSION_5416_PCI, "5416" }, 3176 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3177 { AR_SREV_VERSION_9100, "9100" }, 3178 { AR_SREV_VERSION_9160, "9160" }, 3179 /* Single-chip solutions */ 3180 { AR_SREV_VERSION_9280, "9280" }, 3181 { AR_SREV_VERSION_9285, "9285" }, 3182 { AR_SREV_VERSION_9287, "9287" }, 3183 { AR_SREV_VERSION_9271, "9271" }, 3184 { AR_SREV_VERSION_9300, "9300" }, 3185 { AR_SREV_VERSION_9330, "9330" }, 3186 { AR_SREV_VERSION_9340, "9340" }, 3187 { AR_SREV_VERSION_9485, "9485" }, 3188 { AR_SREV_VERSION_9462, "9462" }, 3189 { AR_SREV_VERSION_9550, "9550" }, 3190 { AR_SREV_VERSION_9565, "9565" }, 3191 }; 3192 3193 /* For devices with external radios */ 3194 static struct { 3195 u16 version; 3196 const char * name; 3197 } ath_rf_names[] = { 3198 { 0, "5133" }, 3199 { AR_RAD5133_SREV_MAJOR, "5133" }, 3200 { AR_RAD5122_SREV_MAJOR, "5122" }, 3201 { AR_RAD2133_SREV_MAJOR, "2133" }, 3202 { AR_RAD2122_SREV_MAJOR, "2122" } 3203 }; 3204 3205 /* 3206 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3207 */ 3208 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3209 { 3210 int i; 3211 3212 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3213 if (ath_mac_bb_names[i].version == mac_bb_version) { 3214 return ath_mac_bb_names[i].name; 3215 } 3216 } 3217 3218 return "????"; 3219 } 3220 3221 /* 3222 * Return the RF name. "????" is returned if the RF is unknown. 3223 * Used for devices with external radios. 3224 */ 3225 static const char *ath9k_hw_rf_name(u16 rf_version) 3226 { 3227 int i; 3228 3229 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3230 if (ath_rf_names[i].version == rf_version) { 3231 return ath_rf_names[i].name; 3232 } 3233 } 3234 3235 return "????"; 3236 } 3237 3238 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3239 { 3240 int used; 3241 3242 /* chipsets >= AR9280 are single-chip */ 3243 if (AR_SREV_9280_20_OR_LATER(ah)) { 3244 used = snprintf(hw_name, len, 3245 "Atheros AR%s Rev:%x", 3246 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3247 ah->hw_version.macRev); 3248 } 3249 else { 3250 used = snprintf(hw_name, len, 3251 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3252 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3253 ah->hw_version.macRev, 3254 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3255 AR_RADIO_SREV_MAJOR)), 3256 ah->hw_version.phyRev); 3257 } 3258 3259 hw_name[used] = '\0'; 3260 } 3261 EXPORT_SYMBOL(ath9k_hw_name); 3262