1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <asm/unaligned.h> 24 25 #include "hw.h" 26 #include "hw-ops.h" 27 #include "ar9003_mac.h" 28 #include "ar9003_mci.h" 29 #include "ar9003_phy.h" 30 #include "ath9k.h" 31 32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 33 34 MODULE_AUTHOR("Atheros Communications"); 35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 39 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 40 { 41 struct ath_common *common = ath9k_hw_common(ah); 42 struct ath9k_channel *chan = ah->curchan; 43 unsigned int clockrate; 44 45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 47 clockrate = 117; 48 else if (!chan) /* should really check for CCK instead */ 49 clockrate = ATH9K_CLOCK_RATE_CCK; 50 else if (IS_CHAN_2GHZ(chan)) 51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 54 else 55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 56 57 if (chan) { 58 if (IS_CHAN_HT40(chan)) 59 clockrate *= 2; 60 if (IS_CHAN_HALF_RATE(chan)) 61 clockrate /= 2; 62 if (IS_CHAN_QUARTER_RATE(chan)) 63 clockrate /= 4; 64 } 65 66 common->clockrate = clockrate; 67 } 68 69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 70 { 71 struct ath_common *common = ath9k_hw_common(ah); 72 73 return usecs * common->clockrate; 74 } 75 76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 77 { 78 int i; 79 80 BUG_ON(timeout < AH_TIME_QUANTUM); 81 82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 83 if ((REG_READ(ah, reg) & mask) == val) 84 return true; 85 86 udelay(AH_TIME_QUANTUM); 87 } 88 89 ath_dbg(ath9k_hw_common(ah), ANY, 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 91 timeout, reg, REG_READ(ah, reg), mask, val); 92 93 return false; 94 } 95 EXPORT_SYMBOL(ath9k_hw_wait); 96 97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 98 int hw_delay) 99 { 100 hw_delay /= 10; 101 102 if (IS_CHAN_HALF_RATE(chan)) 103 hw_delay *= 2; 104 else if (IS_CHAN_QUARTER_RATE(chan)) 105 hw_delay *= 4; 106 107 udelay(hw_delay + BASE_ACTIVATE_DELAY); 108 } 109 110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 111 int column, unsigned int *writecnt) 112 { 113 int r; 114 115 ENABLE_REGWRITE_BUFFER(ah); 116 for (r = 0; r < array->ia_rows; r++) { 117 REG_WRITE(ah, INI_RA(array, r, 0), 118 INI_RA(array, r, column)); 119 DO_DELAY(*writecnt); 120 } 121 REGWRITE_BUFFER_FLUSH(ah); 122 } 123 124 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 125 { 126 u32 retval; 127 int i; 128 129 for (i = 0, retval = 0; i < n; i++) { 130 retval = (retval << 1) | (val & 1); 131 val >>= 1; 132 } 133 return retval; 134 } 135 136 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 137 u8 phy, int kbps, 138 u32 frameLen, u16 rateix, 139 bool shortPreamble) 140 { 141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 142 143 if (kbps == 0) 144 return 0; 145 146 switch (phy) { 147 case WLAN_RC_PHY_CCK: 148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 149 if (shortPreamble) 150 phyTime >>= 1; 151 numBits = frameLen << 3; 152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 153 break; 154 case WLAN_RC_PHY_OFDM: 155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 157 numBits = OFDM_PLCP_BITS + (frameLen << 3); 158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 159 txTime = OFDM_SIFS_TIME_QUARTER 160 + OFDM_PREAMBLE_TIME_QUARTER 161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 162 } else if (ah->curchan && 163 IS_CHAN_HALF_RATE(ah->curchan)) { 164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 165 numBits = OFDM_PLCP_BITS + (frameLen << 3); 166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 167 txTime = OFDM_SIFS_TIME_HALF + 168 OFDM_PREAMBLE_TIME_HALF 169 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 170 } else { 171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 172 numBits = OFDM_PLCP_BITS + (frameLen << 3); 173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 175 + (numSymbols * OFDM_SYMBOL_TIME); 176 } 177 break; 178 default: 179 ath_err(ath9k_hw_common(ah), 180 "Unknown phy %u (rate ix %u)\n", phy, rateix); 181 txTime = 0; 182 break; 183 } 184 185 return txTime; 186 } 187 EXPORT_SYMBOL(ath9k_hw_computetxtime); 188 189 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 190 struct ath9k_channel *chan, 191 struct chan_centers *centers) 192 { 193 int8_t extoff; 194 195 if (!IS_CHAN_HT40(chan)) { 196 centers->ctl_center = centers->ext_center = 197 centers->synth_center = chan->channel; 198 return; 199 } 200 201 if (IS_CHAN_HT40PLUS(chan)) { 202 centers->synth_center = 203 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 204 extoff = 1; 205 } else { 206 centers->synth_center = 207 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 208 extoff = -1; 209 } 210 211 centers->ctl_center = 212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 213 /* 25 MHz spacing is supported by hw but not on upper layers */ 214 centers->ext_center = 215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 } 217 218 /******************/ 219 /* Chip Revisions */ 220 /******************/ 221 222 static void ath9k_hw_read_revisions(struct ath_hw *ah) 223 { 224 u32 val; 225 226 if (ah->get_mac_revision) 227 ah->hw_version.macRev = ah->get_mac_revision(); 228 229 switch (ah->hw_version.devid) { 230 case AR5416_AR9100_DEVID: 231 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 232 break; 233 case AR9300_DEVID_AR9330: 234 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 235 if (!ah->get_mac_revision) { 236 val = REG_READ(ah, AR_SREV); 237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 238 } 239 return; 240 case AR9300_DEVID_AR9340: 241 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 242 return; 243 case AR9300_DEVID_QCA955X: 244 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 245 return; 246 case AR9300_DEVID_AR953X: 247 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 248 return; 249 } 250 251 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 252 253 if (val == 0xFF) { 254 val = REG_READ(ah, AR_SREV); 255 ah->hw_version.macVersion = 256 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 258 259 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 260 ah->is_pciexpress = true; 261 else 262 ah->is_pciexpress = (val & 263 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 264 } else { 265 if (!AR_SREV_9100(ah)) 266 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 267 268 ah->hw_version.macRev = val & AR_SREV_REVISION; 269 270 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 271 ah->is_pciexpress = true; 272 } 273 } 274 275 /************************************/ 276 /* HW Attach, Detach, Init Routines */ 277 /************************************/ 278 279 static void ath9k_hw_disablepcie(struct ath_hw *ah) 280 { 281 if (!AR_SREV_5416(ah)) 282 return; 283 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 293 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 295 } 296 297 /* This should work for all families including legacy */ 298 static bool ath9k_hw_chip_test(struct ath_hw *ah) 299 { 300 struct ath_common *common = ath9k_hw_common(ah); 301 u32 regAddr[2] = { AR_STA_ID0 }; 302 u32 regHold[2]; 303 static const u32 patternData[4] = { 304 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 305 }; 306 int i, j, loop_max; 307 308 if (!AR_SREV_9300_20_OR_LATER(ah)) { 309 loop_max = 2; 310 regAddr[1] = AR_PHY_BASE + (8 << 2); 311 } else 312 loop_max = 1; 313 314 for (i = 0; i < loop_max; i++) { 315 u32 addr = regAddr[i]; 316 u32 wrData, rdData; 317 318 regHold[i] = REG_READ(ah, addr); 319 for (j = 0; j < 0x100; j++) { 320 wrData = (j << 16) | j; 321 REG_WRITE(ah, addr, wrData); 322 rdData = REG_READ(ah, addr); 323 if (rdData != wrData) { 324 ath_err(common, 325 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 326 addr, wrData, rdData); 327 return false; 328 } 329 } 330 for (j = 0; j < 4; j++) { 331 wrData = patternData[j]; 332 REG_WRITE(ah, addr, wrData); 333 rdData = REG_READ(ah, addr); 334 if (wrData != rdData) { 335 ath_err(common, 336 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 337 addr, wrData, rdData); 338 return false; 339 } 340 } 341 REG_WRITE(ah, regAddr[i], regHold[i]); 342 } 343 udelay(100); 344 345 return true; 346 } 347 348 static void ath9k_hw_init_config(struct ath_hw *ah) 349 { 350 struct ath_common *common = ath9k_hw_common(ah); 351 352 ah->config.dma_beacon_response_time = 1; 353 ah->config.sw_beacon_response_time = 6; 354 ah->config.cwm_ignore_extcca = 0; 355 ah->config.analog_shiftreg = 1; 356 357 ah->config.rx_intr_mitigation = true; 358 359 if (AR_SREV_9300_20_OR_LATER(ah)) { 360 ah->config.rimt_last = 500; 361 ah->config.rimt_first = 2000; 362 } else { 363 ah->config.rimt_last = 250; 364 ah->config.rimt_first = 700; 365 } 366 367 /* 368 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 369 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 370 * This means we use it for all AR5416 devices, and the few 371 * minor PCI AR9280 devices out there. 372 * 373 * Serialization is required because these devices do not handle 374 * well the case of two concurrent reads/writes due to the latency 375 * involved. During one read/write another read/write can be issued 376 * on another CPU while the previous read/write may still be working 377 * on our hardware, if we hit this case the hardware poops in a loop. 378 * We prevent this by serializing reads and writes. 379 * 380 * This issue is not present on PCI-Express devices or pre-AR5416 381 * devices (legacy, 802.11abg). 382 */ 383 if (num_possible_cpus() > 1) 384 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 385 386 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 387 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 388 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 389 !ah->is_pciexpress)) { 390 ah->config.serialize_regmode = SER_REG_MODE_ON; 391 } else { 392 ah->config.serialize_regmode = SER_REG_MODE_OFF; 393 } 394 } 395 396 ath_dbg(common, RESET, "serialize_regmode is %d\n", 397 ah->config.serialize_regmode); 398 399 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 400 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 401 else 402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 403 } 404 405 static void ath9k_hw_init_defaults(struct ath_hw *ah) 406 { 407 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 408 409 regulatory->country_code = CTRY_DEFAULT; 410 regulatory->power_limit = MAX_RATE_POWER; 411 412 ah->hw_version.magic = AR5416_MAGIC; 413 ah->hw_version.subvendorid = 0; 414 415 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 416 AR_STA_ID1_MCAST_KSRCH; 417 if (AR_SREV_9100(ah)) 418 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 419 420 ah->slottime = ATH9K_SLOT_TIME_9; 421 ah->globaltxtimeout = (u32) -1; 422 ah->power_mode = ATH9K_PM_UNDEFINED; 423 ah->htc_reset_init = true; 424 425 ah->ani_function = ATH9K_ANI_ALL; 426 if (!AR_SREV_9300_20_OR_LATER(ah)) 427 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 428 429 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 430 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 431 else 432 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 433 } 434 435 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 436 { 437 struct ath_common *common = ath9k_hw_common(ah); 438 u32 sum; 439 int i; 440 u16 eeval; 441 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 442 443 sum = 0; 444 for (i = 0; i < 3; i++) { 445 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 446 sum += eeval; 447 common->macaddr[2 * i] = eeval >> 8; 448 common->macaddr[2 * i + 1] = eeval & 0xff; 449 } 450 if (!is_valid_ether_addr(common->macaddr)) { 451 ath_err(common, 452 "eeprom contains invalid mac address: %pM\n", 453 common->macaddr); 454 455 random_ether_addr(common->macaddr); 456 ath_err(common, 457 "random mac address will be used: %pM\n", 458 common->macaddr); 459 } 460 461 return 0; 462 } 463 464 static int ath9k_hw_post_init(struct ath_hw *ah) 465 { 466 struct ath_common *common = ath9k_hw_common(ah); 467 int ecode; 468 469 if (common->bus_ops->ath_bus_type != ATH_USB) { 470 if (!ath9k_hw_chip_test(ah)) 471 return -ENODEV; 472 } 473 474 if (!AR_SREV_9300_20_OR_LATER(ah)) { 475 ecode = ar9002_hw_rf_claim(ah); 476 if (ecode != 0) 477 return ecode; 478 } 479 480 ecode = ath9k_hw_eeprom_init(ah); 481 if (ecode != 0) 482 return ecode; 483 484 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 485 ah->eep_ops->get_eeprom_ver(ah), 486 ah->eep_ops->get_eeprom_rev(ah)); 487 488 ath9k_hw_ani_init(ah); 489 490 /* 491 * EEPROM needs to be initialized before we do this. 492 * This is required for regulatory compliance. 493 */ 494 if (AR_SREV_9300_20_OR_LATER(ah)) { 495 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 496 if ((regdmn & 0xF0) == CTL_FCC) { 497 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 498 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 499 } 500 } 501 502 return 0; 503 } 504 505 static int ath9k_hw_attach_ops(struct ath_hw *ah) 506 { 507 if (!AR_SREV_9300_20_OR_LATER(ah)) 508 return ar9002_hw_attach_ops(ah); 509 510 ar9003_hw_attach_ops(ah); 511 return 0; 512 } 513 514 /* Called for all hardware families */ 515 static int __ath9k_hw_init(struct ath_hw *ah) 516 { 517 struct ath_common *common = ath9k_hw_common(ah); 518 int r = 0; 519 520 ath9k_hw_read_revisions(ah); 521 522 switch (ah->hw_version.macVersion) { 523 case AR_SREV_VERSION_5416_PCI: 524 case AR_SREV_VERSION_5416_PCIE: 525 case AR_SREV_VERSION_9160: 526 case AR_SREV_VERSION_9100: 527 case AR_SREV_VERSION_9280: 528 case AR_SREV_VERSION_9285: 529 case AR_SREV_VERSION_9287: 530 case AR_SREV_VERSION_9271: 531 case AR_SREV_VERSION_9300: 532 case AR_SREV_VERSION_9330: 533 case AR_SREV_VERSION_9485: 534 case AR_SREV_VERSION_9340: 535 case AR_SREV_VERSION_9462: 536 case AR_SREV_VERSION_9550: 537 case AR_SREV_VERSION_9565: 538 case AR_SREV_VERSION_9531: 539 break; 540 default: 541 ath_err(common, 542 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 543 ah->hw_version.macVersion, ah->hw_version.macRev); 544 return -EOPNOTSUPP; 545 } 546 547 /* 548 * Read back AR_WA into a permanent copy and set bits 14 and 17. 549 * We need to do this to avoid RMW of this register. We cannot 550 * read the reg when chip is asleep. 551 */ 552 if (AR_SREV_9300_20_OR_LATER(ah)) { 553 ah->WARegVal = REG_READ(ah, AR_WA); 554 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 555 AR_WA_ASPM_TIMER_BASED_DISABLE); 556 } 557 558 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 559 ath_err(common, "Couldn't reset chip\n"); 560 return -EIO; 561 } 562 563 if (AR_SREV_9565(ah)) { 564 ah->WARegVal |= AR_WA_BIT22; 565 REG_WRITE(ah, AR_WA, ah->WARegVal); 566 } 567 568 ath9k_hw_init_defaults(ah); 569 ath9k_hw_init_config(ah); 570 571 r = ath9k_hw_attach_ops(ah); 572 if (r) 573 return r; 574 575 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 576 ath_err(common, "Couldn't wakeup chip\n"); 577 return -EIO; 578 } 579 580 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 581 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 582 ah->is_pciexpress = false; 583 584 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 585 ath9k_hw_init_cal_settings(ah); 586 587 if (!ah->is_pciexpress) 588 ath9k_hw_disablepcie(ah); 589 590 r = ath9k_hw_post_init(ah); 591 if (r) 592 return r; 593 594 ath9k_hw_init_mode_gain_regs(ah); 595 r = ath9k_hw_fill_cap_info(ah); 596 if (r) 597 return r; 598 599 r = ath9k_hw_init_macaddr(ah); 600 if (r) { 601 ath_err(common, "Failed to initialize MAC address\n"); 602 return r; 603 } 604 605 ath9k_hw_init_hang_checks(ah); 606 607 common->state = ATH_HW_INITIALIZED; 608 609 return 0; 610 } 611 612 int ath9k_hw_init(struct ath_hw *ah) 613 { 614 int ret; 615 struct ath_common *common = ath9k_hw_common(ah); 616 617 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 618 switch (ah->hw_version.devid) { 619 case AR5416_DEVID_PCI: 620 case AR5416_DEVID_PCIE: 621 case AR5416_AR9100_DEVID: 622 case AR9160_DEVID_PCI: 623 case AR9280_DEVID_PCI: 624 case AR9280_DEVID_PCIE: 625 case AR9285_DEVID_PCIE: 626 case AR9287_DEVID_PCI: 627 case AR9287_DEVID_PCIE: 628 case AR2427_DEVID_PCIE: 629 case AR9300_DEVID_PCIE: 630 case AR9300_DEVID_AR9485_PCIE: 631 case AR9300_DEVID_AR9330: 632 case AR9300_DEVID_AR9340: 633 case AR9300_DEVID_QCA955X: 634 case AR9300_DEVID_AR9580: 635 case AR9300_DEVID_AR9462: 636 case AR9485_DEVID_AR1111: 637 case AR9300_DEVID_AR9565: 638 case AR9300_DEVID_AR953X: 639 break; 640 default: 641 if (common->bus_ops->ath_bus_type == ATH_USB) 642 break; 643 ath_err(common, "Hardware device ID 0x%04x not supported\n", 644 ah->hw_version.devid); 645 return -EOPNOTSUPP; 646 } 647 648 ret = __ath9k_hw_init(ah); 649 if (ret) { 650 ath_err(common, 651 "Unable to initialize hardware; initialization status: %d\n", 652 ret); 653 return ret; 654 } 655 656 ath_dynack_init(ah); 657 658 return 0; 659 } 660 EXPORT_SYMBOL(ath9k_hw_init); 661 662 static void ath9k_hw_init_qos(struct ath_hw *ah) 663 { 664 ENABLE_REGWRITE_BUFFER(ah); 665 666 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 667 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 668 669 REG_WRITE(ah, AR_QOS_NO_ACK, 670 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 671 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 672 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 673 674 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 675 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 676 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 677 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 678 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 679 680 REGWRITE_BUFFER_FLUSH(ah); 681 } 682 683 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 684 { 685 struct ath_common *common = ath9k_hw_common(ah); 686 int i = 0; 687 688 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 689 udelay(100); 690 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 691 692 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 693 694 udelay(100); 695 696 if (WARN_ON_ONCE(i >= 100)) { 697 ath_err(common, "PLL4 meaurement not done\n"); 698 break; 699 } 700 701 i++; 702 } 703 704 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 705 } 706 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 707 708 static void ath9k_hw_init_pll(struct ath_hw *ah, 709 struct ath9k_channel *chan) 710 { 711 u32 pll; 712 713 pll = ath9k_hw_compute_pll_control(ah, chan); 714 715 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 716 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 718 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 720 AR_CH0_DPLL2_KD, 0x40); 721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 722 AR_CH0_DPLL2_KI, 0x4); 723 724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 725 AR_CH0_BB_DPLL1_REFDIV, 0x5); 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 727 AR_CH0_BB_DPLL1_NINI, 0x58); 728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 729 AR_CH0_BB_DPLL1_NFRAC, 0x0); 730 731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 732 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 734 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 735 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 736 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 737 738 /* program BB PLL phase_shift to 0x6 */ 739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 740 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 741 742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 743 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 744 udelay(1000); 745 } else if (AR_SREV_9330(ah)) { 746 u32 ddr_dpll2, pll_control2, kd; 747 748 if (ah->is_clk_25mhz) { 749 ddr_dpll2 = 0x18e82f01; 750 pll_control2 = 0xe04a3d; 751 kd = 0x1d; 752 } else { 753 ddr_dpll2 = 0x19e82f01; 754 pll_control2 = 0x886666; 755 kd = 0x3d; 756 } 757 758 /* program DDR PLL ki and kd value */ 759 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 760 761 /* program DDR PLL phase_shift */ 762 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 763 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 764 765 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 766 pll | AR_RTC_9300_PLL_BYPASS); 767 udelay(1000); 768 769 /* program refdiv, nint, frac to RTC register */ 770 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 771 772 /* program BB PLL kd and ki value */ 773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 775 776 /* program BB PLL phase_shift */ 777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 778 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 779 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 780 u32 regval, pll2_divint, pll2_divfrac, refdiv; 781 782 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 783 pll | AR_RTC_9300_SOC_PLL_BYPASS); 784 udelay(1000); 785 786 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 787 udelay(100); 788 789 if (ah->is_clk_25mhz) { 790 if (AR_SREV_9531(ah)) { 791 pll2_divint = 0x1c; 792 pll2_divfrac = 0xa3d2; 793 refdiv = 1; 794 } else { 795 pll2_divint = 0x54; 796 pll2_divfrac = 0x1eb85; 797 refdiv = 3; 798 } 799 } else { 800 if (AR_SREV_9340(ah)) { 801 pll2_divint = 88; 802 pll2_divfrac = 0; 803 refdiv = 5; 804 } else { 805 pll2_divint = 0x11; 806 pll2_divfrac = 807 AR_SREV_9531(ah) ? 0x26665 : 0x26666; 808 refdiv = 1; 809 } 810 } 811 812 regval = REG_READ(ah, AR_PHY_PLL_MODE); 813 if (AR_SREV_9531(ah)) 814 regval |= (0x1 << 22); 815 else 816 regval |= (0x1 << 16); 817 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 818 udelay(100); 819 820 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 821 (pll2_divint << 18) | pll2_divfrac); 822 udelay(100); 823 824 regval = REG_READ(ah, AR_PHY_PLL_MODE); 825 if (AR_SREV_9340(ah)) 826 regval = (regval & 0x80071fff) | 827 (0x1 << 30) | 828 (0x1 << 13) | 829 (0x4 << 26) | 830 (0x18 << 19); 831 else if (AR_SREV_9531(ah)) 832 regval = (regval & 0x01c00fff) | 833 (0x1 << 31) | 834 (0x2 << 29) | 835 (0xa << 25) | 836 (0x1 << 19) | 837 (0x6 << 12); 838 else 839 regval = (regval & 0x80071fff) | 840 (0x3 << 30) | 841 (0x1 << 13) | 842 (0x4 << 26) | 843 (0x60 << 19); 844 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 845 846 if (AR_SREV_9531(ah)) 847 REG_WRITE(ah, AR_PHY_PLL_MODE, 848 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 849 else 850 REG_WRITE(ah, AR_PHY_PLL_MODE, 851 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 852 853 udelay(1000); 854 } 855 856 if (AR_SREV_9565(ah)) 857 pll |= 0x40000; 858 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 859 860 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 861 AR_SREV_9550(ah)) 862 udelay(1000); 863 864 /* Switch the core clock for ar9271 to 117Mhz */ 865 if (AR_SREV_9271(ah)) { 866 udelay(500); 867 REG_WRITE(ah, 0x50040, 0x304); 868 } 869 870 udelay(RTC_PLL_SETTLE_DELAY); 871 872 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 873 } 874 875 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 876 enum nl80211_iftype opmode) 877 { 878 u32 sync_default = AR_INTR_SYNC_DEFAULT; 879 u32 imr_reg = AR_IMR_TXERR | 880 AR_IMR_TXURN | 881 AR_IMR_RXERR | 882 AR_IMR_RXORN | 883 AR_IMR_BCNMISC; 884 885 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 886 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 887 888 if (AR_SREV_9300_20_OR_LATER(ah)) { 889 imr_reg |= AR_IMR_RXOK_HP; 890 if (ah->config.rx_intr_mitigation) 891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 892 else 893 imr_reg |= AR_IMR_RXOK_LP; 894 895 } else { 896 if (ah->config.rx_intr_mitigation) 897 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 898 else 899 imr_reg |= AR_IMR_RXOK; 900 } 901 902 if (ah->config.tx_intr_mitigation) 903 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 904 else 905 imr_reg |= AR_IMR_TXOK; 906 907 ENABLE_REGWRITE_BUFFER(ah); 908 909 REG_WRITE(ah, AR_IMR, imr_reg); 910 ah->imrs2_reg |= AR_IMR_S2_GTT; 911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 912 913 if (!AR_SREV_9100(ah)) { 914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 917 } 918 919 REGWRITE_BUFFER_FLUSH(ah); 920 921 if (AR_SREV_9300_20_OR_LATER(ah)) { 922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 926 } 927 } 928 929 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 930 { 931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 932 val = min(val, (u32) 0xFFFF); 933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 934 } 935 936 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 937 { 938 u32 val = ath9k_hw_mac_to_clks(ah, us); 939 val = min(val, (u32) 0xFFFF); 940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 941 } 942 943 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 944 { 945 u32 val = ath9k_hw_mac_to_clks(ah, us); 946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 948 } 949 950 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 951 { 952 u32 val = ath9k_hw_mac_to_clks(ah, us); 953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 955 } 956 957 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 958 { 959 if (tu > 0xFFFF) { 960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 961 tu); 962 ah->globaltxtimeout = (u32) -1; 963 return false; 964 } else { 965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 966 ah->globaltxtimeout = tu; 967 return true; 968 } 969 } 970 971 void ath9k_hw_init_global_settings(struct ath_hw *ah) 972 { 973 struct ath_common *common = ath9k_hw_common(ah); 974 const struct ath9k_channel *chan = ah->curchan; 975 int acktimeout, ctstimeout, ack_offset = 0; 976 int slottime; 977 int sifstime; 978 int rx_lat = 0, tx_lat = 0, eifs = 0; 979 u32 reg; 980 981 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 982 ah->misc_mode); 983 984 if (!chan) 985 return; 986 987 if (ah->misc_mode != 0) 988 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 989 990 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 991 rx_lat = 41; 992 else 993 rx_lat = 37; 994 tx_lat = 54; 995 996 if (IS_CHAN_5GHZ(chan)) 997 sifstime = 16; 998 else 999 sifstime = 10; 1000 1001 if (IS_CHAN_HALF_RATE(chan)) { 1002 eifs = 175; 1003 rx_lat *= 2; 1004 tx_lat *= 2; 1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1006 tx_lat += 11; 1007 1008 sifstime = 32; 1009 ack_offset = 16; 1010 slottime = 13; 1011 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1012 eifs = 340; 1013 rx_lat = (rx_lat * 4) - 1; 1014 tx_lat *= 4; 1015 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1016 tx_lat += 22; 1017 1018 sifstime = 64; 1019 ack_offset = 32; 1020 slottime = 21; 1021 } else { 1022 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1023 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1024 reg = AR_USEC_ASYNC_FIFO; 1025 } else { 1026 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1027 common->clockrate; 1028 reg = REG_READ(ah, AR_USEC); 1029 } 1030 rx_lat = MS(reg, AR_USEC_RX_LAT); 1031 tx_lat = MS(reg, AR_USEC_TX_LAT); 1032 1033 slottime = ah->slottime; 1034 } 1035 1036 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1037 slottime += 3 * ah->coverage_class; 1038 acktimeout = slottime + sifstime + ack_offset; 1039 ctstimeout = acktimeout; 1040 1041 /* 1042 * Workaround for early ACK timeouts, add an offset to match the 1043 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1044 * This was initially only meant to work around an issue with delayed 1045 * BA frames in some implementations, but it has been found to fix ACK 1046 * timeout issues in other cases as well. 1047 */ 1048 if (IS_CHAN_2GHZ(chan) && 1049 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1050 acktimeout += 64 - sifstime - ah->slottime; 1051 ctstimeout += 48 - sifstime - ah->slottime; 1052 } 1053 1054 if (ah->dynack.enabled) { 1055 acktimeout = ah->dynack.ackto; 1056 ctstimeout = acktimeout; 1057 slottime = (acktimeout - 3) / 2; 1058 } else { 1059 ah->dynack.ackto = acktimeout; 1060 } 1061 1062 ath9k_hw_set_sifs_time(ah, sifstime); 1063 ath9k_hw_setslottime(ah, slottime); 1064 ath9k_hw_set_ack_timeout(ah, acktimeout); 1065 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1066 if (ah->globaltxtimeout != (u32) -1) 1067 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1068 1069 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1070 REG_RMW(ah, AR_USEC, 1071 (common->clockrate - 1) | 1072 SM(rx_lat, AR_USEC_RX_LAT) | 1073 SM(tx_lat, AR_USEC_TX_LAT), 1074 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1075 1076 } 1077 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1078 1079 void ath9k_hw_deinit(struct ath_hw *ah) 1080 { 1081 struct ath_common *common = ath9k_hw_common(ah); 1082 1083 if (common->state < ATH_HW_INITIALIZED) 1084 return; 1085 1086 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1087 } 1088 EXPORT_SYMBOL(ath9k_hw_deinit); 1089 1090 /*******/ 1091 /* INI */ 1092 /*******/ 1093 1094 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1095 { 1096 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1097 1098 if (IS_CHAN_2GHZ(chan)) 1099 ctl |= CTL_11G; 1100 else 1101 ctl |= CTL_11A; 1102 1103 return ctl; 1104 } 1105 1106 /****************************************/ 1107 /* Reset and Channel Switching Routines */ 1108 /****************************************/ 1109 1110 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1111 { 1112 struct ath_common *common = ath9k_hw_common(ah); 1113 int txbuf_size; 1114 1115 ENABLE_REGWRITE_BUFFER(ah); 1116 1117 /* 1118 * set AHB_MODE not to do cacheline prefetches 1119 */ 1120 if (!AR_SREV_9300_20_OR_LATER(ah)) 1121 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1122 1123 /* 1124 * let mac dma reads be in 128 byte chunks 1125 */ 1126 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1127 1128 REGWRITE_BUFFER_FLUSH(ah); 1129 1130 /* 1131 * Restore TX Trigger Level to its pre-reset value. 1132 * The initial value depends on whether aggregation is enabled, and is 1133 * adjusted whenever underruns are detected. 1134 */ 1135 if (!AR_SREV_9300_20_OR_LATER(ah)) 1136 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1137 1138 ENABLE_REGWRITE_BUFFER(ah); 1139 1140 /* 1141 * let mac dma writes be in 128 byte chunks 1142 */ 1143 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1144 1145 /* 1146 * Setup receive FIFO threshold to hold off TX activities 1147 */ 1148 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1149 1150 if (AR_SREV_9300_20_OR_LATER(ah)) { 1151 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1152 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1153 1154 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1155 ah->caps.rx_status_len); 1156 } 1157 1158 /* 1159 * reduce the number of usable entries in PCU TXBUF to avoid 1160 * wrap around issues. 1161 */ 1162 if (AR_SREV_9285(ah)) { 1163 /* For AR9285 the number of Fifos are reduced to half. 1164 * So set the usable tx buf size also to half to 1165 * avoid data/delimiter underruns 1166 */ 1167 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1168 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1169 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1170 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1171 } else { 1172 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1173 } 1174 1175 if (!AR_SREV_9271(ah)) 1176 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1177 1178 REGWRITE_BUFFER_FLUSH(ah); 1179 1180 if (AR_SREV_9300_20_OR_LATER(ah)) 1181 ath9k_hw_reset_txstatus_ring(ah); 1182 } 1183 1184 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1185 { 1186 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1187 u32 set = AR_STA_ID1_KSRCH_MODE; 1188 1189 switch (opmode) { 1190 case NL80211_IFTYPE_ADHOC: 1191 if (!AR_SREV_9340_13(ah)) { 1192 set |= AR_STA_ID1_ADHOC; 1193 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1194 break; 1195 } 1196 /* fall through */ 1197 case NL80211_IFTYPE_MESH_POINT: 1198 case NL80211_IFTYPE_AP: 1199 set |= AR_STA_ID1_STA_AP; 1200 /* fall through */ 1201 case NL80211_IFTYPE_STATION: 1202 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1203 break; 1204 default: 1205 if (!ah->is_monitoring) 1206 set = 0; 1207 break; 1208 } 1209 REG_RMW(ah, AR_STA_ID1, set, mask); 1210 } 1211 1212 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1213 u32 *coef_mantissa, u32 *coef_exponent) 1214 { 1215 u32 coef_exp, coef_man; 1216 1217 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1218 if ((coef_scaled >> coef_exp) & 0x1) 1219 break; 1220 1221 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1222 1223 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1224 1225 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1226 *coef_exponent = coef_exp - 16; 1227 } 1228 1229 /* AR9330 WAR: 1230 * call external reset function to reset WMAC if: 1231 * - doing a cold reset 1232 * - we have pending frames in the TX queues. 1233 */ 1234 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1235 { 1236 int i, npend = 0; 1237 1238 for (i = 0; i < AR_NUM_QCU; i++) { 1239 npend = ath9k_hw_numtxpending(ah, i); 1240 if (npend) 1241 break; 1242 } 1243 1244 if (ah->external_reset && 1245 (npend || type == ATH9K_RESET_COLD)) { 1246 int reset_err = 0; 1247 1248 ath_dbg(ath9k_hw_common(ah), RESET, 1249 "reset MAC via external reset\n"); 1250 1251 reset_err = ah->external_reset(); 1252 if (reset_err) { 1253 ath_err(ath9k_hw_common(ah), 1254 "External reset failed, err=%d\n", 1255 reset_err); 1256 return false; 1257 } 1258 1259 REG_WRITE(ah, AR_RTC_RESET, 1); 1260 } 1261 1262 return true; 1263 } 1264 1265 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1266 { 1267 u32 rst_flags; 1268 u32 tmpReg; 1269 1270 if (AR_SREV_9100(ah)) { 1271 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1272 AR_RTC_DERIVED_CLK_PERIOD, 1); 1273 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1274 } 1275 1276 ENABLE_REGWRITE_BUFFER(ah); 1277 1278 if (AR_SREV_9300_20_OR_LATER(ah)) { 1279 REG_WRITE(ah, AR_WA, ah->WARegVal); 1280 udelay(10); 1281 } 1282 1283 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1284 AR_RTC_FORCE_WAKE_ON_INT); 1285 1286 if (AR_SREV_9100(ah)) { 1287 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1288 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1289 } else { 1290 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1291 if (AR_SREV_9340(ah)) 1292 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1293 else 1294 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1295 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1296 1297 if (tmpReg) { 1298 u32 val; 1299 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1300 1301 val = AR_RC_HOSTIF; 1302 if (!AR_SREV_9300_20_OR_LATER(ah)) 1303 val |= AR_RC_AHB; 1304 REG_WRITE(ah, AR_RC, val); 1305 1306 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1307 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1308 1309 rst_flags = AR_RTC_RC_MAC_WARM; 1310 if (type == ATH9K_RESET_COLD) 1311 rst_flags |= AR_RTC_RC_MAC_COLD; 1312 } 1313 1314 if (AR_SREV_9330(ah)) { 1315 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1316 return false; 1317 } 1318 1319 if (ath9k_hw_mci_is_enabled(ah)) 1320 ar9003_mci_check_gpm_offset(ah); 1321 1322 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1323 1324 REGWRITE_BUFFER_FLUSH(ah); 1325 1326 if (AR_SREV_9300_20_OR_LATER(ah)) 1327 udelay(50); 1328 else if (AR_SREV_9100(ah)) 1329 mdelay(10); 1330 else 1331 udelay(100); 1332 1333 REG_WRITE(ah, AR_RTC_RC, 0); 1334 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1335 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1336 return false; 1337 } 1338 1339 if (!AR_SREV_9100(ah)) 1340 REG_WRITE(ah, AR_RC, 0); 1341 1342 if (AR_SREV_9100(ah)) 1343 udelay(50); 1344 1345 return true; 1346 } 1347 1348 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1349 { 1350 ENABLE_REGWRITE_BUFFER(ah); 1351 1352 if (AR_SREV_9300_20_OR_LATER(ah)) { 1353 REG_WRITE(ah, AR_WA, ah->WARegVal); 1354 udelay(10); 1355 } 1356 1357 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1358 AR_RTC_FORCE_WAKE_ON_INT); 1359 1360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1361 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1362 1363 REG_WRITE(ah, AR_RTC_RESET, 0); 1364 1365 REGWRITE_BUFFER_FLUSH(ah); 1366 1367 udelay(2); 1368 1369 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1370 REG_WRITE(ah, AR_RC, 0); 1371 1372 REG_WRITE(ah, AR_RTC_RESET, 1); 1373 1374 if (!ath9k_hw_wait(ah, 1375 AR_RTC_STATUS, 1376 AR_RTC_STATUS_M, 1377 AR_RTC_STATUS_ON, 1378 AH_WAIT_TIMEOUT)) { 1379 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1380 return false; 1381 } 1382 1383 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1384 } 1385 1386 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1387 { 1388 bool ret = false; 1389 1390 if (AR_SREV_9300_20_OR_LATER(ah)) { 1391 REG_WRITE(ah, AR_WA, ah->WARegVal); 1392 udelay(10); 1393 } 1394 1395 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1396 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1397 1398 if (!ah->reset_power_on) 1399 type = ATH9K_RESET_POWER_ON; 1400 1401 switch (type) { 1402 case ATH9K_RESET_POWER_ON: 1403 ret = ath9k_hw_set_reset_power_on(ah); 1404 if (ret) 1405 ah->reset_power_on = true; 1406 break; 1407 case ATH9K_RESET_WARM: 1408 case ATH9K_RESET_COLD: 1409 ret = ath9k_hw_set_reset(ah, type); 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 return ret; 1416 } 1417 1418 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1419 struct ath9k_channel *chan) 1420 { 1421 int reset_type = ATH9K_RESET_WARM; 1422 1423 if (AR_SREV_9280(ah)) { 1424 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1425 reset_type = ATH9K_RESET_POWER_ON; 1426 else 1427 reset_type = ATH9K_RESET_COLD; 1428 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1429 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1430 reset_type = ATH9K_RESET_COLD; 1431 1432 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1433 return false; 1434 1435 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1436 return false; 1437 1438 ah->chip_fullsleep = false; 1439 1440 if (AR_SREV_9330(ah)) 1441 ar9003_hw_internal_regulator_apply(ah); 1442 ath9k_hw_init_pll(ah, chan); 1443 1444 return true; 1445 } 1446 1447 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1448 struct ath9k_channel *chan) 1449 { 1450 struct ath_common *common = ath9k_hw_common(ah); 1451 struct ath9k_hw_capabilities *pCap = &ah->caps; 1452 bool band_switch = false, mode_diff = false; 1453 u8 ini_reloaded = 0; 1454 u32 qnum; 1455 int r; 1456 1457 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1458 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1459 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1460 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1461 } 1462 1463 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1464 if (ath9k_hw_numtxpending(ah, qnum)) { 1465 ath_dbg(common, QUEUE, 1466 "Transmit frames pending on queue %d\n", qnum); 1467 return false; 1468 } 1469 } 1470 1471 if (!ath9k_hw_rfbus_req(ah)) { 1472 ath_err(common, "Could not kill baseband RX\n"); 1473 return false; 1474 } 1475 1476 if (band_switch || mode_diff) { 1477 ath9k_hw_mark_phy_inactive(ah); 1478 udelay(5); 1479 1480 if (band_switch) 1481 ath9k_hw_init_pll(ah, chan); 1482 1483 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1484 ath_err(common, "Failed to do fast channel change\n"); 1485 return false; 1486 } 1487 } 1488 1489 ath9k_hw_set_channel_regs(ah, chan); 1490 1491 r = ath9k_hw_rf_set_freq(ah, chan); 1492 if (r) { 1493 ath_err(common, "Failed to set channel\n"); 1494 return false; 1495 } 1496 ath9k_hw_set_clockrate(ah); 1497 ath9k_hw_apply_txpower(ah, chan, false); 1498 1499 ath9k_hw_set_delta_slope(ah, chan); 1500 ath9k_hw_spur_mitigate_freq(ah, chan); 1501 1502 if (band_switch || ini_reloaded) 1503 ah->eep_ops->set_board_values(ah, chan); 1504 1505 ath9k_hw_init_bb(ah, chan); 1506 ath9k_hw_rfbus_done(ah); 1507 1508 if (band_switch || ini_reloaded) { 1509 ah->ah_flags |= AH_FASTCC; 1510 ath9k_hw_init_cal(ah, chan); 1511 ah->ah_flags &= ~AH_FASTCC; 1512 } 1513 1514 return true; 1515 } 1516 1517 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1518 { 1519 u32 gpio_mask = ah->gpio_mask; 1520 int i; 1521 1522 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1523 if (!(gpio_mask & 1)) 1524 continue; 1525 1526 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1527 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1528 } 1529 } 1530 1531 void ath9k_hw_check_nav(struct ath_hw *ah) 1532 { 1533 struct ath_common *common = ath9k_hw_common(ah); 1534 u32 val; 1535 1536 val = REG_READ(ah, AR_NAV); 1537 if (val != 0xdeadbeef && val > 0x7fff) { 1538 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1539 REG_WRITE(ah, AR_NAV, 0); 1540 } 1541 } 1542 EXPORT_SYMBOL(ath9k_hw_check_nav); 1543 1544 bool ath9k_hw_check_alive(struct ath_hw *ah) 1545 { 1546 int count = 50; 1547 u32 reg, last_val; 1548 1549 if (AR_SREV_9300(ah)) 1550 return !ath9k_hw_detect_mac_hang(ah); 1551 1552 if (AR_SREV_9285_12_OR_LATER(ah)) 1553 return true; 1554 1555 last_val = REG_READ(ah, AR_OBS_BUS_1); 1556 do { 1557 reg = REG_READ(ah, AR_OBS_BUS_1); 1558 if (reg != last_val) 1559 return true; 1560 1561 udelay(1); 1562 last_val = reg; 1563 if ((reg & 0x7E7FFFEF) == 0x00702400) 1564 continue; 1565 1566 switch (reg & 0x7E000B00) { 1567 case 0x1E000000: 1568 case 0x52000B00: 1569 case 0x18000B00: 1570 continue; 1571 default: 1572 return true; 1573 } 1574 } while (count-- > 0); 1575 1576 return false; 1577 } 1578 EXPORT_SYMBOL(ath9k_hw_check_alive); 1579 1580 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1581 { 1582 /* Setup MFP options for CCMP */ 1583 if (AR_SREV_9280_20_OR_LATER(ah)) { 1584 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1585 * frames when constructing CCMP AAD. */ 1586 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1587 0xc7ff); 1588 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1589 ah->sw_mgmt_crypto_tx = true; 1590 else 1591 ah->sw_mgmt_crypto_tx = false; 1592 ah->sw_mgmt_crypto_rx = false; 1593 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1594 /* Disable hardware crypto for management frames */ 1595 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1596 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1597 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1598 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1599 ah->sw_mgmt_crypto_tx = true; 1600 ah->sw_mgmt_crypto_rx = true; 1601 } else { 1602 ah->sw_mgmt_crypto_tx = true; 1603 ah->sw_mgmt_crypto_rx = true; 1604 } 1605 } 1606 1607 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1608 u32 macStaId1, u32 saveDefAntenna) 1609 { 1610 struct ath_common *common = ath9k_hw_common(ah); 1611 1612 ENABLE_REGWRITE_BUFFER(ah); 1613 1614 REG_RMW(ah, AR_STA_ID1, macStaId1 1615 | AR_STA_ID1_RTS_USE_DEF 1616 | ah->sta_id1_defaults, 1617 ~AR_STA_ID1_SADH_MASK); 1618 ath_hw_setbssidmask(common); 1619 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1620 ath9k_hw_write_associd(ah); 1621 REG_WRITE(ah, AR_ISR, ~0); 1622 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1623 1624 REGWRITE_BUFFER_FLUSH(ah); 1625 1626 ath9k_hw_set_operating_mode(ah, ah->opmode); 1627 } 1628 1629 static void ath9k_hw_init_queues(struct ath_hw *ah) 1630 { 1631 int i; 1632 1633 ENABLE_REGWRITE_BUFFER(ah); 1634 1635 for (i = 0; i < AR_NUM_DCU; i++) 1636 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1637 1638 REGWRITE_BUFFER_FLUSH(ah); 1639 1640 ah->intr_txqs = 0; 1641 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1642 ath9k_hw_resettxqueue(ah, i); 1643 } 1644 1645 /* 1646 * For big endian systems turn on swapping for descriptors 1647 */ 1648 static void ath9k_hw_init_desc(struct ath_hw *ah) 1649 { 1650 struct ath_common *common = ath9k_hw_common(ah); 1651 1652 if (AR_SREV_9100(ah)) { 1653 u32 mask; 1654 mask = REG_READ(ah, AR_CFG); 1655 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1656 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1657 mask); 1658 } else { 1659 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1660 REG_WRITE(ah, AR_CFG, mask); 1661 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1662 REG_READ(ah, AR_CFG)); 1663 } 1664 } else { 1665 if (common->bus_ops->ath_bus_type == ATH_USB) { 1666 /* Configure AR9271 target WLAN */ 1667 if (AR_SREV_9271(ah)) 1668 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1669 else 1670 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1671 } 1672 #ifdef __BIG_ENDIAN 1673 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1674 AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1675 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1676 else 1677 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1678 #endif 1679 } 1680 } 1681 1682 /* 1683 * Fast channel change: 1684 * (Change synthesizer based on channel freq without resetting chip) 1685 */ 1686 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1687 { 1688 struct ath_common *common = ath9k_hw_common(ah); 1689 struct ath9k_hw_capabilities *pCap = &ah->caps; 1690 int ret; 1691 1692 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1693 goto fail; 1694 1695 if (ah->chip_fullsleep) 1696 goto fail; 1697 1698 if (!ah->curchan) 1699 goto fail; 1700 1701 if (chan->channel == ah->curchan->channel) 1702 goto fail; 1703 1704 if ((ah->curchan->channelFlags | chan->channelFlags) & 1705 (CHANNEL_HALF | CHANNEL_QUARTER)) 1706 goto fail; 1707 1708 /* 1709 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1710 */ 1711 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1712 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1713 goto fail; 1714 1715 if (!ath9k_hw_check_alive(ah)) 1716 goto fail; 1717 1718 /* 1719 * For AR9462, make sure that calibration data for 1720 * re-using are present. 1721 */ 1722 if (AR_SREV_9462(ah) && (ah->caldata && 1723 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1724 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1725 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1726 goto fail; 1727 1728 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1729 ah->curchan->channel, chan->channel); 1730 1731 ret = ath9k_hw_channel_change(ah, chan); 1732 if (!ret) 1733 goto fail; 1734 1735 if (ath9k_hw_mci_is_enabled(ah)) 1736 ar9003_mci_2g5g_switch(ah, false); 1737 1738 ath9k_hw_loadnf(ah, ah->curchan); 1739 ath9k_hw_start_nfcal(ah, true); 1740 1741 if (AR_SREV_9271(ah)) 1742 ar9002_hw_load_ani_reg(ah, chan); 1743 1744 return 0; 1745 fail: 1746 return -EINVAL; 1747 } 1748 1749 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1750 { 1751 struct timespec ts; 1752 s64 usec; 1753 1754 if (!cur) { 1755 getrawmonotonic(&ts); 1756 cur = &ts; 1757 } 1758 1759 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1760 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1761 1762 return (u32) usec; 1763 } 1764 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1765 1766 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1767 struct ath9k_hw_cal_data *caldata, bool fastcc) 1768 { 1769 struct ath_common *common = ath9k_hw_common(ah); 1770 u32 saveLedState; 1771 u32 saveDefAntenna; 1772 u32 macStaId1; 1773 u64 tsf = 0; 1774 s64 usec = 0; 1775 int r; 1776 bool start_mci_reset = false; 1777 bool save_fullsleep = ah->chip_fullsleep; 1778 1779 if (ath9k_hw_mci_is_enabled(ah)) { 1780 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1781 if (start_mci_reset) 1782 return 0; 1783 } 1784 1785 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1786 return -EIO; 1787 1788 if (ah->curchan && !ah->chip_fullsleep) 1789 ath9k_hw_getnf(ah, ah->curchan); 1790 1791 ah->caldata = caldata; 1792 if (caldata && (chan->channel != caldata->channel || 1793 chan->channelFlags != caldata->channelFlags)) { 1794 /* Operating channel changed, reset channel calibration data */ 1795 memset(caldata, 0, sizeof(*caldata)); 1796 ath9k_init_nfcal_hist_buffer(ah, chan); 1797 } else if (caldata) { 1798 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1799 } 1800 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1801 1802 if (fastcc) { 1803 r = ath9k_hw_do_fastcc(ah, chan); 1804 if (!r) 1805 return r; 1806 } 1807 1808 if (ath9k_hw_mci_is_enabled(ah)) 1809 ar9003_mci_stop_bt(ah, save_fullsleep); 1810 1811 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1812 if (saveDefAntenna == 0) 1813 saveDefAntenna = 1; 1814 1815 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1816 1817 /* Save TSF before chip reset, a cold reset clears it */ 1818 tsf = ath9k_hw_gettsf64(ah); 1819 usec = ktime_to_us(ktime_get_raw()); 1820 1821 saveLedState = REG_READ(ah, AR_CFG_LED) & 1822 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1823 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1824 1825 ath9k_hw_mark_phy_inactive(ah); 1826 1827 ah->paprd_table_write_done = false; 1828 1829 /* Only required on the first reset */ 1830 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1831 REG_WRITE(ah, 1832 AR9271_RESET_POWER_DOWN_CONTROL, 1833 AR9271_RADIO_RF_RST); 1834 udelay(50); 1835 } 1836 1837 if (!ath9k_hw_chip_reset(ah, chan)) { 1838 ath_err(common, "Chip reset failed\n"); 1839 return -EINVAL; 1840 } 1841 1842 /* Only required on the first reset */ 1843 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1844 ah->htc_reset_init = false; 1845 REG_WRITE(ah, 1846 AR9271_RESET_POWER_DOWN_CONTROL, 1847 AR9271_GATE_MAC_CTL); 1848 udelay(50); 1849 } 1850 1851 /* Restore TSF */ 1852 usec = ktime_to_us(ktime_get_raw()) - usec; 1853 ath9k_hw_settsf64(ah, tsf + usec); 1854 1855 if (AR_SREV_9280_20_OR_LATER(ah)) 1856 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1857 1858 if (!AR_SREV_9300_20_OR_LATER(ah)) 1859 ar9002_hw_enable_async_fifo(ah); 1860 1861 r = ath9k_hw_process_ini(ah, chan); 1862 if (r) 1863 return r; 1864 1865 ath9k_hw_set_rfmode(ah, chan); 1866 1867 if (ath9k_hw_mci_is_enabled(ah)) 1868 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1869 1870 /* 1871 * Some AR91xx SoC devices frequently fail to accept TSF writes 1872 * right after the chip reset. When that happens, write a new 1873 * value after the initvals have been applied, with an offset 1874 * based on measured time difference 1875 */ 1876 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1877 tsf += 1500; 1878 ath9k_hw_settsf64(ah, tsf); 1879 } 1880 1881 ath9k_hw_init_mfp(ah); 1882 1883 ath9k_hw_set_delta_slope(ah, chan); 1884 ath9k_hw_spur_mitigate_freq(ah, chan); 1885 ah->eep_ops->set_board_values(ah, chan); 1886 1887 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1888 1889 r = ath9k_hw_rf_set_freq(ah, chan); 1890 if (r) 1891 return r; 1892 1893 ath9k_hw_set_clockrate(ah); 1894 1895 ath9k_hw_init_queues(ah); 1896 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1897 ath9k_hw_ani_cache_ini_regs(ah); 1898 ath9k_hw_init_qos(ah); 1899 1900 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1901 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1902 1903 ath9k_hw_init_global_settings(ah); 1904 1905 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1906 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1907 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1908 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1909 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1910 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1911 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1912 } 1913 1914 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1915 1916 ath9k_hw_set_dma(ah); 1917 1918 if (!ath9k_hw_mci_is_enabled(ah)) 1919 REG_WRITE(ah, AR_OBS, 8); 1920 1921 if (ah->config.rx_intr_mitigation) { 1922 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1923 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1924 } 1925 1926 if (ah->config.tx_intr_mitigation) { 1927 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1928 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1929 } 1930 1931 ath9k_hw_init_bb(ah, chan); 1932 1933 if (caldata) { 1934 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1935 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1936 } 1937 if (!ath9k_hw_init_cal(ah, chan)) 1938 return -EIO; 1939 1940 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1941 return -EIO; 1942 1943 ENABLE_REGWRITE_BUFFER(ah); 1944 1945 ath9k_hw_restore_chainmask(ah); 1946 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1947 1948 REGWRITE_BUFFER_FLUSH(ah); 1949 1950 ath9k_hw_gen_timer_start_tsf2(ah); 1951 1952 ath9k_hw_init_desc(ah); 1953 1954 if (ath9k_hw_btcoex_is_enabled(ah)) 1955 ath9k_hw_btcoex_enable(ah); 1956 1957 if (ath9k_hw_mci_is_enabled(ah)) 1958 ar9003_mci_check_bt(ah); 1959 1960 if (AR_SREV_9300_20_OR_LATER(ah)) { 1961 ath9k_hw_loadnf(ah, chan); 1962 ath9k_hw_start_nfcal(ah, true); 1963 } 1964 1965 if (AR_SREV_9300_20_OR_LATER(ah)) 1966 ar9003_hw_bb_watchdog_config(ah); 1967 1968 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1969 ar9003_hw_disable_phy_restart(ah); 1970 1971 ath9k_hw_apply_gpio_override(ah); 1972 1973 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1974 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1975 1976 if (ah->hw->conf.radar_enabled) { 1977 /* set HW specific DFS configuration */ 1978 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 1979 ath9k_hw_set_radar_params(ah); 1980 } 1981 1982 return 0; 1983 } 1984 EXPORT_SYMBOL(ath9k_hw_reset); 1985 1986 /******************************/ 1987 /* Power Management (Chipset) */ 1988 /******************************/ 1989 1990 /* 1991 * Notify Power Mgt is disabled in self-generated frames. 1992 * If requested, force chip to sleep. 1993 */ 1994 static void ath9k_set_power_sleep(struct ath_hw *ah) 1995 { 1996 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1997 1998 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1999 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2000 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2001 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2002 /* xxx Required for WLAN only case ? */ 2003 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2004 udelay(100); 2005 } 2006 2007 /* 2008 * Clear the RTC force wake bit to allow the 2009 * mac to go to sleep. 2010 */ 2011 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2012 2013 if (ath9k_hw_mci_is_enabled(ah)) 2014 udelay(100); 2015 2016 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2017 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2018 2019 /* Shutdown chip. Active low */ 2020 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2021 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2022 udelay(2); 2023 } 2024 2025 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2026 if (AR_SREV_9300_20_OR_LATER(ah)) 2027 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2028 } 2029 2030 /* 2031 * Notify Power Management is enabled in self-generating 2032 * frames. If request, set power mode of chip to 2033 * auto/normal. Duration in units of 128us (1/8 TU). 2034 */ 2035 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2036 { 2037 struct ath9k_hw_capabilities *pCap = &ah->caps; 2038 2039 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2040 2041 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2042 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2043 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2044 AR_RTC_FORCE_WAKE_ON_INT); 2045 } else { 2046 2047 /* When chip goes into network sleep, it could be waken 2048 * up by MCI_INT interrupt caused by BT's HW messages 2049 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2050 * rate (~100us). This will cause chip to leave and 2051 * re-enter network sleep mode frequently, which in 2052 * consequence will have WLAN MCI HW to generate lots of 2053 * SYS_WAKING and SYS_SLEEPING messages which will make 2054 * BT CPU to busy to process. 2055 */ 2056 if (ath9k_hw_mci_is_enabled(ah)) 2057 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2058 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2059 /* 2060 * Clear the RTC force wake bit to allow the 2061 * mac to go to sleep. 2062 */ 2063 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2064 2065 if (ath9k_hw_mci_is_enabled(ah)) 2066 udelay(30); 2067 } 2068 2069 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2070 if (AR_SREV_9300_20_OR_LATER(ah)) 2071 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2072 } 2073 2074 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2075 { 2076 u32 val; 2077 int i; 2078 2079 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2080 if (AR_SREV_9300_20_OR_LATER(ah)) { 2081 REG_WRITE(ah, AR_WA, ah->WARegVal); 2082 udelay(10); 2083 } 2084 2085 if ((REG_READ(ah, AR_RTC_STATUS) & 2086 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2087 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2088 return false; 2089 } 2090 if (!AR_SREV_9300_20_OR_LATER(ah)) 2091 ath9k_hw_init_pll(ah, NULL); 2092 } 2093 if (AR_SREV_9100(ah)) 2094 REG_SET_BIT(ah, AR_RTC_RESET, 2095 AR_RTC_RESET_EN); 2096 2097 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2098 AR_RTC_FORCE_WAKE_EN); 2099 if (AR_SREV_9100(ah)) 2100 mdelay(10); 2101 else 2102 udelay(50); 2103 2104 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2105 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2106 if (val == AR_RTC_STATUS_ON) 2107 break; 2108 udelay(50); 2109 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2110 AR_RTC_FORCE_WAKE_EN); 2111 } 2112 if (i == 0) { 2113 ath_err(ath9k_hw_common(ah), 2114 "Failed to wakeup in %uus\n", 2115 POWER_UP_TIME / 20); 2116 return false; 2117 } 2118 2119 if (ath9k_hw_mci_is_enabled(ah)) 2120 ar9003_mci_set_power_awake(ah); 2121 2122 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2123 2124 return true; 2125 } 2126 2127 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2128 { 2129 struct ath_common *common = ath9k_hw_common(ah); 2130 int status = true; 2131 static const char *modes[] = { 2132 "AWAKE", 2133 "FULL-SLEEP", 2134 "NETWORK SLEEP", 2135 "UNDEFINED" 2136 }; 2137 2138 if (ah->power_mode == mode) 2139 return status; 2140 2141 ath_dbg(common, RESET, "%s -> %s\n", 2142 modes[ah->power_mode], modes[mode]); 2143 2144 switch (mode) { 2145 case ATH9K_PM_AWAKE: 2146 status = ath9k_hw_set_power_awake(ah); 2147 break; 2148 case ATH9K_PM_FULL_SLEEP: 2149 if (ath9k_hw_mci_is_enabled(ah)) 2150 ar9003_mci_set_full_sleep(ah); 2151 2152 ath9k_set_power_sleep(ah); 2153 ah->chip_fullsleep = true; 2154 break; 2155 case ATH9K_PM_NETWORK_SLEEP: 2156 ath9k_set_power_network_sleep(ah); 2157 break; 2158 default: 2159 ath_err(common, "Unknown power mode %u\n", mode); 2160 return false; 2161 } 2162 ah->power_mode = mode; 2163 2164 /* 2165 * XXX: If this warning never comes up after a while then 2166 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2167 * ath9k_hw_setpower() return type void. 2168 */ 2169 2170 if (!(ah->ah_flags & AH_UNPLUGGED)) 2171 ATH_DBG_WARN_ON_ONCE(!status); 2172 2173 return status; 2174 } 2175 EXPORT_SYMBOL(ath9k_hw_setpower); 2176 2177 /*******************/ 2178 /* Beacon Handling */ 2179 /*******************/ 2180 2181 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2182 { 2183 int flags = 0; 2184 2185 ENABLE_REGWRITE_BUFFER(ah); 2186 2187 switch (ah->opmode) { 2188 case NL80211_IFTYPE_ADHOC: 2189 REG_SET_BIT(ah, AR_TXCFG, 2190 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2191 case NL80211_IFTYPE_MESH_POINT: 2192 case NL80211_IFTYPE_AP: 2193 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2194 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2195 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2196 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2197 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2198 flags |= 2199 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2200 break; 2201 default: 2202 ath_dbg(ath9k_hw_common(ah), BEACON, 2203 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2204 return; 2205 break; 2206 } 2207 2208 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2209 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2210 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2211 2212 REGWRITE_BUFFER_FLUSH(ah); 2213 2214 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2215 } 2216 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2217 2218 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2219 const struct ath9k_beacon_state *bs) 2220 { 2221 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2222 struct ath9k_hw_capabilities *pCap = &ah->caps; 2223 struct ath_common *common = ath9k_hw_common(ah); 2224 2225 ENABLE_REGWRITE_BUFFER(ah); 2226 2227 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2228 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2229 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2230 2231 REGWRITE_BUFFER_FLUSH(ah); 2232 2233 REG_RMW_FIELD(ah, AR_RSSI_THR, 2234 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2235 2236 beaconintval = bs->bs_intval; 2237 2238 if (bs->bs_sleepduration > beaconintval) 2239 beaconintval = bs->bs_sleepduration; 2240 2241 dtimperiod = bs->bs_dtimperiod; 2242 if (bs->bs_sleepduration > dtimperiod) 2243 dtimperiod = bs->bs_sleepduration; 2244 2245 if (beaconintval == dtimperiod) 2246 nextTbtt = bs->bs_nextdtim; 2247 else 2248 nextTbtt = bs->bs_nexttbtt; 2249 2250 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2251 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2252 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2253 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2254 2255 ENABLE_REGWRITE_BUFFER(ah); 2256 2257 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2258 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2259 2260 REG_WRITE(ah, AR_SLEEP1, 2261 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2262 | AR_SLEEP1_ASSUME_DTIM); 2263 2264 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2265 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2266 else 2267 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2268 2269 REG_WRITE(ah, AR_SLEEP2, 2270 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2271 2272 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2273 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2274 2275 REGWRITE_BUFFER_FLUSH(ah); 2276 2277 REG_SET_BIT(ah, AR_TIMER_MODE, 2278 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2279 AR_DTIM_TIMER_EN); 2280 2281 /* TSF Out of Range Threshold */ 2282 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2283 } 2284 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2285 2286 /*******************/ 2287 /* HW Capabilities */ 2288 /*******************/ 2289 2290 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2291 { 2292 eeprom_chainmask &= chip_chainmask; 2293 if (eeprom_chainmask) 2294 return eeprom_chainmask; 2295 else 2296 return chip_chainmask; 2297 } 2298 2299 /** 2300 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2301 * @ah: the atheros hardware data structure 2302 * 2303 * We enable DFS support upstream on chipsets which have passed a series 2304 * of tests. The testing requirements are going to be documented. Desired 2305 * test requirements are documented at: 2306 * 2307 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2308 * 2309 * Once a new chipset gets properly tested an individual commit can be used 2310 * to document the testing for DFS for that chipset. 2311 */ 2312 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2313 { 2314 2315 switch (ah->hw_version.macVersion) { 2316 /* for temporary testing DFS with 9280 */ 2317 case AR_SREV_VERSION_9280: 2318 /* AR9580 will likely be our first target to get testing on */ 2319 case AR_SREV_VERSION_9580: 2320 return true; 2321 default: 2322 return false; 2323 } 2324 } 2325 2326 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2327 { 2328 struct ath9k_hw_capabilities *pCap = &ah->caps; 2329 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2330 struct ath_common *common = ath9k_hw_common(ah); 2331 2332 u16 eeval; 2333 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2334 2335 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2336 regulatory->current_rd = eeval; 2337 2338 if (ah->opmode != NL80211_IFTYPE_AP && 2339 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2340 if (regulatory->current_rd == 0x64 || 2341 regulatory->current_rd == 0x65) 2342 regulatory->current_rd += 5; 2343 else if (regulatory->current_rd == 0x41) 2344 regulatory->current_rd = 0x43; 2345 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2346 regulatory->current_rd); 2347 } 2348 2349 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2350 2351 if (eeval & AR5416_OPFLAGS_11A) { 2352 if (ah->disable_5ghz) 2353 ath_warn(common, "disabling 5GHz band\n"); 2354 else 2355 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2356 } 2357 2358 if (eeval & AR5416_OPFLAGS_11G) { 2359 if (ah->disable_2ghz) 2360 ath_warn(common, "disabling 2GHz band\n"); 2361 else 2362 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2363 } 2364 2365 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2366 ath_err(common, "both bands are disabled\n"); 2367 return -EINVAL; 2368 } 2369 2370 if (AR_SREV_9485(ah) || 2371 AR_SREV_9285(ah) || 2372 AR_SREV_9330(ah) || 2373 AR_SREV_9565(ah)) 2374 pCap->chip_chainmask = 1; 2375 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2376 pCap->chip_chainmask = 7; 2377 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2378 AR_SREV_9340(ah) || 2379 AR_SREV_9462(ah) || 2380 AR_SREV_9531(ah)) 2381 pCap->chip_chainmask = 3; 2382 else 2383 pCap->chip_chainmask = 7; 2384 2385 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2386 /* 2387 * For AR9271 we will temporarilly uses the rx chainmax as read from 2388 * the EEPROM. 2389 */ 2390 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2391 !(eeval & AR5416_OPFLAGS_11A) && 2392 !(AR_SREV_9271(ah))) 2393 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2394 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2395 else if (AR_SREV_9100(ah)) 2396 pCap->rx_chainmask = 0x7; 2397 else 2398 /* Use rx_chainmask from EEPROM. */ 2399 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2400 2401 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2402 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2403 ah->txchainmask = pCap->tx_chainmask; 2404 ah->rxchainmask = pCap->rx_chainmask; 2405 2406 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2407 2408 /* enable key search for every frame in an aggregate */ 2409 if (AR_SREV_9300_20_OR_LATER(ah)) 2410 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2411 2412 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2413 2414 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2415 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2416 else 2417 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2418 2419 if (AR_SREV_9271(ah)) 2420 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2421 else if (AR_DEVID_7010(ah)) 2422 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2423 else if (AR_SREV_9300_20_OR_LATER(ah)) 2424 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2425 else if (AR_SREV_9287_11_OR_LATER(ah)) 2426 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2427 else if (AR_SREV_9285_12_OR_LATER(ah)) 2428 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2429 else if (AR_SREV_9280_20_OR_LATER(ah)) 2430 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2431 else 2432 pCap->num_gpio_pins = AR_NUM_GPIO; 2433 2434 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2435 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2436 else 2437 pCap->rts_aggr_limit = (8 * 1024); 2438 2439 #ifdef CONFIG_ATH9K_RFKILL 2440 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2441 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2442 ah->rfkill_gpio = 2443 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2444 ah->rfkill_polarity = 2445 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2446 2447 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2448 } 2449 #endif 2450 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2451 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2452 else 2453 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2454 2455 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2456 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2457 else 2458 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2459 2460 if (AR_SREV_9300_20_OR_LATER(ah)) { 2461 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2462 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2463 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2464 2465 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2466 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2467 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2468 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2469 pCap->txs_len = sizeof(struct ar9003_txs); 2470 } else { 2471 pCap->tx_desc_len = sizeof(struct ath_desc); 2472 if (AR_SREV_9280_20(ah)) 2473 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2474 } 2475 2476 if (AR_SREV_9300_20_OR_LATER(ah)) 2477 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2478 2479 if (AR_SREV_9300_20_OR_LATER(ah)) 2480 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2481 2482 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2483 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2484 2485 if (AR_SREV_9285(ah)) { 2486 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2487 ant_div_ctl1 = 2488 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2489 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2490 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2491 ath_info(common, "Enable LNA combining\n"); 2492 } 2493 } 2494 } 2495 2496 if (AR_SREV_9300_20_OR_LATER(ah)) { 2497 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2498 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2499 } 2500 2501 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2502 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2503 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2504 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2505 ath_info(common, "Enable LNA combining\n"); 2506 } 2507 } 2508 2509 if (ath9k_hw_dfs_tested(ah)) 2510 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2511 2512 tx_chainmask = pCap->tx_chainmask; 2513 rx_chainmask = pCap->rx_chainmask; 2514 while (tx_chainmask || rx_chainmask) { 2515 if (tx_chainmask & BIT(0)) 2516 pCap->max_txchains++; 2517 if (rx_chainmask & BIT(0)) 2518 pCap->max_rxchains++; 2519 2520 tx_chainmask >>= 1; 2521 rx_chainmask >>= 1; 2522 } 2523 2524 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2525 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2526 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2527 2528 if (AR_SREV_9462_20_OR_LATER(ah)) 2529 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2530 } 2531 2532 if (AR_SREV_9462(ah)) 2533 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2534 2535 if (AR_SREV_9300_20_OR_LATER(ah) && 2536 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2537 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2538 2539 return 0; 2540 } 2541 2542 /****************************/ 2543 /* GPIO / RFKILL / Antennae */ 2544 /****************************/ 2545 2546 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2547 u32 gpio, u32 type) 2548 { 2549 int addr; 2550 u32 gpio_shift, tmp; 2551 2552 if (gpio > 11) 2553 addr = AR_GPIO_OUTPUT_MUX3; 2554 else if (gpio > 5) 2555 addr = AR_GPIO_OUTPUT_MUX2; 2556 else 2557 addr = AR_GPIO_OUTPUT_MUX1; 2558 2559 gpio_shift = (gpio % 6) * 5; 2560 2561 if (AR_SREV_9280_20_OR_LATER(ah) 2562 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2563 REG_RMW(ah, addr, (type << gpio_shift), 2564 (0x1f << gpio_shift)); 2565 } else { 2566 tmp = REG_READ(ah, addr); 2567 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2568 tmp &= ~(0x1f << gpio_shift); 2569 tmp |= (type << gpio_shift); 2570 REG_WRITE(ah, addr, tmp); 2571 } 2572 } 2573 2574 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2575 { 2576 u32 gpio_shift; 2577 2578 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2579 2580 if (AR_DEVID_7010(ah)) { 2581 gpio_shift = gpio; 2582 REG_RMW(ah, AR7010_GPIO_OE, 2583 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2584 (AR7010_GPIO_OE_MASK << gpio_shift)); 2585 return; 2586 } 2587 2588 gpio_shift = gpio << 1; 2589 REG_RMW(ah, 2590 AR_GPIO_OE_OUT, 2591 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2592 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2593 } 2594 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2595 2596 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2597 { 2598 #define MS_REG_READ(x, y) \ 2599 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2600 2601 if (gpio >= ah->caps.num_gpio_pins) 2602 return 0xffffffff; 2603 2604 if (AR_DEVID_7010(ah)) { 2605 u32 val; 2606 val = REG_READ(ah, AR7010_GPIO_IN); 2607 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2608 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2609 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2610 AR_GPIO_BIT(gpio)) != 0; 2611 else if (AR_SREV_9271(ah)) 2612 return MS_REG_READ(AR9271, gpio) != 0; 2613 else if (AR_SREV_9287_11_OR_LATER(ah)) 2614 return MS_REG_READ(AR9287, gpio) != 0; 2615 else if (AR_SREV_9285_12_OR_LATER(ah)) 2616 return MS_REG_READ(AR9285, gpio) != 0; 2617 else if (AR_SREV_9280_20_OR_LATER(ah)) 2618 return MS_REG_READ(AR928X, gpio) != 0; 2619 else 2620 return MS_REG_READ(AR, gpio) != 0; 2621 } 2622 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2623 2624 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2625 u32 ah_signal_type) 2626 { 2627 u32 gpio_shift; 2628 2629 if (AR_DEVID_7010(ah)) { 2630 gpio_shift = gpio; 2631 REG_RMW(ah, AR7010_GPIO_OE, 2632 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2633 (AR7010_GPIO_OE_MASK << gpio_shift)); 2634 return; 2635 } 2636 2637 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2638 gpio_shift = 2 * gpio; 2639 REG_RMW(ah, 2640 AR_GPIO_OE_OUT, 2641 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2642 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2643 } 2644 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2645 2646 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2647 { 2648 if (AR_DEVID_7010(ah)) { 2649 val = val ? 0 : 1; 2650 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2651 AR_GPIO_BIT(gpio)); 2652 return; 2653 } 2654 2655 if (AR_SREV_9271(ah)) 2656 val = ~val; 2657 2658 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2659 AR_GPIO_BIT(gpio)); 2660 } 2661 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2662 2663 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2664 { 2665 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2666 } 2667 EXPORT_SYMBOL(ath9k_hw_setantenna); 2668 2669 /*********************/ 2670 /* General Operation */ 2671 /*********************/ 2672 2673 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2674 { 2675 u32 bits = REG_READ(ah, AR_RX_FILTER); 2676 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2677 2678 if (phybits & AR_PHY_ERR_RADAR) 2679 bits |= ATH9K_RX_FILTER_PHYRADAR; 2680 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2681 bits |= ATH9K_RX_FILTER_PHYERR; 2682 2683 return bits; 2684 } 2685 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2686 2687 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2688 { 2689 u32 phybits; 2690 2691 ENABLE_REGWRITE_BUFFER(ah); 2692 2693 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2694 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2695 2696 REG_WRITE(ah, AR_RX_FILTER, bits); 2697 2698 phybits = 0; 2699 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2700 phybits |= AR_PHY_ERR_RADAR; 2701 if (bits & ATH9K_RX_FILTER_PHYERR) 2702 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2703 REG_WRITE(ah, AR_PHY_ERR, phybits); 2704 2705 if (phybits) 2706 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2707 else 2708 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2709 2710 REGWRITE_BUFFER_FLUSH(ah); 2711 } 2712 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2713 2714 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2715 { 2716 if (ath9k_hw_mci_is_enabled(ah)) 2717 ar9003_mci_bt_gain_ctrl(ah); 2718 2719 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2720 return false; 2721 2722 ath9k_hw_init_pll(ah, NULL); 2723 ah->htc_reset_init = true; 2724 return true; 2725 } 2726 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2727 2728 bool ath9k_hw_disable(struct ath_hw *ah) 2729 { 2730 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2731 return false; 2732 2733 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2734 return false; 2735 2736 ath9k_hw_init_pll(ah, NULL); 2737 return true; 2738 } 2739 EXPORT_SYMBOL(ath9k_hw_disable); 2740 2741 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2742 { 2743 enum eeprom_param gain_param; 2744 2745 if (IS_CHAN_2GHZ(chan)) 2746 gain_param = EEP_ANTENNA_GAIN_2G; 2747 else 2748 gain_param = EEP_ANTENNA_GAIN_5G; 2749 2750 return ah->eep_ops->get_eeprom(ah, gain_param); 2751 } 2752 2753 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2754 bool test) 2755 { 2756 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2757 struct ieee80211_channel *channel; 2758 int chan_pwr, new_pwr, max_gain; 2759 int ant_gain, ant_reduction = 0; 2760 2761 if (!chan) 2762 return; 2763 2764 channel = chan->chan; 2765 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2766 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2767 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2768 2769 ant_gain = get_antenna_gain(ah, chan); 2770 if (ant_gain > max_gain) 2771 ant_reduction = ant_gain - max_gain; 2772 2773 ah->eep_ops->set_txpower(ah, chan, 2774 ath9k_regd_get_ctl(reg, chan), 2775 ant_reduction, new_pwr, test); 2776 } 2777 2778 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2779 { 2780 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2781 struct ath9k_channel *chan = ah->curchan; 2782 struct ieee80211_channel *channel = chan->chan; 2783 2784 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2785 if (test) 2786 channel->max_power = MAX_RATE_POWER / 2; 2787 2788 ath9k_hw_apply_txpower(ah, chan, test); 2789 2790 if (test) 2791 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2792 } 2793 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2794 2795 void ath9k_hw_setopmode(struct ath_hw *ah) 2796 { 2797 ath9k_hw_set_operating_mode(ah, ah->opmode); 2798 } 2799 EXPORT_SYMBOL(ath9k_hw_setopmode); 2800 2801 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2802 { 2803 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2804 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2805 } 2806 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2807 2808 void ath9k_hw_write_associd(struct ath_hw *ah) 2809 { 2810 struct ath_common *common = ath9k_hw_common(ah); 2811 2812 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2813 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2814 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2815 } 2816 EXPORT_SYMBOL(ath9k_hw_write_associd); 2817 2818 #define ATH9K_MAX_TSF_READ 10 2819 2820 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2821 { 2822 u32 tsf_lower, tsf_upper1, tsf_upper2; 2823 int i; 2824 2825 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2826 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2827 tsf_lower = REG_READ(ah, AR_TSF_L32); 2828 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2829 if (tsf_upper2 == tsf_upper1) 2830 break; 2831 tsf_upper1 = tsf_upper2; 2832 } 2833 2834 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2835 2836 return (((u64)tsf_upper1 << 32) | tsf_lower); 2837 } 2838 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2839 2840 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2841 { 2842 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2843 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2844 } 2845 EXPORT_SYMBOL(ath9k_hw_settsf64); 2846 2847 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2848 { 2849 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2850 AH_TSF_WRITE_TIMEOUT)) 2851 ath_dbg(ath9k_hw_common(ah), RESET, 2852 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2853 2854 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2855 } 2856 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2857 2858 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2859 { 2860 if (set) 2861 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2862 else 2863 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2864 } 2865 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2866 2867 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2868 { 2869 u32 macmode; 2870 2871 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2872 macmode = AR_2040_JOINED_RX_CLEAR; 2873 else 2874 macmode = 0; 2875 2876 REG_WRITE(ah, AR_2040_MODE, macmode); 2877 } 2878 2879 /* HW Generic timers configuration */ 2880 2881 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2882 { 2883 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2884 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2885 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2886 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2887 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2888 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2889 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2890 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2891 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2892 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2893 AR_NDP2_TIMER_MODE, 0x0002}, 2894 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2895 AR_NDP2_TIMER_MODE, 0x0004}, 2896 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2897 AR_NDP2_TIMER_MODE, 0x0008}, 2898 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2899 AR_NDP2_TIMER_MODE, 0x0010}, 2900 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2901 AR_NDP2_TIMER_MODE, 0x0020}, 2902 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2903 AR_NDP2_TIMER_MODE, 0x0040}, 2904 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2905 AR_NDP2_TIMER_MODE, 0x0080} 2906 }; 2907 2908 /* HW generic timer primitives */ 2909 2910 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2911 { 2912 return REG_READ(ah, AR_TSF_L32); 2913 } 2914 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2915 2916 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 2917 { 2918 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2919 2920 if (timer_table->tsf2_enabled) { 2921 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 2922 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 2923 } 2924 } 2925 2926 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2927 void (*trigger)(void *), 2928 void (*overflow)(void *), 2929 void *arg, 2930 u8 timer_index) 2931 { 2932 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2933 struct ath_gen_timer *timer; 2934 2935 if ((timer_index < AR_FIRST_NDP_TIMER) || 2936 (timer_index >= ATH_MAX_GEN_TIMER)) 2937 return NULL; 2938 2939 if ((timer_index > AR_FIRST_NDP_TIMER) && 2940 !AR_SREV_9300_20_OR_LATER(ah)) 2941 return NULL; 2942 2943 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2944 if (timer == NULL) 2945 return NULL; 2946 2947 /* allocate a hardware generic timer slot */ 2948 timer_table->timers[timer_index] = timer; 2949 timer->index = timer_index; 2950 timer->trigger = trigger; 2951 timer->overflow = overflow; 2952 timer->arg = arg; 2953 2954 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 2955 timer_table->tsf2_enabled = true; 2956 ath9k_hw_gen_timer_start_tsf2(ah); 2957 } 2958 2959 return timer; 2960 } 2961 EXPORT_SYMBOL(ath_gen_timer_alloc); 2962 2963 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2964 struct ath_gen_timer *timer, 2965 u32 timer_next, 2966 u32 timer_period) 2967 { 2968 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2969 u32 mask = 0; 2970 2971 timer_table->timer_mask |= BIT(timer->index); 2972 2973 /* 2974 * Program generic timer registers 2975 */ 2976 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2977 timer_next); 2978 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2979 timer_period); 2980 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2981 gen_tmr_configuration[timer->index].mode_mask); 2982 2983 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2984 /* 2985 * Starting from AR9462, each generic timer can select which tsf 2986 * to use. But we still follow the old rule, 0 - 7 use tsf and 2987 * 8 - 15 use tsf2. 2988 */ 2989 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2990 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2991 (1 << timer->index)); 2992 else 2993 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2994 (1 << timer->index)); 2995 } 2996 2997 if (timer->trigger) 2998 mask |= SM(AR_GENTMR_BIT(timer->index), 2999 AR_IMR_S5_GENTIMER_TRIG); 3000 if (timer->overflow) 3001 mask |= SM(AR_GENTMR_BIT(timer->index), 3002 AR_IMR_S5_GENTIMER_THRESH); 3003 3004 REG_SET_BIT(ah, AR_IMR_S5, mask); 3005 3006 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3007 ah->imask |= ATH9K_INT_GENTIMER; 3008 ath9k_hw_set_interrupts(ah); 3009 } 3010 } 3011 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3012 3013 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3014 { 3015 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3016 3017 /* Clear generic timer enable bits. */ 3018 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3019 gen_tmr_configuration[timer->index].mode_mask); 3020 3021 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3022 /* 3023 * Need to switch back to TSF if it was using TSF2. 3024 */ 3025 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3026 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3027 (1 << timer->index)); 3028 } 3029 } 3030 3031 /* Disable both trigger and thresh interrupt masks */ 3032 REG_CLR_BIT(ah, AR_IMR_S5, 3033 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3034 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3035 3036 timer_table->timer_mask &= ~BIT(timer->index); 3037 3038 if (timer_table->timer_mask == 0) { 3039 ah->imask &= ~ATH9K_INT_GENTIMER; 3040 ath9k_hw_set_interrupts(ah); 3041 } 3042 } 3043 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3044 3045 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3046 { 3047 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3048 3049 /* free the hardware generic timer slot */ 3050 timer_table->timers[timer->index] = NULL; 3051 kfree(timer); 3052 } 3053 EXPORT_SYMBOL(ath_gen_timer_free); 3054 3055 /* 3056 * Generic Timer Interrupts handling 3057 */ 3058 void ath_gen_timer_isr(struct ath_hw *ah) 3059 { 3060 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3061 struct ath_gen_timer *timer; 3062 unsigned long trigger_mask, thresh_mask; 3063 unsigned int index; 3064 3065 /* get hardware generic timer interrupt status */ 3066 trigger_mask = ah->intr_gen_timer_trigger; 3067 thresh_mask = ah->intr_gen_timer_thresh; 3068 trigger_mask &= timer_table->timer_mask; 3069 thresh_mask &= timer_table->timer_mask; 3070 3071 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3072 timer = timer_table->timers[index]; 3073 if (!timer) 3074 continue; 3075 if (!timer->overflow) 3076 continue; 3077 3078 trigger_mask &= ~BIT(index); 3079 timer->overflow(timer->arg); 3080 } 3081 3082 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3083 timer = timer_table->timers[index]; 3084 if (!timer) 3085 continue; 3086 if (!timer->trigger) 3087 continue; 3088 timer->trigger(timer->arg); 3089 } 3090 } 3091 EXPORT_SYMBOL(ath_gen_timer_isr); 3092 3093 /********/ 3094 /* HTC */ 3095 /********/ 3096 3097 static struct { 3098 u32 version; 3099 const char * name; 3100 } ath_mac_bb_names[] = { 3101 /* Devices with external radios */ 3102 { AR_SREV_VERSION_5416_PCI, "5416" }, 3103 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3104 { AR_SREV_VERSION_9100, "9100" }, 3105 { AR_SREV_VERSION_9160, "9160" }, 3106 /* Single-chip solutions */ 3107 { AR_SREV_VERSION_9280, "9280" }, 3108 { AR_SREV_VERSION_9285, "9285" }, 3109 { AR_SREV_VERSION_9287, "9287" }, 3110 { AR_SREV_VERSION_9271, "9271" }, 3111 { AR_SREV_VERSION_9300, "9300" }, 3112 { AR_SREV_VERSION_9330, "9330" }, 3113 { AR_SREV_VERSION_9340, "9340" }, 3114 { AR_SREV_VERSION_9485, "9485" }, 3115 { AR_SREV_VERSION_9462, "9462" }, 3116 { AR_SREV_VERSION_9550, "9550" }, 3117 { AR_SREV_VERSION_9565, "9565" }, 3118 { AR_SREV_VERSION_9531, "9531" }, 3119 }; 3120 3121 /* For devices with external radios */ 3122 static struct { 3123 u16 version; 3124 const char * name; 3125 } ath_rf_names[] = { 3126 { 0, "5133" }, 3127 { AR_RAD5133_SREV_MAJOR, "5133" }, 3128 { AR_RAD5122_SREV_MAJOR, "5122" }, 3129 { AR_RAD2133_SREV_MAJOR, "2133" }, 3130 { AR_RAD2122_SREV_MAJOR, "2122" } 3131 }; 3132 3133 /* 3134 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3135 */ 3136 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3137 { 3138 int i; 3139 3140 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3141 if (ath_mac_bb_names[i].version == mac_bb_version) { 3142 return ath_mac_bb_names[i].name; 3143 } 3144 } 3145 3146 return "????"; 3147 } 3148 3149 /* 3150 * Return the RF name. "????" is returned if the RF is unknown. 3151 * Used for devices with external radios. 3152 */ 3153 static const char *ath9k_hw_rf_name(u16 rf_version) 3154 { 3155 int i; 3156 3157 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3158 if (ath_rf_names[i].version == rf_version) { 3159 return ath_rf_names[i].name; 3160 } 3161 } 3162 3163 return "????"; 3164 } 3165 3166 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3167 { 3168 int used; 3169 3170 /* chipsets >= AR9280 are single-chip */ 3171 if (AR_SREV_9280_20_OR_LATER(ah)) { 3172 used = scnprintf(hw_name, len, 3173 "Atheros AR%s Rev:%x", 3174 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3175 ah->hw_version.macRev); 3176 } 3177 else { 3178 used = scnprintf(hw_name, len, 3179 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3180 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3181 ah->hw_version.macRev, 3182 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3183 & AR_RADIO_SREV_MAJOR)), 3184 ah->hw_version.phyRev); 3185 } 3186 3187 hw_name[used] = '\0'; 3188 } 3189 EXPORT_SYMBOL(ath9k_hw_name); 3190