1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <linux/gpio.h> 24 #include <asm/unaligned.h> 25 26 #include "hw.h" 27 #include "hw-ops.h" 28 #include "ar9003_mac.h" 29 #include "ar9003_mci.h" 30 #include "ar9003_phy.h" 31 #include "ath9k.h" 32 33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 41 { 42 struct ath_common *common = ath9k_hw_common(ah); 43 struct ath9k_channel *chan = ah->curchan; 44 unsigned int clockrate; 45 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 48 clockrate = 117; 49 else if (!chan) /* should really check for CCK instead */ 50 clockrate = ATH9K_CLOCK_RATE_CCK; 51 else if (IS_CHAN_2GHZ(chan)) 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 55 else 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 57 58 if (chan) { 59 if (IS_CHAN_HT40(chan)) 60 clockrate *= 2; 61 if (IS_CHAN_HALF_RATE(chan)) 62 clockrate /= 2; 63 if (IS_CHAN_QUARTER_RATE(chan)) 64 clockrate /= 4; 65 } 66 67 common->clockrate = clockrate; 68 } 69 70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 71 { 72 struct ath_common *common = ath9k_hw_common(ah); 73 74 return usecs * common->clockrate; 75 } 76 77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 78 { 79 int i; 80 81 BUG_ON(timeout < AH_TIME_QUANTUM); 82 83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 84 if ((REG_READ(ah, reg) & mask) == val) 85 return true; 86 87 udelay(AH_TIME_QUANTUM); 88 } 89 90 ath_dbg(ath9k_hw_common(ah), ANY, 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 92 timeout, reg, REG_READ(ah, reg), mask, val); 93 94 return false; 95 } 96 EXPORT_SYMBOL(ath9k_hw_wait); 97 98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 99 int hw_delay) 100 { 101 hw_delay /= 10; 102 103 if (IS_CHAN_HALF_RATE(chan)) 104 hw_delay *= 2; 105 else if (IS_CHAN_QUARTER_RATE(chan)) 106 hw_delay *= 4; 107 108 udelay(hw_delay + BASE_ACTIVATE_DELAY); 109 } 110 111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 112 int column, unsigned int *writecnt) 113 { 114 int r; 115 116 ENABLE_REGWRITE_BUFFER(ah); 117 for (r = 0; r < array->ia_rows; r++) { 118 REG_WRITE(ah, INI_RA(array, r, 0), 119 INI_RA(array, r, column)); 120 DO_DELAY(*writecnt); 121 } 122 REGWRITE_BUFFER_FLUSH(ah); 123 } 124 125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) 126 { 127 u32 *tmp_reg_list, *tmp_data; 128 int i; 129 130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL); 131 if (!tmp_reg_list) { 132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); 133 return; 134 } 135 136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL); 137 if (!tmp_data) { 138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); 139 goto error_tmp_data; 140 } 141 142 for (i = 0; i < size; i++) 143 tmp_reg_list[i] = array[i][0]; 144 145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); 146 147 for (i = 0; i < size; i++) 148 array[i][1] = tmp_data[i]; 149 150 kfree(tmp_data); 151 error_tmp_data: 152 kfree(tmp_reg_list); 153 } 154 155 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 156 { 157 u32 retval; 158 int i; 159 160 for (i = 0, retval = 0; i < n; i++) { 161 retval = (retval << 1) | (val & 1); 162 val >>= 1; 163 } 164 return retval; 165 } 166 167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 168 u8 phy, int kbps, 169 u32 frameLen, u16 rateix, 170 bool shortPreamble) 171 { 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 173 174 if (kbps == 0) 175 return 0; 176 177 switch (phy) { 178 case WLAN_RC_PHY_CCK: 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 180 if (shortPreamble) 181 phyTime >>= 1; 182 numBits = frameLen << 3; 183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 184 break; 185 case WLAN_RC_PHY_OFDM: 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 188 numBits = OFDM_PLCP_BITS + (frameLen << 3); 189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 190 txTime = OFDM_SIFS_TIME_QUARTER 191 + OFDM_PREAMBLE_TIME_QUARTER 192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 193 } else if (ah->curchan && 194 IS_CHAN_HALF_RATE(ah->curchan)) { 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 196 numBits = OFDM_PLCP_BITS + (frameLen << 3); 197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 198 txTime = OFDM_SIFS_TIME_HALF + 199 OFDM_PREAMBLE_TIME_HALF 200 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 201 } else { 202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 203 numBits = OFDM_PLCP_BITS + (frameLen << 3); 204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 206 + (numSymbols * OFDM_SYMBOL_TIME); 207 } 208 break; 209 default: 210 ath_err(ath9k_hw_common(ah), 211 "Unknown phy %u (rate ix %u)\n", phy, rateix); 212 txTime = 0; 213 break; 214 } 215 216 return txTime; 217 } 218 EXPORT_SYMBOL(ath9k_hw_computetxtime); 219 220 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 221 struct ath9k_channel *chan, 222 struct chan_centers *centers) 223 { 224 int8_t extoff; 225 226 if (!IS_CHAN_HT40(chan)) { 227 centers->ctl_center = centers->ext_center = 228 centers->synth_center = chan->channel; 229 return; 230 } 231 232 if (IS_CHAN_HT40PLUS(chan)) { 233 centers->synth_center = 234 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 235 extoff = 1; 236 } else { 237 centers->synth_center = 238 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 239 extoff = -1; 240 } 241 242 centers->ctl_center = 243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 244 /* 25 MHz spacing is supported by hw but not on upper layers */ 245 centers->ext_center = 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 247 } 248 249 /******************/ 250 /* Chip Revisions */ 251 /******************/ 252 253 static void ath9k_hw_read_revisions(struct ath_hw *ah) 254 { 255 u32 val; 256 257 if (ah->get_mac_revision) 258 ah->hw_version.macRev = ah->get_mac_revision(); 259 260 switch (ah->hw_version.devid) { 261 case AR5416_AR9100_DEVID: 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 263 break; 264 case AR9300_DEVID_AR9330: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 266 if (!ah->get_mac_revision) { 267 val = REG_READ(ah, AR_SREV); 268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 269 } 270 return; 271 case AR9300_DEVID_AR9340: 272 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 273 return; 274 case AR9300_DEVID_QCA955X: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 276 return; 277 case AR9300_DEVID_AR953X: 278 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 279 return; 280 case AR9300_DEVID_QCA956X: 281 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 282 return; 283 } 284 285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 286 287 if (val == 0xFF) { 288 val = REG_READ(ah, AR_SREV); 289 ah->hw_version.macVersion = 290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 292 293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 294 ah->is_pciexpress = true; 295 else 296 ah->is_pciexpress = (val & 297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 298 } else { 299 if (!AR_SREV_9100(ah)) 300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 301 302 ah->hw_version.macRev = val & AR_SREV_REVISION; 303 304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 305 ah->is_pciexpress = true; 306 } 307 } 308 309 /************************************/ 310 /* HW Attach, Detach, Init Routines */ 311 /************************************/ 312 313 static void ath9k_hw_disablepcie(struct ath_hw *ah) 314 { 315 if (!AR_SREV_5416(ah)) 316 return; 317 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 327 328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 329 } 330 331 /* This should work for all families including legacy */ 332 static bool ath9k_hw_chip_test(struct ath_hw *ah) 333 { 334 struct ath_common *common = ath9k_hw_common(ah); 335 u32 regAddr[2] = { AR_STA_ID0 }; 336 u32 regHold[2]; 337 static const u32 patternData[4] = { 338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 339 }; 340 int i, j, loop_max; 341 342 if (!AR_SREV_9300_20_OR_LATER(ah)) { 343 loop_max = 2; 344 regAddr[1] = AR_PHY_BASE + (8 << 2); 345 } else 346 loop_max = 1; 347 348 for (i = 0; i < loop_max; i++) { 349 u32 addr = regAddr[i]; 350 u32 wrData, rdData; 351 352 regHold[i] = REG_READ(ah, addr); 353 for (j = 0; j < 0x100; j++) { 354 wrData = (j << 16) | j; 355 REG_WRITE(ah, addr, wrData); 356 rdData = REG_READ(ah, addr); 357 if (rdData != wrData) { 358 ath_err(common, 359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 360 addr, wrData, rdData); 361 return false; 362 } 363 } 364 for (j = 0; j < 4; j++) { 365 wrData = patternData[j]; 366 REG_WRITE(ah, addr, wrData); 367 rdData = REG_READ(ah, addr); 368 if (wrData != rdData) { 369 ath_err(common, 370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 371 addr, wrData, rdData); 372 return false; 373 } 374 } 375 REG_WRITE(ah, regAddr[i], regHold[i]); 376 } 377 udelay(100); 378 379 return true; 380 } 381 382 static void ath9k_hw_init_config(struct ath_hw *ah) 383 { 384 struct ath_common *common = ath9k_hw_common(ah); 385 386 ah->config.dma_beacon_response_time = 1; 387 ah->config.sw_beacon_response_time = 6; 388 ah->config.cwm_ignore_extcca = false; 389 ah->config.analog_shiftreg = 1; 390 391 ah->config.rx_intr_mitigation = true; 392 393 if (AR_SREV_9300_20_OR_LATER(ah)) { 394 ah->config.rimt_last = 500; 395 ah->config.rimt_first = 2000; 396 } else { 397 ah->config.rimt_last = 250; 398 ah->config.rimt_first = 700; 399 } 400 401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 402 ah->config.pll_pwrsave = 7; 403 404 /* 405 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 407 * This means we use it for all AR5416 devices, and the few 408 * minor PCI AR9280 devices out there. 409 * 410 * Serialization is required because these devices do not handle 411 * well the case of two concurrent reads/writes due to the latency 412 * involved. During one read/write another read/write can be issued 413 * on another CPU while the previous read/write may still be working 414 * on our hardware, if we hit this case the hardware poops in a loop. 415 * We prevent this by serializing reads and writes. 416 * 417 * This issue is not present on PCI-Express devices or pre-AR5416 418 * devices (legacy, 802.11abg). 419 */ 420 if (num_possible_cpus() > 1) 421 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 422 423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 426 !ah->is_pciexpress)) { 427 ah->config.serialize_regmode = SER_REG_MODE_ON; 428 } else { 429 ah->config.serialize_regmode = SER_REG_MODE_OFF; 430 } 431 } 432 433 ath_dbg(common, RESET, "serialize_regmode is %d\n", 434 ah->config.serialize_regmode); 435 436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 438 else 439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 440 } 441 442 static void ath9k_hw_init_defaults(struct ath_hw *ah) 443 { 444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 445 446 regulatory->country_code = CTRY_DEFAULT; 447 regulatory->power_limit = MAX_RATE_POWER; 448 449 ah->hw_version.magic = AR5416_MAGIC; 450 ah->hw_version.subvendorid = 0; 451 452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 453 AR_STA_ID1_MCAST_KSRCH; 454 if (AR_SREV_9100(ah)) 455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 456 457 ah->slottime = 9; 458 ah->globaltxtimeout = (u32) -1; 459 ah->power_mode = ATH9K_PM_UNDEFINED; 460 ah->htc_reset_init = true; 461 462 ah->tpc_enabled = false; 463 464 ah->ani_function = ATH9K_ANI_ALL; 465 if (!AR_SREV_9300_20_OR_LATER(ah)) 466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 467 468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 470 else 471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 472 } 473 474 static void ath9k_hw_init_macaddr(struct ath_hw *ah) 475 { 476 struct ath_common *common = ath9k_hw_common(ah); 477 int i; 478 u16 eeval; 479 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 480 481 /* MAC address may already be loaded via ath9k_platform_data */ 482 if (is_valid_ether_addr(common->macaddr)) 483 return; 484 485 for (i = 0; i < 3; i++) { 486 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 487 common->macaddr[2 * i] = eeval >> 8; 488 common->macaddr[2 * i + 1] = eeval & 0xff; 489 } 490 491 if (is_valid_ether_addr(common->macaddr)) 492 return; 493 494 ath_err(common, "eeprom contains invalid mac address: %pM\n", 495 common->macaddr); 496 497 random_ether_addr(common->macaddr); 498 ath_err(common, "random mac address will be used: %pM\n", 499 common->macaddr); 500 501 return; 502 } 503 504 static int ath9k_hw_post_init(struct ath_hw *ah) 505 { 506 struct ath_common *common = ath9k_hw_common(ah); 507 int ecode; 508 509 if (common->bus_ops->ath_bus_type != ATH_USB) { 510 if (!ath9k_hw_chip_test(ah)) 511 return -ENODEV; 512 } 513 514 if (!AR_SREV_9300_20_OR_LATER(ah)) { 515 ecode = ar9002_hw_rf_claim(ah); 516 if (ecode != 0) 517 return ecode; 518 } 519 520 ecode = ath9k_hw_eeprom_init(ah); 521 if (ecode != 0) 522 return ecode; 523 524 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 525 ah->eep_ops->get_eeprom_ver(ah), 526 ah->eep_ops->get_eeprom_rev(ah)); 527 528 ath9k_hw_ani_init(ah); 529 530 /* 531 * EEPROM needs to be initialized before we do this. 532 * This is required for regulatory compliance. 533 */ 534 if (AR_SREV_9300_20_OR_LATER(ah)) { 535 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 536 if ((regdmn & 0xF0) == CTL_FCC) { 537 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 538 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 539 } 540 } 541 542 return 0; 543 } 544 545 static int ath9k_hw_attach_ops(struct ath_hw *ah) 546 { 547 if (!AR_SREV_9300_20_OR_LATER(ah)) 548 return ar9002_hw_attach_ops(ah); 549 550 ar9003_hw_attach_ops(ah); 551 return 0; 552 } 553 554 /* Called for all hardware families */ 555 static int __ath9k_hw_init(struct ath_hw *ah) 556 { 557 struct ath_common *common = ath9k_hw_common(ah); 558 int r = 0; 559 560 ath9k_hw_read_revisions(ah); 561 562 switch (ah->hw_version.macVersion) { 563 case AR_SREV_VERSION_5416_PCI: 564 case AR_SREV_VERSION_5416_PCIE: 565 case AR_SREV_VERSION_9160: 566 case AR_SREV_VERSION_9100: 567 case AR_SREV_VERSION_9280: 568 case AR_SREV_VERSION_9285: 569 case AR_SREV_VERSION_9287: 570 case AR_SREV_VERSION_9271: 571 case AR_SREV_VERSION_9300: 572 case AR_SREV_VERSION_9330: 573 case AR_SREV_VERSION_9485: 574 case AR_SREV_VERSION_9340: 575 case AR_SREV_VERSION_9462: 576 case AR_SREV_VERSION_9550: 577 case AR_SREV_VERSION_9565: 578 case AR_SREV_VERSION_9531: 579 case AR_SREV_VERSION_9561: 580 break; 581 default: 582 ath_err(common, 583 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 584 ah->hw_version.macVersion, ah->hw_version.macRev); 585 return -EOPNOTSUPP; 586 } 587 588 /* 589 * Read back AR_WA into a permanent copy and set bits 14 and 17. 590 * We need to do this to avoid RMW of this register. We cannot 591 * read the reg when chip is asleep. 592 */ 593 if (AR_SREV_9300_20_OR_LATER(ah)) { 594 ah->WARegVal = REG_READ(ah, AR_WA); 595 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 596 AR_WA_ASPM_TIMER_BASED_DISABLE); 597 } 598 599 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 600 ath_err(common, "Couldn't reset chip\n"); 601 return -EIO; 602 } 603 604 if (AR_SREV_9565(ah)) { 605 ah->WARegVal |= AR_WA_BIT22; 606 REG_WRITE(ah, AR_WA, ah->WARegVal); 607 } 608 609 ath9k_hw_init_defaults(ah); 610 ath9k_hw_init_config(ah); 611 612 r = ath9k_hw_attach_ops(ah); 613 if (r) 614 return r; 615 616 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 617 ath_err(common, "Couldn't wakeup chip\n"); 618 return -EIO; 619 } 620 621 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 622 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 623 ah->is_pciexpress = false; 624 625 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 626 ath9k_hw_init_cal_settings(ah); 627 628 if (!ah->is_pciexpress) 629 ath9k_hw_disablepcie(ah); 630 631 r = ath9k_hw_post_init(ah); 632 if (r) 633 return r; 634 635 ath9k_hw_init_mode_gain_regs(ah); 636 r = ath9k_hw_fill_cap_info(ah); 637 if (r) 638 return r; 639 640 ath9k_hw_init_macaddr(ah); 641 ath9k_hw_init_hang_checks(ah); 642 643 common->state = ATH_HW_INITIALIZED; 644 645 return 0; 646 } 647 648 int ath9k_hw_init(struct ath_hw *ah) 649 { 650 int ret; 651 struct ath_common *common = ath9k_hw_common(ah); 652 653 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 654 switch (ah->hw_version.devid) { 655 case AR5416_DEVID_PCI: 656 case AR5416_DEVID_PCIE: 657 case AR5416_AR9100_DEVID: 658 case AR9160_DEVID_PCI: 659 case AR9280_DEVID_PCI: 660 case AR9280_DEVID_PCIE: 661 case AR9285_DEVID_PCIE: 662 case AR9287_DEVID_PCI: 663 case AR9287_DEVID_PCIE: 664 case AR2427_DEVID_PCIE: 665 case AR9300_DEVID_PCIE: 666 case AR9300_DEVID_AR9485_PCIE: 667 case AR9300_DEVID_AR9330: 668 case AR9300_DEVID_AR9340: 669 case AR9300_DEVID_QCA955X: 670 case AR9300_DEVID_AR9580: 671 case AR9300_DEVID_AR9462: 672 case AR9485_DEVID_AR1111: 673 case AR9300_DEVID_AR9565: 674 case AR9300_DEVID_AR953X: 675 case AR9300_DEVID_QCA956X: 676 break; 677 default: 678 if (common->bus_ops->ath_bus_type == ATH_USB) 679 break; 680 ath_err(common, "Hardware device ID 0x%04x not supported\n", 681 ah->hw_version.devid); 682 return -EOPNOTSUPP; 683 } 684 685 ret = __ath9k_hw_init(ah); 686 if (ret) { 687 ath_err(common, 688 "Unable to initialize hardware; initialization status: %d\n", 689 ret); 690 return ret; 691 } 692 693 ath_dynack_init(ah); 694 695 return 0; 696 } 697 EXPORT_SYMBOL(ath9k_hw_init); 698 699 static void ath9k_hw_init_qos(struct ath_hw *ah) 700 { 701 ENABLE_REGWRITE_BUFFER(ah); 702 703 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 704 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 705 706 REG_WRITE(ah, AR_QOS_NO_ACK, 707 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 708 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 709 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 710 711 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 712 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 713 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 714 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 715 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 716 717 REGWRITE_BUFFER_FLUSH(ah); 718 } 719 720 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 721 { 722 struct ath_common *common = ath9k_hw_common(ah); 723 int i = 0; 724 725 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 726 udelay(100); 727 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 728 729 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 730 731 udelay(100); 732 733 if (WARN_ON_ONCE(i >= 100)) { 734 ath_err(common, "PLL4 measurement not done\n"); 735 break; 736 } 737 738 i++; 739 } 740 741 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 742 } 743 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 744 745 static void ath9k_hw_init_pll(struct ath_hw *ah, 746 struct ath9k_channel *chan) 747 { 748 u32 pll; 749 750 pll = ath9k_hw_compute_pll_control(ah, chan); 751 752 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 753 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 755 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 757 AR_CH0_DPLL2_KD, 0x40); 758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 759 AR_CH0_DPLL2_KI, 0x4); 760 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 762 AR_CH0_BB_DPLL1_REFDIV, 0x5); 763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 764 AR_CH0_BB_DPLL1_NINI, 0x58); 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 766 AR_CH0_BB_DPLL1_NFRAC, 0x0); 767 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 769 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 771 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 773 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 774 775 /* program BB PLL phase_shift to 0x6 */ 776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 777 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 778 779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 780 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 781 udelay(1000); 782 } else if (AR_SREV_9330(ah)) { 783 u32 ddr_dpll2, pll_control2, kd; 784 785 if (ah->is_clk_25mhz) { 786 ddr_dpll2 = 0x18e82f01; 787 pll_control2 = 0xe04a3d; 788 kd = 0x1d; 789 } else { 790 ddr_dpll2 = 0x19e82f01; 791 pll_control2 = 0x886666; 792 kd = 0x3d; 793 } 794 795 /* program DDR PLL ki and kd value */ 796 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 797 798 /* program DDR PLL phase_shift */ 799 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 800 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 801 802 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 803 pll | AR_RTC_9300_PLL_BYPASS); 804 udelay(1000); 805 806 /* program refdiv, nint, frac to RTC register */ 807 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 808 809 /* program BB PLL kd and ki value */ 810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 812 813 /* program BB PLL phase_shift */ 814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 815 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 816 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 817 AR_SREV_9561(ah)) { 818 u32 regval, pll2_divint, pll2_divfrac, refdiv; 819 820 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 821 pll | AR_RTC_9300_SOC_PLL_BYPASS); 822 udelay(1000); 823 824 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 825 udelay(100); 826 827 if (ah->is_clk_25mhz) { 828 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 829 pll2_divint = 0x1c; 830 pll2_divfrac = 0xa3d2; 831 refdiv = 1; 832 } else { 833 pll2_divint = 0x54; 834 pll2_divfrac = 0x1eb85; 835 refdiv = 3; 836 } 837 } else { 838 if (AR_SREV_9340(ah)) { 839 pll2_divint = 88; 840 pll2_divfrac = 0; 841 refdiv = 5; 842 } else { 843 pll2_divint = 0x11; 844 pll2_divfrac = (AR_SREV_9531(ah) || 845 AR_SREV_9561(ah)) ? 846 0x26665 : 0x26666; 847 refdiv = 1; 848 } 849 } 850 851 regval = REG_READ(ah, AR_PHY_PLL_MODE); 852 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 853 regval |= (0x1 << 22); 854 else 855 regval |= (0x1 << 16); 856 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 857 udelay(100); 858 859 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 860 (pll2_divint << 18) | pll2_divfrac); 861 udelay(100); 862 863 regval = REG_READ(ah, AR_PHY_PLL_MODE); 864 if (AR_SREV_9340(ah)) 865 regval = (regval & 0x80071fff) | 866 (0x1 << 30) | 867 (0x1 << 13) | 868 (0x4 << 26) | 869 (0x18 << 19); 870 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 871 regval = (regval & 0x01c00fff) | 872 (0x1 << 31) | 873 (0x2 << 29) | 874 (0xa << 25) | 875 (0x1 << 19); 876 877 if (AR_SREV_9531(ah)) 878 regval |= (0x6 << 12); 879 } else 880 regval = (regval & 0x80071fff) | 881 (0x3 << 30) | 882 (0x1 << 13) | 883 (0x4 << 26) | 884 (0x60 << 19); 885 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 886 887 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 888 REG_WRITE(ah, AR_PHY_PLL_MODE, 889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 890 else 891 REG_WRITE(ah, AR_PHY_PLL_MODE, 892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 893 894 udelay(1000); 895 } 896 897 if (AR_SREV_9565(ah)) 898 pll |= 0x40000; 899 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 900 901 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 902 AR_SREV_9550(ah)) 903 udelay(1000); 904 905 /* Switch the core clock for ar9271 to 117Mhz */ 906 if (AR_SREV_9271(ah)) { 907 udelay(500); 908 REG_WRITE(ah, 0x50040, 0x304); 909 } 910 911 udelay(RTC_PLL_SETTLE_DELAY); 912 913 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 914 } 915 916 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 917 enum nl80211_iftype opmode) 918 { 919 u32 sync_default = AR_INTR_SYNC_DEFAULT; 920 u32 imr_reg = AR_IMR_TXERR | 921 AR_IMR_TXURN | 922 AR_IMR_RXERR | 923 AR_IMR_RXORN | 924 AR_IMR_BCNMISC; 925 u32 msi_cfg = 0; 926 927 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 928 AR_SREV_9561(ah)) 929 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 930 931 if (AR_SREV_9300_20_OR_LATER(ah)) { 932 imr_reg |= AR_IMR_RXOK_HP; 933 if (ah->config.rx_intr_mitigation) { 934 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 935 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 936 } else { 937 imr_reg |= AR_IMR_RXOK_LP; 938 msi_cfg |= AR_INTCFG_MSI_RXOK; 939 } 940 } else { 941 if (ah->config.rx_intr_mitigation) { 942 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 943 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 944 } else { 945 imr_reg |= AR_IMR_RXOK; 946 msi_cfg |= AR_INTCFG_MSI_RXOK; 947 } 948 } 949 950 if (ah->config.tx_intr_mitigation) { 951 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 952 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR; 953 } else { 954 imr_reg |= AR_IMR_TXOK; 955 msi_cfg |= AR_INTCFG_MSI_TXOK; 956 } 957 958 ENABLE_REGWRITE_BUFFER(ah); 959 960 REG_WRITE(ah, AR_IMR, imr_reg); 961 ah->imrs2_reg |= AR_IMR_S2_GTT; 962 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 963 964 if (ah->msi_enabled) { 965 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); 966 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; 967 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; 968 REG_WRITE(ah, AR_INTCFG, msi_cfg); 969 ath_dbg(ath9k_hw_common(ah), ANY, 970 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n", 971 REG_READ(ah, AR_INTCFG), msi_cfg); 972 } 973 974 if (!AR_SREV_9100(ah)) { 975 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 976 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 977 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 978 } 979 980 REGWRITE_BUFFER_FLUSH(ah); 981 982 if (AR_SREV_9300_20_OR_LATER(ah)) { 983 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 984 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 985 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 986 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 987 } 988 } 989 990 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 991 { 992 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 993 val = min(val, (u32) 0xFFFF); 994 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 995 } 996 997 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 998 { 999 u32 val = ath9k_hw_mac_to_clks(ah, us); 1000 val = min(val, (u32) 0xFFFF); 1001 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1002 } 1003 1004 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1005 { 1006 u32 val = ath9k_hw_mac_to_clks(ah, us); 1007 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1008 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1009 } 1010 1011 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1012 { 1013 u32 val = ath9k_hw_mac_to_clks(ah, us); 1014 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1015 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1016 } 1017 1018 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1019 { 1020 if (tu > 0xFFFF) { 1021 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1022 tu); 1023 ah->globaltxtimeout = (u32) -1; 1024 return false; 1025 } else { 1026 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1027 ah->globaltxtimeout = tu; 1028 return true; 1029 } 1030 } 1031 1032 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1033 { 1034 struct ath_common *common = ath9k_hw_common(ah); 1035 const struct ath9k_channel *chan = ah->curchan; 1036 int acktimeout, ctstimeout, ack_offset = 0; 1037 int slottime; 1038 int sifstime; 1039 int rx_lat = 0, tx_lat = 0, eifs = 0; 1040 u32 reg; 1041 1042 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1043 ah->misc_mode); 1044 1045 if (!chan) 1046 return; 1047 1048 if (ah->misc_mode != 0) 1049 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1050 1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1052 rx_lat = 41; 1053 else 1054 rx_lat = 37; 1055 tx_lat = 54; 1056 1057 if (IS_CHAN_5GHZ(chan)) 1058 sifstime = 16; 1059 else 1060 sifstime = 10; 1061 1062 if (IS_CHAN_HALF_RATE(chan)) { 1063 eifs = 175; 1064 rx_lat *= 2; 1065 tx_lat *= 2; 1066 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1067 tx_lat += 11; 1068 1069 sifstime = 32; 1070 ack_offset = 16; 1071 slottime = 13; 1072 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1073 eifs = 340; 1074 rx_lat = (rx_lat * 4) - 1; 1075 tx_lat *= 4; 1076 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1077 tx_lat += 22; 1078 1079 sifstime = 64; 1080 ack_offset = 32; 1081 slottime = 21; 1082 } else { 1083 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1084 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1085 reg = AR_USEC_ASYNC_FIFO; 1086 } else { 1087 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1088 common->clockrate; 1089 reg = REG_READ(ah, AR_USEC); 1090 } 1091 rx_lat = MS(reg, AR_USEC_RX_LAT); 1092 tx_lat = MS(reg, AR_USEC_TX_LAT); 1093 1094 slottime = ah->slottime; 1095 } 1096 1097 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1098 slottime += 3 * ah->coverage_class; 1099 acktimeout = slottime + sifstime + ack_offset; 1100 ctstimeout = acktimeout; 1101 1102 /* 1103 * Workaround for early ACK timeouts, add an offset to match the 1104 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1105 * This was initially only meant to work around an issue with delayed 1106 * BA frames in some implementations, but it has been found to fix ACK 1107 * timeout issues in other cases as well. 1108 */ 1109 if (IS_CHAN_2GHZ(chan) && 1110 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1111 acktimeout += 64 - sifstime - ah->slottime; 1112 ctstimeout += 48 - sifstime - ah->slottime; 1113 } 1114 1115 if (ah->dynack.enabled) { 1116 acktimeout = ah->dynack.ackto; 1117 ctstimeout = acktimeout; 1118 slottime = (acktimeout - 3) / 2; 1119 } else { 1120 ah->dynack.ackto = acktimeout; 1121 } 1122 1123 ath9k_hw_set_sifs_time(ah, sifstime); 1124 ath9k_hw_setslottime(ah, slottime); 1125 ath9k_hw_set_ack_timeout(ah, acktimeout); 1126 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1127 if (ah->globaltxtimeout != (u32) -1) 1128 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1129 1130 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1131 REG_RMW(ah, AR_USEC, 1132 (common->clockrate - 1) | 1133 SM(rx_lat, AR_USEC_RX_LAT) | 1134 SM(tx_lat, AR_USEC_TX_LAT), 1135 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1136 1137 } 1138 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1139 1140 void ath9k_hw_deinit(struct ath_hw *ah) 1141 { 1142 struct ath_common *common = ath9k_hw_common(ah); 1143 1144 if (common->state < ATH_HW_INITIALIZED) 1145 return; 1146 1147 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1148 } 1149 EXPORT_SYMBOL(ath9k_hw_deinit); 1150 1151 /*******/ 1152 /* INI */ 1153 /*******/ 1154 1155 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1156 { 1157 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1158 1159 if (IS_CHAN_2GHZ(chan)) 1160 ctl |= CTL_11G; 1161 else 1162 ctl |= CTL_11A; 1163 1164 return ctl; 1165 } 1166 1167 /****************************************/ 1168 /* Reset and Channel Switching Routines */ 1169 /****************************************/ 1170 1171 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1172 { 1173 struct ath_common *common = ath9k_hw_common(ah); 1174 int txbuf_size; 1175 1176 ENABLE_REGWRITE_BUFFER(ah); 1177 1178 /* 1179 * set AHB_MODE not to do cacheline prefetches 1180 */ 1181 if (!AR_SREV_9300_20_OR_LATER(ah)) 1182 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1183 1184 /* 1185 * let mac dma reads be in 128 byte chunks 1186 */ 1187 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1188 1189 REGWRITE_BUFFER_FLUSH(ah); 1190 1191 /* 1192 * Restore TX Trigger Level to its pre-reset value. 1193 * The initial value depends on whether aggregation is enabled, and is 1194 * adjusted whenever underruns are detected. 1195 */ 1196 if (!AR_SREV_9300_20_OR_LATER(ah)) 1197 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1198 1199 ENABLE_REGWRITE_BUFFER(ah); 1200 1201 /* 1202 * let mac dma writes be in 128 byte chunks 1203 */ 1204 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1205 1206 /* 1207 * Setup receive FIFO threshold to hold off TX activities 1208 */ 1209 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1210 1211 if (AR_SREV_9300_20_OR_LATER(ah)) { 1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1213 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1214 1215 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1216 ah->caps.rx_status_len); 1217 } 1218 1219 /* 1220 * reduce the number of usable entries in PCU TXBUF to avoid 1221 * wrap around issues. 1222 */ 1223 if (AR_SREV_9285(ah)) { 1224 /* For AR9285 the number of Fifos are reduced to half. 1225 * So set the usable tx buf size also to half to 1226 * avoid data/delimiter underruns 1227 */ 1228 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1229 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1230 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1231 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1232 } else { 1233 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1234 } 1235 1236 if (!AR_SREV_9271(ah)) 1237 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1238 1239 REGWRITE_BUFFER_FLUSH(ah); 1240 1241 if (AR_SREV_9300_20_OR_LATER(ah)) 1242 ath9k_hw_reset_txstatus_ring(ah); 1243 } 1244 1245 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1246 { 1247 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1248 u32 set = AR_STA_ID1_KSRCH_MODE; 1249 1250 ENABLE_REG_RMW_BUFFER(ah); 1251 switch (opmode) { 1252 case NL80211_IFTYPE_ADHOC: 1253 if (!AR_SREV_9340_13(ah)) { 1254 set |= AR_STA_ID1_ADHOC; 1255 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1256 break; 1257 } 1258 /* fall through */ 1259 case NL80211_IFTYPE_OCB: 1260 case NL80211_IFTYPE_MESH_POINT: 1261 case NL80211_IFTYPE_AP: 1262 set |= AR_STA_ID1_STA_AP; 1263 /* fall through */ 1264 case NL80211_IFTYPE_STATION: 1265 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1266 break; 1267 default: 1268 if (!ah->is_monitoring) 1269 set = 0; 1270 break; 1271 } 1272 REG_RMW(ah, AR_STA_ID1, set, mask); 1273 REG_RMW_BUFFER_FLUSH(ah); 1274 } 1275 1276 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1277 u32 *coef_mantissa, u32 *coef_exponent) 1278 { 1279 u32 coef_exp, coef_man; 1280 1281 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1282 if ((coef_scaled >> coef_exp) & 0x1) 1283 break; 1284 1285 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1286 1287 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1288 1289 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1290 *coef_exponent = coef_exp - 16; 1291 } 1292 1293 /* AR9330 WAR: 1294 * call external reset function to reset WMAC if: 1295 * - doing a cold reset 1296 * - we have pending frames in the TX queues. 1297 */ 1298 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1299 { 1300 int i, npend = 0; 1301 1302 for (i = 0; i < AR_NUM_QCU; i++) { 1303 npend = ath9k_hw_numtxpending(ah, i); 1304 if (npend) 1305 break; 1306 } 1307 1308 if (ah->external_reset && 1309 (npend || type == ATH9K_RESET_COLD)) { 1310 int reset_err = 0; 1311 1312 ath_dbg(ath9k_hw_common(ah), RESET, 1313 "reset MAC via external reset\n"); 1314 1315 reset_err = ah->external_reset(); 1316 if (reset_err) { 1317 ath_err(ath9k_hw_common(ah), 1318 "External reset failed, err=%d\n", 1319 reset_err); 1320 return false; 1321 } 1322 1323 REG_WRITE(ah, AR_RTC_RESET, 1); 1324 } 1325 1326 return true; 1327 } 1328 1329 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1330 { 1331 u32 rst_flags; 1332 u32 tmpReg; 1333 1334 if (AR_SREV_9100(ah)) { 1335 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1336 AR_RTC_DERIVED_CLK_PERIOD, 1); 1337 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1338 } 1339 1340 ENABLE_REGWRITE_BUFFER(ah); 1341 1342 if (AR_SREV_9300_20_OR_LATER(ah)) { 1343 REG_WRITE(ah, AR_WA, ah->WARegVal); 1344 udelay(10); 1345 } 1346 1347 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1348 AR_RTC_FORCE_WAKE_ON_INT); 1349 1350 if (AR_SREV_9100(ah)) { 1351 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1352 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1353 } else { 1354 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1355 if (AR_SREV_9340(ah)) 1356 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1357 else 1358 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1359 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1360 1361 if (tmpReg) { 1362 u32 val; 1363 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1364 1365 val = AR_RC_HOSTIF; 1366 if (!AR_SREV_9300_20_OR_LATER(ah)) 1367 val |= AR_RC_AHB; 1368 REG_WRITE(ah, AR_RC, val); 1369 1370 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1371 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1372 1373 rst_flags = AR_RTC_RC_MAC_WARM; 1374 if (type == ATH9K_RESET_COLD) 1375 rst_flags |= AR_RTC_RC_MAC_COLD; 1376 } 1377 1378 if (AR_SREV_9330(ah)) { 1379 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1380 return false; 1381 } 1382 1383 if (ath9k_hw_mci_is_enabled(ah)) 1384 ar9003_mci_check_gpm_offset(ah); 1385 1386 /* DMA HALT added to resolve ar9300 and ar9580 bus error during 1387 * RTC_RC reg read 1388 */ 1389 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { 1390 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1391 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, 1392 20 * AH_WAIT_TIMEOUT); 1393 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1394 } 1395 1396 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1397 1398 REGWRITE_BUFFER_FLUSH(ah); 1399 1400 if (AR_SREV_9300_20_OR_LATER(ah)) 1401 udelay(50); 1402 else if (AR_SREV_9100(ah)) 1403 mdelay(10); 1404 else 1405 udelay(100); 1406 1407 REG_WRITE(ah, AR_RTC_RC, 0); 1408 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1409 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1410 return false; 1411 } 1412 1413 if (!AR_SREV_9100(ah)) 1414 REG_WRITE(ah, AR_RC, 0); 1415 1416 if (AR_SREV_9100(ah)) 1417 udelay(50); 1418 1419 return true; 1420 } 1421 1422 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1423 { 1424 ENABLE_REGWRITE_BUFFER(ah); 1425 1426 if (AR_SREV_9300_20_OR_LATER(ah)) { 1427 REG_WRITE(ah, AR_WA, ah->WARegVal); 1428 udelay(10); 1429 } 1430 1431 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1432 AR_RTC_FORCE_WAKE_ON_INT); 1433 1434 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1435 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1436 1437 REG_WRITE(ah, AR_RTC_RESET, 0); 1438 1439 REGWRITE_BUFFER_FLUSH(ah); 1440 1441 udelay(2); 1442 1443 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1444 REG_WRITE(ah, AR_RC, 0); 1445 1446 REG_WRITE(ah, AR_RTC_RESET, 1); 1447 1448 if (!ath9k_hw_wait(ah, 1449 AR_RTC_STATUS, 1450 AR_RTC_STATUS_M, 1451 AR_RTC_STATUS_ON, 1452 AH_WAIT_TIMEOUT)) { 1453 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1454 return false; 1455 } 1456 1457 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1458 } 1459 1460 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1461 { 1462 bool ret = false; 1463 1464 if (AR_SREV_9300_20_OR_LATER(ah)) { 1465 REG_WRITE(ah, AR_WA, ah->WARegVal); 1466 udelay(10); 1467 } 1468 1469 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1470 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1471 1472 if (!ah->reset_power_on) 1473 type = ATH9K_RESET_POWER_ON; 1474 1475 switch (type) { 1476 case ATH9K_RESET_POWER_ON: 1477 ret = ath9k_hw_set_reset_power_on(ah); 1478 if (ret) 1479 ah->reset_power_on = true; 1480 break; 1481 case ATH9K_RESET_WARM: 1482 case ATH9K_RESET_COLD: 1483 ret = ath9k_hw_set_reset(ah, type); 1484 break; 1485 default: 1486 break; 1487 } 1488 1489 return ret; 1490 } 1491 1492 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1493 struct ath9k_channel *chan) 1494 { 1495 int reset_type = ATH9K_RESET_WARM; 1496 1497 if (AR_SREV_9280(ah)) { 1498 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1499 reset_type = ATH9K_RESET_POWER_ON; 1500 else 1501 reset_type = ATH9K_RESET_COLD; 1502 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1503 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1504 reset_type = ATH9K_RESET_COLD; 1505 1506 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1507 return false; 1508 1509 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1510 return false; 1511 1512 ah->chip_fullsleep = false; 1513 1514 if (AR_SREV_9330(ah)) 1515 ar9003_hw_internal_regulator_apply(ah); 1516 ath9k_hw_init_pll(ah, chan); 1517 1518 return true; 1519 } 1520 1521 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1522 struct ath9k_channel *chan) 1523 { 1524 struct ath_common *common = ath9k_hw_common(ah); 1525 struct ath9k_hw_capabilities *pCap = &ah->caps; 1526 bool band_switch = false, mode_diff = false; 1527 u8 ini_reloaded = 0; 1528 u32 qnum; 1529 int r; 1530 1531 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1532 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1533 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1534 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1535 } 1536 1537 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1538 if (ath9k_hw_numtxpending(ah, qnum)) { 1539 ath_dbg(common, QUEUE, 1540 "Transmit frames pending on queue %d\n", qnum); 1541 return false; 1542 } 1543 } 1544 1545 if (!ath9k_hw_rfbus_req(ah)) { 1546 ath_err(common, "Could not kill baseband RX\n"); 1547 return false; 1548 } 1549 1550 if (band_switch || mode_diff) { 1551 ath9k_hw_mark_phy_inactive(ah); 1552 udelay(5); 1553 1554 if (band_switch) 1555 ath9k_hw_init_pll(ah, chan); 1556 1557 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1558 ath_err(common, "Failed to do fast channel change\n"); 1559 return false; 1560 } 1561 } 1562 1563 ath9k_hw_set_channel_regs(ah, chan); 1564 1565 r = ath9k_hw_rf_set_freq(ah, chan); 1566 if (r) { 1567 ath_err(common, "Failed to set channel\n"); 1568 return false; 1569 } 1570 ath9k_hw_set_clockrate(ah); 1571 ath9k_hw_apply_txpower(ah, chan, false); 1572 1573 ath9k_hw_set_delta_slope(ah, chan); 1574 ath9k_hw_spur_mitigate_freq(ah, chan); 1575 1576 if (band_switch || ini_reloaded) 1577 ah->eep_ops->set_board_values(ah, chan); 1578 1579 ath9k_hw_init_bb(ah, chan); 1580 ath9k_hw_rfbus_done(ah); 1581 1582 if (band_switch || ini_reloaded) { 1583 ah->ah_flags |= AH_FASTCC; 1584 ath9k_hw_init_cal(ah, chan); 1585 ah->ah_flags &= ~AH_FASTCC; 1586 } 1587 1588 return true; 1589 } 1590 1591 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1592 { 1593 u32 gpio_mask = ah->gpio_mask; 1594 int i; 1595 1596 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1597 if (!(gpio_mask & 1)) 1598 continue; 1599 1600 ath9k_hw_gpio_request_out(ah, i, NULL, 1601 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1602 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1603 ath9k_hw_gpio_free(ah, i); 1604 } 1605 } 1606 1607 void ath9k_hw_check_nav(struct ath_hw *ah) 1608 { 1609 struct ath_common *common = ath9k_hw_common(ah); 1610 u32 val; 1611 1612 val = REG_READ(ah, AR_NAV); 1613 if (val != 0xdeadbeef && val > 0x7fff) { 1614 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1615 REG_WRITE(ah, AR_NAV, 0); 1616 } 1617 } 1618 EXPORT_SYMBOL(ath9k_hw_check_nav); 1619 1620 bool ath9k_hw_check_alive(struct ath_hw *ah) 1621 { 1622 int count = 50; 1623 u32 reg, last_val; 1624 1625 /* Check if chip failed to wake up */ 1626 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) 1627 return false; 1628 1629 if (AR_SREV_9300(ah)) 1630 return !ath9k_hw_detect_mac_hang(ah); 1631 1632 if (AR_SREV_9285_12_OR_LATER(ah)) 1633 return true; 1634 1635 last_val = REG_READ(ah, AR_OBS_BUS_1); 1636 do { 1637 reg = REG_READ(ah, AR_OBS_BUS_1); 1638 if (reg != last_val) 1639 return true; 1640 1641 udelay(1); 1642 last_val = reg; 1643 if ((reg & 0x7E7FFFEF) == 0x00702400) 1644 continue; 1645 1646 switch (reg & 0x7E000B00) { 1647 case 0x1E000000: 1648 case 0x52000B00: 1649 case 0x18000B00: 1650 continue; 1651 default: 1652 return true; 1653 } 1654 } while (count-- > 0); 1655 1656 return false; 1657 } 1658 EXPORT_SYMBOL(ath9k_hw_check_alive); 1659 1660 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1661 { 1662 /* Setup MFP options for CCMP */ 1663 if (AR_SREV_9280_20_OR_LATER(ah)) { 1664 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1665 * frames when constructing CCMP AAD. */ 1666 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1667 0xc7ff); 1668 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1669 ah->sw_mgmt_crypto_tx = true; 1670 else 1671 ah->sw_mgmt_crypto_tx = false; 1672 ah->sw_mgmt_crypto_rx = false; 1673 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1674 /* Disable hardware crypto for management frames */ 1675 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1676 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1677 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1678 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1679 ah->sw_mgmt_crypto_tx = true; 1680 ah->sw_mgmt_crypto_rx = true; 1681 } else { 1682 ah->sw_mgmt_crypto_tx = true; 1683 ah->sw_mgmt_crypto_rx = true; 1684 } 1685 } 1686 1687 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1688 u32 macStaId1, u32 saveDefAntenna) 1689 { 1690 struct ath_common *common = ath9k_hw_common(ah); 1691 1692 ENABLE_REGWRITE_BUFFER(ah); 1693 1694 REG_RMW(ah, AR_STA_ID1, macStaId1 1695 | AR_STA_ID1_RTS_USE_DEF 1696 | ah->sta_id1_defaults, 1697 ~AR_STA_ID1_SADH_MASK); 1698 ath_hw_setbssidmask(common); 1699 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1700 ath9k_hw_write_associd(ah); 1701 REG_WRITE(ah, AR_ISR, ~0); 1702 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1703 1704 REGWRITE_BUFFER_FLUSH(ah); 1705 1706 ath9k_hw_set_operating_mode(ah, ah->opmode); 1707 } 1708 1709 static void ath9k_hw_init_queues(struct ath_hw *ah) 1710 { 1711 int i; 1712 1713 ENABLE_REGWRITE_BUFFER(ah); 1714 1715 for (i = 0; i < AR_NUM_DCU; i++) 1716 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1717 1718 REGWRITE_BUFFER_FLUSH(ah); 1719 1720 ah->intr_txqs = 0; 1721 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1722 ath9k_hw_resettxqueue(ah, i); 1723 } 1724 1725 /* 1726 * For big endian systems turn on swapping for descriptors 1727 */ 1728 static void ath9k_hw_init_desc(struct ath_hw *ah) 1729 { 1730 struct ath_common *common = ath9k_hw_common(ah); 1731 1732 if (AR_SREV_9100(ah)) { 1733 u32 mask; 1734 mask = REG_READ(ah, AR_CFG); 1735 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1736 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1737 mask); 1738 } else { 1739 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1740 REG_WRITE(ah, AR_CFG, mask); 1741 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1742 REG_READ(ah, AR_CFG)); 1743 } 1744 } else { 1745 if (common->bus_ops->ath_bus_type == ATH_USB) { 1746 /* Configure AR9271 target WLAN */ 1747 if (AR_SREV_9271(ah)) 1748 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1749 else 1750 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1751 } 1752 #ifdef __BIG_ENDIAN 1753 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1754 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1755 AR_SREV_9561(ah)) 1756 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1757 else 1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1759 #endif 1760 } 1761 } 1762 1763 /* 1764 * Fast channel change: 1765 * (Change synthesizer based on channel freq without resetting chip) 1766 */ 1767 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1768 { 1769 struct ath_common *common = ath9k_hw_common(ah); 1770 struct ath9k_hw_capabilities *pCap = &ah->caps; 1771 int ret; 1772 1773 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1774 goto fail; 1775 1776 if (ah->chip_fullsleep) 1777 goto fail; 1778 1779 if (!ah->curchan) 1780 goto fail; 1781 1782 if (chan->channel == ah->curchan->channel) 1783 goto fail; 1784 1785 if ((ah->curchan->channelFlags | chan->channelFlags) & 1786 (CHANNEL_HALF | CHANNEL_QUARTER)) 1787 goto fail; 1788 1789 /* 1790 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1791 */ 1792 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1793 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1794 goto fail; 1795 1796 if (!ath9k_hw_check_alive(ah)) 1797 goto fail; 1798 1799 /* 1800 * For AR9462, make sure that calibration data for 1801 * re-using are present. 1802 */ 1803 if (AR_SREV_9462(ah) && (ah->caldata && 1804 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1805 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1806 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1807 goto fail; 1808 1809 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1810 ah->curchan->channel, chan->channel); 1811 1812 ret = ath9k_hw_channel_change(ah, chan); 1813 if (!ret) 1814 goto fail; 1815 1816 if (ath9k_hw_mci_is_enabled(ah)) 1817 ar9003_mci_2g5g_switch(ah, false); 1818 1819 ath9k_hw_loadnf(ah, ah->curchan); 1820 ath9k_hw_start_nfcal(ah, true); 1821 1822 if (AR_SREV_9271(ah)) 1823 ar9002_hw_load_ani_reg(ah, chan); 1824 1825 return 0; 1826 fail: 1827 return -EINVAL; 1828 } 1829 1830 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1831 { 1832 struct timespec ts; 1833 s64 usec; 1834 1835 if (!cur) { 1836 getrawmonotonic(&ts); 1837 cur = &ts; 1838 } 1839 1840 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1841 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1842 1843 return (u32) usec; 1844 } 1845 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1846 1847 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1848 struct ath9k_hw_cal_data *caldata, bool fastcc) 1849 { 1850 struct ath_common *common = ath9k_hw_common(ah); 1851 u32 saveLedState; 1852 u32 saveDefAntenna; 1853 u32 macStaId1; 1854 struct timespec tsf_ts; 1855 u32 tsf_offset; 1856 u64 tsf = 0; 1857 int r; 1858 bool start_mci_reset = false; 1859 bool save_fullsleep = ah->chip_fullsleep; 1860 1861 if (ath9k_hw_mci_is_enabled(ah)) { 1862 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1863 if (start_mci_reset) 1864 return 0; 1865 } 1866 1867 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1868 return -EIO; 1869 1870 if (ah->curchan && !ah->chip_fullsleep) 1871 ath9k_hw_getnf(ah, ah->curchan); 1872 1873 ah->caldata = caldata; 1874 if (caldata && (chan->channel != caldata->channel || 1875 chan->channelFlags != caldata->channelFlags)) { 1876 /* Operating channel changed, reset channel calibration data */ 1877 memset(caldata, 0, sizeof(*caldata)); 1878 ath9k_init_nfcal_hist_buffer(ah, chan); 1879 } else if (caldata) { 1880 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1881 } 1882 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1883 1884 if (fastcc) { 1885 r = ath9k_hw_do_fastcc(ah, chan); 1886 if (!r) 1887 return r; 1888 } 1889 1890 if (ath9k_hw_mci_is_enabled(ah)) 1891 ar9003_mci_stop_bt(ah, save_fullsleep); 1892 1893 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1894 if (saveDefAntenna == 0) 1895 saveDefAntenna = 1; 1896 1897 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1898 1899 /* Save TSF before chip reset, a cold reset clears it */ 1900 getrawmonotonic(&tsf_ts); 1901 tsf = ath9k_hw_gettsf64(ah); 1902 1903 saveLedState = REG_READ(ah, AR_CFG_LED) & 1904 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1905 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1906 1907 ath9k_hw_mark_phy_inactive(ah); 1908 1909 ah->paprd_table_write_done = false; 1910 1911 /* Only required on the first reset */ 1912 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1913 REG_WRITE(ah, 1914 AR9271_RESET_POWER_DOWN_CONTROL, 1915 AR9271_RADIO_RF_RST); 1916 udelay(50); 1917 } 1918 1919 if (!ath9k_hw_chip_reset(ah, chan)) { 1920 ath_err(common, "Chip reset failed\n"); 1921 return -EINVAL; 1922 } 1923 1924 /* Only required on the first reset */ 1925 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1926 ah->htc_reset_init = false; 1927 REG_WRITE(ah, 1928 AR9271_RESET_POWER_DOWN_CONTROL, 1929 AR9271_GATE_MAC_CTL); 1930 udelay(50); 1931 } 1932 1933 /* Restore TSF */ 1934 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1935 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1936 1937 if (AR_SREV_9280_20_OR_LATER(ah)) 1938 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1939 1940 if (!AR_SREV_9300_20_OR_LATER(ah)) 1941 ar9002_hw_enable_async_fifo(ah); 1942 1943 r = ath9k_hw_process_ini(ah, chan); 1944 if (r) 1945 return r; 1946 1947 ath9k_hw_set_rfmode(ah, chan); 1948 1949 if (ath9k_hw_mci_is_enabled(ah)) 1950 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1951 1952 /* 1953 * Some AR91xx SoC devices frequently fail to accept TSF writes 1954 * right after the chip reset. When that happens, write a new 1955 * value after the initvals have been applied. 1956 */ 1957 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1958 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1959 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1960 } 1961 1962 ath9k_hw_init_mfp(ah); 1963 1964 ath9k_hw_set_delta_slope(ah, chan); 1965 ath9k_hw_spur_mitigate_freq(ah, chan); 1966 ah->eep_ops->set_board_values(ah, chan); 1967 1968 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1969 1970 r = ath9k_hw_rf_set_freq(ah, chan); 1971 if (r) 1972 return r; 1973 1974 ath9k_hw_set_clockrate(ah); 1975 1976 ath9k_hw_init_queues(ah); 1977 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1978 ath9k_hw_ani_cache_ini_regs(ah); 1979 ath9k_hw_init_qos(ah); 1980 1981 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1982 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); 1983 1984 ath9k_hw_init_global_settings(ah); 1985 1986 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1987 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1988 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1989 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1990 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1991 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1992 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1993 } 1994 1995 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1996 1997 ath9k_hw_set_dma(ah); 1998 1999 if (!ath9k_hw_mci_is_enabled(ah)) 2000 REG_WRITE(ah, AR_OBS, 8); 2001 2002 ENABLE_REG_RMW_BUFFER(ah); 2003 if (ah->config.rx_intr_mitigation) { 2004 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 2005 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 2006 } 2007 2008 if (ah->config.tx_intr_mitigation) { 2009 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2010 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2011 } 2012 REG_RMW_BUFFER_FLUSH(ah); 2013 2014 ath9k_hw_init_bb(ah, chan); 2015 2016 if (caldata) { 2017 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 2018 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 2019 } 2020 if (!ath9k_hw_init_cal(ah, chan)) 2021 return -EIO; 2022 2023 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2024 return -EIO; 2025 2026 ENABLE_REGWRITE_BUFFER(ah); 2027 2028 ath9k_hw_restore_chainmask(ah); 2029 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2030 2031 REGWRITE_BUFFER_FLUSH(ah); 2032 2033 ath9k_hw_gen_timer_start_tsf2(ah); 2034 2035 ath9k_hw_init_desc(ah); 2036 2037 if (ath9k_hw_btcoex_is_enabled(ah)) 2038 ath9k_hw_btcoex_enable(ah); 2039 2040 if (ath9k_hw_mci_is_enabled(ah)) 2041 ar9003_mci_check_bt(ah); 2042 2043 if (AR_SREV_9300_20_OR_LATER(ah)) { 2044 ath9k_hw_loadnf(ah, chan); 2045 ath9k_hw_start_nfcal(ah, true); 2046 } 2047 2048 if (AR_SREV_9300_20_OR_LATER(ah)) 2049 ar9003_hw_bb_watchdog_config(ah); 2050 2051 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 2052 ar9003_hw_disable_phy_restart(ah); 2053 2054 ath9k_hw_apply_gpio_override(ah); 2055 2056 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2057 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2058 2059 if (ah->hw->conf.radar_enabled) { 2060 /* set HW specific DFS configuration */ 2061 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 2062 ath9k_hw_set_radar_params(ah); 2063 } 2064 2065 return 0; 2066 } 2067 EXPORT_SYMBOL(ath9k_hw_reset); 2068 2069 /******************************/ 2070 /* Power Management (Chipset) */ 2071 /******************************/ 2072 2073 /* 2074 * Notify Power Mgt is disabled in self-generated frames. 2075 * If requested, force chip to sleep. 2076 */ 2077 static void ath9k_set_power_sleep(struct ath_hw *ah) 2078 { 2079 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2080 2081 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2082 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2083 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2084 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2085 /* xxx Required for WLAN only case ? */ 2086 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2087 udelay(100); 2088 } 2089 2090 /* 2091 * Clear the RTC force wake bit to allow the 2092 * mac to go to sleep. 2093 */ 2094 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2095 2096 if (ath9k_hw_mci_is_enabled(ah)) 2097 udelay(100); 2098 2099 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2100 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2101 2102 /* Shutdown chip. Active low */ 2103 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2104 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2105 udelay(2); 2106 } 2107 2108 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2109 if (AR_SREV_9300_20_OR_LATER(ah)) 2110 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2111 } 2112 2113 /* 2114 * Notify Power Management is enabled in self-generating 2115 * frames. If request, set power mode of chip to 2116 * auto/normal. Duration in units of 128us (1/8 TU). 2117 */ 2118 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2119 { 2120 struct ath9k_hw_capabilities *pCap = &ah->caps; 2121 2122 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2123 2124 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2125 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2126 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2127 AR_RTC_FORCE_WAKE_ON_INT); 2128 } else { 2129 2130 /* When chip goes into network sleep, it could be waken 2131 * up by MCI_INT interrupt caused by BT's HW messages 2132 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2133 * rate (~100us). This will cause chip to leave and 2134 * re-enter network sleep mode frequently, which in 2135 * consequence will have WLAN MCI HW to generate lots of 2136 * SYS_WAKING and SYS_SLEEPING messages which will make 2137 * BT CPU to busy to process. 2138 */ 2139 if (ath9k_hw_mci_is_enabled(ah)) 2140 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2141 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2142 /* 2143 * Clear the RTC force wake bit to allow the 2144 * mac to go to sleep. 2145 */ 2146 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2147 2148 if (ath9k_hw_mci_is_enabled(ah)) 2149 udelay(30); 2150 } 2151 2152 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2153 if (AR_SREV_9300_20_OR_LATER(ah)) 2154 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2155 } 2156 2157 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2158 { 2159 u32 val; 2160 int i; 2161 2162 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2163 if (AR_SREV_9300_20_OR_LATER(ah)) { 2164 REG_WRITE(ah, AR_WA, ah->WARegVal); 2165 udelay(10); 2166 } 2167 2168 if ((REG_READ(ah, AR_RTC_STATUS) & 2169 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2170 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2171 return false; 2172 } 2173 if (!AR_SREV_9300_20_OR_LATER(ah)) 2174 ath9k_hw_init_pll(ah, NULL); 2175 } 2176 if (AR_SREV_9100(ah)) 2177 REG_SET_BIT(ah, AR_RTC_RESET, 2178 AR_RTC_RESET_EN); 2179 2180 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2181 AR_RTC_FORCE_WAKE_EN); 2182 if (AR_SREV_9100(ah)) 2183 mdelay(10); 2184 else 2185 udelay(50); 2186 2187 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2188 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2189 if (val == AR_RTC_STATUS_ON) 2190 break; 2191 udelay(50); 2192 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2193 AR_RTC_FORCE_WAKE_EN); 2194 } 2195 if (i == 0) { 2196 ath_err(ath9k_hw_common(ah), 2197 "Failed to wakeup in %uus\n", 2198 POWER_UP_TIME / 20); 2199 return false; 2200 } 2201 2202 if (ath9k_hw_mci_is_enabled(ah)) 2203 ar9003_mci_set_power_awake(ah); 2204 2205 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2206 2207 return true; 2208 } 2209 2210 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2211 { 2212 struct ath_common *common = ath9k_hw_common(ah); 2213 int status = true; 2214 static const char *modes[] = { 2215 "AWAKE", 2216 "FULL-SLEEP", 2217 "NETWORK SLEEP", 2218 "UNDEFINED" 2219 }; 2220 2221 if (ah->power_mode == mode) 2222 return status; 2223 2224 ath_dbg(common, RESET, "%s -> %s\n", 2225 modes[ah->power_mode], modes[mode]); 2226 2227 switch (mode) { 2228 case ATH9K_PM_AWAKE: 2229 status = ath9k_hw_set_power_awake(ah); 2230 break; 2231 case ATH9K_PM_FULL_SLEEP: 2232 if (ath9k_hw_mci_is_enabled(ah)) 2233 ar9003_mci_set_full_sleep(ah); 2234 2235 ath9k_set_power_sleep(ah); 2236 ah->chip_fullsleep = true; 2237 break; 2238 case ATH9K_PM_NETWORK_SLEEP: 2239 ath9k_set_power_network_sleep(ah); 2240 break; 2241 default: 2242 ath_err(common, "Unknown power mode %u\n", mode); 2243 return false; 2244 } 2245 ah->power_mode = mode; 2246 2247 /* 2248 * XXX: If this warning never comes up after a while then 2249 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2250 * ath9k_hw_setpower() return type void. 2251 */ 2252 2253 if (!(ah->ah_flags & AH_UNPLUGGED)) 2254 ATH_DBG_WARN_ON_ONCE(!status); 2255 2256 return status; 2257 } 2258 EXPORT_SYMBOL(ath9k_hw_setpower); 2259 2260 /*******************/ 2261 /* Beacon Handling */ 2262 /*******************/ 2263 2264 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2265 { 2266 int flags = 0; 2267 2268 ENABLE_REGWRITE_BUFFER(ah); 2269 2270 switch (ah->opmode) { 2271 case NL80211_IFTYPE_ADHOC: 2272 REG_SET_BIT(ah, AR_TXCFG, 2273 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2274 case NL80211_IFTYPE_MESH_POINT: 2275 case NL80211_IFTYPE_AP: 2276 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2277 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2278 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2279 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2280 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2281 flags |= 2282 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2283 break; 2284 default: 2285 ath_dbg(ath9k_hw_common(ah), BEACON, 2286 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2287 return; 2288 break; 2289 } 2290 2291 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2292 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2293 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2294 2295 REGWRITE_BUFFER_FLUSH(ah); 2296 2297 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2298 } 2299 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2300 2301 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2302 const struct ath9k_beacon_state *bs) 2303 { 2304 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2305 struct ath9k_hw_capabilities *pCap = &ah->caps; 2306 struct ath_common *common = ath9k_hw_common(ah); 2307 2308 ENABLE_REGWRITE_BUFFER(ah); 2309 2310 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2311 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2313 2314 REGWRITE_BUFFER_FLUSH(ah); 2315 2316 REG_RMW_FIELD(ah, AR_RSSI_THR, 2317 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2318 2319 beaconintval = bs->bs_intval; 2320 2321 if (bs->bs_sleepduration > beaconintval) 2322 beaconintval = bs->bs_sleepduration; 2323 2324 dtimperiod = bs->bs_dtimperiod; 2325 if (bs->bs_sleepduration > dtimperiod) 2326 dtimperiod = bs->bs_sleepduration; 2327 2328 if (beaconintval == dtimperiod) 2329 nextTbtt = bs->bs_nextdtim; 2330 else 2331 nextTbtt = bs->bs_nexttbtt; 2332 2333 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); 2334 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt); 2335 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval); 2336 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod); 2337 2338 ENABLE_REGWRITE_BUFFER(ah); 2339 2340 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2341 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2342 2343 REG_WRITE(ah, AR_SLEEP1, 2344 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2345 | AR_SLEEP1_ASSUME_DTIM); 2346 2347 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2348 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2349 else 2350 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2351 2352 REG_WRITE(ah, AR_SLEEP2, 2353 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2354 2355 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2356 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2357 2358 REGWRITE_BUFFER_FLUSH(ah); 2359 2360 REG_SET_BIT(ah, AR_TIMER_MODE, 2361 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2362 AR_DTIM_TIMER_EN); 2363 2364 /* TSF Out of Range Threshold */ 2365 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2366 } 2367 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2368 2369 /*******************/ 2370 /* HW Capabilities */ 2371 /*******************/ 2372 2373 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2374 { 2375 eeprom_chainmask &= chip_chainmask; 2376 if (eeprom_chainmask) 2377 return eeprom_chainmask; 2378 else 2379 return chip_chainmask; 2380 } 2381 2382 /** 2383 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2384 * @ah: the atheros hardware data structure 2385 * 2386 * We enable DFS support upstream on chipsets which have passed a series 2387 * of tests. The testing requirements are going to be documented. Desired 2388 * test requirements are documented at: 2389 * 2390 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2391 * 2392 * Once a new chipset gets properly tested an individual commit can be used 2393 * to document the testing for DFS for that chipset. 2394 */ 2395 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2396 { 2397 2398 switch (ah->hw_version.macVersion) { 2399 /* for temporary testing DFS with 9280 */ 2400 case AR_SREV_VERSION_9280: 2401 /* AR9580 will likely be our first target to get testing on */ 2402 case AR_SREV_VERSION_9580: 2403 return true; 2404 default: 2405 return false; 2406 } 2407 } 2408 2409 static void ath9k_gpio_cap_init(struct ath_hw *ah) 2410 { 2411 struct ath9k_hw_capabilities *pCap = &ah->caps; 2412 2413 if (AR_SREV_9271(ah)) { 2414 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2415 pCap->gpio_mask = AR9271_GPIO_MASK; 2416 } else if (AR_DEVID_7010(ah)) { 2417 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2418 pCap->gpio_mask = AR7010_GPIO_MASK; 2419 } else if (AR_SREV_9287(ah)) { 2420 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2421 pCap->gpio_mask = AR9287_GPIO_MASK; 2422 } else if (AR_SREV_9285(ah)) { 2423 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2424 pCap->gpio_mask = AR9285_GPIO_MASK; 2425 } else if (AR_SREV_9280(ah)) { 2426 pCap->num_gpio_pins = AR9280_NUM_GPIO; 2427 pCap->gpio_mask = AR9280_GPIO_MASK; 2428 } else if (AR_SREV_9300(ah)) { 2429 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2430 pCap->gpio_mask = AR9300_GPIO_MASK; 2431 } else if (AR_SREV_9330(ah)) { 2432 pCap->num_gpio_pins = AR9330_NUM_GPIO; 2433 pCap->gpio_mask = AR9330_GPIO_MASK; 2434 } else if (AR_SREV_9340(ah)) { 2435 pCap->num_gpio_pins = AR9340_NUM_GPIO; 2436 pCap->gpio_mask = AR9340_GPIO_MASK; 2437 } else if (AR_SREV_9462(ah)) { 2438 pCap->num_gpio_pins = AR9462_NUM_GPIO; 2439 pCap->gpio_mask = AR9462_GPIO_MASK; 2440 } else if (AR_SREV_9485(ah)) { 2441 pCap->num_gpio_pins = AR9485_NUM_GPIO; 2442 pCap->gpio_mask = AR9485_GPIO_MASK; 2443 } else if (AR_SREV_9531(ah)) { 2444 pCap->num_gpio_pins = AR9531_NUM_GPIO; 2445 pCap->gpio_mask = AR9531_GPIO_MASK; 2446 } else if (AR_SREV_9550(ah)) { 2447 pCap->num_gpio_pins = AR9550_NUM_GPIO; 2448 pCap->gpio_mask = AR9550_GPIO_MASK; 2449 } else if (AR_SREV_9561(ah)) { 2450 pCap->num_gpio_pins = AR9561_NUM_GPIO; 2451 pCap->gpio_mask = AR9561_GPIO_MASK; 2452 } else if (AR_SREV_9565(ah)) { 2453 pCap->num_gpio_pins = AR9565_NUM_GPIO; 2454 pCap->gpio_mask = AR9565_GPIO_MASK; 2455 } else if (AR_SREV_9580(ah)) { 2456 pCap->num_gpio_pins = AR9580_NUM_GPIO; 2457 pCap->gpio_mask = AR9580_GPIO_MASK; 2458 } else { 2459 pCap->num_gpio_pins = AR_NUM_GPIO; 2460 pCap->gpio_mask = AR_GPIO_MASK; 2461 } 2462 } 2463 2464 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2465 { 2466 struct ath9k_hw_capabilities *pCap = &ah->caps; 2467 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2468 struct ath_common *common = ath9k_hw_common(ah); 2469 2470 u16 eeval; 2471 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2472 2473 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2474 regulatory->current_rd = eeval; 2475 2476 if (ah->opmode != NL80211_IFTYPE_AP && 2477 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2478 if (regulatory->current_rd == 0x64 || 2479 regulatory->current_rd == 0x65) 2480 regulatory->current_rd += 5; 2481 else if (regulatory->current_rd == 0x41) 2482 regulatory->current_rd = 0x43; 2483 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2484 regulatory->current_rd); 2485 } 2486 2487 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2488 2489 if (eeval & AR5416_OPFLAGS_11A) { 2490 if (ah->disable_5ghz) 2491 ath_warn(common, "disabling 5GHz band\n"); 2492 else 2493 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2494 } 2495 2496 if (eeval & AR5416_OPFLAGS_11G) { 2497 if (ah->disable_2ghz) 2498 ath_warn(common, "disabling 2GHz band\n"); 2499 else 2500 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2501 } 2502 2503 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2504 ath_err(common, "both bands are disabled\n"); 2505 return -EINVAL; 2506 } 2507 2508 ath9k_gpio_cap_init(ah); 2509 2510 if (AR_SREV_9485(ah) || 2511 AR_SREV_9285(ah) || 2512 AR_SREV_9330(ah) || 2513 AR_SREV_9565(ah)) 2514 pCap->chip_chainmask = 1; 2515 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2516 pCap->chip_chainmask = 7; 2517 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2518 AR_SREV_9340(ah) || 2519 AR_SREV_9462(ah) || 2520 AR_SREV_9531(ah)) 2521 pCap->chip_chainmask = 3; 2522 else 2523 pCap->chip_chainmask = 7; 2524 2525 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2526 /* 2527 * For AR9271 we will temporarilly uses the rx chainmax as read from 2528 * the EEPROM. 2529 */ 2530 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2531 !(eeval & AR5416_OPFLAGS_11A) && 2532 !(AR_SREV_9271(ah))) 2533 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2534 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2535 else if (AR_SREV_9100(ah)) 2536 pCap->rx_chainmask = 0x7; 2537 else 2538 /* Use rx_chainmask from EEPROM. */ 2539 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2540 2541 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2542 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2543 ah->txchainmask = pCap->tx_chainmask; 2544 ah->rxchainmask = pCap->rx_chainmask; 2545 2546 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2547 2548 /* enable key search for every frame in an aggregate */ 2549 if (AR_SREV_9300_20_OR_LATER(ah)) 2550 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2551 2552 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2553 2554 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2555 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2556 else 2557 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2558 2559 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2560 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2561 else 2562 pCap->rts_aggr_limit = (8 * 1024); 2563 2564 #ifdef CONFIG_ATH9K_RFKILL 2565 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2566 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2567 ah->rfkill_gpio = 2568 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2569 ah->rfkill_polarity = 2570 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2571 2572 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2573 } 2574 #endif 2575 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2576 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2577 else 2578 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2579 2580 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2581 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2582 else 2583 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2584 2585 if (AR_SREV_9300_20_OR_LATER(ah)) { 2586 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2587 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2588 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2589 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2590 2591 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2592 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2593 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2594 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2595 pCap->txs_len = sizeof(struct ar9003_txs); 2596 } else { 2597 pCap->tx_desc_len = sizeof(struct ath_desc); 2598 if (AR_SREV_9280_20(ah)) 2599 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2600 } 2601 2602 if (AR_SREV_9300_20_OR_LATER(ah)) 2603 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2604 2605 if (AR_SREV_9561(ah)) 2606 ah->ent_mode = 0x3BDA000; 2607 else if (AR_SREV_9300_20_OR_LATER(ah)) 2608 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2609 2610 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2611 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2612 2613 if (AR_SREV_9285(ah)) { 2614 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2615 ant_div_ctl1 = 2616 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2617 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2618 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2619 ath_info(common, "Enable LNA combining\n"); 2620 } 2621 } 2622 } 2623 2624 if (AR_SREV_9300_20_OR_LATER(ah)) { 2625 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2626 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2627 } 2628 2629 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2630 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2631 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2632 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2633 ath_info(common, "Enable LNA combining\n"); 2634 } 2635 } 2636 2637 if (ath9k_hw_dfs_tested(ah)) 2638 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2639 2640 tx_chainmask = pCap->tx_chainmask; 2641 rx_chainmask = pCap->rx_chainmask; 2642 while (tx_chainmask || rx_chainmask) { 2643 if (tx_chainmask & BIT(0)) 2644 pCap->max_txchains++; 2645 if (rx_chainmask & BIT(0)) 2646 pCap->max_rxchains++; 2647 2648 tx_chainmask >>= 1; 2649 rx_chainmask >>= 1; 2650 } 2651 2652 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2653 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2654 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2655 2656 if (AR_SREV_9462_20_OR_LATER(ah)) 2657 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2658 } 2659 2660 if (AR_SREV_9300_20_OR_LATER(ah) && 2661 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2662 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2663 2664 #ifdef CONFIG_ATH9K_WOW 2665 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2666 ah->wow.max_patterns = MAX_NUM_PATTERN; 2667 else 2668 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2669 #endif 2670 2671 return 0; 2672 } 2673 2674 /****************************/ 2675 /* GPIO / RFKILL / Antennae */ 2676 /****************************/ 2677 2678 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) 2679 { 2680 int addr; 2681 u32 gpio_shift, tmp; 2682 2683 if (gpio > 11) 2684 addr = AR_GPIO_OUTPUT_MUX3; 2685 else if (gpio > 5) 2686 addr = AR_GPIO_OUTPUT_MUX2; 2687 else 2688 addr = AR_GPIO_OUTPUT_MUX1; 2689 2690 gpio_shift = (gpio % 6) * 5; 2691 2692 if (AR_SREV_9280_20_OR_LATER(ah) || 2693 (addr != AR_GPIO_OUTPUT_MUX1)) { 2694 REG_RMW(ah, addr, (type << gpio_shift), 2695 (0x1f << gpio_shift)); 2696 } else { 2697 tmp = REG_READ(ah, addr); 2698 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2699 tmp &= ~(0x1f << gpio_shift); 2700 tmp |= (type << gpio_shift); 2701 REG_WRITE(ah, addr, tmp); 2702 } 2703 } 2704 2705 /* BSP should set the corresponding MUX register correctly. 2706 */ 2707 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, 2708 const char *label) 2709 { 2710 if (ah->caps.gpio_requested & BIT(gpio)) 2711 return; 2712 2713 /* may be requested by BSP, free anyway */ 2714 gpio_free(gpio); 2715 2716 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label)) 2717 return; 2718 2719 ah->caps.gpio_requested |= BIT(gpio); 2720 } 2721 2722 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, 2723 u32 ah_signal_type) 2724 { 2725 u32 gpio_set, gpio_shift = gpio; 2726 2727 if (AR_DEVID_7010(ah)) { 2728 gpio_set = out ? 2729 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT; 2730 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, 2731 AR7010_GPIO_OE_MASK << gpio_shift); 2732 } else if (AR_SREV_SOC(ah)) { 2733 gpio_set = out ? 1 : 0; 2734 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2735 gpio_set << gpio_shift); 2736 } else { 2737 gpio_shift = gpio << 1; 2738 gpio_set = out ? 2739 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO; 2740 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2741 AR_GPIO_OE_OUT_DRV << gpio_shift); 2742 2743 if (out) 2744 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2745 } 2746 } 2747 2748 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, 2749 const char *label, u32 ah_signal_type) 2750 { 2751 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2752 2753 if (BIT(gpio) & ah->caps.gpio_mask) 2754 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); 2755 else if (AR_SREV_SOC(ah)) 2756 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); 2757 else 2758 WARN_ON(1); 2759 } 2760 2761 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) 2762 { 2763 ath9k_hw_gpio_request(ah, gpio, false, label, 0); 2764 } 2765 EXPORT_SYMBOL(ath9k_hw_gpio_request_in); 2766 2767 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, 2768 u32 ah_signal_type) 2769 { 2770 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); 2771 } 2772 EXPORT_SYMBOL(ath9k_hw_gpio_request_out); 2773 2774 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) 2775 { 2776 if (!AR_SREV_SOC(ah)) 2777 return; 2778 2779 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2780 2781 if (ah->caps.gpio_requested & BIT(gpio)) { 2782 gpio_free(gpio); 2783 ah->caps.gpio_requested &= ~BIT(gpio); 2784 } 2785 } 2786 EXPORT_SYMBOL(ath9k_hw_gpio_free); 2787 2788 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2789 { 2790 u32 val = 0xffffffff; 2791 2792 #define MS_REG_READ(x, y) \ 2793 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) 2794 2795 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2796 2797 if (BIT(gpio) & ah->caps.gpio_mask) { 2798 if (AR_SREV_9271(ah)) 2799 val = MS_REG_READ(AR9271, gpio); 2800 else if (AR_SREV_9287(ah)) 2801 val = MS_REG_READ(AR9287, gpio); 2802 else if (AR_SREV_9285(ah)) 2803 val = MS_REG_READ(AR9285, gpio); 2804 else if (AR_SREV_9280(ah)) 2805 val = MS_REG_READ(AR928X, gpio); 2806 else if (AR_DEVID_7010(ah)) 2807 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); 2808 else if (AR_SREV_9300_20_OR_LATER(ah)) 2809 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); 2810 else 2811 val = MS_REG_READ(AR, gpio); 2812 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2813 val = gpio_get_value(gpio) & BIT(gpio); 2814 } else { 2815 WARN_ON(1); 2816 } 2817 2818 return !!val; 2819 } 2820 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2821 2822 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2823 { 2824 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2825 2826 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) 2827 val = !val; 2828 else 2829 val = !!val; 2830 2831 if (BIT(gpio) & ah->caps.gpio_mask) { 2832 u32 out_addr = AR_DEVID_7010(ah) ? 2833 AR7010_GPIO_OUT : AR_GPIO_IN_OUT; 2834 2835 REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); 2836 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2837 gpio_set_value(gpio, val); 2838 } else { 2839 WARN_ON(1); 2840 } 2841 } 2842 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2843 2844 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2845 { 2846 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2847 } 2848 EXPORT_SYMBOL(ath9k_hw_setantenna); 2849 2850 /*********************/ 2851 /* General Operation */ 2852 /*********************/ 2853 2854 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2855 { 2856 u32 bits = REG_READ(ah, AR_RX_FILTER); 2857 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2858 2859 if (phybits & AR_PHY_ERR_RADAR) 2860 bits |= ATH9K_RX_FILTER_PHYRADAR; 2861 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2862 bits |= ATH9K_RX_FILTER_PHYERR; 2863 2864 return bits; 2865 } 2866 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2867 2868 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2869 { 2870 u32 phybits; 2871 2872 ENABLE_REGWRITE_BUFFER(ah); 2873 2874 REG_WRITE(ah, AR_RX_FILTER, bits); 2875 2876 phybits = 0; 2877 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2878 phybits |= AR_PHY_ERR_RADAR; 2879 if (bits & ATH9K_RX_FILTER_PHYERR) 2880 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2881 REG_WRITE(ah, AR_PHY_ERR, phybits); 2882 2883 if (phybits) 2884 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2885 else 2886 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2887 2888 REGWRITE_BUFFER_FLUSH(ah); 2889 } 2890 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2891 2892 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2893 { 2894 if (ath9k_hw_mci_is_enabled(ah)) 2895 ar9003_mci_bt_gain_ctrl(ah); 2896 2897 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2898 return false; 2899 2900 ath9k_hw_init_pll(ah, NULL); 2901 ah->htc_reset_init = true; 2902 return true; 2903 } 2904 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2905 2906 bool ath9k_hw_disable(struct ath_hw *ah) 2907 { 2908 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2909 return false; 2910 2911 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2912 return false; 2913 2914 ath9k_hw_init_pll(ah, NULL); 2915 return true; 2916 } 2917 EXPORT_SYMBOL(ath9k_hw_disable); 2918 2919 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2920 { 2921 enum eeprom_param gain_param; 2922 2923 if (IS_CHAN_2GHZ(chan)) 2924 gain_param = EEP_ANTENNA_GAIN_2G; 2925 else 2926 gain_param = EEP_ANTENNA_GAIN_5G; 2927 2928 return ah->eep_ops->get_eeprom(ah, gain_param); 2929 } 2930 2931 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2932 bool test) 2933 { 2934 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2935 struct ieee80211_channel *channel; 2936 int chan_pwr, new_pwr; 2937 2938 if (!chan) 2939 return; 2940 2941 channel = chan->chan; 2942 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2943 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2944 2945 ah->eep_ops->set_txpower(ah, chan, 2946 ath9k_regd_get_ctl(reg, chan), 2947 get_antenna_gain(ah, chan), new_pwr, test); 2948 } 2949 2950 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2951 { 2952 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2953 struct ath9k_channel *chan = ah->curchan; 2954 struct ieee80211_channel *channel = chan->chan; 2955 2956 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2957 if (test) 2958 channel->max_power = MAX_RATE_POWER / 2; 2959 2960 ath9k_hw_apply_txpower(ah, chan, test); 2961 2962 if (test) 2963 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2964 } 2965 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2966 2967 void ath9k_hw_setopmode(struct ath_hw *ah) 2968 { 2969 ath9k_hw_set_operating_mode(ah, ah->opmode); 2970 } 2971 EXPORT_SYMBOL(ath9k_hw_setopmode); 2972 2973 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2974 { 2975 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2976 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2977 } 2978 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2979 2980 void ath9k_hw_write_associd(struct ath_hw *ah) 2981 { 2982 struct ath_common *common = ath9k_hw_common(ah); 2983 2984 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2985 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2986 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2987 } 2988 EXPORT_SYMBOL(ath9k_hw_write_associd); 2989 2990 #define ATH9K_MAX_TSF_READ 10 2991 2992 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2993 { 2994 u32 tsf_lower, tsf_upper1, tsf_upper2; 2995 int i; 2996 2997 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2998 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2999 tsf_lower = REG_READ(ah, AR_TSF_L32); 3000 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 3001 if (tsf_upper2 == tsf_upper1) 3002 break; 3003 tsf_upper1 = tsf_upper2; 3004 } 3005 3006 WARN_ON( i == ATH9K_MAX_TSF_READ ); 3007 3008 return (((u64)tsf_upper1 << 32) | tsf_lower); 3009 } 3010 EXPORT_SYMBOL(ath9k_hw_gettsf64); 3011 3012 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3013 { 3014 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3015 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3016 } 3017 EXPORT_SYMBOL(ath9k_hw_settsf64); 3018 3019 void ath9k_hw_reset_tsf(struct ath_hw *ah) 3020 { 3021 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3022 AH_TSF_WRITE_TIMEOUT)) 3023 ath_dbg(ath9k_hw_common(ah), RESET, 3024 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3025 3026 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3027 } 3028 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 3029 3030 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 3031 { 3032 if (set) 3033 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3034 else 3035 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3036 } 3037 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 3038 3039 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 3040 { 3041 u32 macmode; 3042 3043 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 3044 macmode = AR_2040_JOINED_RX_CLEAR; 3045 else 3046 macmode = 0; 3047 3048 REG_WRITE(ah, AR_2040_MODE, macmode); 3049 } 3050 3051 /* HW Generic timers configuration */ 3052 3053 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 3054 { 3055 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3056 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3057 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3058 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3059 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3060 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3061 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3062 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3063 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 3064 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 3065 AR_NDP2_TIMER_MODE, 0x0002}, 3066 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3067 AR_NDP2_TIMER_MODE, 0x0004}, 3068 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3069 AR_NDP2_TIMER_MODE, 0x0008}, 3070 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3071 AR_NDP2_TIMER_MODE, 0x0010}, 3072 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3073 AR_NDP2_TIMER_MODE, 0x0020}, 3074 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3075 AR_NDP2_TIMER_MODE, 0x0040}, 3076 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3077 AR_NDP2_TIMER_MODE, 0x0080} 3078 }; 3079 3080 /* HW generic timer primitives */ 3081 3082 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3083 { 3084 return REG_READ(ah, AR_TSF_L32); 3085 } 3086 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3087 3088 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 3089 { 3090 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3091 3092 if (timer_table->tsf2_enabled) { 3093 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 3094 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 3095 } 3096 } 3097 3098 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3099 void (*trigger)(void *), 3100 void (*overflow)(void *), 3101 void *arg, 3102 u8 timer_index) 3103 { 3104 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3105 struct ath_gen_timer *timer; 3106 3107 if ((timer_index < AR_FIRST_NDP_TIMER) || 3108 (timer_index >= ATH_MAX_GEN_TIMER)) 3109 return NULL; 3110 3111 if ((timer_index > AR_FIRST_NDP_TIMER) && 3112 !AR_SREV_9300_20_OR_LATER(ah)) 3113 return NULL; 3114 3115 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3116 if (timer == NULL) 3117 return NULL; 3118 3119 /* allocate a hardware generic timer slot */ 3120 timer_table->timers[timer_index] = timer; 3121 timer->index = timer_index; 3122 timer->trigger = trigger; 3123 timer->overflow = overflow; 3124 timer->arg = arg; 3125 3126 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 3127 timer_table->tsf2_enabled = true; 3128 ath9k_hw_gen_timer_start_tsf2(ah); 3129 } 3130 3131 return timer; 3132 } 3133 EXPORT_SYMBOL(ath_gen_timer_alloc); 3134 3135 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3136 struct ath_gen_timer *timer, 3137 u32 timer_next, 3138 u32 timer_period) 3139 { 3140 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3141 u32 mask = 0; 3142 3143 timer_table->timer_mask |= BIT(timer->index); 3144 3145 /* 3146 * Program generic timer registers 3147 */ 3148 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3149 timer_next); 3150 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3151 timer_period); 3152 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3153 gen_tmr_configuration[timer->index].mode_mask); 3154 3155 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3156 /* 3157 * Starting from AR9462, each generic timer can select which tsf 3158 * to use. But we still follow the old rule, 0 - 7 use tsf and 3159 * 8 - 15 use tsf2. 3160 */ 3161 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3162 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3163 (1 << timer->index)); 3164 else 3165 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3166 (1 << timer->index)); 3167 } 3168 3169 if (timer->trigger) 3170 mask |= SM(AR_GENTMR_BIT(timer->index), 3171 AR_IMR_S5_GENTIMER_TRIG); 3172 if (timer->overflow) 3173 mask |= SM(AR_GENTMR_BIT(timer->index), 3174 AR_IMR_S5_GENTIMER_THRESH); 3175 3176 REG_SET_BIT(ah, AR_IMR_S5, mask); 3177 3178 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3179 ah->imask |= ATH9K_INT_GENTIMER; 3180 ath9k_hw_set_interrupts(ah); 3181 } 3182 } 3183 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3184 3185 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3186 { 3187 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3188 3189 /* Clear generic timer enable bits. */ 3190 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3191 gen_tmr_configuration[timer->index].mode_mask); 3192 3193 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3194 /* 3195 * Need to switch back to TSF if it was using TSF2. 3196 */ 3197 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3198 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3199 (1 << timer->index)); 3200 } 3201 } 3202 3203 /* Disable both trigger and thresh interrupt masks */ 3204 REG_CLR_BIT(ah, AR_IMR_S5, 3205 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3206 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3207 3208 timer_table->timer_mask &= ~BIT(timer->index); 3209 3210 if (timer_table->timer_mask == 0) { 3211 ah->imask &= ~ATH9K_INT_GENTIMER; 3212 ath9k_hw_set_interrupts(ah); 3213 } 3214 } 3215 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3216 3217 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3218 { 3219 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3220 3221 /* free the hardware generic timer slot */ 3222 timer_table->timers[timer->index] = NULL; 3223 kfree(timer); 3224 } 3225 EXPORT_SYMBOL(ath_gen_timer_free); 3226 3227 /* 3228 * Generic Timer Interrupts handling 3229 */ 3230 void ath_gen_timer_isr(struct ath_hw *ah) 3231 { 3232 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3233 struct ath_gen_timer *timer; 3234 unsigned long trigger_mask, thresh_mask; 3235 unsigned int index; 3236 3237 /* get hardware generic timer interrupt status */ 3238 trigger_mask = ah->intr_gen_timer_trigger; 3239 thresh_mask = ah->intr_gen_timer_thresh; 3240 trigger_mask &= timer_table->timer_mask; 3241 thresh_mask &= timer_table->timer_mask; 3242 3243 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3244 timer = timer_table->timers[index]; 3245 if (!timer) 3246 continue; 3247 if (!timer->overflow) 3248 continue; 3249 3250 trigger_mask &= ~BIT(index); 3251 timer->overflow(timer->arg); 3252 } 3253 3254 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3255 timer = timer_table->timers[index]; 3256 if (!timer) 3257 continue; 3258 if (!timer->trigger) 3259 continue; 3260 timer->trigger(timer->arg); 3261 } 3262 } 3263 EXPORT_SYMBOL(ath_gen_timer_isr); 3264 3265 /********/ 3266 /* HTC */ 3267 /********/ 3268 3269 static struct { 3270 u32 version; 3271 const char * name; 3272 } ath_mac_bb_names[] = { 3273 /* Devices with external radios */ 3274 { AR_SREV_VERSION_5416_PCI, "5416" }, 3275 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3276 { AR_SREV_VERSION_9100, "9100" }, 3277 { AR_SREV_VERSION_9160, "9160" }, 3278 /* Single-chip solutions */ 3279 { AR_SREV_VERSION_9280, "9280" }, 3280 { AR_SREV_VERSION_9285, "9285" }, 3281 { AR_SREV_VERSION_9287, "9287" }, 3282 { AR_SREV_VERSION_9271, "9271" }, 3283 { AR_SREV_VERSION_9300, "9300" }, 3284 { AR_SREV_VERSION_9330, "9330" }, 3285 { AR_SREV_VERSION_9340, "9340" }, 3286 { AR_SREV_VERSION_9485, "9485" }, 3287 { AR_SREV_VERSION_9462, "9462" }, 3288 { AR_SREV_VERSION_9550, "9550" }, 3289 { AR_SREV_VERSION_9565, "9565" }, 3290 { AR_SREV_VERSION_9531, "9531" }, 3291 { AR_SREV_VERSION_9561, "9561" }, 3292 }; 3293 3294 /* For devices with external radios */ 3295 static struct { 3296 u16 version; 3297 const char * name; 3298 } ath_rf_names[] = { 3299 { 0, "5133" }, 3300 { AR_RAD5133_SREV_MAJOR, "5133" }, 3301 { AR_RAD5122_SREV_MAJOR, "5122" }, 3302 { AR_RAD2133_SREV_MAJOR, "2133" }, 3303 { AR_RAD2122_SREV_MAJOR, "2122" } 3304 }; 3305 3306 /* 3307 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3308 */ 3309 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3310 { 3311 int i; 3312 3313 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3314 if (ath_mac_bb_names[i].version == mac_bb_version) { 3315 return ath_mac_bb_names[i].name; 3316 } 3317 } 3318 3319 return "????"; 3320 } 3321 3322 /* 3323 * Return the RF name. "????" is returned if the RF is unknown. 3324 * Used for devices with external radios. 3325 */ 3326 static const char *ath9k_hw_rf_name(u16 rf_version) 3327 { 3328 int i; 3329 3330 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3331 if (ath_rf_names[i].version == rf_version) { 3332 return ath_rf_names[i].name; 3333 } 3334 } 3335 3336 return "????"; 3337 } 3338 3339 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3340 { 3341 int used; 3342 3343 /* chipsets >= AR9280 are single-chip */ 3344 if (AR_SREV_9280_20_OR_LATER(ah)) { 3345 used = scnprintf(hw_name, len, 3346 "Atheros AR%s Rev:%x", 3347 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3348 ah->hw_version.macRev); 3349 } 3350 else { 3351 used = scnprintf(hw_name, len, 3352 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3353 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3354 ah->hw_version.macRev, 3355 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3356 & AR_RADIO_SREV_MAJOR)), 3357 ah->hw_version.phyRev); 3358 } 3359 3360 hw_name[used] = '\0'; 3361 } 3362 EXPORT_SYMBOL(ath9k_hw_name); 3363