1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <asm/unaligned.h> 23 24 #include "hw.h" 25 #include "hw-ops.h" 26 #include "ar9003_mac.h" 27 #include "ar9003_mci.h" 28 #include "ar9003_phy.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 39 { 40 struct ath_common *common = ath9k_hw_common(ah); 41 struct ath9k_channel *chan = ah->curchan; 42 unsigned int clockrate; 43 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 46 clockrate = 117; 47 else if (!chan) /* should really check for CCK instead */ 48 clockrate = ATH9K_CLOCK_RATE_CCK; 49 else if (IS_CHAN_2GHZ(chan)) 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 53 else 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 55 56 if (chan) { 57 if (IS_CHAN_HT40(chan)) 58 clockrate *= 2; 59 if (IS_CHAN_HALF_RATE(chan)) 60 clockrate /= 2; 61 if (IS_CHAN_QUARTER_RATE(chan)) 62 clockrate /= 4; 63 } 64 65 common->clockrate = clockrate; 66 } 67 68 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 69 { 70 struct ath_common *common = ath9k_hw_common(ah); 71 72 return usecs * common->clockrate; 73 } 74 75 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 76 { 77 int i; 78 79 BUG_ON(timeout < AH_TIME_QUANTUM); 80 81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 82 if ((REG_READ(ah, reg) & mask) == val) 83 return true; 84 85 udelay(AH_TIME_QUANTUM); 86 } 87 88 ath_dbg(ath9k_hw_common(ah), ANY, 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 90 timeout, reg, REG_READ(ah, reg), mask, val); 91 92 return false; 93 } 94 EXPORT_SYMBOL(ath9k_hw_wait); 95 96 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 97 int hw_delay) 98 { 99 hw_delay /= 10; 100 101 if (IS_CHAN_HALF_RATE(chan)) 102 hw_delay *= 2; 103 else if (IS_CHAN_QUARTER_RATE(chan)) 104 hw_delay *= 4; 105 106 udelay(hw_delay + BASE_ACTIVATE_DELAY); 107 } 108 109 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 110 int column, unsigned int *writecnt) 111 { 112 int r; 113 114 ENABLE_REGWRITE_BUFFER(ah); 115 for (r = 0; r < array->ia_rows; r++) { 116 REG_WRITE(ah, INI_RA(array, r, 0), 117 INI_RA(array, r, column)); 118 DO_DELAY(*writecnt); 119 } 120 REGWRITE_BUFFER_FLUSH(ah); 121 } 122 123 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 124 { 125 u32 retval; 126 int i; 127 128 for (i = 0, retval = 0; i < n; i++) { 129 retval = (retval << 1) | (val & 1); 130 val >>= 1; 131 } 132 return retval; 133 } 134 135 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 136 u8 phy, int kbps, 137 u32 frameLen, u16 rateix, 138 bool shortPreamble) 139 { 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 141 142 if (kbps == 0) 143 return 0; 144 145 switch (phy) { 146 case WLAN_RC_PHY_CCK: 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 148 if (shortPreamble) 149 phyTime >>= 1; 150 numBits = frameLen << 3; 151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 152 break; 153 case WLAN_RC_PHY_OFDM: 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 156 numBits = OFDM_PLCP_BITS + (frameLen << 3); 157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 158 txTime = OFDM_SIFS_TIME_QUARTER 159 + OFDM_PREAMBLE_TIME_QUARTER 160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 161 } else if (ah->curchan && 162 IS_CHAN_HALF_RATE(ah->curchan)) { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME_HALF + 167 OFDM_PREAMBLE_TIME_HALF 168 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 169 } else { 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 171 numBits = OFDM_PLCP_BITS + (frameLen << 3); 172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 174 + (numSymbols * OFDM_SYMBOL_TIME); 175 } 176 break; 177 default: 178 ath_err(ath9k_hw_common(ah), 179 "Unknown phy %u (rate ix %u)\n", phy, rateix); 180 txTime = 0; 181 break; 182 } 183 184 return txTime; 185 } 186 EXPORT_SYMBOL(ath9k_hw_computetxtime); 187 188 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 189 struct ath9k_channel *chan, 190 struct chan_centers *centers) 191 { 192 int8_t extoff; 193 194 if (!IS_CHAN_HT40(chan)) { 195 centers->ctl_center = centers->ext_center = 196 centers->synth_center = chan->channel; 197 return; 198 } 199 200 if (IS_CHAN_HT40PLUS(chan)) { 201 centers->synth_center = 202 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 203 extoff = 1; 204 } else { 205 centers->synth_center = 206 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 207 extoff = -1; 208 } 209 210 centers->ctl_center = 211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 212 /* 25 MHz spacing is supported by hw but not on upper layers */ 213 centers->ext_center = 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 215 } 216 217 /******************/ 218 /* Chip Revisions */ 219 /******************/ 220 221 static void ath9k_hw_read_revisions(struct ath_hw *ah) 222 { 223 u32 val; 224 225 if (ah->get_mac_revision) 226 ah->hw_version.macRev = ah->get_mac_revision(); 227 228 switch (ah->hw_version.devid) { 229 case AR5416_AR9100_DEVID: 230 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 231 break; 232 case AR9300_DEVID_AR9330: 233 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 234 if (!ah->get_mac_revision) { 235 val = REG_READ(ah, AR_SREV); 236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 237 } 238 return; 239 case AR9300_DEVID_AR9340: 240 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 241 return; 242 case AR9300_DEVID_QCA955X: 243 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 244 return; 245 case AR9300_DEVID_AR953X: 246 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 247 return; 248 } 249 250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 251 252 if (val == 0xFF) { 253 val = REG_READ(ah, AR_SREV); 254 ah->hw_version.macVersion = 255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 257 258 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 259 ah->is_pciexpress = true; 260 else 261 ah->is_pciexpress = (val & 262 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 263 } else { 264 if (!AR_SREV_9100(ah)) 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 266 267 ah->hw_version.macRev = val & AR_SREV_REVISION; 268 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 270 ah->is_pciexpress = true; 271 } 272 } 273 274 /************************************/ 275 /* HW Attach, Detach, Init Routines */ 276 /************************************/ 277 278 static void ath9k_hw_disablepcie(struct ath_hw *ah) 279 { 280 if (!AR_SREV_5416(ah)) 281 return; 282 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 292 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 294 } 295 296 /* This should work for all families including legacy */ 297 static bool ath9k_hw_chip_test(struct ath_hw *ah) 298 { 299 struct ath_common *common = ath9k_hw_common(ah); 300 u32 regAddr[2] = { AR_STA_ID0 }; 301 u32 regHold[2]; 302 static const u32 patternData[4] = { 303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 304 }; 305 int i, j, loop_max; 306 307 if (!AR_SREV_9300_20_OR_LATER(ah)) { 308 loop_max = 2; 309 regAddr[1] = AR_PHY_BASE + (8 << 2); 310 } else 311 loop_max = 1; 312 313 for (i = 0; i < loop_max; i++) { 314 u32 addr = regAddr[i]; 315 u32 wrData, rdData; 316 317 regHold[i] = REG_READ(ah, addr); 318 for (j = 0; j < 0x100; j++) { 319 wrData = (j << 16) | j; 320 REG_WRITE(ah, addr, wrData); 321 rdData = REG_READ(ah, addr); 322 if (rdData != wrData) { 323 ath_err(common, 324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 325 addr, wrData, rdData); 326 return false; 327 } 328 } 329 for (j = 0; j < 4; j++) { 330 wrData = patternData[j]; 331 REG_WRITE(ah, addr, wrData); 332 rdData = REG_READ(ah, addr); 333 if (wrData != rdData) { 334 ath_err(common, 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 336 addr, wrData, rdData); 337 return false; 338 } 339 } 340 REG_WRITE(ah, regAddr[i], regHold[i]); 341 } 342 udelay(100); 343 344 return true; 345 } 346 347 static void ath9k_hw_init_config(struct ath_hw *ah) 348 { 349 struct ath_common *common = ath9k_hw_common(ah); 350 351 ah->config.dma_beacon_response_time = 1; 352 ah->config.sw_beacon_response_time = 6; 353 ah->config.cwm_ignore_extcca = 0; 354 ah->config.analog_shiftreg = 1; 355 356 ah->config.rx_intr_mitigation = true; 357 358 if (AR_SREV_9300_20_OR_LATER(ah)) { 359 ah->config.rimt_last = 500; 360 ah->config.rimt_first = 2000; 361 } else { 362 ah->config.rimt_last = 250; 363 ah->config.rimt_first = 700; 364 } 365 366 /* 367 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 368 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 369 * This means we use it for all AR5416 devices, and the few 370 * minor PCI AR9280 devices out there. 371 * 372 * Serialization is required because these devices do not handle 373 * well the case of two concurrent reads/writes due to the latency 374 * involved. During one read/write another read/write can be issued 375 * on another CPU while the previous read/write may still be working 376 * on our hardware, if we hit this case the hardware poops in a loop. 377 * We prevent this by serializing reads and writes. 378 * 379 * This issue is not present on PCI-Express devices or pre-AR5416 380 * devices (legacy, 802.11abg). 381 */ 382 if (num_possible_cpus() > 1) 383 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 384 385 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 386 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 387 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 388 !ah->is_pciexpress)) { 389 ah->config.serialize_regmode = SER_REG_MODE_ON; 390 } else { 391 ah->config.serialize_regmode = SER_REG_MODE_OFF; 392 } 393 } 394 395 ath_dbg(common, RESET, "serialize_regmode is %d\n", 396 ah->config.serialize_regmode); 397 398 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 399 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 400 else 401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 402 } 403 404 static void ath9k_hw_init_defaults(struct ath_hw *ah) 405 { 406 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 407 408 regulatory->country_code = CTRY_DEFAULT; 409 regulatory->power_limit = MAX_RATE_POWER; 410 411 ah->hw_version.magic = AR5416_MAGIC; 412 ah->hw_version.subvendorid = 0; 413 414 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 415 AR_STA_ID1_MCAST_KSRCH; 416 if (AR_SREV_9100(ah)) 417 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 418 419 ah->slottime = ATH9K_SLOT_TIME_9; 420 ah->globaltxtimeout = (u32) -1; 421 ah->power_mode = ATH9K_PM_UNDEFINED; 422 ah->htc_reset_init = true; 423 424 ah->ani_function = ATH9K_ANI_ALL; 425 if (!AR_SREV_9300_20_OR_LATER(ah)) 426 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 427 428 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 429 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 430 else 431 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 432 } 433 434 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 435 { 436 struct ath_common *common = ath9k_hw_common(ah); 437 u32 sum; 438 int i; 439 u16 eeval; 440 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 441 442 sum = 0; 443 for (i = 0; i < 3; i++) { 444 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 445 sum += eeval; 446 common->macaddr[2 * i] = eeval >> 8; 447 common->macaddr[2 * i + 1] = eeval & 0xff; 448 } 449 if (sum == 0 || sum == 0xffff * 3) 450 return -EADDRNOTAVAIL; 451 452 return 0; 453 } 454 455 static int ath9k_hw_post_init(struct ath_hw *ah) 456 { 457 struct ath_common *common = ath9k_hw_common(ah); 458 int ecode; 459 460 if (common->bus_ops->ath_bus_type != ATH_USB) { 461 if (!ath9k_hw_chip_test(ah)) 462 return -ENODEV; 463 } 464 465 if (!AR_SREV_9300_20_OR_LATER(ah)) { 466 ecode = ar9002_hw_rf_claim(ah); 467 if (ecode != 0) 468 return ecode; 469 } 470 471 ecode = ath9k_hw_eeprom_init(ah); 472 if (ecode != 0) 473 return ecode; 474 475 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 476 ah->eep_ops->get_eeprom_ver(ah), 477 ah->eep_ops->get_eeprom_rev(ah)); 478 479 ath9k_hw_ani_init(ah); 480 481 /* 482 * EEPROM needs to be initialized before we do this. 483 * This is required for regulatory compliance. 484 */ 485 if (AR_SREV_9300_20_OR_LATER(ah)) { 486 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 487 if ((regdmn & 0xF0) == CTL_FCC) { 488 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 489 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 490 } 491 } 492 493 return 0; 494 } 495 496 static int ath9k_hw_attach_ops(struct ath_hw *ah) 497 { 498 if (!AR_SREV_9300_20_OR_LATER(ah)) 499 return ar9002_hw_attach_ops(ah); 500 501 ar9003_hw_attach_ops(ah); 502 return 0; 503 } 504 505 /* Called for all hardware families */ 506 static int __ath9k_hw_init(struct ath_hw *ah) 507 { 508 struct ath_common *common = ath9k_hw_common(ah); 509 int r = 0; 510 511 ath9k_hw_read_revisions(ah); 512 513 switch (ah->hw_version.macVersion) { 514 case AR_SREV_VERSION_5416_PCI: 515 case AR_SREV_VERSION_5416_PCIE: 516 case AR_SREV_VERSION_9160: 517 case AR_SREV_VERSION_9100: 518 case AR_SREV_VERSION_9280: 519 case AR_SREV_VERSION_9285: 520 case AR_SREV_VERSION_9287: 521 case AR_SREV_VERSION_9271: 522 case AR_SREV_VERSION_9300: 523 case AR_SREV_VERSION_9330: 524 case AR_SREV_VERSION_9485: 525 case AR_SREV_VERSION_9340: 526 case AR_SREV_VERSION_9462: 527 case AR_SREV_VERSION_9550: 528 case AR_SREV_VERSION_9565: 529 case AR_SREV_VERSION_9531: 530 break; 531 default: 532 ath_err(common, 533 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 534 ah->hw_version.macVersion, ah->hw_version.macRev); 535 return -EOPNOTSUPP; 536 } 537 538 /* 539 * Read back AR_WA into a permanent copy and set bits 14 and 17. 540 * We need to do this to avoid RMW of this register. We cannot 541 * read the reg when chip is asleep. 542 */ 543 if (AR_SREV_9300_20_OR_LATER(ah)) { 544 ah->WARegVal = REG_READ(ah, AR_WA); 545 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 546 AR_WA_ASPM_TIMER_BASED_DISABLE); 547 } 548 549 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 550 ath_err(common, "Couldn't reset chip\n"); 551 return -EIO; 552 } 553 554 if (AR_SREV_9565(ah)) { 555 ah->WARegVal |= AR_WA_BIT22; 556 REG_WRITE(ah, AR_WA, ah->WARegVal); 557 } 558 559 ath9k_hw_init_defaults(ah); 560 ath9k_hw_init_config(ah); 561 562 r = ath9k_hw_attach_ops(ah); 563 if (r) 564 return r; 565 566 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 567 ath_err(common, "Couldn't wakeup chip\n"); 568 return -EIO; 569 } 570 571 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 572 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 573 ah->is_pciexpress = false; 574 575 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 576 ath9k_hw_init_cal_settings(ah); 577 578 if (!ah->is_pciexpress) 579 ath9k_hw_disablepcie(ah); 580 581 r = ath9k_hw_post_init(ah); 582 if (r) 583 return r; 584 585 ath9k_hw_init_mode_gain_regs(ah); 586 r = ath9k_hw_fill_cap_info(ah); 587 if (r) 588 return r; 589 590 r = ath9k_hw_init_macaddr(ah); 591 if (r) { 592 ath_err(common, "Failed to initialize MAC address\n"); 593 return r; 594 } 595 596 ath9k_hw_init_hang_checks(ah); 597 598 common->state = ATH_HW_INITIALIZED; 599 600 return 0; 601 } 602 603 int ath9k_hw_init(struct ath_hw *ah) 604 { 605 int ret; 606 struct ath_common *common = ath9k_hw_common(ah); 607 608 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 609 switch (ah->hw_version.devid) { 610 case AR5416_DEVID_PCI: 611 case AR5416_DEVID_PCIE: 612 case AR5416_AR9100_DEVID: 613 case AR9160_DEVID_PCI: 614 case AR9280_DEVID_PCI: 615 case AR9280_DEVID_PCIE: 616 case AR9285_DEVID_PCIE: 617 case AR9287_DEVID_PCI: 618 case AR9287_DEVID_PCIE: 619 case AR2427_DEVID_PCIE: 620 case AR9300_DEVID_PCIE: 621 case AR9300_DEVID_AR9485_PCIE: 622 case AR9300_DEVID_AR9330: 623 case AR9300_DEVID_AR9340: 624 case AR9300_DEVID_QCA955X: 625 case AR9300_DEVID_AR9580: 626 case AR9300_DEVID_AR9462: 627 case AR9485_DEVID_AR1111: 628 case AR9300_DEVID_AR9565: 629 case AR9300_DEVID_AR953X: 630 break; 631 default: 632 if (common->bus_ops->ath_bus_type == ATH_USB) 633 break; 634 ath_err(common, "Hardware device ID 0x%04x not supported\n", 635 ah->hw_version.devid); 636 return -EOPNOTSUPP; 637 } 638 639 ret = __ath9k_hw_init(ah); 640 if (ret) { 641 ath_err(common, 642 "Unable to initialize hardware; initialization status: %d\n", 643 ret); 644 return ret; 645 } 646 647 ath_dynack_init(ah); 648 649 return 0; 650 } 651 EXPORT_SYMBOL(ath9k_hw_init); 652 653 static void ath9k_hw_init_qos(struct ath_hw *ah) 654 { 655 ENABLE_REGWRITE_BUFFER(ah); 656 657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 659 660 REG_WRITE(ah, AR_QOS_NO_ACK, 661 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 662 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 663 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 664 665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 670 671 REGWRITE_BUFFER_FLUSH(ah); 672 } 673 674 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 675 { 676 struct ath_common *common = ath9k_hw_common(ah); 677 int i = 0; 678 679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 680 udelay(100); 681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 682 683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 684 685 udelay(100); 686 687 if (WARN_ON_ONCE(i >= 100)) { 688 ath_err(common, "PLL4 meaurement not done\n"); 689 break; 690 } 691 692 i++; 693 } 694 695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 696 } 697 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 698 699 static void ath9k_hw_init_pll(struct ath_hw *ah, 700 struct ath9k_channel *chan) 701 { 702 u32 pll; 703 704 pll = ath9k_hw_compute_pll_control(ah, chan); 705 706 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 707 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 709 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 711 AR_CH0_DPLL2_KD, 0x40); 712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 713 AR_CH0_DPLL2_KI, 0x4); 714 715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 716 AR_CH0_BB_DPLL1_REFDIV, 0x5); 717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 718 AR_CH0_BB_DPLL1_NINI, 0x58); 719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 720 AR_CH0_BB_DPLL1_NFRAC, 0x0); 721 722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 723 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 725 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 727 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 728 729 /* program BB PLL phase_shift to 0x6 */ 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 731 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 732 733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 734 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 735 udelay(1000); 736 } else if (AR_SREV_9330(ah)) { 737 u32 ddr_dpll2, pll_control2, kd; 738 739 if (ah->is_clk_25mhz) { 740 ddr_dpll2 = 0x18e82f01; 741 pll_control2 = 0xe04a3d; 742 kd = 0x1d; 743 } else { 744 ddr_dpll2 = 0x19e82f01; 745 pll_control2 = 0x886666; 746 kd = 0x3d; 747 } 748 749 /* program DDR PLL ki and kd value */ 750 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 751 752 /* program DDR PLL phase_shift */ 753 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 754 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 755 756 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 757 pll | AR_RTC_9300_PLL_BYPASS); 758 udelay(1000); 759 760 /* program refdiv, nint, frac to RTC register */ 761 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 762 763 /* program BB PLL kd and ki value */ 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 766 767 /* program BB PLL phase_shift */ 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 769 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 770 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 771 u32 regval, pll2_divint, pll2_divfrac, refdiv; 772 773 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 774 pll | AR_RTC_9300_SOC_PLL_BYPASS); 775 udelay(1000); 776 777 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 778 udelay(100); 779 780 if (ah->is_clk_25mhz) { 781 if (AR_SREV_9531(ah)) { 782 pll2_divint = 0x1c; 783 pll2_divfrac = 0xa3d2; 784 refdiv = 1; 785 } else { 786 pll2_divint = 0x54; 787 pll2_divfrac = 0x1eb85; 788 refdiv = 3; 789 } 790 } else { 791 if (AR_SREV_9340(ah)) { 792 pll2_divint = 88; 793 pll2_divfrac = 0; 794 refdiv = 5; 795 } else { 796 pll2_divint = 0x11; 797 pll2_divfrac = 798 AR_SREV_9531(ah) ? 0x26665 : 0x26666; 799 refdiv = 1; 800 } 801 } 802 803 regval = REG_READ(ah, AR_PHY_PLL_MODE); 804 if (AR_SREV_9531(ah)) 805 regval |= (0x1 << 22); 806 else 807 regval |= (0x1 << 16); 808 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 809 udelay(100); 810 811 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 812 (pll2_divint << 18) | pll2_divfrac); 813 udelay(100); 814 815 regval = REG_READ(ah, AR_PHY_PLL_MODE); 816 if (AR_SREV_9340(ah)) 817 regval = (regval & 0x80071fff) | 818 (0x1 << 30) | 819 (0x1 << 13) | 820 (0x4 << 26) | 821 (0x18 << 19); 822 else if (AR_SREV_9531(ah)) 823 regval = (regval & 0x01c00fff) | 824 (0x1 << 31) | 825 (0x2 << 29) | 826 (0xa << 25) | 827 (0x1 << 19) | 828 (0x6 << 12); 829 else 830 regval = (regval & 0x80071fff) | 831 (0x3 << 30) | 832 (0x1 << 13) | 833 (0x4 << 26) | 834 (0x60 << 19); 835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 836 837 if (AR_SREV_9531(ah)) 838 REG_WRITE(ah, AR_PHY_PLL_MODE, 839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 840 else 841 REG_WRITE(ah, AR_PHY_PLL_MODE, 842 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 843 844 udelay(1000); 845 } 846 847 if (AR_SREV_9565(ah)) 848 pll |= 0x40000; 849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 850 851 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 852 AR_SREV_9550(ah)) 853 udelay(1000); 854 855 /* Switch the core clock for ar9271 to 117Mhz */ 856 if (AR_SREV_9271(ah)) { 857 udelay(500); 858 REG_WRITE(ah, 0x50040, 0x304); 859 } 860 861 udelay(RTC_PLL_SETTLE_DELAY); 862 863 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 864 } 865 866 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 867 enum nl80211_iftype opmode) 868 { 869 u32 sync_default = AR_INTR_SYNC_DEFAULT; 870 u32 imr_reg = AR_IMR_TXERR | 871 AR_IMR_TXURN | 872 AR_IMR_RXERR | 873 AR_IMR_RXORN | 874 AR_IMR_BCNMISC; 875 876 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 877 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 878 879 if (AR_SREV_9300_20_OR_LATER(ah)) { 880 imr_reg |= AR_IMR_RXOK_HP; 881 if (ah->config.rx_intr_mitigation) 882 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 883 else 884 imr_reg |= AR_IMR_RXOK_LP; 885 886 } else { 887 if (ah->config.rx_intr_mitigation) 888 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 889 else 890 imr_reg |= AR_IMR_RXOK; 891 } 892 893 if (ah->config.tx_intr_mitigation) 894 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 895 else 896 imr_reg |= AR_IMR_TXOK; 897 898 ENABLE_REGWRITE_BUFFER(ah); 899 900 REG_WRITE(ah, AR_IMR, imr_reg); 901 ah->imrs2_reg |= AR_IMR_S2_GTT; 902 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 903 904 if (!AR_SREV_9100(ah)) { 905 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 906 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 907 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 908 } 909 910 REGWRITE_BUFFER_FLUSH(ah); 911 912 if (AR_SREV_9300_20_OR_LATER(ah)) { 913 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 914 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 915 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 916 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 917 } 918 } 919 920 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 921 { 922 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 923 val = min(val, (u32) 0xFFFF); 924 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 925 } 926 927 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 928 { 929 u32 val = ath9k_hw_mac_to_clks(ah, us); 930 val = min(val, (u32) 0xFFFF); 931 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 932 } 933 934 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 935 { 936 u32 val = ath9k_hw_mac_to_clks(ah, us); 937 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 938 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 939 } 940 941 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 942 { 943 u32 val = ath9k_hw_mac_to_clks(ah, us); 944 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 945 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 946 } 947 948 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 949 { 950 if (tu > 0xFFFF) { 951 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 952 tu); 953 ah->globaltxtimeout = (u32) -1; 954 return false; 955 } else { 956 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 957 ah->globaltxtimeout = tu; 958 return true; 959 } 960 } 961 962 void ath9k_hw_init_global_settings(struct ath_hw *ah) 963 { 964 struct ath_common *common = ath9k_hw_common(ah); 965 const struct ath9k_channel *chan = ah->curchan; 966 int acktimeout, ctstimeout, ack_offset = 0; 967 int slottime; 968 int sifstime; 969 int rx_lat = 0, tx_lat = 0, eifs = 0; 970 u32 reg; 971 972 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 973 ah->misc_mode); 974 975 if (!chan) 976 return; 977 978 if (ah->misc_mode != 0) 979 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 980 981 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 982 rx_lat = 41; 983 else 984 rx_lat = 37; 985 tx_lat = 54; 986 987 if (IS_CHAN_5GHZ(chan)) 988 sifstime = 16; 989 else 990 sifstime = 10; 991 992 if (IS_CHAN_HALF_RATE(chan)) { 993 eifs = 175; 994 rx_lat *= 2; 995 tx_lat *= 2; 996 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 997 tx_lat += 11; 998 999 sifstime = 32; 1000 ack_offset = 16; 1001 slottime = 13; 1002 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1003 eifs = 340; 1004 rx_lat = (rx_lat * 4) - 1; 1005 tx_lat *= 4; 1006 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1007 tx_lat += 22; 1008 1009 sifstime = 64; 1010 ack_offset = 32; 1011 slottime = 21; 1012 } else { 1013 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1014 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1015 reg = AR_USEC_ASYNC_FIFO; 1016 } else { 1017 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1018 common->clockrate; 1019 reg = REG_READ(ah, AR_USEC); 1020 } 1021 rx_lat = MS(reg, AR_USEC_RX_LAT); 1022 tx_lat = MS(reg, AR_USEC_TX_LAT); 1023 1024 slottime = ah->slottime; 1025 } 1026 1027 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1028 slottime += 3 * ah->coverage_class; 1029 acktimeout = slottime + sifstime + ack_offset; 1030 ctstimeout = acktimeout; 1031 1032 /* 1033 * Workaround for early ACK timeouts, add an offset to match the 1034 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1035 * This was initially only meant to work around an issue with delayed 1036 * BA frames in some implementations, but it has been found to fix ACK 1037 * timeout issues in other cases as well. 1038 */ 1039 if (IS_CHAN_2GHZ(chan) && 1040 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1041 acktimeout += 64 - sifstime - ah->slottime; 1042 ctstimeout += 48 - sifstime - ah->slottime; 1043 } 1044 1045 if (ah->dynack.enabled) { 1046 acktimeout = ah->dynack.ackto; 1047 ctstimeout = acktimeout; 1048 slottime = (acktimeout - 3) / 2; 1049 } else { 1050 ah->dynack.ackto = acktimeout; 1051 } 1052 1053 ath9k_hw_set_sifs_time(ah, sifstime); 1054 ath9k_hw_setslottime(ah, slottime); 1055 ath9k_hw_set_ack_timeout(ah, acktimeout); 1056 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1057 if (ah->globaltxtimeout != (u32) -1) 1058 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1059 1060 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1061 REG_RMW(ah, AR_USEC, 1062 (common->clockrate - 1) | 1063 SM(rx_lat, AR_USEC_RX_LAT) | 1064 SM(tx_lat, AR_USEC_TX_LAT), 1065 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1066 1067 } 1068 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1069 1070 void ath9k_hw_deinit(struct ath_hw *ah) 1071 { 1072 struct ath_common *common = ath9k_hw_common(ah); 1073 1074 if (common->state < ATH_HW_INITIALIZED) 1075 return; 1076 1077 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1078 } 1079 EXPORT_SYMBOL(ath9k_hw_deinit); 1080 1081 /*******/ 1082 /* INI */ 1083 /*******/ 1084 1085 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1086 { 1087 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1088 1089 if (IS_CHAN_2GHZ(chan)) 1090 ctl |= CTL_11G; 1091 else 1092 ctl |= CTL_11A; 1093 1094 return ctl; 1095 } 1096 1097 /****************************************/ 1098 /* Reset and Channel Switching Routines */ 1099 /****************************************/ 1100 1101 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1102 { 1103 struct ath_common *common = ath9k_hw_common(ah); 1104 int txbuf_size; 1105 1106 ENABLE_REGWRITE_BUFFER(ah); 1107 1108 /* 1109 * set AHB_MODE not to do cacheline prefetches 1110 */ 1111 if (!AR_SREV_9300_20_OR_LATER(ah)) 1112 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1113 1114 /* 1115 * let mac dma reads be in 128 byte chunks 1116 */ 1117 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1118 1119 REGWRITE_BUFFER_FLUSH(ah); 1120 1121 /* 1122 * Restore TX Trigger Level to its pre-reset value. 1123 * The initial value depends on whether aggregation is enabled, and is 1124 * adjusted whenever underruns are detected. 1125 */ 1126 if (!AR_SREV_9300_20_OR_LATER(ah)) 1127 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1128 1129 ENABLE_REGWRITE_BUFFER(ah); 1130 1131 /* 1132 * let mac dma writes be in 128 byte chunks 1133 */ 1134 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1135 1136 /* 1137 * Setup receive FIFO threshold to hold off TX activities 1138 */ 1139 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1140 1141 if (AR_SREV_9300_20_OR_LATER(ah)) { 1142 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1144 1145 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1146 ah->caps.rx_status_len); 1147 } 1148 1149 /* 1150 * reduce the number of usable entries in PCU TXBUF to avoid 1151 * wrap around issues. 1152 */ 1153 if (AR_SREV_9285(ah)) { 1154 /* For AR9285 the number of Fifos are reduced to half. 1155 * So set the usable tx buf size also to half to 1156 * avoid data/delimiter underruns 1157 */ 1158 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1159 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1160 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1161 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1162 } else { 1163 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1164 } 1165 1166 if (!AR_SREV_9271(ah)) 1167 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1168 1169 REGWRITE_BUFFER_FLUSH(ah); 1170 1171 if (AR_SREV_9300_20_OR_LATER(ah)) 1172 ath9k_hw_reset_txstatus_ring(ah); 1173 } 1174 1175 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1176 { 1177 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1178 u32 set = AR_STA_ID1_KSRCH_MODE; 1179 1180 switch (opmode) { 1181 case NL80211_IFTYPE_ADHOC: 1182 if (!AR_SREV_9340_13(ah)) { 1183 set |= AR_STA_ID1_ADHOC; 1184 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1185 break; 1186 } 1187 /* fall through */ 1188 case NL80211_IFTYPE_MESH_POINT: 1189 case NL80211_IFTYPE_AP: 1190 set |= AR_STA_ID1_STA_AP; 1191 /* fall through */ 1192 case NL80211_IFTYPE_STATION: 1193 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1194 break; 1195 default: 1196 if (!ah->is_monitoring) 1197 set = 0; 1198 break; 1199 } 1200 REG_RMW(ah, AR_STA_ID1, set, mask); 1201 } 1202 1203 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1204 u32 *coef_mantissa, u32 *coef_exponent) 1205 { 1206 u32 coef_exp, coef_man; 1207 1208 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1209 if ((coef_scaled >> coef_exp) & 0x1) 1210 break; 1211 1212 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1213 1214 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1215 1216 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1217 *coef_exponent = coef_exp - 16; 1218 } 1219 1220 /* AR9330 WAR: 1221 * call external reset function to reset WMAC if: 1222 * - doing a cold reset 1223 * - we have pending frames in the TX queues. 1224 */ 1225 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1226 { 1227 int i, npend = 0; 1228 1229 for (i = 0; i < AR_NUM_QCU; i++) { 1230 npend = ath9k_hw_numtxpending(ah, i); 1231 if (npend) 1232 break; 1233 } 1234 1235 if (ah->external_reset && 1236 (npend || type == ATH9K_RESET_COLD)) { 1237 int reset_err = 0; 1238 1239 ath_dbg(ath9k_hw_common(ah), RESET, 1240 "reset MAC via external reset\n"); 1241 1242 reset_err = ah->external_reset(); 1243 if (reset_err) { 1244 ath_err(ath9k_hw_common(ah), 1245 "External reset failed, err=%d\n", 1246 reset_err); 1247 return false; 1248 } 1249 1250 REG_WRITE(ah, AR_RTC_RESET, 1); 1251 } 1252 1253 return true; 1254 } 1255 1256 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1257 { 1258 u32 rst_flags; 1259 u32 tmpReg; 1260 1261 if (AR_SREV_9100(ah)) { 1262 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1263 AR_RTC_DERIVED_CLK_PERIOD, 1); 1264 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1265 } 1266 1267 ENABLE_REGWRITE_BUFFER(ah); 1268 1269 if (AR_SREV_9300_20_OR_LATER(ah)) { 1270 REG_WRITE(ah, AR_WA, ah->WARegVal); 1271 udelay(10); 1272 } 1273 1274 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1275 AR_RTC_FORCE_WAKE_ON_INT); 1276 1277 if (AR_SREV_9100(ah)) { 1278 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1279 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1280 } else { 1281 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1282 if (AR_SREV_9340(ah)) 1283 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1284 else 1285 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1286 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1287 1288 if (tmpReg) { 1289 u32 val; 1290 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1291 1292 val = AR_RC_HOSTIF; 1293 if (!AR_SREV_9300_20_OR_LATER(ah)) 1294 val |= AR_RC_AHB; 1295 REG_WRITE(ah, AR_RC, val); 1296 1297 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1298 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1299 1300 rst_flags = AR_RTC_RC_MAC_WARM; 1301 if (type == ATH9K_RESET_COLD) 1302 rst_flags |= AR_RTC_RC_MAC_COLD; 1303 } 1304 1305 if (AR_SREV_9330(ah)) { 1306 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1307 return false; 1308 } 1309 1310 if (ath9k_hw_mci_is_enabled(ah)) 1311 ar9003_mci_check_gpm_offset(ah); 1312 1313 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1314 1315 REGWRITE_BUFFER_FLUSH(ah); 1316 1317 if (AR_SREV_9300_20_OR_LATER(ah)) 1318 udelay(50); 1319 else if (AR_SREV_9100(ah)) 1320 mdelay(10); 1321 else 1322 udelay(100); 1323 1324 REG_WRITE(ah, AR_RTC_RC, 0); 1325 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1326 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1327 return false; 1328 } 1329 1330 if (!AR_SREV_9100(ah)) 1331 REG_WRITE(ah, AR_RC, 0); 1332 1333 if (AR_SREV_9100(ah)) 1334 udelay(50); 1335 1336 return true; 1337 } 1338 1339 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1340 { 1341 ENABLE_REGWRITE_BUFFER(ah); 1342 1343 if (AR_SREV_9300_20_OR_LATER(ah)) { 1344 REG_WRITE(ah, AR_WA, ah->WARegVal); 1345 udelay(10); 1346 } 1347 1348 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1349 AR_RTC_FORCE_WAKE_ON_INT); 1350 1351 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1352 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1353 1354 REG_WRITE(ah, AR_RTC_RESET, 0); 1355 1356 REGWRITE_BUFFER_FLUSH(ah); 1357 1358 udelay(2); 1359 1360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1361 REG_WRITE(ah, AR_RC, 0); 1362 1363 REG_WRITE(ah, AR_RTC_RESET, 1); 1364 1365 if (!ath9k_hw_wait(ah, 1366 AR_RTC_STATUS, 1367 AR_RTC_STATUS_M, 1368 AR_RTC_STATUS_ON, 1369 AH_WAIT_TIMEOUT)) { 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1371 return false; 1372 } 1373 1374 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1375 } 1376 1377 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1378 { 1379 bool ret = false; 1380 1381 if (AR_SREV_9300_20_OR_LATER(ah)) { 1382 REG_WRITE(ah, AR_WA, ah->WARegVal); 1383 udelay(10); 1384 } 1385 1386 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1387 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1388 1389 if (!ah->reset_power_on) 1390 type = ATH9K_RESET_POWER_ON; 1391 1392 switch (type) { 1393 case ATH9K_RESET_POWER_ON: 1394 ret = ath9k_hw_set_reset_power_on(ah); 1395 if (ret) 1396 ah->reset_power_on = true; 1397 break; 1398 case ATH9K_RESET_WARM: 1399 case ATH9K_RESET_COLD: 1400 ret = ath9k_hw_set_reset(ah, type); 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 return ret; 1407 } 1408 1409 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1410 struct ath9k_channel *chan) 1411 { 1412 int reset_type = ATH9K_RESET_WARM; 1413 1414 if (AR_SREV_9280(ah)) { 1415 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1416 reset_type = ATH9K_RESET_POWER_ON; 1417 else 1418 reset_type = ATH9K_RESET_COLD; 1419 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1420 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1421 reset_type = ATH9K_RESET_COLD; 1422 1423 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1424 return false; 1425 1426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1427 return false; 1428 1429 ah->chip_fullsleep = false; 1430 1431 if (AR_SREV_9330(ah)) 1432 ar9003_hw_internal_regulator_apply(ah); 1433 ath9k_hw_init_pll(ah, chan); 1434 1435 return true; 1436 } 1437 1438 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1439 struct ath9k_channel *chan) 1440 { 1441 struct ath_common *common = ath9k_hw_common(ah); 1442 struct ath9k_hw_capabilities *pCap = &ah->caps; 1443 bool band_switch = false, mode_diff = false; 1444 u8 ini_reloaded = 0; 1445 u32 qnum; 1446 int r; 1447 1448 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1449 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1450 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1451 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1452 } 1453 1454 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1455 if (ath9k_hw_numtxpending(ah, qnum)) { 1456 ath_dbg(common, QUEUE, 1457 "Transmit frames pending on queue %d\n", qnum); 1458 return false; 1459 } 1460 } 1461 1462 if (!ath9k_hw_rfbus_req(ah)) { 1463 ath_err(common, "Could not kill baseband RX\n"); 1464 return false; 1465 } 1466 1467 if (band_switch || mode_diff) { 1468 ath9k_hw_mark_phy_inactive(ah); 1469 udelay(5); 1470 1471 if (band_switch) 1472 ath9k_hw_init_pll(ah, chan); 1473 1474 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1475 ath_err(common, "Failed to do fast channel change\n"); 1476 return false; 1477 } 1478 } 1479 1480 ath9k_hw_set_channel_regs(ah, chan); 1481 1482 r = ath9k_hw_rf_set_freq(ah, chan); 1483 if (r) { 1484 ath_err(common, "Failed to set channel\n"); 1485 return false; 1486 } 1487 ath9k_hw_set_clockrate(ah); 1488 ath9k_hw_apply_txpower(ah, chan, false); 1489 1490 ath9k_hw_set_delta_slope(ah, chan); 1491 ath9k_hw_spur_mitigate_freq(ah, chan); 1492 1493 if (band_switch || ini_reloaded) 1494 ah->eep_ops->set_board_values(ah, chan); 1495 1496 ath9k_hw_init_bb(ah, chan); 1497 ath9k_hw_rfbus_done(ah); 1498 1499 if (band_switch || ini_reloaded) { 1500 ah->ah_flags |= AH_FASTCC; 1501 ath9k_hw_init_cal(ah, chan); 1502 ah->ah_flags &= ~AH_FASTCC; 1503 } 1504 1505 return true; 1506 } 1507 1508 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1509 { 1510 u32 gpio_mask = ah->gpio_mask; 1511 int i; 1512 1513 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1514 if (!(gpio_mask & 1)) 1515 continue; 1516 1517 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1518 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1519 } 1520 } 1521 1522 void ath9k_hw_check_nav(struct ath_hw *ah) 1523 { 1524 struct ath_common *common = ath9k_hw_common(ah); 1525 u32 val; 1526 1527 val = REG_READ(ah, AR_NAV); 1528 if (val != 0xdeadbeef && val > 0x7fff) { 1529 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1530 REG_WRITE(ah, AR_NAV, 0); 1531 } 1532 } 1533 EXPORT_SYMBOL(ath9k_hw_check_nav); 1534 1535 bool ath9k_hw_check_alive(struct ath_hw *ah) 1536 { 1537 int count = 50; 1538 u32 reg, last_val; 1539 1540 if (AR_SREV_9300(ah)) 1541 return !ath9k_hw_detect_mac_hang(ah); 1542 1543 if (AR_SREV_9285_12_OR_LATER(ah)) 1544 return true; 1545 1546 last_val = REG_READ(ah, AR_OBS_BUS_1); 1547 do { 1548 reg = REG_READ(ah, AR_OBS_BUS_1); 1549 if (reg != last_val) 1550 return true; 1551 1552 udelay(1); 1553 last_val = reg; 1554 if ((reg & 0x7E7FFFEF) == 0x00702400) 1555 continue; 1556 1557 switch (reg & 0x7E000B00) { 1558 case 0x1E000000: 1559 case 0x52000B00: 1560 case 0x18000B00: 1561 continue; 1562 default: 1563 return true; 1564 } 1565 } while (count-- > 0); 1566 1567 return false; 1568 } 1569 EXPORT_SYMBOL(ath9k_hw_check_alive); 1570 1571 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1572 { 1573 /* Setup MFP options for CCMP */ 1574 if (AR_SREV_9280_20_OR_LATER(ah)) { 1575 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1576 * frames when constructing CCMP AAD. */ 1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1578 0xc7ff); 1579 ah->sw_mgmt_crypto = false; 1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1581 /* Disable hardware crypto for management frames */ 1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1583 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1585 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1586 ah->sw_mgmt_crypto = true; 1587 } else { 1588 ah->sw_mgmt_crypto = true; 1589 } 1590 } 1591 1592 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1593 u32 macStaId1, u32 saveDefAntenna) 1594 { 1595 struct ath_common *common = ath9k_hw_common(ah); 1596 1597 ENABLE_REGWRITE_BUFFER(ah); 1598 1599 REG_RMW(ah, AR_STA_ID1, macStaId1 1600 | AR_STA_ID1_RTS_USE_DEF 1601 | ah->sta_id1_defaults, 1602 ~AR_STA_ID1_SADH_MASK); 1603 ath_hw_setbssidmask(common); 1604 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1605 ath9k_hw_write_associd(ah); 1606 REG_WRITE(ah, AR_ISR, ~0); 1607 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1608 1609 REGWRITE_BUFFER_FLUSH(ah); 1610 1611 ath9k_hw_set_operating_mode(ah, ah->opmode); 1612 } 1613 1614 static void ath9k_hw_init_queues(struct ath_hw *ah) 1615 { 1616 int i; 1617 1618 ENABLE_REGWRITE_BUFFER(ah); 1619 1620 for (i = 0; i < AR_NUM_DCU; i++) 1621 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1622 1623 REGWRITE_BUFFER_FLUSH(ah); 1624 1625 ah->intr_txqs = 0; 1626 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1627 ath9k_hw_resettxqueue(ah, i); 1628 } 1629 1630 /* 1631 * For big endian systems turn on swapping for descriptors 1632 */ 1633 static void ath9k_hw_init_desc(struct ath_hw *ah) 1634 { 1635 struct ath_common *common = ath9k_hw_common(ah); 1636 1637 if (AR_SREV_9100(ah)) { 1638 u32 mask; 1639 mask = REG_READ(ah, AR_CFG); 1640 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1641 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1642 mask); 1643 } else { 1644 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1645 REG_WRITE(ah, AR_CFG, mask); 1646 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1647 REG_READ(ah, AR_CFG)); 1648 } 1649 } else { 1650 if (common->bus_ops->ath_bus_type == ATH_USB) { 1651 /* Configure AR9271 target WLAN */ 1652 if (AR_SREV_9271(ah)) 1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1654 else 1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1656 } 1657 #ifdef __BIG_ENDIAN 1658 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1659 AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1660 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1661 else 1662 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1663 #endif 1664 } 1665 } 1666 1667 /* 1668 * Fast channel change: 1669 * (Change synthesizer based on channel freq without resetting chip) 1670 */ 1671 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1672 { 1673 struct ath_common *common = ath9k_hw_common(ah); 1674 struct ath9k_hw_capabilities *pCap = &ah->caps; 1675 int ret; 1676 1677 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1678 goto fail; 1679 1680 if (ah->chip_fullsleep) 1681 goto fail; 1682 1683 if (!ah->curchan) 1684 goto fail; 1685 1686 if (chan->channel == ah->curchan->channel) 1687 goto fail; 1688 1689 if ((ah->curchan->channelFlags | chan->channelFlags) & 1690 (CHANNEL_HALF | CHANNEL_QUARTER)) 1691 goto fail; 1692 1693 /* 1694 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1695 */ 1696 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1697 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1698 goto fail; 1699 1700 if (!ath9k_hw_check_alive(ah)) 1701 goto fail; 1702 1703 /* 1704 * For AR9462, make sure that calibration data for 1705 * re-using are present. 1706 */ 1707 if (AR_SREV_9462(ah) && (ah->caldata && 1708 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1709 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1710 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1711 goto fail; 1712 1713 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1714 ah->curchan->channel, chan->channel); 1715 1716 ret = ath9k_hw_channel_change(ah, chan); 1717 if (!ret) 1718 goto fail; 1719 1720 if (ath9k_hw_mci_is_enabled(ah)) 1721 ar9003_mci_2g5g_switch(ah, false); 1722 1723 ath9k_hw_loadnf(ah, ah->curchan); 1724 ath9k_hw_start_nfcal(ah, true); 1725 1726 if (AR_SREV_9271(ah)) 1727 ar9002_hw_load_ani_reg(ah, chan); 1728 1729 return 0; 1730 fail: 1731 return -EINVAL; 1732 } 1733 1734 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1735 { 1736 struct timespec ts; 1737 s64 usec; 1738 1739 if (!cur) { 1740 getrawmonotonic(&ts); 1741 cur = &ts; 1742 } 1743 1744 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1745 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1746 1747 return (u32) usec; 1748 } 1749 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1750 1751 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1752 struct ath9k_hw_cal_data *caldata, bool fastcc) 1753 { 1754 struct ath_common *common = ath9k_hw_common(ah); 1755 u32 saveLedState; 1756 u32 saveDefAntenna; 1757 u32 macStaId1; 1758 u64 tsf = 0; 1759 s64 usec = 0; 1760 int r; 1761 bool start_mci_reset = false; 1762 bool save_fullsleep = ah->chip_fullsleep; 1763 1764 if (ath9k_hw_mci_is_enabled(ah)) { 1765 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1766 if (start_mci_reset) 1767 return 0; 1768 } 1769 1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1771 return -EIO; 1772 1773 if (ah->curchan && !ah->chip_fullsleep) 1774 ath9k_hw_getnf(ah, ah->curchan); 1775 1776 ah->caldata = caldata; 1777 if (caldata && (chan->channel != caldata->channel || 1778 chan->channelFlags != caldata->channelFlags)) { 1779 /* Operating channel changed, reset channel calibration data */ 1780 memset(caldata, 0, sizeof(*caldata)); 1781 ath9k_init_nfcal_hist_buffer(ah, chan); 1782 } else if (caldata) { 1783 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1784 } 1785 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1786 1787 if (fastcc) { 1788 r = ath9k_hw_do_fastcc(ah, chan); 1789 if (!r) 1790 return r; 1791 } 1792 1793 if (ath9k_hw_mci_is_enabled(ah)) 1794 ar9003_mci_stop_bt(ah, save_fullsleep); 1795 1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1797 if (saveDefAntenna == 0) 1798 saveDefAntenna = 1; 1799 1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1801 1802 /* Save TSF before chip reset, a cold reset clears it */ 1803 tsf = ath9k_hw_gettsf64(ah); 1804 usec = ktime_to_us(ktime_get_raw()); 1805 1806 saveLedState = REG_READ(ah, AR_CFG_LED) & 1807 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1808 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1809 1810 ath9k_hw_mark_phy_inactive(ah); 1811 1812 ah->paprd_table_write_done = false; 1813 1814 /* Only required on the first reset */ 1815 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1816 REG_WRITE(ah, 1817 AR9271_RESET_POWER_DOWN_CONTROL, 1818 AR9271_RADIO_RF_RST); 1819 udelay(50); 1820 } 1821 1822 if (!ath9k_hw_chip_reset(ah, chan)) { 1823 ath_err(common, "Chip reset failed\n"); 1824 return -EINVAL; 1825 } 1826 1827 /* Only required on the first reset */ 1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1829 ah->htc_reset_init = false; 1830 REG_WRITE(ah, 1831 AR9271_RESET_POWER_DOWN_CONTROL, 1832 AR9271_GATE_MAC_CTL); 1833 udelay(50); 1834 } 1835 1836 /* Restore TSF */ 1837 usec = ktime_to_us(ktime_get_raw()) - usec; 1838 ath9k_hw_settsf64(ah, tsf + usec); 1839 1840 if (AR_SREV_9280_20_OR_LATER(ah)) 1841 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1842 1843 if (!AR_SREV_9300_20_OR_LATER(ah)) 1844 ar9002_hw_enable_async_fifo(ah); 1845 1846 r = ath9k_hw_process_ini(ah, chan); 1847 if (r) 1848 return r; 1849 1850 ath9k_hw_set_rfmode(ah, chan); 1851 1852 if (ath9k_hw_mci_is_enabled(ah)) 1853 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1854 1855 /* 1856 * Some AR91xx SoC devices frequently fail to accept TSF writes 1857 * right after the chip reset. When that happens, write a new 1858 * value after the initvals have been applied, with an offset 1859 * based on measured time difference 1860 */ 1861 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1862 tsf += 1500; 1863 ath9k_hw_settsf64(ah, tsf); 1864 } 1865 1866 ath9k_hw_init_mfp(ah); 1867 1868 ath9k_hw_set_delta_slope(ah, chan); 1869 ath9k_hw_spur_mitigate_freq(ah, chan); 1870 ah->eep_ops->set_board_values(ah, chan); 1871 1872 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1873 1874 r = ath9k_hw_rf_set_freq(ah, chan); 1875 if (r) 1876 return r; 1877 1878 ath9k_hw_set_clockrate(ah); 1879 1880 ath9k_hw_init_queues(ah); 1881 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1882 ath9k_hw_ani_cache_ini_regs(ah); 1883 ath9k_hw_init_qos(ah); 1884 1885 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1886 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1887 1888 ath9k_hw_init_global_settings(ah); 1889 1890 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1891 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1892 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1893 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1894 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1895 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1896 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1897 } 1898 1899 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1900 1901 ath9k_hw_set_dma(ah); 1902 1903 if (!ath9k_hw_mci_is_enabled(ah)) 1904 REG_WRITE(ah, AR_OBS, 8); 1905 1906 if (ah->config.rx_intr_mitigation) { 1907 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1908 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1909 } 1910 1911 if (ah->config.tx_intr_mitigation) { 1912 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1913 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1914 } 1915 1916 ath9k_hw_init_bb(ah, chan); 1917 1918 if (caldata) { 1919 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1920 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1921 } 1922 if (!ath9k_hw_init_cal(ah, chan)) 1923 return -EIO; 1924 1925 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1926 return -EIO; 1927 1928 ENABLE_REGWRITE_BUFFER(ah); 1929 1930 ath9k_hw_restore_chainmask(ah); 1931 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1932 1933 REGWRITE_BUFFER_FLUSH(ah); 1934 1935 ath9k_hw_init_desc(ah); 1936 1937 if (ath9k_hw_btcoex_is_enabled(ah)) 1938 ath9k_hw_btcoex_enable(ah); 1939 1940 if (ath9k_hw_mci_is_enabled(ah)) 1941 ar9003_mci_check_bt(ah); 1942 1943 ath9k_hw_loadnf(ah, chan); 1944 ath9k_hw_start_nfcal(ah, true); 1945 1946 if (AR_SREV_9300_20_OR_LATER(ah)) 1947 ar9003_hw_bb_watchdog_config(ah); 1948 1949 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1950 ar9003_hw_disable_phy_restart(ah); 1951 1952 ath9k_hw_apply_gpio_override(ah); 1953 1954 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1955 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1956 1957 if (ah->hw->conf.radar_enabled) { 1958 /* set HW specific DFS configuration */ 1959 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 1960 ath9k_hw_set_radar_params(ah); 1961 } 1962 1963 return 0; 1964 } 1965 EXPORT_SYMBOL(ath9k_hw_reset); 1966 1967 /******************************/ 1968 /* Power Management (Chipset) */ 1969 /******************************/ 1970 1971 /* 1972 * Notify Power Mgt is disabled in self-generated frames. 1973 * If requested, force chip to sleep. 1974 */ 1975 static void ath9k_set_power_sleep(struct ath_hw *ah) 1976 { 1977 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1978 1979 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1980 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 1981 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 1982 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 1983 /* xxx Required for WLAN only case ? */ 1984 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1985 udelay(100); 1986 } 1987 1988 /* 1989 * Clear the RTC force wake bit to allow the 1990 * mac to go to sleep. 1991 */ 1992 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1993 1994 if (ath9k_hw_mci_is_enabled(ah)) 1995 udelay(100); 1996 1997 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1998 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1999 2000 /* Shutdown chip. Active low */ 2001 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2002 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2003 udelay(2); 2004 } 2005 2006 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2007 if (AR_SREV_9300_20_OR_LATER(ah)) 2008 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2009 } 2010 2011 /* 2012 * Notify Power Management is enabled in self-generating 2013 * frames. If request, set power mode of chip to 2014 * auto/normal. Duration in units of 128us (1/8 TU). 2015 */ 2016 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2017 { 2018 struct ath9k_hw_capabilities *pCap = &ah->caps; 2019 2020 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2021 2022 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2023 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2024 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2025 AR_RTC_FORCE_WAKE_ON_INT); 2026 } else { 2027 2028 /* When chip goes into network sleep, it could be waken 2029 * up by MCI_INT interrupt caused by BT's HW messages 2030 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2031 * rate (~100us). This will cause chip to leave and 2032 * re-enter network sleep mode frequently, which in 2033 * consequence will have WLAN MCI HW to generate lots of 2034 * SYS_WAKING and SYS_SLEEPING messages which will make 2035 * BT CPU to busy to process. 2036 */ 2037 if (ath9k_hw_mci_is_enabled(ah)) 2038 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2039 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2040 /* 2041 * Clear the RTC force wake bit to allow the 2042 * mac to go to sleep. 2043 */ 2044 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2045 2046 if (ath9k_hw_mci_is_enabled(ah)) 2047 udelay(30); 2048 } 2049 2050 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2051 if (AR_SREV_9300_20_OR_LATER(ah)) 2052 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2053 } 2054 2055 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2056 { 2057 u32 val; 2058 int i; 2059 2060 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2061 if (AR_SREV_9300_20_OR_LATER(ah)) { 2062 REG_WRITE(ah, AR_WA, ah->WARegVal); 2063 udelay(10); 2064 } 2065 2066 if ((REG_READ(ah, AR_RTC_STATUS) & 2067 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2068 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2069 return false; 2070 } 2071 if (!AR_SREV_9300_20_OR_LATER(ah)) 2072 ath9k_hw_init_pll(ah, NULL); 2073 } 2074 if (AR_SREV_9100(ah)) 2075 REG_SET_BIT(ah, AR_RTC_RESET, 2076 AR_RTC_RESET_EN); 2077 2078 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2079 AR_RTC_FORCE_WAKE_EN); 2080 if (AR_SREV_9100(ah)) 2081 mdelay(10); 2082 else 2083 udelay(50); 2084 2085 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2086 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2087 if (val == AR_RTC_STATUS_ON) 2088 break; 2089 udelay(50); 2090 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2091 AR_RTC_FORCE_WAKE_EN); 2092 } 2093 if (i == 0) { 2094 ath_err(ath9k_hw_common(ah), 2095 "Failed to wakeup in %uus\n", 2096 POWER_UP_TIME / 20); 2097 return false; 2098 } 2099 2100 if (ath9k_hw_mci_is_enabled(ah)) 2101 ar9003_mci_set_power_awake(ah); 2102 2103 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2104 2105 return true; 2106 } 2107 2108 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2109 { 2110 struct ath_common *common = ath9k_hw_common(ah); 2111 int status = true; 2112 static const char *modes[] = { 2113 "AWAKE", 2114 "FULL-SLEEP", 2115 "NETWORK SLEEP", 2116 "UNDEFINED" 2117 }; 2118 2119 if (ah->power_mode == mode) 2120 return status; 2121 2122 ath_dbg(common, RESET, "%s -> %s\n", 2123 modes[ah->power_mode], modes[mode]); 2124 2125 switch (mode) { 2126 case ATH9K_PM_AWAKE: 2127 status = ath9k_hw_set_power_awake(ah); 2128 break; 2129 case ATH9K_PM_FULL_SLEEP: 2130 if (ath9k_hw_mci_is_enabled(ah)) 2131 ar9003_mci_set_full_sleep(ah); 2132 2133 ath9k_set_power_sleep(ah); 2134 ah->chip_fullsleep = true; 2135 break; 2136 case ATH9K_PM_NETWORK_SLEEP: 2137 ath9k_set_power_network_sleep(ah); 2138 break; 2139 default: 2140 ath_err(common, "Unknown power mode %u\n", mode); 2141 return false; 2142 } 2143 ah->power_mode = mode; 2144 2145 /* 2146 * XXX: If this warning never comes up after a while then 2147 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2148 * ath9k_hw_setpower() return type void. 2149 */ 2150 2151 if (!(ah->ah_flags & AH_UNPLUGGED)) 2152 ATH_DBG_WARN_ON_ONCE(!status); 2153 2154 return status; 2155 } 2156 EXPORT_SYMBOL(ath9k_hw_setpower); 2157 2158 /*******************/ 2159 /* Beacon Handling */ 2160 /*******************/ 2161 2162 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2163 { 2164 int flags = 0; 2165 2166 ENABLE_REGWRITE_BUFFER(ah); 2167 2168 switch (ah->opmode) { 2169 case NL80211_IFTYPE_ADHOC: 2170 REG_SET_BIT(ah, AR_TXCFG, 2171 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2172 case NL80211_IFTYPE_MESH_POINT: 2173 case NL80211_IFTYPE_AP: 2174 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2175 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2176 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2177 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2178 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2179 flags |= 2180 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2181 break; 2182 default: 2183 ath_dbg(ath9k_hw_common(ah), BEACON, 2184 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2185 return; 2186 break; 2187 } 2188 2189 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2190 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2191 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2192 2193 REGWRITE_BUFFER_FLUSH(ah); 2194 2195 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2196 } 2197 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2198 2199 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2200 const struct ath9k_beacon_state *bs) 2201 { 2202 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2203 struct ath9k_hw_capabilities *pCap = &ah->caps; 2204 struct ath_common *common = ath9k_hw_common(ah); 2205 2206 ENABLE_REGWRITE_BUFFER(ah); 2207 2208 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2209 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2210 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2211 2212 REGWRITE_BUFFER_FLUSH(ah); 2213 2214 REG_RMW_FIELD(ah, AR_RSSI_THR, 2215 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2216 2217 beaconintval = bs->bs_intval; 2218 2219 if (bs->bs_sleepduration > beaconintval) 2220 beaconintval = bs->bs_sleepduration; 2221 2222 dtimperiod = bs->bs_dtimperiod; 2223 if (bs->bs_sleepduration > dtimperiod) 2224 dtimperiod = bs->bs_sleepduration; 2225 2226 if (beaconintval == dtimperiod) 2227 nextTbtt = bs->bs_nextdtim; 2228 else 2229 nextTbtt = bs->bs_nexttbtt; 2230 2231 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2232 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2233 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2234 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2235 2236 ENABLE_REGWRITE_BUFFER(ah); 2237 2238 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2239 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2240 2241 REG_WRITE(ah, AR_SLEEP1, 2242 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2243 | AR_SLEEP1_ASSUME_DTIM); 2244 2245 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2246 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2247 else 2248 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2249 2250 REG_WRITE(ah, AR_SLEEP2, 2251 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2252 2253 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2254 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2255 2256 REGWRITE_BUFFER_FLUSH(ah); 2257 2258 REG_SET_BIT(ah, AR_TIMER_MODE, 2259 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2260 AR_DTIM_TIMER_EN); 2261 2262 /* TSF Out of Range Threshold */ 2263 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2264 } 2265 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2266 2267 /*******************/ 2268 /* HW Capabilities */ 2269 /*******************/ 2270 2271 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2272 { 2273 eeprom_chainmask &= chip_chainmask; 2274 if (eeprom_chainmask) 2275 return eeprom_chainmask; 2276 else 2277 return chip_chainmask; 2278 } 2279 2280 /** 2281 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2282 * @ah: the atheros hardware data structure 2283 * 2284 * We enable DFS support upstream on chipsets which have passed a series 2285 * of tests. The testing requirements are going to be documented. Desired 2286 * test requirements are documented at: 2287 * 2288 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2289 * 2290 * Once a new chipset gets properly tested an individual commit can be used 2291 * to document the testing for DFS for that chipset. 2292 */ 2293 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2294 { 2295 2296 switch (ah->hw_version.macVersion) { 2297 /* for temporary testing DFS with 9280 */ 2298 case AR_SREV_VERSION_9280: 2299 /* AR9580 will likely be our first target to get testing on */ 2300 case AR_SREV_VERSION_9580: 2301 return true; 2302 default: 2303 return false; 2304 } 2305 } 2306 2307 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2308 { 2309 struct ath9k_hw_capabilities *pCap = &ah->caps; 2310 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2311 struct ath_common *common = ath9k_hw_common(ah); 2312 unsigned int chip_chainmask; 2313 2314 u16 eeval; 2315 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2316 2317 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2318 regulatory->current_rd = eeval; 2319 2320 if (ah->opmode != NL80211_IFTYPE_AP && 2321 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2322 if (regulatory->current_rd == 0x64 || 2323 regulatory->current_rd == 0x65) 2324 regulatory->current_rd += 5; 2325 else if (regulatory->current_rd == 0x41) 2326 regulatory->current_rd = 0x43; 2327 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2328 regulatory->current_rd); 2329 } 2330 2331 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2332 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2333 ath_err(common, 2334 "no band has been marked as supported in EEPROM\n"); 2335 return -EINVAL; 2336 } 2337 2338 if (eeval & AR5416_OPFLAGS_11A) 2339 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2340 2341 if (eeval & AR5416_OPFLAGS_11G) 2342 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2343 2344 if (AR_SREV_9485(ah) || 2345 AR_SREV_9285(ah) || 2346 AR_SREV_9330(ah) || 2347 AR_SREV_9565(ah)) 2348 chip_chainmask = 1; 2349 else if (AR_SREV_9462(ah)) 2350 chip_chainmask = 3; 2351 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2352 chip_chainmask = 7; 2353 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2354 chip_chainmask = 3; 2355 else 2356 chip_chainmask = 7; 2357 2358 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2359 /* 2360 * For AR9271 we will temporarilly uses the rx chainmax as read from 2361 * the EEPROM. 2362 */ 2363 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2364 !(eeval & AR5416_OPFLAGS_11A) && 2365 !(AR_SREV_9271(ah))) 2366 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2367 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2368 else if (AR_SREV_9100(ah)) 2369 pCap->rx_chainmask = 0x7; 2370 else 2371 /* Use rx_chainmask from EEPROM. */ 2372 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2373 2374 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2375 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2376 ah->txchainmask = pCap->tx_chainmask; 2377 ah->rxchainmask = pCap->rx_chainmask; 2378 2379 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2380 2381 /* enable key search for every frame in an aggregate */ 2382 if (AR_SREV_9300_20_OR_LATER(ah)) 2383 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2384 2385 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2386 2387 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2388 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2389 else 2390 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2391 2392 if (AR_SREV_9271(ah)) 2393 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2394 else if (AR_DEVID_7010(ah)) 2395 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2396 else if (AR_SREV_9300_20_OR_LATER(ah)) 2397 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2398 else if (AR_SREV_9287_11_OR_LATER(ah)) 2399 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2400 else if (AR_SREV_9285_12_OR_LATER(ah)) 2401 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2402 else if (AR_SREV_9280_20_OR_LATER(ah)) 2403 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2404 else 2405 pCap->num_gpio_pins = AR_NUM_GPIO; 2406 2407 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2408 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2409 else 2410 pCap->rts_aggr_limit = (8 * 1024); 2411 2412 #ifdef CONFIG_ATH9K_RFKILL 2413 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2414 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2415 ah->rfkill_gpio = 2416 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2417 ah->rfkill_polarity = 2418 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2419 2420 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2421 } 2422 #endif 2423 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2424 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2425 else 2426 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2427 2428 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2429 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2430 else 2431 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2432 2433 if (AR_SREV_9300_20_OR_LATER(ah)) { 2434 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2435 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2436 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2437 2438 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2439 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2440 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2441 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2442 pCap->txs_len = sizeof(struct ar9003_txs); 2443 } else { 2444 pCap->tx_desc_len = sizeof(struct ath_desc); 2445 if (AR_SREV_9280_20(ah)) 2446 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2447 } 2448 2449 if (AR_SREV_9300_20_OR_LATER(ah)) 2450 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2451 2452 if (AR_SREV_9300_20_OR_LATER(ah)) 2453 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2454 2455 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2456 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2457 2458 if (AR_SREV_9285(ah)) { 2459 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2460 ant_div_ctl1 = 2461 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2462 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2463 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2464 ath_info(common, "Enable LNA combining\n"); 2465 } 2466 } 2467 } 2468 2469 if (AR_SREV_9300_20_OR_LATER(ah)) { 2470 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2471 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2472 } 2473 2474 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2475 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2476 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2477 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2478 ath_info(common, "Enable LNA combining\n"); 2479 } 2480 } 2481 2482 if (ath9k_hw_dfs_tested(ah)) 2483 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2484 2485 tx_chainmask = pCap->tx_chainmask; 2486 rx_chainmask = pCap->rx_chainmask; 2487 while (tx_chainmask || rx_chainmask) { 2488 if (tx_chainmask & BIT(0)) 2489 pCap->max_txchains++; 2490 if (rx_chainmask & BIT(0)) 2491 pCap->max_rxchains++; 2492 2493 tx_chainmask >>= 1; 2494 rx_chainmask >>= 1; 2495 } 2496 2497 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2498 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2499 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2500 2501 if (AR_SREV_9462_20_OR_LATER(ah)) 2502 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2503 } 2504 2505 if (AR_SREV_9462(ah)) 2506 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2507 2508 if (AR_SREV_9300_20_OR_LATER(ah) && 2509 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2510 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2511 2512 return 0; 2513 } 2514 2515 /****************************/ 2516 /* GPIO / RFKILL / Antennae */ 2517 /****************************/ 2518 2519 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2520 u32 gpio, u32 type) 2521 { 2522 int addr; 2523 u32 gpio_shift, tmp; 2524 2525 if (gpio > 11) 2526 addr = AR_GPIO_OUTPUT_MUX3; 2527 else if (gpio > 5) 2528 addr = AR_GPIO_OUTPUT_MUX2; 2529 else 2530 addr = AR_GPIO_OUTPUT_MUX1; 2531 2532 gpio_shift = (gpio % 6) * 5; 2533 2534 if (AR_SREV_9280_20_OR_LATER(ah) 2535 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2536 REG_RMW(ah, addr, (type << gpio_shift), 2537 (0x1f << gpio_shift)); 2538 } else { 2539 tmp = REG_READ(ah, addr); 2540 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2541 tmp &= ~(0x1f << gpio_shift); 2542 tmp |= (type << gpio_shift); 2543 REG_WRITE(ah, addr, tmp); 2544 } 2545 } 2546 2547 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2548 { 2549 u32 gpio_shift; 2550 2551 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2552 2553 if (AR_DEVID_7010(ah)) { 2554 gpio_shift = gpio; 2555 REG_RMW(ah, AR7010_GPIO_OE, 2556 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2557 (AR7010_GPIO_OE_MASK << gpio_shift)); 2558 return; 2559 } 2560 2561 gpio_shift = gpio << 1; 2562 REG_RMW(ah, 2563 AR_GPIO_OE_OUT, 2564 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2565 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2566 } 2567 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2568 2569 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2570 { 2571 #define MS_REG_READ(x, y) \ 2572 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2573 2574 if (gpio >= ah->caps.num_gpio_pins) 2575 return 0xffffffff; 2576 2577 if (AR_DEVID_7010(ah)) { 2578 u32 val; 2579 val = REG_READ(ah, AR7010_GPIO_IN); 2580 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2581 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2582 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2583 AR_GPIO_BIT(gpio)) != 0; 2584 else if (AR_SREV_9271(ah)) 2585 return MS_REG_READ(AR9271, gpio) != 0; 2586 else if (AR_SREV_9287_11_OR_LATER(ah)) 2587 return MS_REG_READ(AR9287, gpio) != 0; 2588 else if (AR_SREV_9285_12_OR_LATER(ah)) 2589 return MS_REG_READ(AR9285, gpio) != 0; 2590 else if (AR_SREV_9280_20_OR_LATER(ah)) 2591 return MS_REG_READ(AR928X, gpio) != 0; 2592 else 2593 return MS_REG_READ(AR, gpio) != 0; 2594 } 2595 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2596 2597 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2598 u32 ah_signal_type) 2599 { 2600 u32 gpio_shift; 2601 2602 if (AR_DEVID_7010(ah)) { 2603 gpio_shift = gpio; 2604 REG_RMW(ah, AR7010_GPIO_OE, 2605 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2606 (AR7010_GPIO_OE_MASK << gpio_shift)); 2607 return; 2608 } 2609 2610 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2611 gpio_shift = 2 * gpio; 2612 REG_RMW(ah, 2613 AR_GPIO_OE_OUT, 2614 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2615 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2616 } 2617 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2618 2619 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2620 { 2621 if (AR_DEVID_7010(ah)) { 2622 val = val ? 0 : 1; 2623 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2624 AR_GPIO_BIT(gpio)); 2625 return; 2626 } 2627 2628 if (AR_SREV_9271(ah)) 2629 val = ~val; 2630 2631 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2632 AR_GPIO_BIT(gpio)); 2633 } 2634 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2635 2636 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2637 { 2638 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2639 } 2640 EXPORT_SYMBOL(ath9k_hw_setantenna); 2641 2642 /*********************/ 2643 /* General Operation */ 2644 /*********************/ 2645 2646 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2647 { 2648 u32 bits = REG_READ(ah, AR_RX_FILTER); 2649 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2650 2651 if (phybits & AR_PHY_ERR_RADAR) 2652 bits |= ATH9K_RX_FILTER_PHYRADAR; 2653 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2654 bits |= ATH9K_RX_FILTER_PHYERR; 2655 2656 return bits; 2657 } 2658 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2659 2660 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2661 { 2662 u32 phybits; 2663 2664 ENABLE_REGWRITE_BUFFER(ah); 2665 2666 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2667 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2668 2669 REG_WRITE(ah, AR_RX_FILTER, bits); 2670 2671 phybits = 0; 2672 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2673 phybits |= AR_PHY_ERR_RADAR; 2674 if (bits & ATH9K_RX_FILTER_PHYERR) 2675 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2676 REG_WRITE(ah, AR_PHY_ERR, phybits); 2677 2678 if (phybits) 2679 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2680 else 2681 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2682 2683 REGWRITE_BUFFER_FLUSH(ah); 2684 } 2685 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2686 2687 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2688 { 2689 if (ath9k_hw_mci_is_enabled(ah)) 2690 ar9003_mci_bt_gain_ctrl(ah); 2691 2692 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2693 return false; 2694 2695 ath9k_hw_init_pll(ah, NULL); 2696 ah->htc_reset_init = true; 2697 return true; 2698 } 2699 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2700 2701 bool ath9k_hw_disable(struct ath_hw *ah) 2702 { 2703 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2704 return false; 2705 2706 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2707 return false; 2708 2709 ath9k_hw_init_pll(ah, NULL); 2710 return true; 2711 } 2712 EXPORT_SYMBOL(ath9k_hw_disable); 2713 2714 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2715 { 2716 enum eeprom_param gain_param; 2717 2718 if (IS_CHAN_2GHZ(chan)) 2719 gain_param = EEP_ANTENNA_GAIN_2G; 2720 else 2721 gain_param = EEP_ANTENNA_GAIN_5G; 2722 2723 return ah->eep_ops->get_eeprom(ah, gain_param); 2724 } 2725 2726 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2727 bool test) 2728 { 2729 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2730 struct ieee80211_channel *channel; 2731 int chan_pwr, new_pwr, max_gain; 2732 int ant_gain, ant_reduction = 0; 2733 2734 if (!chan) 2735 return; 2736 2737 channel = chan->chan; 2738 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2739 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2740 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2741 2742 ant_gain = get_antenna_gain(ah, chan); 2743 if (ant_gain > max_gain) 2744 ant_reduction = ant_gain - max_gain; 2745 2746 ah->eep_ops->set_txpower(ah, chan, 2747 ath9k_regd_get_ctl(reg, chan), 2748 ant_reduction, new_pwr, test); 2749 } 2750 2751 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2752 { 2753 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2754 struct ath9k_channel *chan = ah->curchan; 2755 struct ieee80211_channel *channel = chan->chan; 2756 2757 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2758 if (test) 2759 channel->max_power = MAX_RATE_POWER / 2; 2760 2761 ath9k_hw_apply_txpower(ah, chan, test); 2762 2763 if (test) 2764 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2765 } 2766 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2767 2768 void ath9k_hw_setopmode(struct ath_hw *ah) 2769 { 2770 ath9k_hw_set_operating_mode(ah, ah->opmode); 2771 } 2772 EXPORT_SYMBOL(ath9k_hw_setopmode); 2773 2774 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2775 { 2776 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2777 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2778 } 2779 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2780 2781 void ath9k_hw_write_associd(struct ath_hw *ah) 2782 { 2783 struct ath_common *common = ath9k_hw_common(ah); 2784 2785 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2786 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2787 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2788 } 2789 EXPORT_SYMBOL(ath9k_hw_write_associd); 2790 2791 #define ATH9K_MAX_TSF_READ 10 2792 2793 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2794 { 2795 u32 tsf_lower, tsf_upper1, tsf_upper2; 2796 int i; 2797 2798 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2799 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2800 tsf_lower = REG_READ(ah, AR_TSF_L32); 2801 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2802 if (tsf_upper2 == tsf_upper1) 2803 break; 2804 tsf_upper1 = tsf_upper2; 2805 } 2806 2807 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2808 2809 return (((u64)tsf_upper1 << 32) | tsf_lower); 2810 } 2811 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2812 2813 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2814 { 2815 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2816 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2817 } 2818 EXPORT_SYMBOL(ath9k_hw_settsf64); 2819 2820 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2821 { 2822 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2823 AH_TSF_WRITE_TIMEOUT)) 2824 ath_dbg(ath9k_hw_common(ah), RESET, 2825 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2826 2827 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2828 } 2829 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2830 2831 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2832 { 2833 if (set) 2834 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2835 else 2836 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2837 } 2838 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2839 2840 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2841 { 2842 u32 macmode; 2843 2844 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2845 macmode = AR_2040_JOINED_RX_CLEAR; 2846 else 2847 macmode = 0; 2848 2849 REG_WRITE(ah, AR_2040_MODE, macmode); 2850 } 2851 2852 /* HW Generic timers configuration */ 2853 2854 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2855 { 2856 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2858 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2859 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2860 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2861 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2862 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2863 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2864 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2865 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2866 AR_NDP2_TIMER_MODE, 0x0002}, 2867 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2868 AR_NDP2_TIMER_MODE, 0x0004}, 2869 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2870 AR_NDP2_TIMER_MODE, 0x0008}, 2871 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2872 AR_NDP2_TIMER_MODE, 0x0010}, 2873 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2874 AR_NDP2_TIMER_MODE, 0x0020}, 2875 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2876 AR_NDP2_TIMER_MODE, 0x0040}, 2877 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2878 AR_NDP2_TIMER_MODE, 0x0080} 2879 }; 2880 2881 /* HW generic timer primitives */ 2882 2883 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2884 { 2885 return REG_READ(ah, AR_TSF_L32); 2886 } 2887 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2888 2889 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2890 void (*trigger)(void *), 2891 void (*overflow)(void *), 2892 void *arg, 2893 u8 timer_index) 2894 { 2895 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2896 struct ath_gen_timer *timer; 2897 2898 if ((timer_index < AR_FIRST_NDP_TIMER) || 2899 (timer_index >= ATH_MAX_GEN_TIMER)) 2900 return NULL; 2901 2902 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2903 if (timer == NULL) 2904 return NULL; 2905 2906 /* allocate a hardware generic timer slot */ 2907 timer_table->timers[timer_index] = timer; 2908 timer->index = timer_index; 2909 timer->trigger = trigger; 2910 timer->overflow = overflow; 2911 timer->arg = arg; 2912 2913 return timer; 2914 } 2915 EXPORT_SYMBOL(ath_gen_timer_alloc); 2916 2917 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2918 struct ath_gen_timer *timer, 2919 u32 timer_next, 2920 u32 timer_period) 2921 { 2922 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2923 u32 mask = 0; 2924 2925 timer_table->timer_mask |= BIT(timer->index); 2926 2927 /* 2928 * Program generic timer registers 2929 */ 2930 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2931 timer_next); 2932 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2933 timer_period); 2934 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2935 gen_tmr_configuration[timer->index].mode_mask); 2936 2937 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2938 /* 2939 * Starting from AR9462, each generic timer can select which tsf 2940 * to use. But we still follow the old rule, 0 - 7 use tsf and 2941 * 8 - 15 use tsf2. 2942 */ 2943 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2944 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2945 (1 << timer->index)); 2946 else 2947 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2948 (1 << timer->index)); 2949 } 2950 2951 if (timer->trigger) 2952 mask |= SM(AR_GENTMR_BIT(timer->index), 2953 AR_IMR_S5_GENTIMER_TRIG); 2954 if (timer->overflow) 2955 mask |= SM(AR_GENTMR_BIT(timer->index), 2956 AR_IMR_S5_GENTIMER_THRESH); 2957 2958 REG_SET_BIT(ah, AR_IMR_S5, mask); 2959 2960 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 2961 ah->imask |= ATH9K_INT_GENTIMER; 2962 ath9k_hw_set_interrupts(ah); 2963 } 2964 } 2965 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2966 2967 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2968 { 2969 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2970 2971 /* Clear generic timer enable bits. */ 2972 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2973 gen_tmr_configuration[timer->index].mode_mask); 2974 2975 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2976 /* 2977 * Need to switch back to TSF if it was using TSF2. 2978 */ 2979 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 2980 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2981 (1 << timer->index)); 2982 } 2983 } 2984 2985 /* Disable both trigger and thresh interrupt masks */ 2986 REG_CLR_BIT(ah, AR_IMR_S5, 2987 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2988 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2989 2990 timer_table->timer_mask &= ~BIT(timer->index); 2991 2992 if (timer_table->timer_mask == 0) { 2993 ah->imask &= ~ATH9K_INT_GENTIMER; 2994 ath9k_hw_set_interrupts(ah); 2995 } 2996 } 2997 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2998 2999 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3000 { 3001 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3002 3003 /* free the hardware generic timer slot */ 3004 timer_table->timers[timer->index] = NULL; 3005 kfree(timer); 3006 } 3007 EXPORT_SYMBOL(ath_gen_timer_free); 3008 3009 /* 3010 * Generic Timer Interrupts handling 3011 */ 3012 void ath_gen_timer_isr(struct ath_hw *ah) 3013 { 3014 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3015 struct ath_gen_timer *timer; 3016 unsigned long trigger_mask, thresh_mask; 3017 unsigned int index; 3018 3019 /* get hardware generic timer interrupt status */ 3020 trigger_mask = ah->intr_gen_timer_trigger; 3021 thresh_mask = ah->intr_gen_timer_thresh; 3022 trigger_mask &= timer_table->timer_mask; 3023 thresh_mask &= timer_table->timer_mask; 3024 3025 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3026 timer = timer_table->timers[index]; 3027 if (!timer) 3028 continue; 3029 if (!timer->overflow) 3030 continue; 3031 3032 trigger_mask &= ~BIT(index); 3033 timer->overflow(timer->arg); 3034 } 3035 3036 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3037 timer = timer_table->timers[index]; 3038 if (!timer) 3039 continue; 3040 if (!timer->trigger) 3041 continue; 3042 timer->trigger(timer->arg); 3043 } 3044 } 3045 EXPORT_SYMBOL(ath_gen_timer_isr); 3046 3047 /********/ 3048 /* HTC */ 3049 /********/ 3050 3051 static struct { 3052 u32 version; 3053 const char * name; 3054 } ath_mac_bb_names[] = { 3055 /* Devices with external radios */ 3056 { AR_SREV_VERSION_5416_PCI, "5416" }, 3057 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3058 { AR_SREV_VERSION_9100, "9100" }, 3059 { AR_SREV_VERSION_9160, "9160" }, 3060 /* Single-chip solutions */ 3061 { AR_SREV_VERSION_9280, "9280" }, 3062 { AR_SREV_VERSION_9285, "9285" }, 3063 { AR_SREV_VERSION_9287, "9287" }, 3064 { AR_SREV_VERSION_9271, "9271" }, 3065 { AR_SREV_VERSION_9300, "9300" }, 3066 { AR_SREV_VERSION_9330, "9330" }, 3067 { AR_SREV_VERSION_9340, "9340" }, 3068 { AR_SREV_VERSION_9485, "9485" }, 3069 { AR_SREV_VERSION_9462, "9462" }, 3070 { AR_SREV_VERSION_9550, "9550" }, 3071 { AR_SREV_VERSION_9565, "9565" }, 3072 { AR_SREV_VERSION_9531, "9531" }, 3073 }; 3074 3075 /* For devices with external radios */ 3076 static struct { 3077 u16 version; 3078 const char * name; 3079 } ath_rf_names[] = { 3080 { 0, "5133" }, 3081 { AR_RAD5133_SREV_MAJOR, "5133" }, 3082 { AR_RAD5122_SREV_MAJOR, "5122" }, 3083 { AR_RAD2133_SREV_MAJOR, "2133" }, 3084 { AR_RAD2122_SREV_MAJOR, "2122" } 3085 }; 3086 3087 /* 3088 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3089 */ 3090 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3091 { 3092 int i; 3093 3094 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3095 if (ath_mac_bb_names[i].version == mac_bb_version) { 3096 return ath_mac_bb_names[i].name; 3097 } 3098 } 3099 3100 return "????"; 3101 } 3102 3103 /* 3104 * Return the RF name. "????" is returned if the RF is unknown. 3105 * Used for devices with external radios. 3106 */ 3107 static const char *ath9k_hw_rf_name(u16 rf_version) 3108 { 3109 int i; 3110 3111 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3112 if (ath_rf_names[i].version == rf_version) { 3113 return ath_rf_names[i].name; 3114 } 3115 } 3116 3117 return "????"; 3118 } 3119 3120 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3121 { 3122 int used; 3123 3124 /* chipsets >= AR9280 are single-chip */ 3125 if (AR_SREV_9280_20_OR_LATER(ah)) { 3126 used = scnprintf(hw_name, len, 3127 "Atheros AR%s Rev:%x", 3128 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3129 ah->hw_version.macRev); 3130 } 3131 else { 3132 used = scnprintf(hw_name, len, 3133 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3134 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3135 ah->hw_version.macRev, 3136 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3137 & AR_RADIO_SREV_MAJOR)), 3138 ah->hw_version.phyRev); 3139 } 3140 3141 hw_name[used] = '\0'; 3142 } 3143 EXPORT_SYMBOL(ath9k_hw_name); 3144