1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <asm/unaligned.h> 20 21 #include "hw.h" 22 #include "hw-ops.h" 23 #include "rc.h" 24 #include "ar9003_mac.h" 25 26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28 MODULE_AUTHOR("Atheros Communications"); 29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31 MODULE_LICENSE("Dual BSD/GPL"); 32 33 static int __init ath9k_init(void) 34 { 35 return 0; 36 } 37 module_init(ath9k_init); 38 39 static void __exit ath9k_exit(void) 40 { 41 return; 42 } 43 module_exit(ath9k_exit); 44 45 /* Private hardware callbacks */ 46 47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48 { 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50 } 51 52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55 } 56 57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59 { 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61 } 62 63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64 { 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69 } 70 71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72 { 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78 } 79 80 /********************/ 81 /* Helper Functions */ 82 /********************/ 83 84 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 85 { 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 87 struct ath_common *common = ath9k_hw_common(ah); 88 unsigned int clockrate; 89 90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 92 clockrate = 117; 93 else if (!ah->curchan) /* should really check for CCK instead */ 94 clockrate = ATH9K_CLOCK_RATE_CCK; 95 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 99 else 100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 101 102 if (conf_is_ht40(conf)) 103 clockrate *= 2; 104 105 if (ah->curchan) { 106 if (IS_CHAN_HALF_RATE(ah->curchan)) 107 clockrate /= 2; 108 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 109 clockrate /= 4; 110 } 111 112 common->clockrate = clockrate; 113 } 114 115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 116 { 117 struct ath_common *common = ath9k_hw_common(ah); 118 119 return usecs * common->clockrate; 120 } 121 122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 123 { 124 int i; 125 126 BUG_ON(timeout < AH_TIME_QUANTUM); 127 128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 129 if ((REG_READ(ah, reg) & mask) == val) 130 return true; 131 132 udelay(AH_TIME_QUANTUM); 133 } 134 135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 137 timeout, reg, REG_READ(ah, reg), mask, val); 138 139 return false; 140 } 141 EXPORT_SYMBOL(ath9k_hw_wait); 142 143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 144 int column, unsigned int *writecnt) 145 { 146 int r; 147 148 ENABLE_REGWRITE_BUFFER(ah); 149 for (r = 0; r < array->ia_rows; r++) { 150 REG_WRITE(ah, INI_RA(array, r, 0), 151 INI_RA(array, r, column)); 152 DO_DELAY(*writecnt); 153 } 154 REGWRITE_BUFFER_FLUSH(ah); 155 } 156 157 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 158 { 159 u32 retval; 160 int i; 161 162 for (i = 0, retval = 0; i < n; i++) { 163 retval = (retval << 1) | (val & 1); 164 val >>= 1; 165 } 166 return retval; 167 } 168 169 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 170 u8 phy, int kbps, 171 u32 frameLen, u16 rateix, 172 bool shortPreamble) 173 { 174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 175 176 if (kbps == 0) 177 return 0; 178 179 switch (phy) { 180 case WLAN_RC_PHY_CCK: 181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 182 if (shortPreamble) 183 phyTime >>= 1; 184 numBits = frameLen << 3; 185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 186 break; 187 case WLAN_RC_PHY_OFDM: 188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 190 numBits = OFDM_PLCP_BITS + (frameLen << 3); 191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 192 txTime = OFDM_SIFS_TIME_QUARTER 193 + OFDM_PREAMBLE_TIME_QUARTER 194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 195 } else if (ah->curchan && 196 IS_CHAN_HALF_RATE(ah->curchan)) { 197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 198 numBits = OFDM_PLCP_BITS + (frameLen << 3); 199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 200 txTime = OFDM_SIFS_TIME_HALF + 201 OFDM_PREAMBLE_TIME_HALF 202 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 203 } else { 204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 205 numBits = OFDM_PLCP_BITS + (frameLen << 3); 206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 208 + (numSymbols * OFDM_SYMBOL_TIME); 209 } 210 break; 211 default: 212 ath_err(ath9k_hw_common(ah), 213 "Unknown phy %u (rate ix %u)\n", phy, rateix); 214 txTime = 0; 215 break; 216 } 217 218 return txTime; 219 } 220 EXPORT_SYMBOL(ath9k_hw_computetxtime); 221 222 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 223 struct ath9k_channel *chan, 224 struct chan_centers *centers) 225 { 226 int8_t extoff; 227 228 if (!IS_CHAN_HT40(chan)) { 229 centers->ctl_center = centers->ext_center = 230 centers->synth_center = chan->channel; 231 return; 232 } 233 234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 235 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 236 centers->synth_center = 237 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 238 extoff = 1; 239 } else { 240 centers->synth_center = 241 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 242 extoff = -1; 243 } 244 245 centers->ctl_center = 246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 247 /* 25 MHz spacing is supported by hw but not on upper layers */ 248 centers->ext_center = 249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 250 } 251 252 /******************/ 253 /* Chip Revisions */ 254 /******************/ 255 256 static void ath9k_hw_read_revisions(struct ath_hw *ah) 257 { 258 u32 val; 259 260 switch (ah->hw_version.devid) { 261 case AR5416_AR9100_DEVID: 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 263 break; 264 case AR9300_DEVID_AR9330: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 266 if (ah->get_mac_revision) { 267 ah->hw_version.macRev = ah->get_mac_revision(); 268 } else { 269 val = REG_READ(ah, AR_SREV); 270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 271 } 272 return; 273 case AR9300_DEVID_AR9340: 274 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 275 val = REG_READ(ah, AR_SREV); 276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 277 return; 278 } 279 280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 281 282 if (val == 0xFF) { 283 val = REG_READ(ah, AR_SREV); 284 ah->hw_version.macVersion = 285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 288 } else { 289 if (!AR_SREV_9100(ah)) 290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 291 292 ah->hw_version.macRev = val & AR_SREV_REVISION; 293 294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 295 ah->is_pciexpress = true; 296 } 297 } 298 299 /************************************/ 300 /* HW Attach, Detach, Init Routines */ 301 /************************************/ 302 303 static void ath9k_hw_disablepcie(struct ath_hw *ah) 304 { 305 if (!AR_SREV_5416(ah)) 306 return; 307 308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 317 318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 319 } 320 321 static void ath9k_hw_aspm_init(struct ath_hw *ah) 322 { 323 struct ath_common *common = ath9k_hw_common(ah); 324 325 if (common->bus_ops->aspm_init) 326 common->bus_ops->aspm_init(common); 327 } 328 329 /* This should work for all families including legacy */ 330 static bool ath9k_hw_chip_test(struct ath_hw *ah) 331 { 332 struct ath_common *common = ath9k_hw_common(ah); 333 u32 regAddr[2] = { AR_STA_ID0 }; 334 u32 regHold[2]; 335 static const u32 patternData[4] = { 336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 337 }; 338 int i, j, loop_max; 339 340 if (!AR_SREV_9300_20_OR_LATER(ah)) { 341 loop_max = 2; 342 regAddr[1] = AR_PHY_BASE + (8 << 2); 343 } else 344 loop_max = 1; 345 346 for (i = 0; i < loop_max; i++) { 347 u32 addr = regAddr[i]; 348 u32 wrData, rdData; 349 350 regHold[i] = REG_READ(ah, addr); 351 for (j = 0; j < 0x100; j++) { 352 wrData = (j << 16) | j; 353 REG_WRITE(ah, addr, wrData); 354 rdData = REG_READ(ah, addr); 355 if (rdData != wrData) { 356 ath_err(common, 357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 358 addr, wrData, rdData); 359 return false; 360 } 361 } 362 for (j = 0; j < 4; j++) { 363 wrData = patternData[j]; 364 REG_WRITE(ah, addr, wrData); 365 rdData = REG_READ(ah, addr); 366 if (wrData != rdData) { 367 ath_err(common, 368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 369 addr, wrData, rdData); 370 return false; 371 } 372 } 373 REG_WRITE(ah, regAddr[i], regHold[i]); 374 } 375 udelay(100); 376 377 return true; 378 } 379 380 static void ath9k_hw_init_config(struct ath_hw *ah) 381 { 382 int i; 383 384 ah->config.dma_beacon_response_time = 2; 385 ah->config.sw_beacon_response_time = 10; 386 ah->config.additional_swba_backoff = 0; 387 ah->config.ack_6mb = 0x0; 388 ah->config.cwm_ignore_extcca = 0; 389 ah->config.pcie_clock_req = 0; 390 ah->config.pcie_waen = 0; 391 ah->config.analog_shiftreg = 1; 392 ah->config.enable_ani = true; 393 394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 395 ah->config.spurchans[i][0] = AR_NO_SPUR; 396 ah->config.spurchans[i][1] = AR_NO_SPUR; 397 } 398 399 /* PAPRD needs some more work to be enabled */ 400 ah->config.paprd_disable = 1; 401 402 ah->config.rx_intr_mitigation = true; 403 ah->config.pcieSerDesWrite = true; 404 405 /* 406 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 408 * This means we use it for all AR5416 devices, and the few 409 * minor PCI AR9280 devices out there. 410 * 411 * Serialization is required because these devices do not handle 412 * well the case of two concurrent reads/writes due to the latency 413 * involved. During one read/write another read/write can be issued 414 * on another CPU while the previous read/write may still be working 415 * on our hardware, if we hit this case the hardware poops in a loop. 416 * We prevent this by serializing reads and writes. 417 * 418 * This issue is not present on PCI-Express devices or pre-AR5416 419 * devices (legacy, 802.11abg). 420 */ 421 if (num_possible_cpus() > 1) 422 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 423 } 424 425 static void ath9k_hw_init_defaults(struct ath_hw *ah) 426 { 427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 428 429 regulatory->country_code = CTRY_DEFAULT; 430 regulatory->power_limit = MAX_RATE_POWER; 431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 432 433 ah->hw_version.magic = AR5416_MAGIC; 434 ah->hw_version.subvendorid = 0; 435 436 ah->atim_window = 0; 437 ah->sta_id1_defaults = 438 AR_STA_ID1_CRPT_MIC_ENABLE | 439 AR_STA_ID1_MCAST_KSRCH; 440 if (AR_SREV_9100(ah)) 441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 442 ah->enable_32kHz_clock = DONT_USE_32KHZ; 443 ah->slottime = 20; 444 ah->globaltxtimeout = (u32) -1; 445 ah->power_mode = ATH9K_PM_UNDEFINED; 446 } 447 448 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 449 { 450 struct ath_common *common = ath9k_hw_common(ah); 451 u32 sum; 452 int i; 453 u16 eeval; 454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 455 456 sum = 0; 457 for (i = 0; i < 3; i++) { 458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 459 sum += eeval; 460 common->macaddr[2 * i] = eeval >> 8; 461 common->macaddr[2 * i + 1] = eeval & 0xff; 462 } 463 if (sum == 0 || sum == 0xffff * 3) 464 return -EADDRNOTAVAIL; 465 466 return 0; 467 } 468 469 static int ath9k_hw_post_init(struct ath_hw *ah) 470 { 471 struct ath_common *common = ath9k_hw_common(ah); 472 int ecode; 473 474 if (common->bus_ops->ath_bus_type != ATH_USB) { 475 if (!ath9k_hw_chip_test(ah)) 476 return -ENODEV; 477 } 478 479 if (!AR_SREV_9300_20_OR_LATER(ah)) { 480 ecode = ar9002_hw_rf_claim(ah); 481 if (ecode != 0) 482 return ecode; 483 } 484 485 ecode = ath9k_hw_eeprom_init(ah); 486 if (ecode != 0) 487 return ecode; 488 489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 490 "Eeprom VER: %d, REV: %d\n", 491 ah->eep_ops->get_eeprom_ver(ah), 492 ah->eep_ops->get_eeprom_rev(ah)); 493 494 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 495 if (ecode) { 496 ath_err(ath9k_hw_common(ah), 497 "Failed allocating banks for external radio\n"); 498 ath9k_hw_rf_free_ext_banks(ah); 499 return ecode; 500 } 501 502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { 503 ath9k_hw_ani_setup(ah); 504 ath9k_hw_ani_init(ah); 505 } 506 507 return 0; 508 } 509 510 static void ath9k_hw_attach_ops(struct ath_hw *ah) 511 { 512 if (AR_SREV_9300_20_OR_LATER(ah)) 513 ar9003_hw_attach_ops(ah); 514 else 515 ar9002_hw_attach_ops(ah); 516 } 517 518 /* Called for all hardware families */ 519 static int __ath9k_hw_init(struct ath_hw *ah) 520 { 521 struct ath_common *common = ath9k_hw_common(ah); 522 int r = 0; 523 524 ath9k_hw_read_revisions(ah); 525 526 /* 527 * Read back AR_WA into a permanent copy and set bits 14 and 17. 528 * We need to do this to avoid RMW of this register. We cannot 529 * read the reg when chip is asleep. 530 */ 531 ah->WARegVal = REG_READ(ah, AR_WA); 532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 533 AR_WA_ASPM_TIMER_BASED_DISABLE); 534 535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 536 ath_err(common, "Couldn't reset chip\n"); 537 return -EIO; 538 } 539 540 ath9k_hw_init_defaults(ah); 541 ath9k_hw_init_config(ah); 542 543 ath9k_hw_attach_ops(ah); 544 545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 546 ath_err(common, "Couldn't wakeup chip\n"); 547 return -EIO; 548 } 549 550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 553 !ah->is_pciexpress)) { 554 ah->config.serialize_regmode = 555 SER_REG_MODE_ON; 556 } else { 557 ah->config.serialize_regmode = 558 SER_REG_MODE_OFF; 559 } 560 } 561 562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 563 ah->config.serialize_regmode); 564 565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 567 else 568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 569 570 switch (ah->hw_version.macVersion) { 571 case AR_SREV_VERSION_5416_PCI: 572 case AR_SREV_VERSION_5416_PCIE: 573 case AR_SREV_VERSION_9160: 574 case AR_SREV_VERSION_9100: 575 case AR_SREV_VERSION_9280: 576 case AR_SREV_VERSION_9285: 577 case AR_SREV_VERSION_9287: 578 case AR_SREV_VERSION_9271: 579 case AR_SREV_VERSION_9300: 580 case AR_SREV_VERSION_9330: 581 case AR_SREV_VERSION_9485: 582 case AR_SREV_VERSION_9340: 583 break; 584 default: 585 ath_err(common, 586 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 587 ah->hw_version.macVersion, ah->hw_version.macRev); 588 return -EOPNOTSUPP; 589 } 590 591 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 592 AR_SREV_9330(ah)) 593 ah->is_pciexpress = false; 594 595 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 596 ath9k_hw_init_cal_settings(ah); 597 598 ah->ani_function = ATH9K_ANI_ALL; 599 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 601 if (!AR_SREV_9300_20_OR_LATER(ah)) 602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 603 604 ath9k_hw_init_mode_regs(ah); 605 606 607 if (ah->is_pciexpress) 608 ath9k_hw_aspm_init(ah); 609 else 610 ath9k_hw_disablepcie(ah); 611 612 if (!AR_SREV_9300_20_OR_LATER(ah)) 613 ar9002_hw_cck_chan14_spread(ah); 614 615 r = ath9k_hw_post_init(ah); 616 if (r) 617 return r; 618 619 ath9k_hw_init_mode_gain_regs(ah); 620 r = ath9k_hw_fill_cap_info(ah); 621 if (r) 622 return r; 623 624 r = ath9k_hw_init_macaddr(ah); 625 if (r) { 626 ath_err(common, "Failed to initialize MAC address\n"); 627 return r; 628 } 629 630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 631 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 632 else 633 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 634 635 if (AR_SREV_9330(ah)) 636 ah->bb_watchdog_timeout_ms = 85; 637 else 638 ah->bb_watchdog_timeout_ms = 25; 639 640 common->state = ATH_HW_INITIALIZED; 641 642 return 0; 643 } 644 645 int ath9k_hw_init(struct ath_hw *ah) 646 { 647 int ret; 648 struct ath_common *common = ath9k_hw_common(ah); 649 650 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 651 switch (ah->hw_version.devid) { 652 case AR5416_DEVID_PCI: 653 case AR5416_DEVID_PCIE: 654 case AR5416_AR9100_DEVID: 655 case AR9160_DEVID_PCI: 656 case AR9280_DEVID_PCI: 657 case AR9280_DEVID_PCIE: 658 case AR9285_DEVID_PCIE: 659 case AR9287_DEVID_PCI: 660 case AR9287_DEVID_PCIE: 661 case AR2427_DEVID_PCIE: 662 case AR9300_DEVID_PCIE: 663 case AR9300_DEVID_AR9485_PCIE: 664 case AR9300_DEVID_AR9330: 665 case AR9300_DEVID_AR9340: 666 break; 667 default: 668 if (common->bus_ops->ath_bus_type == ATH_USB) 669 break; 670 ath_err(common, "Hardware device ID 0x%04x not supported\n", 671 ah->hw_version.devid); 672 return -EOPNOTSUPP; 673 } 674 675 ret = __ath9k_hw_init(ah); 676 if (ret) { 677 ath_err(common, 678 "Unable to initialize hardware; initialization status: %d\n", 679 ret); 680 return ret; 681 } 682 683 return 0; 684 } 685 EXPORT_SYMBOL(ath9k_hw_init); 686 687 static void ath9k_hw_init_qos(struct ath_hw *ah) 688 { 689 ENABLE_REGWRITE_BUFFER(ah); 690 691 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 692 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 693 694 REG_WRITE(ah, AR_QOS_NO_ACK, 695 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 696 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 697 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 698 699 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 700 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 701 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 702 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 703 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 704 705 REGWRITE_BUFFER_FLUSH(ah); 706 } 707 708 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 709 { 710 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 711 udelay(100); 712 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 713 714 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 715 udelay(100); 716 717 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 718 } 719 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 720 721 static void ath9k_hw_init_pll(struct ath_hw *ah, 722 struct ath9k_channel *chan) 723 { 724 u32 pll; 725 726 if (AR_SREV_9485(ah)) { 727 728 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 730 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 732 AR_CH0_DPLL2_KD, 0x40); 733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 734 AR_CH0_DPLL2_KI, 0x4); 735 736 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 737 AR_CH0_BB_DPLL1_REFDIV, 0x5); 738 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 739 AR_CH0_BB_DPLL1_NINI, 0x58); 740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 741 AR_CH0_BB_DPLL1_NFRAC, 0x0); 742 743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 744 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 746 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 748 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 749 750 /* program BB PLL phase_shift to 0x6 */ 751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 752 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 753 754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 755 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 756 udelay(1000); 757 } else if (AR_SREV_9330(ah)) { 758 u32 ddr_dpll2, pll_control2, kd; 759 760 if (ah->is_clk_25mhz) { 761 ddr_dpll2 = 0x18e82f01; 762 pll_control2 = 0xe04a3d; 763 kd = 0x1d; 764 } else { 765 ddr_dpll2 = 0x19e82f01; 766 pll_control2 = 0x886666; 767 kd = 0x3d; 768 } 769 770 /* program DDR PLL ki and kd value */ 771 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 772 773 /* program DDR PLL phase_shift */ 774 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 775 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 776 777 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 778 udelay(1000); 779 780 /* program refdiv, nint, frac to RTC register */ 781 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 782 783 /* program BB PLL kd and ki value */ 784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 786 787 /* program BB PLL phase_shift */ 788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 789 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 790 } else if (AR_SREV_9340(ah)) { 791 u32 regval, pll2_divint, pll2_divfrac, refdiv; 792 793 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 794 udelay(1000); 795 796 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 797 udelay(100); 798 799 if (ah->is_clk_25mhz) { 800 pll2_divint = 0x54; 801 pll2_divfrac = 0x1eb85; 802 refdiv = 3; 803 } else { 804 pll2_divint = 88; 805 pll2_divfrac = 0; 806 refdiv = 5; 807 } 808 809 regval = REG_READ(ah, AR_PHY_PLL_MODE); 810 regval |= (0x1 << 16); 811 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 812 udelay(100); 813 814 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 815 (pll2_divint << 18) | pll2_divfrac); 816 udelay(100); 817 818 regval = REG_READ(ah, AR_PHY_PLL_MODE); 819 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 820 (0x4 << 26) | (0x18 << 19); 821 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 822 REG_WRITE(ah, AR_PHY_PLL_MODE, 823 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 824 udelay(1000); 825 } 826 827 pll = ath9k_hw_compute_pll_control(ah, chan); 828 829 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 830 831 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 832 udelay(1000); 833 834 /* Switch the core clock for ar9271 to 117Mhz */ 835 if (AR_SREV_9271(ah)) { 836 udelay(500); 837 REG_WRITE(ah, 0x50040, 0x304); 838 } 839 840 udelay(RTC_PLL_SETTLE_DELAY); 841 842 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 843 844 if (AR_SREV_9340(ah)) { 845 if (ah->is_clk_25mhz) { 846 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 847 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 848 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 849 } else { 850 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 851 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 852 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 853 } 854 udelay(100); 855 } 856 } 857 858 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 859 enum nl80211_iftype opmode) 860 { 861 u32 sync_default = AR_INTR_SYNC_DEFAULT; 862 u32 imr_reg = AR_IMR_TXERR | 863 AR_IMR_TXURN | 864 AR_IMR_RXERR | 865 AR_IMR_RXORN | 866 AR_IMR_BCNMISC; 867 868 if (AR_SREV_9340(ah)) 869 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 870 871 if (AR_SREV_9300_20_OR_LATER(ah)) { 872 imr_reg |= AR_IMR_RXOK_HP; 873 if (ah->config.rx_intr_mitigation) 874 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 875 else 876 imr_reg |= AR_IMR_RXOK_LP; 877 878 } else { 879 if (ah->config.rx_intr_mitigation) 880 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 881 else 882 imr_reg |= AR_IMR_RXOK; 883 } 884 885 if (ah->config.tx_intr_mitigation) 886 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 887 else 888 imr_reg |= AR_IMR_TXOK; 889 890 if (opmode == NL80211_IFTYPE_AP) 891 imr_reg |= AR_IMR_MIB; 892 893 ENABLE_REGWRITE_BUFFER(ah); 894 895 REG_WRITE(ah, AR_IMR, imr_reg); 896 ah->imrs2_reg |= AR_IMR_S2_GTT; 897 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 898 899 if (!AR_SREV_9100(ah)) { 900 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 901 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 902 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 903 } 904 905 REGWRITE_BUFFER_FLUSH(ah); 906 907 if (AR_SREV_9300_20_OR_LATER(ah)) { 908 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 909 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 910 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 911 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 912 } 913 } 914 915 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 916 { 917 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 918 val = min(val, (u32) 0xFFFF); 919 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 920 } 921 922 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 923 { 924 u32 val = ath9k_hw_mac_to_clks(ah, us); 925 val = min(val, (u32) 0xFFFF); 926 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 927 } 928 929 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 930 { 931 u32 val = ath9k_hw_mac_to_clks(ah, us); 932 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 933 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 934 } 935 936 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 937 { 938 u32 val = ath9k_hw_mac_to_clks(ah, us); 939 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 940 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 941 } 942 943 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 944 { 945 if (tu > 0xFFFF) { 946 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 947 "bad global tx timeout %u\n", tu); 948 ah->globaltxtimeout = (u32) -1; 949 return false; 950 } else { 951 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 952 ah->globaltxtimeout = tu; 953 return true; 954 } 955 } 956 957 void ath9k_hw_init_global_settings(struct ath_hw *ah) 958 { 959 struct ath_common *common = ath9k_hw_common(ah); 960 struct ieee80211_conf *conf = &common->hw->conf; 961 const struct ath9k_channel *chan = ah->curchan; 962 int acktimeout; 963 int slottime; 964 int sifstime; 965 int rx_lat = 0, tx_lat = 0, eifs = 0; 966 u32 reg; 967 968 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 969 ah->misc_mode); 970 971 if (!chan) 972 return; 973 974 if (ah->misc_mode != 0) 975 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 976 977 rx_lat = 37; 978 tx_lat = 54; 979 980 if (IS_CHAN_HALF_RATE(chan)) { 981 eifs = 175; 982 rx_lat *= 2; 983 tx_lat *= 2; 984 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 985 tx_lat += 11; 986 987 slottime = 13; 988 sifstime = 32; 989 } else if (IS_CHAN_QUARTER_RATE(chan)) { 990 eifs = 340; 991 rx_lat *= 4; 992 tx_lat *= 4; 993 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 994 tx_lat += 22; 995 996 slottime = 21; 997 sifstime = 64; 998 } else { 999 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS); 1000 reg = REG_READ(ah, AR_USEC); 1001 rx_lat = MS(reg, AR_USEC_RX_LAT); 1002 tx_lat = MS(reg, AR_USEC_TX_LAT); 1003 1004 slottime = ah->slottime; 1005 if (IS_CHAN_5GHZ(chan)) 1006 sifstime = 16; 1007 else 1008 sifstime = 10; 1009 } 1010 1011 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1012 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1013 1014 /* 1015 * Workaround for early ACK timeouts, add an offset to match the 1016 * initval's 64us ack timeout value. 1017 * This was initially only meant to work around an issue with delayed 1018 * BA frames in some implementations, but it has been found to fix ACK 1019 * timeout issues in other cases as well. 1020 */ 1021 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1022 acktimeout += 64 - sifstime - ah->slottime; 1023 1024 ath9k_hw_set_sifs_time(ah, sifstime); 1025 ath9k_hw_setslottime(ah, slottime); 1026 ath9k_hw_set_ack_timeout(ah, acktimeout); 1027 ath9k_hw_set_cts_timeout(ah, acktimeout); 1028 if (ah->globaltxtimeout != (u32) -1) 1029 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1030 1031 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1032 REG_RMW(ah, AR_USEC, 1033 (common->clockrate - 1) | 1034 SM(rx_lat, AR_USEC_RX_LAT) | 1035 SM(tx_lat, AR_USEC_TX_LAT), 1036 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1037 1038 } 1039 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1040 1041 void ath9k_hw_deinit(struct ath_hw *ah) 1042 { 1043 struct ath_common *common = ath9k_hw_common(ah); 1044 1045 if (common->state < ATH_HW_INITIALIZED) 1046 goto free_hw; 1047 1048 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1049 1050 free_hw: 1051 ath9k_hw_rf_free_ext_banks(ah); 1052 } 1053 EXPORT_SYMBOL(ath9k_hw_deinit); 1054 1055 /*******/ 1056 /* INI */ 1057 /*******/ 1058 1059 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1060 { 1061 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1062 1063 if (IS_CHAN_B(chan)) 1064 ctl |= CTL_11B; 1065 else if (IS_CHAN_G(chan)) 1066 ctl |= CTL_11G; 1067 else 1068 ctl |= CTL_11A; 1069 1070 return ctl; 1071 } 1072 1073 /****************************************/ 1074 /* Reset and Channel Switching Routines */ 1075 /****************************************/ 1076 1077 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1078 { 1079 struct ath_common *common = ath9k_hw_common(ah); 1080 1081 ENABLE_REGWRITE_BUFFER(ah); 1082 1083 /* 1084 * set AHB_MODE not to do cacheline prefetches 1085 */ 1086 if (!AR_SREV_9300_20_OR_LATER(ah)) 1087 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1088 1089 /* 1090 * let mac dma reads be in 128 byte chunks 1091 */ 1092 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1093 1094 REGWRITE_BUFFER_FLUSH(ah); 1095 1096 /* 1097 * Restore TX Trigger Level to its pre-reset value. 1098 * The initial value depends on whether aggregation is enabled, and is 1099 * adjusted whenever underruns are detected. 1100 */ 1101 if (!AR_SREV_9300_20_OR_LATER(ah)) 1102 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1103 1104 ENABLE_REGWRITE_BUFFER(ah); 1105 1106 /* 1107 * let mac dma writes be in 128 byte chunks 1108 */ 1109 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1110 1111 /* 1112 * Setup receive FIFO threshold to hold off TX activities 1113 */ 1114 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1115 1116 if (AR_SREV_9300_20_OR_LATER(ah)) { 1117 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1118 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1119 1120 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1121 ah->caps.rx_status_len); 1122 } 1123 1124 /* 1125 * reduce the number of usable entries in PCU TXBUF to avoid 1126 * wrap around issues. 1127 */ 1128 if (AR_SREV_9285(ah)) { 1129 /* For AR9285 the number of Fifos are reduced to half. 1130 * So set the usable tx buf size also to half to 1131 * avoid data/delimiter underruns 1132 */ 1133 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1134 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1135 } else if (!AR_SREV_9271(ah)) { 1136 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1137 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1138 } 1139 1140 REGWRITE_BUFFER_FLUSH(ah); 1141 1142 if (AR_SREV_9300_20_OR_LATER(ah)) 1143 ath9k_hw_reset_txstatus_ring(ah); 1144 } 1145 1146 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1147 { 1148 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1149 u32 set = AR_STA_ID1_KSRCH_MODE; 1150 1151 switch (opmode) { 1152 case NL80211_IFTYPE_ADHOC: 1153 case NL80211_IFTYPE_MESH_POINT: 1154 set |= AR_STA_ID1_ADHOC; 1155 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1156 break; 1157 case NL80211_IFTYPE_AP: 1158 set |= AR_STA_ID1_STA_AP; 1159 /* fall through */ 1160 case NL80211_IFTYPE_STATION: 1161 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1162 break; 1163 default: 1164 if (!ah->is_monitoring) 1165 set = 0; 1166 break; 1167 } 1168 REG_RMW(ah, AR_STA_ID1, set, mask); 1169 } 1170 1171 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1172 u32 *coef_mantissa, u32 *coef_exponent) 1173 { 1174 u32 coef_exp, coef_man; 1175 1176 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1177 if ((coef_scaled >> coef_exp) & 0x1) 1178 break; 1179 1180 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1181 1182 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1183 1184 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1185 *coef_exponent = coef_exp - 16; 1186 } 1187 1188 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1189 { 1190 u32 rst_flags; 1191 u32 tmpReg; 1192 1193 if (AR_SREV_9100(ah)) { 1194 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1195 AR_RTC_DERIVED_CLK_PERIOD, 1); 1196 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1197 } 1198 1199 ENABLE_REGWRITE_BUFFER(ah); 1200 1201 if (AR_SREV_9300_20_OR_LATER(ah)) { 1202 REG_WRITE(ah, AR_WA, ah->WARegVal); 1203 udelay(10); 1204 } 1205 1206 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1207 AR_RTC_FORCE_WAKE_ON_INT); 1208 1209 if (AR_SREV_9100(ah)) { 1210 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1211 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1212 } else { 1213 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1214 if (tmpReg & 1215 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1216 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1217 u32 val; 1218 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1219 1220 val = AR_RC_HOSTIF; 1221 if (!AR_SREV_9300_20_OR_LATER(ah)) 1222 val |= AR_RC_AHB; 1223 REG_WRITE(ah, AR_RC, val); 1224 1225 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1226 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1227 1228 rst_flags = AR_RTC_RC_MAC_WARM; 1229 if (type == ATH9K_RESET_COLD) 1230 rst_flags |= AR_RTC_RC_MAC_COLD; 1231 } 1232 1233 if (AR_SREV_9330(ah)) { 1234 int npend = 0; 1235 int i; 1236 1237 /* AR9330 WAR: 1238 * call external reset function to reset WMAC if: 1239 * - doing a cold reset 1240 * - we have pending frames in the TX queues 1241 */ 1242 1243 for (i = 0; i < AR_NUM_QCU; i++) { 1244 npend = ath9k_hw_numtxpending(ah, i); 1245 if (npend) 1246 break; 1247 } 1248 1249 if (ah->external_reset && 1250 (npend || type == ATH9K_RESET_COLD)) { 1251 int reset_err = 0; 1252 1253 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1254 "reset MAC via external reset\n"); 1255 1256 reset_err = ah->external_reset(); 1257 if (reset_err) { 1258 ath_err(ath9k_hw_common(ah), 1259 "External reset failed, err=%d\n", 1260 reset_err); 1261 return false; 1262 } 1263 1264 REG_WRITE(ah, AR_RTC_RESET, 1); 1265 } 1266 } 1267 1268 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1269 1270 REGWRITE_BUFFER_FLUSH(ah); 1271 1272 udelay(50); 1273 1274 REG_WRITE(ah, AR_RTC_RC, 0); 1275 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1276 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1277 "RTC stuck in MAC reset\n"); 1278 return false; 1279 } 1280 1281 if (!AR_SREV_9100(ah)) 1282 REG_WRITE(ah, AR_RC, 0); 1283 1284 if (AR_SREV_9100(ah)) 1285 udelay(50); 1286 1287 return true; 1288 } 1289 1290 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1291 { 1292 ENABLE_REGWRITE_BUFFER(ah); 1293 1294 if (AR_SREV_9300_20_OR_LATER(ah)) { 1295 REG_WRITE(ah, AR_WA, ah->WARegVal); 1296 udelay(10); 1297 } 1298 1299 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1300 AR_RTC_FORCE_WAKE_ON_INT); 1301 1302 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1303 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1304 1305 REG_WRITE(ah, AR_RTC_RESET, 0); 1306 1307 REGWRITE_BUFFER_FLUSH(ah); 1308 1309 if (!AR_SREV_9300_20_OR_LATER(ah)) 1310 udelay(2); 1311 1312 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1313 REG_WRITE(ah, AR_RC, 0); 1314 1315 REG_WRITE(ah, AR_RTC_RESET, 1); 1316 1317 if (!ath9k_hw_wait(ah, 1318 AR_RTC_STATUS, 1319 AR_RTC_STATUS_M, 1320 AR_RTC_STATUS_ON, 1321 AH_WAIT_TIMEOUT)) { 1322 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1323 "RTC not waking up\n"); 1324 return false; 1325 } 1326 1327 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1328 } 1329 1330 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1331 { 1332 if (AR_SREV_9300_20_OR_LATER(ah)) { 1333 REG_WRITE(ah, AR_WA, ah->WARegVal); 1334 udelay(10); 1335 } 1336 1337 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1338 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1339 1340 switch (type) { 1341 case ATH9K_RESET_POWER_ON: 1342 return ath9k_hw_set_reset_power_on(ah); 1343 case ATH9K_RESET_WARM: 1344 case ATH9K_RESET_COLD: 1345 return ath9k_hw_set_reset(ah, type); 1346 default: 1347 return false; 1348 } 1349 } 1350 1351 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1352 struct ath9k_channel *chan) 1353 { 1354 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1355 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1356 return false; 1357 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1358 return false; 1359 1360 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1361 return false; 1362 1363 ah->chip_fullsleep = false; 1364 ath9k_hw_init_pll(ah, chan); 1365 ath9k_hw_set_rfmode(ah, chan); 1366 1367 return true; 1368 } 1369 1370 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1371 struct ath9k_channel *chan) 1372 { 1373 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1374 struct ath_common *common = ath9k_hw_common(ah); 1375 struct ieee80211_channel *channel = chan->chan; 1376 u32 qnum; 1377 int r; 1378 1379 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1380 if (ath9k_hw_numtxpending(ah, qnum)) { 1381 ath_dbg(common, ATH_DBG_QUEUE, 1382 "Transmit frames pending on queue %d\n", qnum); 1383 return false; 1384 } 1385 } 1386 1387 if (!ath9k_hw_rfbus_req(ah)) { 1388 ath_err(common, "Could not kill baseband RX\n"); 1389 return false; 1390 } 1391 1392 ath9k_hw_set_channel_regs(ah, chan); 1393 1394 r = ath9k_hw_rf_set_freq(ah, chan); 1395 if (r) { 1396 ath_err(common, "Failed to set channel\n"); 1397 return false; 1398 } 1399 ath9k_hw_set_clockrate(ah); 1400 1401 ah->eep_ops->set_txpower(ah, chan, 1402 ath9k_regd_get_ctl(regulatory, chan), 1403 channel->max_antenna_gain * 2, 1404 channel->max_power * 2, 1405 min((u32) MAX_RATE_POWER, 1406 (u32) regulatory->power_limit), false); 1407 1408 ath9k_hw_rfbus_done(ah); 1409 1410 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1411 ath9k_hw_set_delta_slope(ah, chan); 1412 1413 ath9k_hw_spur_mitigate_freq(ah, chan); 1414 1415 return true; 1416 } 1417 1418 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1419 { 1420 u32 gpio_mask = ah->gpio_mask; 1421 int i; 1422 1423 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1424 if (!(gpio_mask & 1)) 1425 continue; 1426 1427 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1428 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1429 } 1430 } 1431 1432 bool ath9k_hw_check_alive(struct ath_hw *ah) 1433 { 1434 int count = 50; 1435 u32 reg; 1436 1437 if (AR_SREV_9285_12_OR_LATER(ah)) 1438 return true; 1439 1440 do { 1441 reg = REG_READ(ah, AR_OBS_BUS_1); 1442 1443 if ((reg & 0x7E7FFFEF) == 0x00702400) 1444 continue; 1445 1446 switch (reg & 0x7E000B00) { 1447 case 0x1E000000: 1448 case 0x52000B00: 1449 case 0x18000B00: 1450 continue; 1451 default: 1452 return true; 1453 } 1454 } while (count-- > 0); 1455 1456 return false; 1457 } 1458 EXPORT_SYMBOL(ath9k_hw_check_alive); 1459 1460 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1461 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1462 { 1463 struct ath_common *common = ath9k_hw_common(ah); 1464 u32 saveLedState; 1465 struct ath9k_channel *curchan = ah->curchan; 1466 u32 saveDefAntenna; 1467 u32 macStaId1; 1468 u64 tsf = 0; 1469 int i, r; 1470 1471 ah->txchainmask = common->tx_chainmask; 1472 ah->rxchainmask = common->rx_chainmask; 1473 1474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1475 return -EIO; 1476 1477 if (curchan && !ah->chip_fullsleep) 1478 ath9k_hw_getnf(ah, curchan); 1479 1480 ah->caldata = caldata; 1481 if (caldata && 1482 (chan->channel != caldata->channel || 1483 (chan->channelFlags & ~CHANNEL_CW_INT) != 1484 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1485 /* Operating channel changed, reset channel calibration data */ 1486 memset(caldata, 0, sizeof(*caldata)); 1487 ath9k_init_nfcal_hist_buffer(ah, chan); 1488 } 1489 1490 if (bChannelChange && 1491 (ah->chip_fullsleep != true) && 1492 (ah->curchan != NULL) && 1493 (chan->channel != ah->curchan->channel) && 1494 ((chan->channelFlags & CHANNEL_ALL) == 1495 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1496 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1497 1498 if (ath9k_hw_channel_change(ah, chan)) { 1499 ath9k_hw_loadnf(ah, ah->curchan); 1500 ath9k_hw_start_nfcal(ah, true); 1501 if (AR_SREV_9271(ah)) 1502 ar9002_hw_load_ani_reg(ah, chan); 1503 return 0; 1504 } 1505 } 1506 1507 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1508 if (saveDefAntenna == 0) 1509 saveDefAntenna = 1; 1510 1511 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1512 1513 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1514 if (AR_SREV_9100(ah) || 1515 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1516 tsf = ath9k_hw_gettsf64(ah); 1517 1518 saveLedState = REG_READ(ah, AR_CFG_LED) & 1519 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1520 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1521 1522 ath9k_hw_mark_phy_inactive(ah); 1523 1524 ah->paprd_table_write_done = false; 1525 1526 /* Only required on the first reset */ 1527 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1528 REG_WRITE(ah, 1529 AR9271_RESET_POWER_DOWN_CONTROL, 1530 AR9271_RADIO_RF_RST); 1531 udelay(50); 1532 } 1533 1534 if (!ath9k_hw_chip_reset(ah, chan)) { 1535 ath_err(common, "Chip reset failed\n"); 1536 return -EINVAL; 1537 } 1538 1539 /* Only required on the first reset */ 1540 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1541 ah->htc_reset_init = false; 1542 REG_WRITE(ah, 1543 AR9271_RESET_POWER_DOWN_CONTROL, 1544 AR9271_GATE_MAC_CTL); 1545 udelay(50); 1546 } 1547 1548 /* Restore TSF */ 1549 if (tsf) 1550 ath9k_hw_settsf64(ah, tsf); 1551 1552 if (AR_SREV_9280_20_OR_LATER(ah)) 1553 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1554 1555 if (!AR_SREV_9300_20_OR_LATER(ah)) 1556 ar9002_hw_enable_async_fifo(ah); 1557 1558 r = ath9k_hw_process_ini(ah, chan); 1559 if (r) 1560 return r; 1561 1562 /* 1563 * Some AR91xx SoC devices frequently fail to accept TSF writes 1564 * right after the chip reset. When that happens, write a new 1565 * value after the initvals have been applied, with an offset 1566 * based on measured time difference 1567 */ 1568 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1569 tsf += 1500; 1570 ath9k_hw_settsf64(ah, tsf); 1571 } 1572 1573 /* Setup MFP options for CCMP */ 1574 if (AR_SREV_9280_20_OR_LATER(ah)) { 1575 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1576 * frames when constructing CCMP AAD. */ 1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1578 0xc7ff); 1579 ah->sw_mgmt_crypto = false; 1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1581 /* Disable hardware crypto for management frames */ 1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1583 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1585 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1586 ah->sw_mgmt_crypto = true; 1587 } else 1588 ah->sw_mgmt_crypto = true; 1589 1590 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1591 ath9k_hw_set_delta_slope(ah, chan); 1592 1593 ath9k_hw_spur_mitigate_freq(ah, chan); 1594 ah->eep_ops->set_board_values(ah, chan); 1595 1596 ENABLE_REGWRITE_BUFFER(ah); 1597 1598 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1599 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1600 | macStaId1 1601 | AR_STA_ID1_RTS_USE_DEF 1602 | (ah->config. 1603 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1604 | ah->sta_id1_defaults); 1605 ath_hw_setbssidmask(common); 1606 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1607 ath9k_hw_write_associd(ah); 1608 REG_WRITE(ah, AR_ISR, ~0); 1609 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1610 1611 REGWRITE_BUFFER_FLUSH(ah); 1612 1613 ath9k_hw_set_operating_mode(ah, ah->opmode); 1614 1615 r = ath9k_hw_rf_set_freq(ah, chan); 1616 if (r) 1617 return r; 1618 1619 ath9k_hw_set_clockrate(ah); 1620 1621 ENABLE_REGWRITE_BUFFER(ah); 1622 1623 for (i = 0; i < AR_NUM_DCU; i++) 1624 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1625 1626 REGWRITE_BUFFER_FLUSH(ah); 1627 1628 ah->intr_txqs = 0; 1629 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1630 ath9k_hw_resettxqueue(ah, i); 1631 1632 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1633 ath9k_hw_ani_cache_ini_regs(ah); 1634 ath9k_hw_init_qos(ah); 1635 1636 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1637 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1638 1639 ath9k_hw_init_global_settings(ah); 1640 1641 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1642 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1643 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1644 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1645 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1646 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1647 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1648 } 1649 1650 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1651 1652 ath9k_hw_set_dma(ah); 1653 1654 REG_WRITE(ah, AR_OBS, 8); 1655 1656 if (ah->config.rx_intr_mitigation) { 1657 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1658 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1659 } 1660 1661 if (ah->config.tx_intr_mitigation) { 1662 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1663 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1664 } 1665 1666 ath9k_hw_init_bb(ah, chan); 1667 1668 if (!ath9k_hw_init_cal(ah, chan)) 1669 return -EIO; 1670 1671 ENABLE_REGWRITE_BUFFER(ah); 1672 1673 ath9k_hw_restore_chainmask(ah); 1674 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1675 1676 REGWRITE_BUFFER_FLUSH(ah); 1677 1678 /* 1679 * For big endian systems turn on swapping for descriptors 1680 */ 1681 if (AR_SREV_9100(ah)) { 1682 u32 mask; 1683 mask = REG_READ(ah, AR_CFG); 1684 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1685 ath_dbg(common, ATH_DBG_RESET, 1686 "CFG Byte Swap Set 0x%x\n", mask); 1687 } else { 1688 mask = 1689 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1690 REG_WRITE(ah, AR_CFG, mask); 1691 ath_dbg(common, ATH_DBG_RESET, 1692 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1693 } 1694 } else { 1695 if (common->bus_ops->ath_bus_type == ATH_USB) { 1696 /* Configure AR9271 target WLAN */ 1697 if (AR_SREV_9271(ah)) 1698 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1699 else 1700 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1701 } 1702 #ifdef __BIG_ENDIAN 1703 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1704 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1705 else 1706 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1707 #endif 1708 } 1709 1710 if (ah->btcoex_hw.enabled) 1711 ath9k_hw_btcoex_enable(ah); 1712 1713 if (AR_SREV_9300_20_OR_LATER(ah)) { 1714 ar9003_hw_bb_watchdog_config(ah); 1715 1716 ar9003_hw_disable_phy_restart(ah); 1717 } 1718 1719 ath9k_hw_apply_gpio_override(ah); 1720 1721 return 0; 1722 } 1723 EXPORT_SYMBOL(ath9k_hw_reset); 1724 1725 /******************************/ 1726 /* Power Management (Chipset) */ 1727 /******************************/ 1728 1729 /* 1730 * Notify Power Mgt is disabled in self-generated frames. 1731 * If requested, force chip to sleep. 1732 */ 1733 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1734 { 1735 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1736 if (setChip) { 1737 /* 1738 * Clear the RTC force wake bit to allow the 1739 * mac to go to sleep. 1740 */ 1741 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1742 AR_RTC_FORCE_WAKE_EN); 1743 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1744 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1745 1746 /* Shutdown chip. Active low */ 1747 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1748 REG_CLR_BIT(ah, (AR_RTC_RESET), 1749 AR_RTC_RESET_EN); 1750 } 1751 1752 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1753 if (AR_SREV_9300_20_OR_LATER(ah)) 1754 REG_WRITE(ah, AR_WA, 1755 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1756 } 1757 1758 /* 1759 * Notify Power Management is enabled in self-generating 1760 * frames. If request, set power mode of chip to 1761 * auto/normal. Duration in units of 128us (1/8 TU). 1762 */ 1763 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1764 { 1765 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1766 if (setChip) { 1767 struct ath9k_hw_capabilities *pCap = &ah->caps; 1768 1769 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1770 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1771 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1772 AR_RTC_FORCE_WAKE_ON_INT); 1773 } else { 1774 /* 1775 * Clear the RTC force wake bit to allow the 1776 * mac to go to sleep. 1777 */ 1778 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1779 AR_RTC_FORCE_WAKE_EN); 1780 } 1781 } 1782 1783 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1784 if (AR_SREV_9300_20_OR_LATER(ah)) 1785 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1786 } 1787 1788 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1789 { 1790 u32 val; 1791 int i; 1792 1793 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1794 if (AR_SREV_9300_20_OR_LATER(ah)) { 1795 REG_WRITE(ah, AR_WA, ah->WARegVal); 1796 udelay(10); 1797 } 1798 1799 if (setChip) { 1800 if ((REG_READ(ah, AR_RTC_STATUS) & 1801 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1802 if (ath9k_hw_set_reset_reg(ah, 1803 ATH9K_RESET_POWER_ON) != true) { 1804 return false; 1805 } 1806 if (!AR_SREV_9300_20_OR_LATER(ah)) 1807 ath9k_hw_init_pll(ah, NULL); 1808 } 1809 if (AR_SREV_9100(ah)) 1810 REG_SET_BIT(ah, AR_RTC_RESET, 1811 AR_RTC_RESET_EN); 1812 1813 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1814 AR_RTC_FORCE_WAKE_EN); 1815 udelay(50); 1816 1817 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1818 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1819 if (val == AR_RTC_STATUS_ON) 1820 break; 1821 udelay(50); 1822 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1823 AR_RTC_FORCE_WAKE_EN); 1824 } 1825 if (i == 0) { 1826 ath_err(ath9k_hw_common(ah), 1827 "Failed to wakeup in %uus\n", 1828 POWER_UP_TIME / 20); 1829 return false; 1830 } 1831 } 1832 1833 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1834 1835 return true; 1836 } 1837 1838 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1839 { 1840 struct ath_common *common = ath9k_hw_common(ah); 1841 int status = true, setChip = true; 1842 static const char *modes[] = { 1843 "AWAKE", 1844 "FULL-SLEEP", 1845 "NETWORK SLEEP", 1846 "UNDEFINED" 1847 }; 1848 1849 if (ah->power_mode == mode) 1850 return status; 1851 1852 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1853 modes[ah->power_mode], modes[mode]); 1854 1855 switch (mode) { 1856 case ATH9K_PM_AWAKE: 1857 status = ath9k_hw_set_power_awake(ah, setChip); 1858 break; 1859 case ATH9K_PM_FULL_SLEEP: 1860 ath9k_set_power_sleep(ah, setChip); 1861 ah->chip_fullsleep = true; 1862 break; 1863 case ATH9K_PM_NETWORK_SLEEP: 1864 ath9k_set_power_network_sleep(ah, setChip); 1865 break; 1866 default: 1867 ath_err(common, "Unknown power mode %u\n", mode); 1868 return false; 1869 } 1870 ah->power_mode = mode; 1871 1872 /* 1873 * XXX: If this warning never comes up after a while then 1874 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1875 * ath9k_hw_setpower() return type void. 1876 */ 1877 1878 if (!(ah->ah_flags & AH_UNPLUGGED)) 1879 ATH_DBG_WARN_ON_ONCE(!status); 1880 1881 return status; 1882 } 1883 EXPORT_SYMBOL(ath9k_hw_setpower); 1884 1885 /*******************/ 1886 /* Beacon Handling */ 1887 /*******************/ 1888 1889 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1890 { 1891 int flags = 0; 1892 1893 ENABLE_REGWRITE_BUFFER(ah); 1894 1895 switch (ah->opmode) { 1896 case NL80211_IFTYPE_ADHOC: 1897 case NL80211_IFTYPE_MESH_POINT: 1898 REG_SET_BIT(ah, AR_TXCFG, 1899 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1900 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 1901 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 1902 flags |= AR_NDP_TIMER_EN; 1903 case NL80211_IFTYPE_AP: 1904 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 1905 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 1906 TU_TO_USEC(ah->config.dma_beacon_response_time)); 1907 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 1908 TU_TO_USEC(ah->config.sw_beacon_response_time)); 1909 flags |= 1910 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1911 break; 1912 default: 1913 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1914 "%s: unsupported opmode: %d\n", 1915 __func__, ah->opmode); 1916 return; 1917 break; 1918 } 1919 1920 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 1921 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 1922 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 1923 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 1924 1925 REGWRITE_BUFFER_FLUSH(ah); 1926 1927 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1928 } 1929 EXPORT_SYMBOL(ath9k_hw_beaconinit); 1930 1931 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1932 const struct ath9k_beacon_state *bs) 1933 { 1934 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1935 struct ath9k_hw_capabilities *pCap = &ah->caps; 1936 struct ath_common *common = ath9k_hw_common(ah); 1937 1938 ENABLE_REGWRITE_BUFFER(ah); 1939 1940 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1941 1942 REG_WRITE(ah, AR_BEACON_PERIOD, 1943 TU_TO_USEC(bs->bs_intval)); 1944 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1945 TU_TO_USEC(bs->bs_intval)); 1946 1947 REGWRITE_BUFFER_FLUSH(ah); 1948 1949 REG_RMW_FIELD(ah, AR_RSSI_THR, 1950 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1951 1952 beaconintval = bs->bs_intval; 1953 1954 if (bs->bs_sleepduration > beaconintval) 1955 beaconintval = bs->bs_sleepduration; 1956 1957 dtimperiod = bs->bs_dtimperiod; 1958 if (bs->bs_sleepduration > dtimperiod) 1959 dtimperiod = bs->bs_sleepduration; 1960 1961 if (beaconintval == dtimperiod) 1962 nextTbtt = bs->bs_nextdtim; 1963 else 1964 nextTbtt = bs->bs_nexttbtt; 1965 1966 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1967 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1968 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1969 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1970 1971 ENABLE_REGWRITE_BUFFER(ah); 1972 1973 REG_WRITE(ah, AR_NEXT_DTIM, 1974 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1975 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1976 1977 REG_WRITE(ah, AR_SLEEP1, 1978 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1979 | AR_SLEEP1_ASSUME_DTIM); 1980 1981 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1982 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1983 else 1984 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1985 1986 REG_WRITE(ah, AR_SLEEP2, 1987 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1988 1989 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1990 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1991 1992 REGWRITE_BUFFER_FLUSH(ah); 1993 1994 REG_SET_BIT(ah, AR_TIMER_MODE, 1995 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1996 AR_DTIM_TIMER_EN); 1997 1998 /* TSF Out of Range Threshold */ 1999 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2000 } 2001 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2002 2003 /*******************/ 2004 /* HW Capabilities */ 2005 /*******************/ 2006 2007 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2008 { 2009 eeprom_chainmask &= chip_chainmask; 2010 if (eeprom_chainmask) 2011 return eeprom_chainmask; 2012 else 2013 return chip_chainmask; 2014 } 2015 2016 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2017 { 2018 struct ath9k_hw_capabilities *pCap = &ah->caps; 2019 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2020 struct ath_common *common = ath9k_hw_common(ah); 2021 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2022 unsigned int chip_chainmask; 2023 2024 u16 eeval; 2025 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2026 2027 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2028 regulatory->current_rd = eeval; 2029 2030 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 2031 if (AR_SREV_9285_12_OR_LATER(ah)) 2032 eeval |= AR9285_RDEXT_DEFAULT; 2033 regulatory->current_rd_ext = eeval; 2034 2035 if (ah->opmode != NL80211_IFTYPE_AP && 2036 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2037 if (regulatory->current_rd == 0x64 || 2038 regulatory->current_rd == 0x65) 2039 regulatory->current_rd += 5; 2040 else if (regulatory->current_rd == 0x41) 2041 regulatory->current_rd = 0x43; 2042 ath_dbg(common, ATH_DBG_REGULATORY, 2043 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2044 } 2045 2046 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2047 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2048 ath_err(common, 2049 "no band has been marked as supported in EEPROM\n"); 2050 return -EINVAL; 2051 } 2052 2053 if (eeval & AR5416_OPFLAGS_11A) 2054 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2055 2056 if (eeval & AR5416_OPFLAGS_11G) 2057 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2058 2059 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2060 chip_chainmask = 1; 2061 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2062 chip_chainmask = 7; 2063 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2064 chip_chainmask = 3; 2065 else 2066 chip_chainmask = 7; 2067 2068 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2069 /* 2070 * For AR9271 we will temporarilly uses the rx chainmax as read from 2071 * the EEPROM. 2072 */ 2073 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2074 !(eeval & AR5416_OPFLAGS_11A) && 2075 !(AR_SREV_9271(ah))) 2076 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2077 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2078 else if (AR_SREV_9100(ah)) 2079 pCap->rx_chainmask = 0x7; 2080 else 2081 /* Use rx_chainmask from EEPROM. */ 2082 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2083 2084 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2085 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2086 2087 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2088 2089 /* enable key search for every frame in an aggregate */ 2090 if (AR_SREV_9300_20_OR_LATER(ah)) 2091 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2092 2093 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2094 2095 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2096 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2097 else 2098 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2099 2100 if (AR_SREV_9271(ah)) 2101 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2102 else if (AR_DEVID_7010(ah)) 2103 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2104 else if (AR_SREV_9285_12_OR_LATER(ah)) 2105 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2106 else if (AR_SREV_9280_20_OR_LATER(ah)) 2107 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2108 else 2109 pCap->num_gpio_pins = AR_NUM_GPIO; 2110 2111 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2112 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2113 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2114 } else { 2115 pCap->rts_aggr_limit = (8 * 1024); 2116 } 2117 2118 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2119 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2120 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2121 ah->rfkill_gpio = 2122 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2123 ah->rfkill_polarity = 2124 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2125 2126 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2127 } 2128 #endif 2129 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2130 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2131 else 2132 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2133 2134 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2135 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2136 else 2137 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2138 2139 if (common->btcoex_enabled) { 2140 if (AR_SREV_9300_20_OR_LATER(ah)) { 2141 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2142 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 2143 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 2144 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 2145 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 2146 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 2147 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 2148 2149 if (AR_SREV_9285(ah)) { 2150 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2151 btcoex_hw->btpriority_gpio = 2152 ATH_BTPRIORITY_GPIO_9285; 2153 } else { 2154 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2155 } 2156 } 2157 } else { 2158 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2159 } 2160 2161 if (AR_SREV_9300_20_OR_LATER(ah)) { 2162 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2163 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2164 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2165 2166 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2167 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2168 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2169 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2170 pCap->txs_len = sizeof(struct ar9003_txs); 2171 if (!ah->config.paprd_disable && 2172 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2173 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2174 } else { 2175 pCap->tx_desc_len = sizeof(struct ath_desc); 2176 if (AR_SREV_9280_20(ah)) 2177 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2178 } 2179 2180 if (AR_SREV_9300_20_OR_LATER(ah)) 2181 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2182 2183 if (AR_SREV_9300_20_OR_LATER(ah)) 2184 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2185 2186 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2187 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2188 2189 if (AR_SREV_9285(ah)) 2190 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2191 ant_div_ctl1 = 2192 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2193 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2194 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2195 } 2196 if (AR_SREV_9300_20_OR_LATER(ah)) { 2197 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2198 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2199 } 2200 2201 2202 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2203 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2204 /* 2205 * enable the diversity-combining algorithm only when 2206 * both enable_lna_div and enable_fast_div are set 2207 * Table for Diversity 2208 * ant_div_alt_lnaconf bit 0-1 2209 * ant_div_main_lnaconf bit 2-3 2210 * ant_div_alt_gaintb bit 4 2211 * ant_div_main_gaintb bit 5 2212 * enable_ant_div_lnadiv bit 6 2213 * enable_ant_fast_div bit 7 2214 */ 2215 if ((ant_div_ctl1 >> 0x6) == 0x3) 2216 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2217 } 2218 2219 if (AR_SREV_9485_10(ah)) { 2220 pCap->pcie_lcr_extsync_en = true; 2221 pCap->pcie_lcr_offset = 0x80; 2222 } 2223 2224 tx_chainmask = pCap->tx_chainmask; 2225 rx_chainmask = pCap->rx_chainmask; 2226 while (tx_chainmask || rx_chainmask) { 2227 if (tx_chainmask & BIT(0)) 2228 pCap->max_txchains++; 2229 if (rx_chainmask & BIT(0)) 2230 pCap->max_rxchains++; 2231 2232 tx_chainmask >>= 1; 2233 rx_chainmask >>= 1; 2234 } 2235 2236 return 0; 2237 } 2238 2239 /****************************/ 2240 /* GPIO / RFKILL / Antennae */ 2241 /****************************/ 2242 2243 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2244 u32 gpio, u32 type) 2245 { 2246 int addr; 2247 u32 gpio_shift, tmp; 2248 2249 if (gpio > 11) 2250 addr = AR_GPIO_OUTPUT_MUX3; 2251 else if (gpio > 5) 2252 addr = AR_GPIO_OUTPUT_MUX2; 2253 else 2254 addr = AR_GPIO_OUTPUT_MUX1; 2255 2256 gpio_shift = (gpio % 6) * 5; 2257 2258 if (AR_SREV_9280_20_OR_LATER(ah) 2259 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2260 REG_RMW(ah, addr, (type << gpio_shift), 2261 (0x1f << gpio_shift)); 2262 } else { 2263 tmp = REG_READ(ah, addr); 2264 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2265 tmp &= ~(0x1f << gpio_shift); 2266 tmp |= (type << gpio_shift); 2267 REG_WRITE(ah, addr, tmp); 2268 } 2269 } 2270 2271 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2272 { 2273 u32 gpio_shift; 2274 2275 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2276 2277 if (AR_DEVID_7010(ah)) { 2278 gpio_shift = gpio; 2279 REG_RMW(ah, AR7010_GPIO_OE, 2280 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2281 (AR7010_GPIO_OE_MASK << gpio_shift)); 2282 return; 2283 } 2284 2285 gpio_shift = gpio << 1; 2286 REG_RMW(ah, 2287 AR_GPIO_OE_OUT, 2288 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2289 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2290 } 2291 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2292 2293 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2294 { 2295 #define MS_REG_READ(x, y) \ 2296 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2297 2298 if (gpio >= ah->caps.num_gpio_pins) 2299 return 0xffffffff; 2300 2301 if (AR_DEVID_7010(ah)) { 2302 u32 val; 2303 val = REG_READ(ah, AR7010_GPIO_IN); 2304 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2305 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2306 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2307 AR_GPIO_BIT(gpio)) != 0; 2308 else if (AR_SREV_9271(ah)) 2309 return MS_REG_READ(AR9271, gpio) != 0; 2310 else if (AR_SREV_9287_11_OR_LATER(ah)) 2311 return MS_REG_READ(AR9287, gpio) != 0; 2312 else if (AR_SREV_9285_12_OR_LATER(ah)) 2313 return MS_REG_READ(AR9285, gpio) != 0; 2314 else if (AR_SREV_9280_20_OR_LATER(ah)) 2315 return MS_REG_READ(AR928X, gpio) != 0; 2316 else 2317 return MS_REG_READ(AR, gpio) != 0; 2318 } 2319 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2320 2321 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2322 u32 ah_signal_type) 2323 { 2324 u32 gpio_shift; 2325 2326 if (AR_DEVID_7010(ah)) { 2327 gpio_shift = gpio; 2328 REG_RMW(ah, AR7010_GPIO_OE, 2329 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2330 (AR7010_GPIO_OE_MASK << gpio_shift)); 2331 return; 2332 } 2333 2334 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2335 gpio_shift = 2 * gpio; 2336 REG_RMW(ah, 2337 AR_GPIO_OE_OUT, 2338 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2339 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2340 } 2341 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2342 2343 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2344 { 2345 if (AR_DEVID_7010(ah)) { 2346 val = val ? 0 : 1; 2347 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2348 AR_GPIO_BIT(gpio)); 2349 return; 2350 } 2351 2352 if (AR_SREV_9271(ah)) 2353 val = ~val; 2354 2355 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2356 AR_GPIO_BIT(gpio)); 2357 } 2358 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2359 2360 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2361 { 2362 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2363 } 2364 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2365 2366 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2367 { 2368 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2369 } 2370 EXPORT_SYMBOL(ath9k_hw_setantenna); 2371 2372 /*********************/ 2373 /* General Operation */ 2374 /*********************/ 2375 2376 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2377 { 2378 u32 bits = REG_READ(ah, AR_RX_FILTER); 2379 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2380 2381 if (phybits & AR_PHY_ERR_RADAR) 2382 bits |= ATH9K_RX_FILTER_PHYRADAR; 2383 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2384 bits |= ATH9K_RX_FILTER_PHYERR; 2385 2386 return bits; 2387 } 2388 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2389 2390 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2391 { 2392 u32 phybits; 2393 2394 ENABLE_REGWRITE_BUFFER(ah); 2395 2396 REG_WRITE(ah, AR_RX_FILTER, bits); 2397 2398 phybits = 0; 2399 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2400 phybits |= AR_PHY_ERR_RADAR; 2401 if (bits & ATH9K_RX_FILTER_PHYERR) 2402 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2403 REG_WRITE(ah, AR_PHY_ERR, phybits); 2404 2405 if (phybits) 2406 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2407 else 2408 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2409 2410 REGWRITE_BUFFER_FLUSH(ah); 2411 } 2412 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2413 2414 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2415 { 2416 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2417 return false; 2418 2419 ath9k_hw_init_pll(ah, NULL); 2420 return true; 2421 } 2422 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2423 2424 bool ath9k_hw_disable(struct ath_hw *ah) 2425 { 2426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2427 return false; 2428 2429 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2430 return false; 2431 2432 ath9k_hw_init_pll(ah, NULL); 2433 return true; 2434 } 2435 EXPORT_SYMBOL(ath9k_hw_disable); 2436 2437 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2438 { 2439 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2440 struct ath9k_channel *chan = ah->curchan; 2441 struct ieee80211_channel *channel = chan->chan; 2442 2443 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2444 2445 ah->eep_ops->set_txpower(ah, chan, 2446 ath9k_regd_get_ctl(regulatory, chan), 2447 channel->max_antenna_gain * 2, 2448 channel->max_power * 2, 2449 min((u32) MAX_RATE_POWER, 2450 (u32) regulatory->power_limit), test); 2451 } 2452 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2453 2454 void ath9k_hw_setopmode(struct ath_hw *ah) 2455 { 2456 ath9k_hw_set_operating_mode(ah, ah->opmode); 2457 } 2458 EXPORT_SYMBOL(ath9k_hw_setopmode); 2459 2460 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2461 { 2462 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2463 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2464 } 2465 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2466 2467 void ath9k_hw_write_associd(struct ath_hw *ah) 2468 { 2469 struct ath_common *common = ath9k_hw_common(ah); 2470 2471 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2472 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2473 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2474 } 2475 EXPORT_SYMBOL(ath9k_hw_write_associd); 2476 2477 #define ATH9K_MAX_TSF_READ 10 2478 2479 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2480 { 2481 u32 tsf_lower, tsf_upper1, tsf_upper2; 2482 int i; 2483 2484 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2485 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2486 tsf_lower = REG_READ(ah, AR_TSF_L32); 2487 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2488 if (tsf_upper2 == tsf_upper1) 2489 break; 2490 tsf_upper1 = tsf_upper2; 2491 } 2492 2493 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2494 2495 return (((u64)tsf_upper1 << 32) | tsf_lower); 2496 } 2497 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2498 2499 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2500 { 2501 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2502 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2503 } 2504 EXPORT_SYMBOL(ath9k_hw_settsf64); 2505 2506 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2507 { 2508 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2509 AH_TSF_WRITE_TIMEOUT)) 2510 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2511 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2512 2513 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2514 } 2515 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2516 2517 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2518 { 2519 if (setting) 2520 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2521 else 2522 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2523 } 2524 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2525 2526 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2527 { 2528 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2529 u32 macmode; 2530 2531 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2532 macmode = AR_2040_JOINED_RX_CLEAR; 2533 else 2534 macmode = 0; 2535 2536 REG_WRITE(ah, AR_2040_MODE, macmode); 2537 } 2538 2539 /* HW Generic timers configuration */ 2540 2541 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2542 { 2543 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2544 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2545 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2546 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2547 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2548 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2549 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2550 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2551 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2552 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2553 AR_NDP2_TIMER_MODE, 0x0002}, 2554 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2555 AR_NDP2_TIMER_MODE, 0x0004}, 2556 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2557 AR_NDP2_TIMER_MODE, 0x0008}, 2558 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2559 AR_NDP2_TIMER_MODE, 0x0010}, 2560 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2561 AR_NDP2_TIMER_MODE, 0x0020}, 2562 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2563 AR_NDP2_TIMER_MODE, 0x0040}, 2564 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2565 AR_NDP2_TIMER_MODE, 0x0080} 2566 }; 2567 2568 /* HW generic timer primitives */ 2569 2570 /* compute and clear index of rightmost 1 */ 2571 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2572 { 2573 u32 b; 2574 2575 b = *mask; 2576 b &= (0-b); 2577 *mask &= ~b; 2578 b *= debruijn32; 2579 b >>= 27; 2580 2581 return timer_table->gen_timer_index[b]; 2582 } 2583 2584 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2585 { 2586 return REG_READ(ah, AR_TSF_L32); 2587 } 2588 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2589 2590 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2591 void (*trigger)(void *), 2592 void (*overflow)(void *), 2593 void *arg, 2594 u8 timer_index) 2595 { 2596 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2597 struct ath_gen_timer *timer; 2598 2599 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2600 2601 if (timer == NULL) { 2602 ath_err(ath9k_hw_common(ah), 2603 "Failed to allocate memory for hw timer[%d]\n", 2604 timer_index); 2605 return NULL; 2606 } 2607 2608 /* allocate a hardware generic timer slot */ 2609 timer_table->timers[timer_index] = timer; 2610 timer->index = timer_index; 2611 timer->trigger = trigger; 2612 timer->overflow = overflow; 2613 timer->arg = arg; 2614 2615 return timer; 2616 } 2617 EXPORT_SYMBOL(ath_gen_timer_alloc); 2618 2619 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2620 struct ath_gen_timer *timer, 2621 u32 trig_timeout, 2622 u32 timer_period) 2623 { 2624 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2625 u32 tsf, timer_next; 2626 2627 BUG_ON(!timer_period); 2628 2629 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2630 2631 tsf = ath9k_hw_gettsf32(ah); 2632 2633 timer_next = tsf + trig_timeout; 2634 2635 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2636 "current tsf %x period %x timer_next %x\n", 2637 tsf, timer_period, timer_next); 2638 2639 /* 2640 * Program generic timer registers 2641 */ 2642 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2643 timer_next); 2644 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2645 timer_period); 2646 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2647 gen_tmr_configuration[timer->index].mode_mask); 2648 2649 /* Enable both trigger and thresh interrupt masks */ 2650 REG_SET_BIT(ah, AR_IMR_S5, 2651 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2652 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2653 } 2654 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2655 2656 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2657 { 2658 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2659 2660 if ((timer->index < AR_FIRST_NDP_TIMER) || 2661 (timer->index >= ATH_MAX_GEN_TIMER)) { 2662 return; 2663 } 2664 2665 /* Clear generic timer enable bits. */ 2666 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2667 gen_tmr_configuration[timer->index].mode_mask); 2668 2669 /* Disable both trigger and thresh interrupt masks */ 2670 REG_CLR_BIT(ah, AR_IMR_S5, 2671 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2672 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2673 2674 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2675 } 2676 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2677 2678 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2679 { 2680 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2681 2682 /* free the hardware generic timer slot */ 2683 timer_table->timers[timer->index] = NULL; 2684 kfree(timer); 2685 } 2686 EXPORT_SYMBOL(ath_gen_timer_free); 2687 2688 /* 2689 * Generic Timer Interrupts handling 2690 */ 2691 void ath_gen_timer_isr(struct ath_hw *ah) 2692 { 2693 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2694 struct ath_gen_timer *timer; 2695 struct ath_common *common = ath9k_hw_common(ah); 2696 u32 trigger_mask, thresh_mask, index; 2697 2698 /* get hardware generic timer interrupt status */ 2699 trigger_mask = ah->intr_gen_timer_trigger; 2700 thresh_mask = ah->intr_gen_timer_thresh; 2701 trigger_mask &= timer_table->timer_mask.val; 2702 thresh_mask &= timer_table->timer_mask.val; 2703 2704 trigger_mask &= ~thresh_mask; 2705 2706 while (thresh_mask) { 2707 index = rightmost_index(timer_table, &thresh_mask); 2708 timer = timer_table->timers[index]; 2709 BUG_ON(!timer); 2710 ath_dbg(common, ATH_DBG_HWTIMER, 2711 "TSF overflow for Gen timer %d\n", index); 2712 timer->overflow(timer->arg); 2713 } 2714 2715 while (trigger_mask) { 2716 index = rightmost_index(timer_table, &trigger_mask); 2717 timer = timer_table->timers[index]; 2718 BUG_ON(!timer); 2719 ath_dbg(common, ATH_DBG_HWTIMER, 2720 "Gen timer[%d] trigger\n", index); 2721 timer->trigger(timer->arg); 2722 } 2723 } 2724 EXPORT_SYMBOL(ath_gen_timer_isr); 2725 2726 /********/ 2727 /* HTC */ 2728 /********/ 2729 2730 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2731 { 2732 ah->htc_reset_init = true; 2733 } 2734 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2735 2736 static struct { 2737 u32 version; 2738 const char * name; 2739 } ath_mac_bb_names[] = { 2740 /* Devices with external radios */ 2741 { AR_SREV_VERSION_5416_PCI, "5416" }, 2742 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2743 { AR_SREV_VERSION_9100, "9100" }, 2744 { AR_SREV_VERSION_9160, "9160" }, 2745 /* Single-chip solutions */ 2746 { AR_SREV_VERSION_9280, "9280" }, 2747 { AR_SREV_VERSION_9285, "9285" }, 2748 { AR_SREV_VERSION_9287, "9287" }, 2749 { AR_SREV_VERSION_9271, "9271" }, 2750 { AR_SREV_VERSION_9300, "9300" }, 2751 { AR_SREV_VERSION_9330, "9330" }, 2752 { AR_SREV_VERSION_9485, "9485" }, 2753 }; 2754 2755 /* For devices with external radios */ 2756 static struct { 2757 u16 version; 2758 const char * name; 2759 } ath_rf_names[] = { 2760 { 0, "5133" }, 2761 { AR_RAD5133_SREV_MAJOR, "5133" }, 2762 { AR_RAD5122_SREV_MAJOR, "5122" }, 2763 { AR_RAD2133_SREV_MAJOR, "2133" }, 2764 { AR_RAD2122_SREV_MAJOR, "2122" } 2765 }; 2766 2767 /* 2768 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2769 */ 2770 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2771 { 2772 int i; 2773 2774 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2775 if (ath_mac_bb_names[i].version == mac_bb_version) { 2776 return ath_mac_bb_names[i].name; 2777 } 2778 } 2779 2780 return "????"; 2781 } 2782 2783 /* 2784 * Return the RF name. "????" is returned if the RF is unknown. 2785 * Used for devices with external radios. 2786 */ 2787 static const char *ath9k_hw_rf_name(u16 rf_version) 2788 { 2789 int i; 2790 2791 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2792 if (ath_rf_names[i].version == rf_version) { 2793 return ath_rf_names[i].name; 2794 } 2795 } 2796 2797 return "????"; 2798 } 2799 2800 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2801 { 2802 int used; 2803 2804 /* chipsets >= AR9280 are single-chip */ 2805 if (AR_SREV_9280_20_OR_LATER(ah)) { 2806 used = snprintf(hw_name, len, 2807 "Atheros AR%s Rev:%x", 2808 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2809 ah->hw_version.macRev); 2810 } 2811 else { 2812 used = snprintf(hw_name, len, 2813 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2814 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2815 ah->hw_version.macRev, 2816 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2817 AR_RADIO_SREV_MAJOR)), 2818 ah->hw_version.phyRev); 2819 } 2820 2821 hw_name[used] = '\0'; 2822 } 2823 EXPORT_SYMBOL(ath9k_hw_name); 2824