1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <asm/unaligned.h> 24 25 #include "hw.h" 26 #include "hw-ops.h" 27 #include "ar9003_mac.h" 28 #include "ar9003_mci.h" 29 #include "ar9003_phy.h" 30 #include "ath9k.h" 31 32 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 33 34 MODULE_AUTHOR("Atheros Communications"); 35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 37 MODULE_LICENSE("Dual BSD/GPL"); 38 39 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 40 { 41 struct ath_common *common = ath9k_hw_common(ah); 42 struct ath9k_channel *chan = ah->curchan; 43 unsigned int clockrate; 44 45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 47 clockrate = 117; 48 else if (!chan) /* should really check for CCK instead */ 49 clockrate = ATH9K_CLOCK_RATE_CCK; 50 else if (IS_CHAN_2GHZ(chan)) 51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 54 else 55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 56 57 if (chan) { 58 if (IS_CHAN_HT40(chan)) 59 clockrate *= 2; 60 if (IS_CHAN_HALF_RATE(chan)) 61 clockrate /= 2; 62 if (IS_CHAN_QUARTER_RATE(chan)) 63 clockrate /= 4; 64 } 65 66 common->clockrate = clockrate; 67 } 68 69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 70 { 71 struct ath_common *common = ath9k_hw_common(ah); 72 73 return usecs * common->clockrate; 74 } 75 76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 77 { 78 int i; 79 80 BUG_ON(timeout < AH_TIME_QUANTUM); 81 82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 83 if ((REG_READ(ah, reg) & mask) == val) 84 return true; 85 86 udelay(AH_TIME_QUANTUM); 87 } 88 89 ath_dbg(ath9k_hw_common(ah), ANY, 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 91 timeout, reg, REG_READ(ah, reg), mask, val); 92 93 return false; 94 } 95 EXPORT_SYMBOL(ath9k_hw_wait); 96 97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 98 int hw_delay) 99 { 100 hw_delay /= 10; 101 102 if (IS_CHAN_HALF_RATE(chan)) 103 hw_delay *= 2; 104 else if (IS_CHAN_QUARTER_RATE(chan)) 105 hw_delay *= 4; 106 107 udelay(hw_delay + BASE_ACTIVATE_DELAY); 108 } 109 110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 111 int column, unsigned int *writecnt) 112 { 113 int r; 114 115 ENABLE_REGWRITE_BUFFER(ah); 116 for (r = 0; r < array->ia_rows; r++) { 117 REG_WRITE(ah, INI_RA(array, r, 0), 118 INI_RA(array, r, column)); 119 DO_DELAY(*writecnt); 120 } 121 REGWRITE_BUFFER_FLUSH(ah); 122 } 123 124 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 125 { 126 u32 retval; 127 int i; 128 129 for (i = 0, retval = 0; i < n; i++) { 130 retval = (retval << 1) | (val & 1); 131 val >>= 1; 132 } 133 return retval; 134 } 135 136 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 137 u8 phy, int kbps, 138 u32 frameLen, u16 rateix, 139 bool shortPreamble) 140 { 141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 142 143 if (kbps == 0) 144 return 0; 145 146 switch (phy) { 147 case WLAN_RC_PHY_CCK: 148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 149 if (shortPreamble) 150 phyTime >>= 1; 151 numBits = frameLen << 3; 152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 153 break; 154 case WLAN_RC_PHY_OFDM: 155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 157 numBits = OFDM_PLCP_BITS + (frameLen << 3); 158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 159 txTime = OFDM_SIFS_TIME_QUARTER 160 + OFDM_PREAMBLE_TIME_QUARTER 161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 162 } else if (ah->curchan && 163 IS_CHAN_HALF_RATE(ah->curchan)) { 164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 165 numBits = OFDM_PLCP_BITS + (frameLen << 3); 166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 167 txTime = OFDM_SIFS_TIME_HALF + 168 OFDM_PREAMBLE_TIME_HALF 169 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 170 } else { 171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 172 numBits = OFDM_PLCP_BITS + (frameLen << 3); 173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 175 + (numSymbols * OFDM_SYMBOL_TIME); 176 } 177 break; 178 default: 179 ath_err(ath9k_hw_common(ah), 180 "Unknown phy %u (rate ix %u)\n", phy, rateix); 181 txTime = 0; 182 break; 183 } 184 185 return txTime; 186 } 187 EXPORT_SYMBOL(ath9k_hw_computetxtime); 188 189 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 190 struct ath9k_channel *chan, 191 struct chan_centers *centers) 192 { 193 int8_t extoff; 194 195 if (!IS_CHAN_HT40(chan)) { 196 centers->ctl_center = centers->ext_center = 197 centers->synth_center = chan->channel; 198 return; 199 } 200 201 if (IS_CHAN_HT40PLUS(chan)) { 202 centers->synth_center = 203 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 204 extoff = 1; 205 } else { 206 centers->synth_center = 207 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 208 extoff = -1; 209 } 210 211 centers->ctl_center = 212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 213 /* 25 MHz spacing is supported by hw but not on upper layers */ 214 centers->ext_center = 215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 } 217 218 /******************/ 219 /* Chip Revisions */ 220 /******************/ 221 222 static void ath9k_hw_read_revisions(struct ath_hw *ah) 223 { 224 u32 val; 225 226 if (ah->get_mac_revision) 227 ah->hw_version.macRev = ah->get_mac_revision(); 228 229 switch (ah->hw_version.devid) { 230 case AR5416_AR9100_DEVID: 231 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 232 break; 233 case AR9300_DEVID_AR9330: 234 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 235 if (!ah->get_mac_revision) { 236 val = REG_READ(ah, AR_SREV); 237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 238 } 239 return; 240 case AR9300_DEVID_AR9340: 241 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 242 return; 243 case AR9300_DEVID_QCA955X: 244 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 245 return; 246 case AR9300_DEVID_AR953X: 247 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 248 return; 249 case AR9300_DEVID_QCA956X: 250 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 251 } 252 253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 254 255 if (val == 0xFF) { 256 val = REG_READ(ah, AR_SREV); 257 ah->hw_version.macVersion = 258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 260 261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 262 ah->is_pciexpress = true; 263 else 264 ah->is_pciexpress = (val & 265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 266 } else { 267 if (!AR_SREV_9100(ah)) 268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 269 270 ah->hw_version.macRev = val & AR_SREV_REVISION; 271 272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 273 ah->is_pciexpress = true; 274 } 275 } 276 277 /************************************/ 278 /* HW Attach, Detach, Init Routines */ 279 /************************************/ 280 281 static void ath9k_hw_disablepcie(struct ath_hw *ah) 282 { 283 if (!AR_SREV_5416(ah)) 284 return; 285 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 295 296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 297 } 298 299 /* This should work for all families including legacy */ 300 static bool ath9k_hw_chip_test(struct ath_hw *ah) 301 { 302 struct ath_common *common = ath9k_hw_common(ah); 303 u32 regAddr[2] = { AR_STA_ID0 }; 304 u32 regHold[2]; 305 static const u32 patternData[4] = { 306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 307 }; 308 int i, j, loop_max; 309 310 if (!AR_SREV_9300_20_OR_LATER(ah)) { 311 loop_max = 2; 312 regAddr[1] = AR_PHY_BASE + (8 << 2); 313 } else 314 loop_max = 1; 315 316 for (i = 0; i < loop_max; i++) { 317 u32 addr = regAddr[i]; 318 u32 wrData, rdData; 319 320 regHold[i] = REG_READ(ah, addr); 321 for (j = 0; j < 0x100; j++) { 322 wrData = (j << 16) | j; 323 REG_WRITE(ah, addr, wrData); 324 rdData = REG_READ(ah, addr); 325 if (rdData != wrData) { 326 ath_err(common, 327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 328 addr, wrData, rdData); 329 return false; 330 } 331 } 332 for (j = 0; j < 4; j++) { 333 wrData = patternData[j]; 334 REG_WRITE(ah, addr, wrData); 335 rdData = REG_READ(ah, addr); 336 if (wrData != rdData) { 337 ath_err(common, 338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 339 addr, wrData, rdData); 340 return false; 341 } 342 } 343 REG_WRITE(ah, regAddr[i], regHold[i]); 344 } 345 udelay(100); 346 347 return true; 348 } 349 350 static void ath9k_hw_init_config(struct ath_hw *ah) 351 { 352 struct ath_common *common = ath9k_hw_common(ah); 353 354 ah->config.dma_beacon_response_time = 1; 355 ah->config.sw_beacon_response_time = 6; 356 ah->config.cwm_ignore_extcca = 0; 357 ah->config.analog_shiftreg = 1; 358 359 ah->config.rx_intr_mitigation = true; 360 361 if (AR_SREV_9300_20_OR_LATER(ah)) { 362 ah->config.rimt_last = 500; 363 ah->config.rimt_first = 2000; 364 } else { 365 ah->config.rimt_last = 250; 366 ah->config.rimt_first = 700; 367 } 368 369 /* 370 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 372 * This means we use it for all AR5416 devices, and the few 373 * minor PCI AR9280 devices out there. 374 * 375 * Serialization is required because these devices do not handle 376 * well the case of two concurrent reads/writes due to the latency 377 * involved. During one read/write another read/write can be issued 378 * on another CPU while the previous read/write may still be working 379 * on our hardware, if we hit this case the hardware poops in a loop. 380 * We prevent this by serializing reads and writes. 381 * 382 * This issue is not present on PCI-Express devices or pre-AR5416 383 * devices (legacy, 802.11abg). 384 */ 385 if (num_possible_cpus() > 1) 386 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 387 388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 391 !ah->is_pciexpress)) { 392 ah->config.serialize_regmode = SER_REG_MODE_ON; 393 } else { 394 ah->config.serialize_regmode = SER_REG_MODE_OFF; 395 } 396 } 397 398 ath_dbg(common, RESET, "serialize_regmode is %d\n", 399 ah->config.serialize_regmode); 400 401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 403 else 404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 405 } 406 407 static void ath9k_hw_init_defaults(struct ath_hw *ah) 408 { 409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 410 411 regulatory->country_code = CTRY_DEFAULT; 412 regulatory->power_limit = MAX_RATE_POWER; 413 414 ah->hw_version.magic = AR5416_MAGIC; 415 ah->hw_version.subvendorid = 0; 416 417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 418 AR_STA_ID1_MCAST_KSRCH; 419 if (AR_SREV_9100(ah)) 420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 421 422 ah->slottime = ATH9K_SLOT_TIME_9; 423 ah->globaltxtimeout = (u32) -1; 424 ah->power_mode = ATH9K_PM_UNDEFINED; 425 ah->htc_reset_init = true; 426 427 ah->tpc_enabled = true; 428 429 ah->ani_function = ATH9K_ANI_ALL; 430 if (!AR_SREV_9300_20_OR_LATER(ah)) 431 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 432 433 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 434 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 435 else 436 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 437 } 438 439 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 440 { 441 struct ath_common *common = ath9k_hw_common(ah); 442 u32 sum; 443 int i; 444 u16 eeval; 445 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 446 447 sum = 0; 448 for (i = 0; i < 3; i++) { 449 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 450 sum += eeval; 451 common->macaddr[2 * i] = eeval >> 8; 452 common->macaddr[2 * i + 1] = eeval & 0xff; 453 } 454 if (!is_valid_ether_addr(common->macaddr)) { 455 ath_err(common, 456 "eeprom contains invalid mac address: %pM\n", 457 common->macaddr); 458 459 random_ether_addr(common->macaddr); 460 ath_err(common, 461 "random mac address will be used: %pM\n", 462 common->macaddr); 463 } 464 465 return 0; 466 } 467 468 static int ath9k_hw_post_init(struct ath_hw *ah) 469 { 470 struct ath_common *common = ath9k_hw_common(ah); 471 int ecode; 472 473 if (common->bus_ops->ath_bus_type != ATH_USB) { 474 if (!ath9k_hw_chip_test(ah)) 475 return -ENODEV; 476 } 477 478 if (!AR_SREV_9300_20_OR_LATER(ah)) { 479 ecode = ar9002_hw_rf_claim(ah); 480 if (ecode != 0) 481 return ecode; 482 } 483 484 ecode = ath9k_hw_eeprom_init(ah); 485 if (ecode != 0) 486 return ecode; 487 488 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 489 ah->eep_ops->get_eeprom_ver(ah), 490 ah->eep_ops->get_eeprom_rev(ah)); 491 492 ath9k_hw_ani_init(ah); 493 494 /* 495 * EEPROM needs to be initialized before we do this. 496 * This is required for regulatory compliance. 497 */ 498 if (AR_SREV_9300_20_OR_LATER(ah)) { 499 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 500 if ((regdmn & 0xF0) == CTL_FCC) { 501 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 502 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 503 } 504 } 505 506 return 0; 507 } 508 509 static int ath9k_hw_attach_ops(struct ath_hw *ah) 510 { 511 if (!AR_SREV_9300_20_OR_LATER(ah)) 512 return ar9002_hw_attach_ops(ah); 513 514 ar9003_hw_attach_ops(ah); 515 return 0; 516 } 517 518 /* Called for all hardware families */ 519 static int __ath9k_hw_init(struct ath_hw *ah) 520 { 521 struct ath_common *common = ath9k_hw_common(ah); 522 int r = 0; 523 524 ath9k_hw_read_revisions(ah); 525 526 switch (ah->hw_version.macVersion) { 527 case AR_SREV_VERSION_5416_PCI: 528 case AR_SREV_VERSION_5416_PCIE: 529 case AR_SREV_VERSION_9160: 530 case AR_SREV_VERSION_9100: 531 case AR_SREV_VERSION_9280: 532 case AR_SREV_VERSION_9285: 533 case AR_SREV_VERSION_9287: 534 case AR_SREV_VERSION_9271: 535 case AR_SREV_VERSION_9300: 536 case AR_SREV_VERSION_9330: 537 case AR_SREV_VERSION_9485: 538 case AR_SREV_VERSION_9340: 539 case AR_SREV_VERSION_9462: 540 case AR_SREV_VERSION_9550: 541 case AR_SREV_VERSION_9565: 542 case AR_SREV_VERSION_9531: 543 case AR_SREV_VERSION_9561: 544 break; 545 default: 546 ath_err(common, 547 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 548 ah->hw_version.macVersion, ah->hw_version.macRev); 549 return -EOPNOTSUPP; 550 } 551 552 /* 553 * Read back AR_WA into a permanent copy and set bits 14 and 17. 554 * We need to do this to avoid RMW of this register. We cannot 555 * read the reg when chip is asleep. 556 */ 557 if (AR_SREV_9300_20_OR_LATER(ah)) { 558 ah->WARegVal = REG_READ(ah, AR_WA); 559 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 560 AR_WA_ASPM_TIMER_BASED_DISABLE); 561 } 562 563 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 564 ath_err(common, "Couldn't reset chip\n"); 565 return -EIO; 566 } 567 568 if (AR_SREV_9565(ah)) { 569 ah->WARegVal |= AR_WA_BIT22; 570 REG_WRITE(ah, AR_WA, ah->WARegVal); 571 } 572 573 ath9k_hw_init_defaults(ah); 574 ath9k_hw_init_config(ah); 575 576 r = ath9k_hw_attach_ops(ah); 577 if (r) 578 return r; 579 580 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 581 ath_err(common, "Couldn't wakeup chip\n"); 582 return -EIO; 583 } 584 585 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 586 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 587 ah->is_pciexpress = false; 588 589 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 590 ath9k_hw_init_cal_settings(ah); 591 592 if (!ah->is_pciexpress) 593 ath9k_hw_disablepcie(ah); 594 595 r = ath9k_hw_post_init(ah); 596 if (r) 597 return r; 598 599 ath9k_hw_init_mode_gain_regs(ah); 600 r = ath9k_hw_fill_cap_info(ah); 601 if (r) 602 return r; 603 604 r = ath9k_hw_init_macaddr(ah); 605 if (r) { 606 ath_err(common, "Failed to initialize MAC address\n"); 607 return r; 608 } 609 610 ath9k_hw_init_hang_checks(ah); 611 612 common->state = ATH_HW_INITIALIZED; 613 614 return 0; 615 } 616 617 int ath9k_hw_init(struct ath_hw *ah) 618 { 619 int ret; 620 struct ath_common *common = ath9k_hw_common(ah); 621 622 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 623 switch (ah->hw_version.devid) { 624 case AR5416_DEVID_PCI: 625 case AR5416_DEVID_PCIE: 626 case AR5416_AR9100_DEVID: 627 case AR9160_DEVID_PCI: 628 case AR9280_DEVID_PCI: 629 case AR9280_DEVID_PCIE: 630 case AR9285_DEVID_PCIE: 631 case AR9287_DEVID_PCI: 632 case AR9287_DEVID_PCIE: 633 case AR2427_DEVID_PCIE: 634 case AR9300_DEVID_PCIE: 635 case AR9300_DEVID_AR9485_PCIE: 636 case AR9300_DEVID_AR9330: 637 case AR9300_DEVID_AR9340: 638 case AR9300_DEVID_QCA955X: 639 case AR9300_DEVID_AR9580: 640 case AR9300_DEVID_AR9462: 641 case AR9485_DEVID_AR1111: 642 case AR9300_DEVID_AR9565: 643 case AR9300_DEVID_AR953X: 644 case AR9300_DEVID_QCA956X: 645 break; 646 default: 647 if (common->bus_ops->ath_bus_type == ATH_USB) 648 break; 649 ath_err(common, "Hardware device ID 0x%04x not supported\n", 650 ah->hw_version.devid); 651 return -EOPNOTSUPP; 652 } 653 654 ret = __ath9k_hw_init(ah); 655 if (ret) { 656 ath_err(common, 657 "Unable to initialize hardware; initialization status: %d\n", 658 ret); 659 return ret; 660 } 661 662 ath_dynack_init(ah); 663 664 return 0; 665 } 666 EXPORT_SYMBOL(ath9k_hw_init); 667 668 static void ath9k_hw_init_qos(struct ath_hw *ah) 669 { 670 ENABLE_REGWRITE_BUFFER(ah); 671 672 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 673 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 674 675 REG_WRITE(ah, AR_QOS_NO_ACK, 676 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 677 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 678 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 679 680 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 681 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 682 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 683 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 684 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 685 686 REGWRITE_BUFFER_FLUSH(ah); 687 } 688 689 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 690 { 691 struct ath_common *common = ath9k_hw_common(ah); 692 int i = 0; 693 694 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 695 udelay(100); 696 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 697 698 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 699 700 udelay(100); 701 702 if (WARN_ON_ONCE(i >= 100)) { 703 ath_err(common, "PLL4 meaurement not done\n"); 704 break; 705 } 706 707 i++; 708 } 709 710 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 711 } 712 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 713 714 static void ath9k_hw_init_pll(struct ath_hw *ah, 715 struct ath9k_channel *chan) 716 { 717 u32 pll; 718 719 pll = ath9k_hw_compute_pll_control(ah, chan); 720 721 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 722 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 724 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 726 AR_CH0_DPLL2_KD, 0x40); 727 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 728 AR_CH0_DPLL2_KI, 0x4); 729 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 731 AR_CH0_BB_DPLL1_REFDIV, 0x5); 732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 733 AR_CH0_BB_DPLL1_NINI, 0x58); 734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 735 AR_CH0_BB_DPLL1_NFRAC, 0x0); 736 737 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 738 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 740 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 742 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 743 744 /* program BB PLL phase_shift to 0x6 */ 745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 746 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 747 748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 749 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 750 udelay(1000); 751 } else if (AR_SREV_9330(ah)) { 752 u32 ddr_dpll2, pll_control2, kd; 753 754 if (ah->is_clk_25mhz) { 755 ddr_dpll2 = 0x18e82f01; 756 pll_control2 = 0xe04a3d; 757 kd = 0x1d; 758 } else { 759 ddr_dpll2 = 0x19e82f01; 760 pll_control2 = 0x886666; 761 kd = 0x3d; 762 } 763 764 /* program DDR PLL ki and kd value */ 765 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 766 767 /* program DDR PLL phase_shift */ 768 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 769 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 770 771 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 772 pll | AR_RTC_9300_PLL_BYPASS); 773 udelay(1000); 774 775 /* program refdiv, nint, frac to RTC register */ 776 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 777 778 /* program BB PLL kd and ki value */ 779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 781 782 /* program BB PLL phase_shift */ 783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 784 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 785 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 786 AR_SREV_9561(ah)) { 787 u32 regval, pll2_divint, pll2_divfrac, refdiv; 788 789 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 790 pll | AR_RTC_9300_SOC_PLL_BYPASS); 791 udelay(1000); 792 793 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 794 udelay(100); 795 796 if (ah->is_clk_25mhz) { 797 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 798 pll2_divint = 0x1c; 799 pll2_divfrac = 0xa3d2; 800 refdiv = 1; 801 } else { 802 pll2_divint = 0x54; 803 pll2_divfrac = 0x1eb85; 804 refdiv = 3; 805 } 806 } else { 807 if (AR_SREV_9340(ah)) { 808 pll2_divint = 88; 809 pll2_divfrac = 0; 810 refdiv = 5; 811 } else { 812 pll2_divint = 0x11; 813 pll2_divfrac = (AR_SREV_9531(ah) || 814 AR_SREV_9561(ah)) ? 815 0x26665 : 0x26666; 816 refdiv = 1; 817 } 818 } 819 820 regval = REG_READ(ah, AR_PHY_PLL_MODE); 821 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 822 regval |= (0x1 << 22); 823 else 824 regval |= (0x1 << 16); 825 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 826 udelay(100); 827 828 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 829 (pll2_divint << 18) | pll2_divfrac); 830 udelay(100); 831 832 regval = REG_READ(ah, AR_PHY_PLL_MODE); 833 if (AR_SREV_9340(ah)) 834 regval = (regval & 0x80071fff) | 835 (0x1 << 30) | 836 (0x1 << 13) | 837 (0x4 << 26) | 838 (0x18 << 19); 839 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 840 regval = (regval & 0x01c00fff) | 841 (0x1 << 31) | 842 (0x2 << 29) | 843 (0xa << 25) | 844 (0x1 << 19); 845 846 if (AR_SREV_9531(ah)) 847 regval |= (0x6 << 12); 848 } else 849 regval = (regval & 0x80071fff) | 850 (0x3 << 30) | 851 (0x1 << 13) | 852 (0x4 << 26) | 853 (0x60 << 19); 854 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 855 856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 857 REG_WRITE(ah, AR_PHY_PLL_MODE, 858 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 859 else 860 REG_WRITE(ah, AR_PHY_PLL_MODE, 861 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 862 863 udelay(1000); 864 } 865 866 if (AR_SREV_9565(ah)) 867 pll |= 0x40000; 868 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 869 870 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 871 AR_SREV_9550(ah)) 872 udelay(1000); 873 874 /* Switch the core clock for ar9271 to 117Mhz */ 875 if (AR_SREV_9271(ah)) { 876 udelay(500); 877 REG_WRITE(ah, 0x50040, 0x304); 878 } 879 880 udelay(RTC_PLL_SETTLE_DELAY); 881 882 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 883 } 884 885 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 886 enum nl80211_iftype opmode) 887 { 888 u32 sync_default = AR_INTR_SYNC_DEFAULT; 889 u32 imr_reg = AR_IMR_TXERR | 890 AR_IMR_TXURN | 891 AR_IMR_RXERR | 892 AR_IMR_RXORN | 893 AR_IMR_BCNMISC; 894 895 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 896 AR_SREV_9561(ah)) 897 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 898 899 if (AR_SREV_9300_20_OR_LATER(ah)) { 900 imr_reg |= AR_IMR_RXOK_HP; 901 if (ah->config.rx_intr_mitigation) 902 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 903 else 904 imr_reg |= AR_IMR_RXOK_LP; 905 906 } else { 907 if (ah->config.rx_intr_mitigation) 908 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 909 else 910 imr_reg |= AR_IMR_RXOK; 911 } 912 913 if (ah->config.tx_intr_mitigation) 914 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 915 else 916 imr_reg |= AR_IMR_TXOK; 917 918 ENABLE_REGWRITE_BUFFER(ah); 919 920 REG_WRITE(ah, AR_IMR, imr_reg); 921 ah->imrs2_reg |= AR_IMR_S2_GTT; 922 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 923 924 if (!AR_SREV_9100(ah)) { 925 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 926 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 927 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 928 } 929 930 REGWRITE_BUFFER_FLUSH(ah); 931 932 if (AR_SREV_9300_20_OR_LATER(ah)) { 933 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 934 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 935 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 936 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 937 } 938 } 939 940 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 941 { 942 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 943 val = min(val, (u32) 0xFFFF); 944 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 945 } 946 947 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 948 { 949 u32 val = ath9k_hw_mac_to_clks(ah, us); 950 val = min(val, (u32) 0xFFFF); 951 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 952 } 953 954 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 955 { 956 u32 val = ath9k_hw_mac_to_clks(ah, us); 957 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 958 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 959 } 960 961 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 962 { 963 u32 val = ath9k_hw_mac_to_clks(ah, us); 964 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 965 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 966 } 967 968 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 969 { 970 if (tu > 0xFFFF) { 971 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 972 tu); 973 ah->globaltxtimeout = (u32) -1; 974 return false; 975 } else { 976 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 977 ah->globaltxtimeout = tu; 978 return true; 979 } 980 } 981 982 void ath9k_hw_init_global_settings(struct ath_hw *ah) 983 { 984 struct ath_common *common = ath9k_hw_common(ah); 985 const struct ath9k_channel *chan = ah->curchan; 986 int acktimeout, ctstimeout, ack_offset = 0; 987 int slottime; 988 int sifstime; 989 int rx_lat = 0, tx_lat = 0, eifs = 0; 990 u32 reg; 991 992 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 993 ah->misc_mode); 994 995 if (!chan) 996 return; 997 998 if (ah->misc_mode != 0) 999 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1000 1001 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1002 rx_lat = 41; 1003 else 1004 rx_lat = 37; 1005 tx_lat = 54; 1006 1007 if (IS_CHAN_5GHZ(chan)) 1008 sifstime = 16; 1009 else 1010 sifstime = 10; 1011 1012 if (IS_CHAN_HALF_RATE(chan)) { 1013 eifs = 175; 1014 rx_lat *= 2; 1015 tx_lat *= 2; 1016 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1017 tx_lat += 11; 1018 1019 sifstime = 32; 1020 ack_offset = 16; 1021 slottime = 13; 1022 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1023 eifs = 340; 1024 rx_lat = (rx_lat * 4) - 1; 1025 tx_lat *= 4; 1026 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1027 tx_lat += 22; 1028 1029 sifstime = 64; 1030 ack_offset = 32; 1031 slottime = 21; 1032 } else { 1033 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1034 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1035 reg = AR_USEC_ASYNC_FIFO; 1036 } else { 1037 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1038 common->clockrate; 1039 reg = REG_READ(ah, AR_USEC); 1040 } 1041 rx_lat = MS(reg, AR_USEC_RX_LAT); 1042 tx_lat = MS(reg, AR_USEC_TX_LAT); 1043 1044 slottime = ah->slottime; 1045 } 1046 1047 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1048 slottime += 3 * ah->coverage_class; 1049 acktimeout = slottime + sifstime + ack_offset; 1050 ctstimeout = acktimeout; 1051 1052 /* 1053 * Workaround for early ACK timeouts, add an offset to match the 1054 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1055 * This was initially only meant to work around an issue with delayed 1056 * BA frames in some implementations, but it has been found to fix ACK 1057 * timeout issues in other cases as well. 1058 */ 1059 if (IS_CHAN_2GHZ(chan) && 1060 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1061 acktimeout += 64 - sifstime - ah->slottime; 1062 ctstimeout += 48 - sifstime - ah->slottime; 1063 } 1064 1065 if (ah->dynack.enabled) { 1066 acktimeout = ah->dynack.ackto; 1067 ctstimeout = acktimeout; 1068 slottime = (acktimeout - 3) / 2; 1069 } else { 1070 ah->dynack.ackto = acktimeout; 1071 } 1072 1073 ath9k_hw_set_sifs_time(ah, sifstime); 1074 ath9k_hw_setslottime(ah, slottime); 1075 ath9k_hw_set_ack_timeout(ah, acktimeout); 1076 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1077 if (ah->globaltxtimeout != (u32) -1) 1078 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1079 1080 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1081 REG_RMW(ah, AR_USEC, 1082 (common->clockrate - 1) | 1083 SM(rx_lat, AR_USEC_RX_LAT) | 1084 SM(tx_lat, AR_USEC_TX_LAT), 1085 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1086 1087 } 1088 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1089 1090 void ath9k_hw_deinit(struct ath_hw *ah) 1091 { 1092 struct ath_common *common = ath9k_hw_common(ah); 1093 1094 if (common->state < ATH_HW_INITIALIZED) 1095 return; 1096 1097 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1098 } 1099 EXPORT_SYMBOL(ath9k_hw_deinit); 1100 1101 /*******/ 1102 /* INI */ 1103 /*******/ 1104 1105 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1106 { 1107 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1108 1109 if (IS_CHAN_2GHZ(chan)) 1110 ctl |= CTL_11G; 1111 else 1112 ctl |= CTL_11A; 1113 1114 return ctl; 1115 } 1116 1117 /****************************************/ 1118 /* Reset and Channel Switching Routines */ 1119 /****************************************/ 1120 1121 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1122 { 1123 struct ath_common *common = ath9k_hw_common(ah); 1124 int txbuf_size; 1125 1126 ENABLE_REGWRITE_BUFFER(ah); 1127 1128 /* 1129 * set AHB_MODE not to do cacheline prefetches 1130 */ 1131 if (!AR_SREV_9300_20_OR_LATER(ah)) 1132 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1133 1134 /* 1135 * let mac dma reads be in 128 byte chunks 1136 */ 1137 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1138 1139 REGWRITE_BUFFER_FLUSH(ah); 1140 1141 /* 1142 * Restore TX Trigger Level to its pre-reset value. 1143 * The initial value depends on whether aggregation is enabled, and is 1144 * adjusted whenever underruns are detected. 1145 */ 1146 if (!AR_SREV_9300_20_OR_LATER(ah)) 1147 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1148 1149 ENABLE_REGWRITE_BUFFER(ah); 1150 1151 /* 1152 * let mac dma writes be in 128 byte chunks 1153 */ 1154 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1155 1156 /* 1157 * Setup receive FIFO threshold to hold off TX activities 1158 */ 1159 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1160 1161 if (AR_SREV_9300_20_OR_LATER(ah)) { 1162 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1163 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1164 1165 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1166 ah->caps.rx_status_len); 1167 } 1168 1169 /* 1170 * reduce the number of usable entries in PCU TXBUF to avoid 1171 * wrap around issues. 1172 */ 1173 if (AR_SREV_9285(ah)) { 1174 /* For AR9285 the number of Fifos are reduced to half. 1175 * So set the usable tx buf size also to half to 1176 * avoid data/delimiter underruns 1177 */ 1178 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1179 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1180 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1181 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1182 } else { 1183 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1184 } 1185 1186 if (!AR_SREV_9271(ah)) 1187 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1188 1189 REGWRITE_BUFFER_FLUSH(ah); 1190 1191 if (AR_SREV_9300_20_OR_LATER(ah)) 1192 ath9k_hw_reset_txstatus_ring(ah); 1193 } 1194 1195 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1196 { 1197 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1198 u32 set = AR_STA_ID1_KSRCH_MODE; 1199 1200 switch (opmode) { 1201 case NL80211_IFTYPE_ADHOC: 1202 if (!AR_SREV_9340_13(ah)) { 1203 set |= AR_STA_ID1_ADHOC; 1204 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1205 break; 1206 } 1207 /* fall through */ 1208 case NL80211_IFTYPE_MESH_POINT: 1209 case NL80211_IFTYPE_AP: 1210 set |= AR_STA_ID1_STA_AP; 1211 /* fall through */ 1212 case NL80211_IFTYPE_STATION: 1213 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1214 break; 1215 default: 1216 if (!ah->is_monitoring) 1217 set = 0; 1218 break; 1219 } 1220 REG_RMW(ah, AR_STA_ID1, set, mask); 1221 } 1222 1223 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1224 u32 *coef_mantissa, u32 *coef_exponent) 1225 { 1226 u32 coef_exp, coef_man; 1227 1228 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1229 if ((coef_scaled >> coef_exp) & 0x1) 1230 break; 1231 1232 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1233 1234 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1235 1236 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1237 *coef_exponent = coef_exp - 16; 1238 } 1239 1240 /* AR9330 WAR: 1241 * call external reset function to reset WMAC if: 1242 * - doing a cold reset 1243 * - we have pending frames in the TX queues. 1244 */ 1245 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1246 { 1247 int i, npend = 0; 1248 1249 for (i = 0; i < AR_NUM_QCU; i++) { 1250 npend = ath9k_hw_numtxpending(ah, i); 1251 if (npend) 1252 break; 1253 } 1254 1255 if (ah->external_reset && 1256 (npend || type == ATH9K_RESET_COLD)) { 1257 int reset_err = 0; 1258 1259 ath_dbg(ath9k_hw_common(ah), RESET, 1260 "reset MAC via external reset\n"); 1261 1262 reset_err = ah->external_reset(); 1263 if (reset_err) { 1264 ath_err(ath9k_hw_common(ah), 1265 "External reset failed, err=%d\n", 1266 reset_err); 1267 return false; 1268 } 1269 1270 REG_WRITE(ah, AR_RTC_RESET, 1); 1271 } 1272 1273 return true; 1274 } 1275 1276 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1277 { 1278 u32 rst_flags; 1279 u32 tmpReg; 1280 1281 if (AR_SREV_9100(ah)) { 1282 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1283 AR_RTC_DERIVED_CLK_PERIOD, 1); 1284 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1285 } 1286 1287 ENABLE_REGWRITE_BUFFER(ah); 1288 1289 if (AR_SREV_9300_20_OR_LATER(ah)) { 1290 REG_WRITE(ah, AR_WA, ah->WARegVal); 1291 udelay(10); 1292 } 1293 1294 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1295 AR_RTC_FORCE_WAKE_ON_INT); 1296 1297 if (AR_SREV_9100(ah)) { 1298 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1299 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1300 } else { 1301 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1302 if (AR_SREV_9340(ah)) 1303 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1304 else 1305 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1306 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1307 1308 if (tmpReg) { 1309 u32 val; 1310 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1311 1312 val = AR_RC_HOSTIF; 1313 if (!AR_SREV_9300_20_OR_LATER(ah)) 1314 val |= AR_RC_AHB; 1315 REG_WRITE(ah, AR_RC, val); 1316 1317 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1318 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1319 1320 rst_flags = AR_RTC_RC_MAC_WARM; 1321 if (type == ATH9K_RESET_COLD) 1322 rst_flags |= AR_RTC_RC_MAC_COLD; 1323 } 1324 1325 if (AR_SREV_9330(ah)) { 1326 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1327 return false; 1328 } 1329 1330 if (ath9k_hw_mci_is_enabled(ah)) 1331 ar9003_mci_check_gpm_offset(ah); 1332 1333 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1334 1335 REGWRITE_BUFFER_FLUSH(ah); 1336 1337 if (AR_SREV_9300_20_OR_LATER(ah)) 1338 udelay(50); 1339 else if (AR_SREV_9100(ah)) 1340 mdelay(10); 1341 else 1342 udelay(100); 1343 1344 REG_WRITE(ah, AR_RTC_RC, 0); 1345 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1346 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1347 return false; 1348 } 1349 1350 if (!AR_SREV_9100(ah)) 1351 REG_WRITE(ah, AR_RC, 0); 1352 1353 if (AR_SREV_9100(ah)) 1354 udelay(50); 1355 1356 return true; 1357 } 1358 1359 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1360 { 1361 ENABLE_REGWRITE_BUFFER(ah); 1362 1363 if (AR_SREV_9300_20_OR_LATER(ah)) { 1364 REG_WRITE(ah, AR_WA, ah->WARegVal); 1365 udelay(10); 1366 } 1367 1368 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1369 AR_RTC_FORCE_WAKE_ON_INT); 1370 1371 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1372 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1373 1374 REG_WRITE(ah, AR_RTC_RESET, 0); 1375 1376 REGWRITE_BUFFER_FLUSH(ah); 1377 1378 udelay(2); 1379 1380 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1381 REG_WRITE(ah, AR_RC, 0); 1382 1383 REG_WRITE(ah, AR_RTC_RESET, 1); 1384 1385 if (!ath9k_hw_wait(ah, 1386 AR_RTC_STATUS, 1387 AR_RTC_STATUS_M, 1388 AR_RTC_STATUS_ON, 1389 AH_WAIT_TIMEOUT)) { 1390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1391 return false; 1392 } 1393 1394 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1395 } 1396 1397 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1398 { 1399 bool ret = false; 1400 1401 if (AR_SREV_9300_20_OR_LATER(ah)) { 1402 REG_WRITE(ah, AR_WA, ah->WARegVal); 1403 udelay(10); 1404 } 1405 1406 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1407 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1408 1409 if (!ah->reset_power_on) 1410 type = ATH9K_RESET_POWER_ON; 1411 1412 switch (type) { 1413 case ATH9K_RESET_POWER_ON: 1414 ret = ath9k_hw_set_reset_power_on(ah); 1415 if (ret) 1416 ah->reset_power_on = true; 1417 break; 1418 case ATH9K_RESET_WARM: 1419 case ATH9K_RESET_COLD: 1420 ret = ath9k_hw_set_reset(ah, type); 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 return ret; 1427 } 1428 1429 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1430 struct ath9k_channel *chan) 1431 { 1432 int reset_type = ATH9K_RESET_WARM; 1433 1434 if (AR_SREV_9280(ah)) { 1435 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1436 reset_type = ATH9K_RESET_POWER_ON; 1437 else 1438 reset_type = ATH9K_RESET_COLD; 1439 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1440 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1441 reset_type = ATH9K_RESET_COLD; 1442 1443 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1444 return false; 1445 1446 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1447 return false; 1448 1449 ah->chip_fullsleep = false; 1450 1451 if (AR_SREV_9330(ah)) 1452 ar9003_hw_internal_regulator_apply(ah); 1453 ath9k_hw_init_pll(ah, chan); 1454 1455 return true; 1456 } 1457 1458 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1459 struct ath9k_channel *chan) 1460 { 1461 struct ath_common *common = ath9k_hw_common(ah); 1462 struct ath9k_hw_capabilities *pCap = &ah->caps; 1463 bool band_switch = false, mode_diff = false; 1464 u8 ini_reloaded = 0; 1465 u32 qnum; 1466 int r; 1467 1468 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1469 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1470 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1471 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1472 } 1473 1474 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1475 if (ath9k_hw_numtxpending(ah, qnum)) { 1476 ath_dbg(common, QUEUE, 1477 "Transmit frames pending on queue %d\n", qnum); 1478 return false; 1479 } 1480 } 1481 1482 if (!ath9k_hw_rfbus_req(ah)) { 1483 ath_err(common, "Could not kill baseband RX\n"); 1484 return false; 1485 } 1486 1487 if (band_switch || mode_diff) { 1488 ath9k_hw_mark_phy_inactive(ah); 1489 udelay(5); 1490 1491 if (band_switch) 1492 ath9k_hw_init_pll(ah, chan); 1493 1494 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1495 ath_err(common, "Failed to do fast channel change\n"); 1496 return false; 1497 } 1498 } 1499 1500 ath9k_hw_set_channel_regs(ah, chan); 1501 1502 r = ath9k_hw_rf_set_freq(ah, chan); 1503 if (r) { 1504 ath_err(common, "Failed to set channel\n"); 1505 return false; 1506 } 1507 ath9k_hw_set_clockrate(ah); 1508 ath9k_hw_apply_txpower(ah, chan, false); 1509 1510 ath9k_hw_set_delta_slope(ah, chan); 1511 ath9k_hw_spur_mitigate_freq(ah, chan); 1512 1513 if (band_switch || ini_reloaded) 1514 ah->eep_ops->set_board_values(ah, chan); 1515 1516 ath9k_hw_init_bb(ah, chan); 1517 ath9k_hw_rfbus_done(ah); 1518 1519 if (band_switch || ini_reloaded) { 1520 ah->ah_flags |= AH_FASTCC; 1521 ath9k_hw_init_cal(ah, chan); 1522 ah->ah_flags &= ~AH_FASTCC; 1523 } 1524 1525 return true; 1526 } 1527 1528 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1529 { 1530 u32 gpio_mask = ah->gpio_mask; 1531 int i; 1532 1533 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1534 if (!(gpio_mask & 1)) 1535 continue; 1536 1537 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1538 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1539 } 1540 } 1541 1542 void ath9k_hw_check_nav(struct ath_hw *ah) 1543 { 1544 struct ath_common *common = ath9k_hw_common(ah); 1545 u32 val; 1546 1547 val = REG_READ(ah, AR_NAV); 1548 if (val != 0xdeadbeef && val > 0x7fff) { 1549 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1550 REG_WRITE(ah, AR_NAV, 0); 1551 } 1552 } 1553 EXPORT_SYMBOL(ath9k_hw_check_nav); 1554 1555 bool ath9k_hw_check_alive(struct ath_hw *ah) 1556 { 1557 int count = 50; 1558 u32 reg, last_val; 1559 1560 if (AR_SREV_9300(ah)) 1561 return !ath9k_hw_detect_mac_hang(ah); 1562 1563 if (AR_SREV_9285_12_OR_LATER(ah)) 1564 return true; 1565 1566 last_val = REG_READ(ah, AR_OBS_BUS_1); 1567 do { 1568 reg = REG_READ(ah, AR_OBS_BUS_1); 1569 if (reg != last_val) 1570 return true; 1571 1572 udelay(1); 1573 last_val = reg; 1574 if ((reg & 0x7E7FFFEF) == 0x00702400) 1575 continue; 1576 1577 switch (reg & 0x7E000B00) { 1578 case 0x1E000000: 1579 case 0x52000B00: 1580 case 0x18000B00: 1581 continue; 1582 default: 1583 return true; 1584 } 1585 } while (count-- > 0); 1586 1587 return false; 1588 } 1589 EXPORT_SYMBOL(ath9k_hw_check_alive); 1590 1591 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1592 { 1593 /* Setup MFP options for CCMP */ 1594 if (AR_SREV_9280_20_OR_LATER(ah)) { 1595 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1596 * frames when constructing CCMP AAD. */ 1597 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1598 0xc7ff); 1599 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1600 ah->sw_mgmt_crypto_tx = true; 1601 else 1602 ah->sw_mgmt_crypto_tx = false; 1603 ah->sw_mgmt_crypto_rx = false; 1604 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1605 /* Disable hardware crypto for management frames */ 1606 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1607 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1608 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1609 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1610 ah->sw_mgmt_crypto_tx = true; 1611 ah->sw_mgmt_crypto_rx = true; 1612 } else { 1613 ah->sw_mgmt_crypto_tx = true; 1614 ah->sw_mgmt_crypto_rx = true; 1615 } 1616 } 1617 1618 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1619 u32 macStaId1, u32 saveDefAntenna) 1620 { 1621 struct ath_common *common = ath9k_hw_common(ah); 1622 1623 ENABLE_REGWRITE_BUFFER(ah); 1624 1625 REG_RMW(ah, AR_STA_ID1, macStaId1 1626 | AR_STA_ID1_RTS_USE_DEF 1627 | ah->sta_id1_defaults, 1628 ~AR_STA_ID1_SADH_MASK); 1629 ath_hw_setbssidmask(common); 1630 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1631 ath9k_hw_write_associd(ah); 1632 REG_WRITE(ah, AR_ISR, ~0); 1633 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1634 1635 REGWRITE_BUFFER_FLUSH(ah); 1636 1637 ath9k_hw_set_operating_mode(ah, ah->opmode); 1638 } 1639 1640 static void ath9k_hw_init_queues(struct ath_hw *ah) 1641 { 1642 int i; 1643 1644 ENABLE_REGWRITE_BUFFER(ah); 1645 1646 for (i = 0; i < AR_NUM_DCU; i++) 1647 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1648 1649 REGWRITE_BUFFER_FLUSH(ah); 1650 1651 ah->intr_txqs = 0; 1652 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1653 ath9k_hw_resettxqueue(ah, i); 1654 } 1655 1656 /* 1657 * For big endian systems turn on swapping for descriptors 1658 */ 1659 static void ath9k_hw_init_desc(struct ath_hw *ah) 1660 { 1661 struct ath_common *common = ath9k_hw_common(ah); 1662 1663 if (AR_SREV_9100(ah)) { 1664 u32 mask; 1665 mask = REG_READ(ah, AR_CFG); 1666 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1667 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1668 mask); 1669 } else { 1670 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1671 REG_WRITE(ah, AR_CFG, mask); 1672 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1673 REG_READ(ah, AR_CFG)); 1674 } 1675 } else { 1676 if (common->bus_ops->ath_bus_type == ATH_USB) { 1677 /* Configure AR9271 target WLAN */ 1678 if (AR_SREV_9271(ah)) 1679 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1680 else 1681 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1682 } 1683 #ifdef __BIG_ENDIAN 1684 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1685 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1686 AR_SREV_9561(ah)) 1687 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1688 else 1689 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1690 #endif 1691 } 1692 } 1693 1694 /* 1695 * Fast channel change: 1696 * (Change synthesizer based on channel freq without resetting chip) 1697 */ 1698 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1699 { 1700 struct ath_common *common = ath9k_hw_common(ah); 1701 struct ath9k_hw_capabilities *pCap = &ah->caps; 1702 int ret; 1703 1704 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1705 goto fail; 1706 1707 if (ah->chip_fullsleep) 1708 goto fail; 1709 1710 if (!ah->curchan) 1711 goto fail; 1712 1713 if (chan->channel == ah->curchan->channel) 1714 goto fail; 1715 1716 if ((ah->curchan->channelFlags | chan->channelFlags) & 1717 (CHANNEL_HALF | CHANNEL_QUARTER)) 1718 goto fail; 1719 1720 /* 1721 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1722 */ 1723 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1724 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1725 goto fail; 1726 1727 if (!ath9k_hw_check_alive(ah)) 1728 goto fail; 1729 1730 /* 1731 * For AR9462, make sure that calibration data for 1732 * re-using are present. 1733 */ 1734 if (AR_SREV_9462(ah) && (ah->caldata && 1735 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1736 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1737 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1738 goto fail; 1739 1740 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1741 ah->curchan->channel, chan->channel); 1742 1743 ret = ath9k_hw_channel_change(ah, chan); 1744 if (!ret) 1745 goto fail; 1746 1747 if (ath9k_hw_mci_is_enabled(ah)) 1748 ar9003_mci_2g5g_switch(ah, false); 1749 1750 ath9k_hw_loadnf(ah, ah->curchan); 1751 ath9k_hw_start_nfcal(ah, true); 1752 1753 if (AR_SREV_9271(ah)) 1754 ar9002_hw_load_ani_reg(ah, chan); 1755 1756 return 0; 1757 fail: 1758 return -EINVAL; 1759 } 1760 1761 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1762 { 1763 struct timespec ts; 1764 s64 usec; 1765 1766 if (!cur) { 1767 getrawmonotonic(&ts); 1768 cur = &ts; 1769 } 1770 1771 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1772 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1773 1774 return (u32) usec; 1775 } 1776 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1777 1778 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1779 struct ath9k_hw_cal_data *caldata, bool fastcc) 1780 { 1781 struct ath_common *common = ath9k_hw_common(ah); 1782 u32 saveLedState; 1783 u32 saveDefAntenna; 1784 u32 macStaId1; 1785 u64 tsf = 0; 1786 s64 usec = 0; 1787 int r; 1788 bool start_mci_reset = false; 1789 bool save_fullsleep = ah->chip_fullsleep; 1790 1791 if (ath9k_hw_mci_is_enabled(ah)) { 1792 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1793 if (start_mci_reset) 1794 return 0; 1795 } 1796 1797 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1798 return -EIO; 1799 1800 if (ah->curchan && !ah->chip_fullsleep) 1801 ath9k_hw_getnf(ah, ah->curchan); 1802 1803 ah->caldata = caldata; 1804 if (caldata && (chan->channel != caldata->channel || 1805 chan->channelFlags != caldata->channelFlags)) { 1806 /* Operating channel changed, reset channel calibration data */ 1807 memset(caldata, 0, sizeof(*caldata)); 1808 ath9k_init_nfcal_hist_buffer(ah, chan); 1809 } else if (caldata) { 1810 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1811 } 1812 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1813 1814 if (fastcc) { 1815 r = ath9k_hw_do_fastcc(ah, chan); 1816 if (!r) 1817 return r; 1818 } 1819 1820 if (ath9k_hw_mci_is_enabled(ah)) 1821 ar9003_mci_stop_bt(ah, save_fullsleep); 1822 1823 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1824 if (saveDefAntenna == 0) 1825 saveDefAntenna = 1; 1826 1827 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1828 1829 /* Save TSF before chip reset, a cold reset clears it */ 1830 tsf = ath9k_hw_gettsf64(ah); 1831 usec = ktime_to_us(ktime_get_raw()); 1832 1833 saveLedState = REG_READ(ah, AR_CFG_LED) & 1834 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1835 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1836 1837 ath9k_hw_mark_phy_inactive(ah); 1838 1839 ah->paprd_table_write_done = false; 1840 1841 /* Only required on the first reset */ 1842 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1843 REG_WRITE(ah, 1844 AR9271_RESET_POWER_DOWN_CONTROL, 1845 AR9271_RADIO_RF_RST); 1846 udelay(50); 1847 } 1848 1849 if (!ath9k_hw_chip_reset(ah, chan)) { 1850 ath_err(common, "Chip reset failed\n"); 1851 return -EINVAL; 1852 } 1853 1854 /* Only required on the first reset */ 1855 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1856 ah->htc_reset_init = false; 1857 REG_WRITE(ah, 1858 AR9271_RESET_POWER_DOWN_CONTROL, 1859 AR9271_GATE_MAC_CTL); 1860 udelay(50); 1861 } 1862 1863 /* Restore TSF */ 1864 usec = ktime_to_us(ktime_get_raw()) - usec; 1865 ath9k_hw_settsf64(ah, tsf + usec); 1866 1867 if (AR_SREV_9280_20_OR_LATER(ah)) 1868 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1869 1870 if (!AR_SREV_9300_20_OR_LATER(ah)) 1871 ar9002_hw_enable_async_fifo(ah); 1872 1873 r = ath9k_hw_process_ini(ah, chan); 1874 if (r) 1875 return r; 1876 1877 ath9k_hw_set_rfmode(ah, chan); 1878 1879 if (ath9k_hw_mci_is_enabled(ah)) 1880 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1881 1882 /* 1883 * Some AR91xx SoC devices frequently fail to accept TSF writes 1884 * right after the chip reset. When that happens, write a new 1885 * value after the initvals have been applied, with an offset 1886 * based on measured time difference 1887 */ 1888 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1889 tsf += 1500; 1890 ath9k_hw_settsf64(ah, tsf); 1891 } 1892 1893 ath9k_hw_init_mfp(ah); 1894 1895 ath9k_hw_set_delta_slope(ah, chan); 1896 ath9k_hw_spur_mitigate_freq(ah, chan); 1897 ah->eep_ops->set_board_values(ah, chan); 1898 1899 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1900 1901 r = ath9k_hw_rf_set_freq(ah, chan); 1902 if (r) 1903 return r; 1904 1905 ath9k_hw_set_clockrate(ah); 1906 1907 ath9k_hw_init_queues(ah); 1908 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1909 ath9k_hw_ani_cache_ini_regs(ah); 1910 ath9k_hw_init_qos(ah); 1911 1912 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1913 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1914 1915 ath9k_hw_init_global_settings(ah); 1916 1917 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1918 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1919 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1920 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1921 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1922 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1923 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1924 } 1925 1926 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1927 1928 ath9k_hw_set_dma(ah); 1929 1930 if (!ath9k_hw_mci_is_enabled(ah)) 1931 REG_WRITE(ah, AR_OBS, 8); 1932 1933 if (ah->config.rx_intr_mitigation) { 1934 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1935 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1936 } 1937 1938 if (ah->config.tx_intr_mitigation) { 1939 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1940 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1941 } 1942 1943 ath9k_hw_init_bb(ah, chan); 1944 1945 if (caldata) { 1946 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1947 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1948 } 1949 if (!ath9k_hw_init_cal(ah, chan)) 1950 return -EIO; 1951 1952 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1953 return -EIO; 1954 1955 ENABLE_REGWRITE_BUFFER(ah); 1956 1957 ath9k_hw_restore_chainmask(ah); 1958 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1959 1960 REGWRITE_BUFFER_FLUSH(ah); 1961 1962 ath9k_hw_gen_timer_start_tsf2(ah); 1963 1964 ath9k_hw_init_desc(ah); 1965 1966 if (ath9k_hw_btcoex_is_enabled(ah)) 1967 ath9k_hw_btcoex_enable(ah); 1968 1969 if (ath9k_hw_mci_is_enabled(ah)) 1970 ar9003_mci_check_bt(ah); 1971 1972 if (AR_SREV_9300_20_OR_LATER(ah)) { 1973 ath9k_hw_loadnf(ah, chan); 1974 ath9k_hw_start_nfcal(ah, true); 1975 } 1976 1977 if (AR_SREV_9300_20_OR_LATER(ah)) 1978 ar9003_hw_bb_watchdog_config(ah); 1979 1980 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1981 ar9003_hw_disable_phy_restart(ah); 1982 1983 ath9k_hw_apply_gpio_override(ah); 1984 1985 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1986 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1987 1988 if (ah->hw->conf.radar_enabled) { 1989 /* set HW specific DFS configuration */ 1990 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 1991 ath9k_hw_set_radar_params(ah); 1992 } 1993 1994 return 0; 1995 } 1996 EXPORT_SYMBOL(ath9k_hw_reset); 1997 1998 /******************************/ 1999 /* Power Management (Chipset) */ 2000 /******************************/ 2001 2002 /* 2003 * Notify Power Mgt is disabled in self-generated frames. 2004 * If requested, force chip to sleep. 2005 */ 2006 static void ath9k_set_power_sleep(struct ath_hw *ah) 2007 { 2008 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2009 2010 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2011 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2012 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2013 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2014 /* xxx Required for WLAN only case ? */ 2015 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2016 udelay(100); 2017 } 2018 2019 /* 2020 * Clear the RTC force wake bit to allow the 2021 * mac to go to sleep. 2022 */ 2023 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2024 2025 if (ath9k_hw_mci_is_enabled(ah)) 2026 udelay(100); 2027 2028 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2029 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2030 2031 /* Shutdown chip. Active low */ 2032 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2033 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2034 udelay(2); 2035 } 2036 2037 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2038 if (AR_SREV_9300_20_OR_LATER(ah)) 2039 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2040 } 2041 2042 /* 2043 * Notify Power Management is enabled in self-generating 2044 * frames. If request, set power mode of chip to 2045 * auto/normal. Duration in units of 128us (1/8 TU). 2046 */ 2047 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2048 { 2049 struct ath9k_hw_capabilities *pCap = &ah->caps; 2050 2051 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2052 2053 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2054 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2055 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2056 AR_RTC_FORCE_WAKE_ON_INT); 2057 } else { 2058 2059 /* When chip goes into network sleep, it could be waken 2060 * up by MCI_INT interrupt caused by BT's HW messages 2061 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2062 * rate (~100us). This will cause chip to leave and 2063 * re-enter network sleep mode frequently, which in 2064 * consequence will have WLAN MCI HW to generate lots of 2065 * SYS_WAKING and SYS_SLEEPING messages which will make 2066 * BT CPU to busy to process. 2067 */ 2068 if (ath9k_hw_mci_is_enabled(ah)) 2069 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2070 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2071 /* 2072 * Clear the RTC force wake bit to allow the 2073 * mac to go to sleep. 2074 */ 2075 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2076 2077 if (ath9k_hw_mci_is_enabled(ah)) 2078 udelay(30); 2079 } 2080 2081 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2082 if (AR_SREV_9300_20_OR_LATER(ah)) 2083 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2084 } 2085 2086 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2087 { 2088 u32 val; 2089 int i; 2090 2091 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2092 if (AR_SREV_9300_20_OR_LATER(ah)) { 2093 REG_WRITE(ah, AR_WA, ah->WARegVal); 2094 udelay(10); 2095 } 2096 2097 if ((REG_READ(ah, AR_RTC_STATUS) & 2098 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2099 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2100 return false; 2101 } 2102 if (!AR_SREV_9300_20_OR_LATER(ah)) 2103 ath9k_hw_init_pll(ah, NULL); 2104 } 2105 if (AR_SREV_9100(ah)) 2106 REG_SET_BIT(ah, AR_RTC_RESET, 2107 AR_RTC_RESET_EN); 2108 2109 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2110 AR_RTC_FORCE_WAKE_EN); 2111 if (AR_SREV_9100(ah)) 2112 mdelay(10); 2113 else 2114 udelay(50); 2115 2116 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2117 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2118 if (val == AR_RTC_STATUS_ON) 2119 break; 2120 udelay(50); 2121 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2122 AR_RTC_FORCE_WAKE_EN); 2123 } 2124 if (i == 0) { 2125 ath_err(ath9k_hw_common(ah), 2126 "Failed to wakeup in %uus\n", 2127 POWER_UP_TIME / 20); 2128 return false; 2129 } 2130 2131 if (ath9k_hw_mci_is_enabled(ah)) 2132 ar9003_mci_set_power_awake(ah); 2133 2134 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2135 2136 return true; 2137 } 2138 2139 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2140 { 2141 struct ath_common *common = ath9k_hw_common(ah); 2142 int status = true; 2143 static const char *modes[] = { 2144 "AWAKE", 2145 "FULL-SLEEP", 2146 "NETWORK SLEEP", 2147 "UNDEFINED" 2148 }; 2149 2150 if (ah->power_mode == mode) 2151 return status; 2152 2153 ath_dbg(common, RESET, "%s -> %s\n", 2154 modes[ah->power_mode], modes[mode]); 2155 2156 switch (mode) { 2157 case ATH9K_PM_AWAKE: 2158 status = ath9k_hw_set_power_awake(ah); 2159 break; 2160 case ATH9K_PM_FULL_SLEEP: 2161 if (ath9k_hw_mci_is_enabled(ah)) 2162 ar9003_mci_set_full_sleep(ah); 2163 2164 ath9k_set_power_sleep(ah); 2165 ah->chip_fullsleep = true; 2166 break; 2167 case ATH9K_PM_NETWORK_SLEEP: 2168 ath9k_set_power_network_sleep(ah); 2169 break; 2170 default: 2171 ath_err(common, "Unknown power mode %u\n", mode); 2172 return false; 2173 } 2174 ah->power_mode = mode; 2175 2176 /* 2177 * XXX: If this warning never comes up after a while then 2178 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2179 * ath9k_hw_setpower() return type void. 2180 */ 2181 2182 if (!(ah->ah_flags & AH_UNPLUGGED)) 2183 ATH_DBG_WARN_ON_ONCE(!status); 2184 2185 return status; 2186 } 2187 EXPORT_SYMBOL(ath9k_hw_setpower); 2188 2189 /*******************/ 2190 /* Beacon Handling */ 2191 /*******************/ 2192 2193 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2194 { 2195 int flags = 0; 2196 2197 ENABLE_REGWRITE_BUFFER(ah); 2198 2199 switch (ah->opmode) { 2200 case NL80211_IFTYPE_ADHOC: 2201 REG_SET_BIT(ah, AR_TXCFG, 2202 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2203 case NL80211_IFTYPE_MESH_POINT: 2204 case NL80211_IFTYPE_AP: 2205 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2206 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2207 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2208 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2209 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2210 flags |= 2211 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2212 break; 2213 default: 2214 ath_dbg(ath9k_hw_common(ah), BEACON, 2215 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2216 return; 2217 break; 2218 } 2219 2220 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2221 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2222 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2223 2224 REGWRITE_BUFFER_FLUSH(ah); 2225 2226 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2227 } 2228 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2229 2230 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2231 const struct ath9k_beacon_state *bs) 2232 { 2233 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2234 struct ath9k_hw_capabilities *pCap = &ah->caps; 2235 struct ath_common *common = ath9k_hw_common(ah); 2236 2237 ENABLE_REGWRITE_BUFFER(ah); 2238 2239 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2240 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2241 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2242 2243 REGWRITE_BUFFER_FLUSH(ah); 2244 2245 REG_RMW_FIELD(ah, AR_RSSI_THR, 2246 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2247 2248 beaconintval = bs->bs_intval; 2249 2250 if (bs->bs_sleepduration > beaconintval) 2251 beaconintval = bs->bs_sleepduration; 2252 2253 dtimperiod = bs->bs_dtimperiod; 2254 if (bs->bs_sleepduration > dtimperiod) 2255 dtimperiod = bs->bs_sleepduration; 2256 2257 if (beaconintval == dtimperiod) 2258 nextTbtt = bs->bs_nextdtim; 2259 else 2260 nextTbtt = bs->bs_nexttbtt; 2261 2262 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2263 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2264 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2265 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2266 2267 ENABLE_REGWRITE_BUFFER(ah); 2268 2269 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2270 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2271 2272 REG_WRITE(ah, AR_SLEEP1, 2273 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2274 | AR_SLEEP1_ASSUME_DTIM); 2275 2276 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2277 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2278 else 2279 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2280 2281 REG_WRITE(ah, AR_SLEEP2, 2282 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2283 2284 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2285 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2286 2287 REGWRITE_BUFFER_FLUSH(ah); 2288 2289 REG_SET_BIT(ah, AR_TIMER_MODE, 2290 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2291 AR_DTIM_TIMER_EN); 2292 2293 /* TSF Out of Range Threshold */ 2294 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2295 } 2296 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2297 2298 /*******************/ 2299 /* HW Capabilities */ 2300 /*******************/ 2301 2302 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2303 { 2304 eeprom_chainmask &= chip_chainmask; 2305 if (eeprom_chainmask) 2306 return eeprom_chainmask; 2307 else 2308 return chip_chainmask; 2309 } 2310 2311 /** 2312 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2313 * @ah: the atheros hardware data structure 2314 * 2315 * We enable DFS support upstream on chipsets which have passed a series 2316 * of tests. The testing requirements are going to be documented. Desired 2317 * test requirements are documented at: 2318 * 2319 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2320 * 2321 * Once a new chipset gets properly tested an individual commit can be used 2322 * to document the testing for DFS for that chipset. 2323 */ 2324 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2325 { 2326 2327 switch (ah->hw_version.macVersion) { 2328 /* for temporary testing DFS with 9280 */ 2329 case AR_SREV_VERSION_9280: 2330 /* AR9580 will likely be our first target to get testing on */ 2331 case AR_SREV_VERSION_9580: 2332 return true; 2333 default: 2334 return false; 2335 } 2336 } 2337 2338 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2339 { 2340 struct ath9k_hw_capabilities *pCap = &ah->caps; 2341 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2342 struct ath_common *common = ath9k_hw_common(ah); 2343 2344 u16 eeval; 2345 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2346 2347 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2348 regulatory->current_rd = eeval; 2349 2350 if (ah->opmode != NL80211_IFTYPE_AP && 2351 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2352 if (regulatory->current_rd == 0x64 || 2353 regulatory->current_rd == 0x65) 2354 regulatory->current_rd += 5; 2355 else if (regulatory->current_rd == 0x41) 2356 regulatory->current_rd = 0x43; 2357 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2358 regulatory->current_rd); 2359 } 2360 2361 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2362 2363 if (eeval & AR5416_OPFLAGS_11A) { 2364 if (ah->disable_5ghz) 2365 ath_warn(common, "disabling 5GHz band\n"); 2366 else 2367 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2368 } 2369 2370 if (eeval & AR5416_OPFLAGS_11G) { 2371 if (ah->disable_2ghz) 2372 ath_warn(common, "disabling 2GHz band\n"); 2373 else 2374 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2375 } 2376 2377 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2378 ath_err(common, "both bands are disabled\n"); 2379 return -EINVAL; 2380 } 2381 2382 if (AR_SREV_9485(ah) || 2383 AR_SREV_9285(ah) || 2384 AR_SREV_9330(ah) || 2385 AR_SREV_9565(ah)) 2386 pCap->chip_chainmask = 1; 2387 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2388 pCap->chip_chainmask = 7; 2389 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2390 AR_SREV_9340(ah) || 2391 AR_SREV_9462(ah) || 2392 AR_SREV_9531(ah)) 2393 pCap->chip_chainmask = 3; 2394 else 2395 pCap->chip_chainmask = 7; 2396 2397 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2398 /* 2399 * For AR9271 we will temporarilly uses the rx chainmax as read from 2400 * the EEPROM. 2401 */ 2402 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2403 !(eeval & AR5416_OPFLAGS_11A) && 2404 !(AR_SREV_9271(ah))) 2405 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2406 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2407 else if (AR_SREV_9100(ah)) 2408 pCap->rx_chainmask = 0x7; 2409 else 2410 /* Use rx_chainmask from EEPROM. */ 2411 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2412 2413 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2414 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2415 ah->txchainmask = pCap->tx_chainmask; 2416 ah->rxchainmask = pCap->rx_chainmask; 2417 2418 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2419 2420 /* enable key search for every frame in an aggregate */ 2421 if (AR_SREV_9300_20_OR_LATER(ah)) 2422 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2423 2424 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2425 2426 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2427 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2428 else 2429 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2430 2431 if (AR_SREV_9271(ah)) 2432 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2433 else if (AR_DEVID_7010(ah)) 2434 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2435 else if (AR_SREV_9300_20_OR_LATER(ah)) 2436 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2437 else if (AR_SREV_9287_11_OR_LATER(ah)) 2438 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2439 else if (AR_SREV_9285_12_OR_LATER(ah)) 2440 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2441 else if (AR_SREV_9280_20_OR_LATER(ah)) 2442 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2443 else 2444 pCap->num_gpio_pins = AR_NUM_GPIO; 2445 2446 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2447 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2448 else 2449 pCap->rts_aggr_limit = (8 * 1024); 2450 2451 #ifdef CONFIG_ATH9K_RFKILL 2452 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2453 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2454 ah->rfkill_gpio = 2455 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2456 ah->rfkill_polarity = 2457 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2458 2459 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2460 } 2461 #endif 2462 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2463 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2464 else 2465 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2466 2467 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2468 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2469 else 2470 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2471 2472 if (AR_SREV_9300_20_OR_LATER(ah)) { 2473 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2474 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2475 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2476 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2477 2478 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2479 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2480 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2481 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2482 pCap->txs_len = sizeof(struct ar9003_txs); 2483 } else { 2484 pCap->tx_desc_len = sizeof(struct ath_desc); 2485 if (AR_SREV_9280_20(ah)) 2486 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2487 } 2488 2489 if (AR_SREV_9300_20_OR_LATER(ah)) 2490 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2491 2492 if (AR_SREV_9561(ah)) 2493 ah->ent_mode = 0x3BDA000; 2494 else if (AR_SREV_9300_20_OR_LATER(ah)) 2495 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2496 2497 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2498 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2499 2500 if (AR_SREV_9285(ah)) { 2501 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2502 ant_div_ctl1 = 2503 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2504 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2505 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2506 ath_info(common, "Enable LNA combining\n"); 2507 } 2508 } 2509 } 2510 2511 if (AR_SREV_9300_20_OR_LATER(ah)) { 2512 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2513 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2514 } 2515 2516 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2517 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2518 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2519 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2520 ath_info(common, "Enable LNA combining\n"); 2521 } 2522 } 2523 2524 if (ath9k_hw_dfs_tested(ah)) 2525 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2526 2527 tx_chainmask = pCap->tx_chainmask; 2528 rx_chainmask = pCap->rx_chainmask; 2529 while (tx_chainmask || rx_chainmask) { 2530 if (tx_chainmask & BIT(0)) 2531 pCap->max_txchains++; 2532 if (rx_chainmask & BIT(0)) 2533 pCap->max_rxchains++; 2534 2535 tx_chainmask >>= 1; 2536 rx_chainmask >>= 1; 2537 } 2538 2539 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2540 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2541 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2542 2543 if (AR_SREV_9462_20_OR_LATER(ah)) 2544 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2545 } 2546 2547 if (AR_SREV_9300_20_OR_LATER(ah) && 2548 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2549 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2550 2551 #ifdef CONFIG_ATH9K_WOW 2552 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2553 ah->wow.max_patterns = MAX_NUM_PATTERN; 2554 else 2555 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2556 #endif 2557 2558 return 0; 2559 } 2560 2561 /****************************/ 2562 /* GPIO / RFKILL / Antennae */ 2563 /****************************/ 2564 2565 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2566 u32 gpio, u32 type) 2567 { 2568 int addr; 2569 u32 gpio_shift, tmp; 2570 2571 if (gpio > 11) 2572 addr = AR_GPIO_OUTPUT_MUX3; 2573 else if (gpio > 5) 2574 addr = AR_GPIO_OUTPUT_MUX2; 2575 else 2576 addr = AR_GPIO_OUTPUT_MUX1; 2577 2578 gpio_shift = (gpio % 6) * 5; 2579 2580 if (AR_SREV_9280_20_OR_LATER(ah) 2581 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2582 REG_RMW(ah, addr, (type << gpio_shift), 2583 (0x1f << gpio_shift)); 2584 } else { 2585 tmp = REG_READ(ah, addr); 2586 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2587 tmp &= ~(0x1f << gpio_shift); 2588 tmp |= (type << gpio_shift); 2589 REG_WRITE(ah, addr, tmp); 2590 } 2591 } 2592 2593 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2594 { 2595 u32 gpio_shift; 2596 2597 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2598 2599 if (AR_DEVID_7010(ah)) { 2600 gpio_shift = gpio; 2601 REG_RMW(ah, AR7010_GPIO_OE, 2602 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2603 (AR7010_GPIO_OE_MASK << gpio_shift)); 2604 return; 2605 } 2606 2607 gpio_shift = gpio << 1; 2608 REG_RMW(ah, 2609 AR_GPIO_OE_OUT, 2610 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2611 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2612 } 2613 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2614 2615 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2616 { 2617 #define MS_REG_READ(x, y) \ 2618 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2619 2620 if (gpio >= ah->caps.num_gpio_pins) 2621 return 0xffffffff; 2622 2623 if (AR_DEVID_7010(ah)) { 2624 u32 val; 2625 val = REG_READ(ah, AR7010_GPIO_IN); 2626 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2627 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2628 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2629 AR_GPIO_BIT(gpio)) != 0; 2630 else if (AR_SREV_9271(ah)) 2631 return MS_REG_READ(AR9271, gpio) != 0; 2632 else if (AR_SREV_9287_11_OR_LATER(ah)) 2633 return MS_REG_READ(AR9287, gpio) != 0; 2634 else if (AR_SREV_9285_12_OR_LATER(ah)) 2635 return MS_REG_READ(AR9285, gpio) != 0; 2636 else if (AR_SREV_9280_20_OR_LATER(ah)) 2637 return MS_REG_READ(AR928X, gpio) != 0; 2638 else 2639 return MS_REG_READ(AR, gpio) != 0; 2640 } 2641 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2642 2643 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2644 u32 ah_signal_type) 2645 { 2646 u32 gpio_shift; 2647 2648 if (AR_DEVID_7010(ah)) { 2649 gpio_shift = gpio; 2650 REG_RMW(ah, AR7010_GPIO_OE, 2651 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2652 (AR7010_GPIO_OE_MASK << gpio_shift)); 2653 return; 2654 } 2655 2656 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2657 gpio_shift = 2 * gpio; 2658 REG_RMW(ah, 2659 AR_GPIO_OE_OUT, 2660 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2661 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2662 } 2663 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2664 2665 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2666 { 2667 if (AR_DEVID_7010(ah)) { 2668 val = val ? 0 : 1; 2669 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2670 AR_GPIO_BIT(gpio)); 2671 return; 2672 } 2673 2674 if (AR_SREV_9271(ah)) 2675 val = ~val; 2676 2677 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2678 AR_GPIO_BIT(gpio)); 2679 } 2680 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2681 2682 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2683 { 2684 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2685 } 2686 EXPORT_SYMBOL(ath9k_hw_setantenna); 2687 2688 /*********************/ 2689 /* General Operation */ 2690 /*********************/ 2691 2692 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2693 { 2694 u32 bits = REG_READ(ah, AR_RX_FILTER); 2695 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2696 2697 if (phybits & AR_PHY_ERR_RADAR) 2698 bits |= ATH9K_RX_FILTER_PHYRADAR; 2699 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2700 bits |= ATH9K_RX_FILTER_PHYERR; 2701 2702 return bits; 2703 } 2704 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2705 2706 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2707 { 2708 u32 phybits; 2709 2710 ENABLE_REGWRITE_BUFFER(ah); 2711 2712 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2713 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2714 2715 REG_WRITE(ah, AR_RX_FILTER, bits); 2716 2717 phybits = 0; 2718 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2719 phybits |= AR_PHY_ERR_RADAR; 2720 if (bits & ATH9K_RX_FILTER_PHYERR) 2721 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2722 REG_WRITE(ah, AR_PHY_ERR, phybits); 2723 2724 if (phybits) 2725 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2726 else 2727 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2728 2729 REGWRITE_BUFFER_FLUSH(ah); 2730 } 2731 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2732 2733 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2734 { 2735 if (ath9k_hw_mci_is_enabled(ah)) 2736 ar9003_mci_bt_gain_ctrl(ah); 2737 2738 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2739 return false; 2740 2741 ath9k_hw_init_pll(ah, NULL); 2742 ah->htc_reset_init = true; 2743 return true; 2744 } 2745 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2746 2747 bool ath9k_hw_disable(struct ath_hw *ah) 2748 { 2749 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2750 return false; 2751 2752 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2753 return false; 2754 2755 ath9k_hw_init_pll(ah, NULL); 2756 return true; 2757 } 2758 EXPORT_SYMBOL(ath9k_hw_disable); 2759 2760 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2761 { 2762 enum eeprom_param gain_param; 2763 2764 if (IS_CHAN_2GHZ(chan)) 2765 gain_param = EEP_ANTENNA_GAIN_2G; 2766 else 2767 gain_param = EEP_ANTENNA_GAIN_5G; 2768 2769 return ah->eep_ops->get_eeprom(ah, gain_param); 2770 } 2771 2772 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2773 bool test) 2774 { 2775 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2776 struct ieee80211_channel *channel; 2777 int chan_pwr, new_pwr, max_gain; 2778 int ant_gain, ant_reduction = 0; 2779 2780 if (!chan) 2781 return; 2782 2783 channel = chan->chan; 2784 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2785 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2786 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2787 2788 ant_gain = get_antenna_gain(ah, chan); 2789 if (ant_gain > max_gain) 2790 ant_reduction = ant_gain - max_gain; 2791 2792 ah->eep_ops->set_txpower(ah, chan, 2793 ath9k_regd_get_ctl(reg, chan), 2794 ant_reduction, new_pwr, test); 2795 } 2796 2797 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2798 { 2799 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2800 struct ath9k_channel *chan = ah->curchan; 2801 struct ieee80211_channel *channel = chan->chan; 2802 2803 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2804 if (test) 2805 channel->max_power = MAX_RATE_POWER / 2; 2806 2807 ath9k_hw_apply_txpower(ah, chan, test); 2808 2809 if (test) 2810 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2811 } 2812 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2813 2814 void ath9k_hw_setopmode(struct ath_hw *ah) 2815 { 2816 ath9k_hw_set_operating_mode(ah, ah->opmode); 2817 } 2818 EXPORT_SYMBOL(ath9k_hw_setopmode); 2819 2820 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2821 { 2822 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2823 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2824 } 2825 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2826 2827 void ath9k_hw_write_associd(struct ath_hw *ah) 2828 { 2829 struct ath_common *common = ath9k_hw_common(ah); 2830 2831 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2832 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2833 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2834 } 2835 EXPORT_SYMBOL(ath9k_hw_write_associd); 2836 2837 #define ATH9K_MAX_TSF_READ 10 2838 2839 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2840 { 2841 u32 tsf_lower, tsf_upper1, tsf_upper2; 2842 int i; 2843 2844 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2845 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2846 tsf_lower = REG_READ(ah, AR_TSF_L32); 2847 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2848 if (tsf_upper2 == tsf_upper1) 2849 break; 2850 tsf_upper1 = tsf_upper2; 2851 } 2852 2853 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2854 2855 return (((u64)tsf_upper1 << 32) | tsf_lower); 2856 } 2857 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2858 2859 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2860 { 2861 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2862 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2863 } 2864 EXPORT_SYMBOL(ath9k_hw_settsf64); 2865 2866 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2867 { 2868 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2869 AH_TSF_WRITE_TIMEOUT)) 2870 ath_dbg(ath9k_hw_common(ah), RESET, 2871 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2872 2873 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2874 } 2875 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2876 2877 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2878 { 2879 if (set) 2880 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2881 else 2882 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2883 } 2884 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2885 2886 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2887 { 2888 u32 macmode; 2889 2890 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2891 macmode = AR_2040_JOINED_RX_CLEAR; 2892 else 2893 macmode = 0; 2894 2895 REG_WRITE(ah, AR_2040_MODE, macmode); 2896 } 2897 2898 /* HW Generic timers configuration */ 2899 2900 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2901 { 2902 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2903 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2904 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2905 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2906 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2907 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2908 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2909 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2910 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2911 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2912 AR_NDP2_TIMER_MODE, 0x0002}, 2913 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2914 AR_NDP2_TIMER_MODE, 0x0004}, 2915 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2916 AR_NDP2_TIMER_MODE, 0x0008}, 2917 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2918 AR_NDP2_TIMER_MODE, 0x0010}, 2919 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2920 AR_NDP2_TIMER_MODE, 0x0020}, 2921 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2922 AR_NDP2_TIMER_MODE, 0x0040}, 2923 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2924 AR_NDP2_TIMER_MODE, 0x0080} 2925 }; 2926 2927 /* HW generic timer primitives */ 2928 2929 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2930 { 2931 return REG_READ(ah, AR_TSF_L32); 2932 } 2933 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2934 2935 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 2936 { 2937 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2938 2939 if (timer_table->tsf2_enabled) { 2940 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 2941 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 2942 } 2943 } 2944 2945 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2946 void (*trigger)(void *), 2947 void (*overflow)(void *), 2948 void *arg, 2949 u8 timer_index) 2950 { 2951 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2952 struct ath_gen_timer *timer; 2953 2954 if ((timer_index < AR_FIRST_NDP_TIMER) || 2955 (timer_index >= ATH_MAX_GEN_TIMER)) 2956 return NULL; 2957 2958 if ((timer_index > AR_FIRST_NDP_TIMER) && 2959 !AR_SREV_9300_20_OR_LATER(ah)) 2960 return NULL; 2961 2962 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2963 if (timer == NULL) 2964 return NULL; 2965 2966 /* allocate a hardware generic timer slot */ 2967 timer_table->timers[timer_index] = timer; 2968 timer->index = timer_index; 2969 timer->trigger = trigger; 2970 timer->overflow = overflow; 2971 timer->arg = arg; 2972 2973 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 2974 timer_table->tsf2_enabled = true; 2975 ath9k_hw_gen_timer_start_tsf2(ah); 2976 } 2977 2978 return timer; 2979 } 2980 EXPORT_SYMBOL(ath_gen_timer_alloc); 2981 2982 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2983 struct ath_gen_timer *timer, 2984 u32 timer_next, 2985 u32 timer_period) 2986 { 2987 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2988 u32 mask = 0; 2989 2990 timer_table->timer_mask |= BIT(timer->index); 2991 2992 /* 2993 * Program generic timer registers 2994 */ 2995 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2996 timer_next); 2997 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2998 timer_period); 2999 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3000 gen_tmr_configuration[timer->index].mode_mask); 3001 3002 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3003 /* 3004 * Starting from AR9462, each generic timer can select which tsf 3005 * to use. But we still follow the old rule, 0 - 7 use tsf and 3006 * 8 - 15 use tsf2. 3007 */ 3008 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3009 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3010 (1 << timer->index)); 3011 else 3012 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3013 (1 << timer->index)); 3014 } 3015 3016 if (timer->trigger) 3017 mask |= SM(AR_GENTMR_BIT(timer->index), 3018 AR_IMR_S5_GENTIMER_TRIG); 3019 if (timer->overflow) 3020 mask |= SM(AR_GENTMR_BIT(timer->index), 3021 AR_IMR_S5_GENTIMER_THRESH); 3022 3023 REG_SET_BIT(ah, AR_IMR_S5, mask); 3024 3025 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3026 ah->imask |= ATH9K_INT_GENTIMER; 3027 ath9k_hw_set_interrupts(ah); 3028 } 3029 } 3030 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3031 3032 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3033 { 3034 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3035 3036 /* Clear generic timer enable bits. */ 3037 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3038 gen_tmr_configuration[timer->index].mode_mask); 3039 3040 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3041 /* 3042 * Need to switch back to TSF if it was using TSF2. 3043 */ 3044 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3045 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3046 (1 << timer->index)); 3047 } 3048 } 3049 3050 /* Disable both trigger and thresh interrupt masks */ 3051 REG_CLR_BIT(ah, AR_IMR_S5, 3052 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3053 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3054 3055 timer_table->timer_mask &= ~BIT(timer->index); 3056 3057 if (timer_table->timer_mask == 0) { 3058 ah->imask &= ~ATH9K_INT_GENTIMER; 3059 ath9k_hw_set_interrupts(ah); 3060 } 3061 } 3062 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3063 3064 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3065 { 3066 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3067 3068 /* free the hardware generic timer slot */ 3069 timer_table->timers[timer->index] = NULL; 3070 kfree(timer); 3071 } 3072 EXPORT_SYMBOL(ath_gen_timer_free); 3073 3074 /* 3075 * Generic Timer Interrupts handling 3076 */ 3077 void ath_gen_timer_isr(struct ath_hw *ah) 3078 { 3079 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3080 struct ath_gen_timer *timer; 3081 unsigned long trigger_mask, thresh_mask; 3082 unsigned int index; 3083 3084 /* get hardware generic timer interrupt status */ 3085 trigger_mask = ah->intr_gen_timer_trigger; 3086 thresh_mask = ah->intr_gen_timer_thresh; 3087 trigger_mask &= timer_table->timer_mask; 3088 thresh_mask &= timer_table->timer_mask; 3089 3090 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3091 timer = timer_table->timers[index]; 3092 if (!timer) 3093 continue; 3094 if (!timer->overflow) 3095 continue; 3096 3097 trigger_mask &= ~BIT(index); 3098 timer->overflow(timer->arg); 3099 } 3100 3101 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3102 timer = timer_table->timers[index]; 3103 if (!timer) 3104 continue; 3105 if (!timer->trigger) 3106 continue; 3107 timer->trigger(timer->arg); 3108 } 3109 } 3110 EXPORT_SYMBOL(ath_gen_timer_isr); 3111 3112 /********/ 3113 /* HTC */ 3114 /********/ 3115 3116 static struct { 3117 u32 version; 3118 const char * name; 3119 } ath_mac_bb_names[] = { 3120 /* Devices with external radios */ 3121 { AR_SREV_VERSION_5416_PCI, "5416" }, 3122 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3123 { AR_SREV_VERSION_9100, "9100" }, 3124 { AR_SREV_VERSION_9160, "9160" }, 3125 /* Single-chip solutions */ 3126 { AR_SREV_VERSION_9280, "9280" }, 3127 { AR_SREV_VERSION_9285, "9285" }, 3128 { AR_SREV_VERSION_9287, "9287" }, 3129 { AR_SREV_VERSION_9271, "9271" }, 3130 { AR_SREV_VERSION_9300, "9300" }, 3131 { AR_SREV_VERSION_9330, "9330" }, 3132 { AR_SREV_VERSION_9340, "9340" }, 3133 { AR_SREV_VERSION_9485, "9485" }, 3134 { AR_SREV_VERSION_9462, "9462" }, 3135 { AR_SREV_VERSION_9550, "9550" }, 3136 { AR_SREV_VERSION_9565, "9565" }, 3137 { AR_SREV_VERSION_9531, "9531" }, 3138 }; 3139 3140 /* For devices with external radios */ 3141 static struct { 3142 u16 version; 3143 const char * name; 3144 } ath_rf_names[] = { 3145 { 0, "5133" }, 3146 { AR_RAD5133_SREV_MAJOR, "5133" }, 3147 { AR_RAD5122_SREV_MAJOR, "5122" }, 3148 { AR_RAD2133_SREV_MAJOR, "2133" }, 3149 { AR_RAD2122_SREV_MAJOR, "2122" } 3150 }; 3151 3152 /* 3153 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3154 */ 3155 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3156 { 3157 int i; 3158 3159 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3160 if (ath_mac_bb_names[i].version == mac_bb_version) { 3161 return ath_mac_bb_names[i].name; 3162 } 3163 } 3164 3165 return "????"; 3166 } 3167 3168 /* 3169 * Return the RF name. "????" is returned if the RF is unknown. 3170 * Used for devices with external radios. 3171 */ 3172 static const char *ath9k_hw_rf_name(u16 rf_version) 3173 { 3174 int i; 3175 3176 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3177 if (ath_rf_names[i].version == rf_version) { 3178 return ath_rf_names[i].name; 3179 } 3180 } 3181 3182 return "????"; 3183 } 3184 3185 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3186 { 3187 int used; 3188 3189 /* chipsets >= AR9280 are single-chip */ 3190 if (AR_SREV_9280_20_OR_LATER(ah)) { 3191 used = scnprintf(hw_name, len, 3192 "Atheros AR%s Rev:%x", 3193 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3194 ah->hw_version.macRev); 3195 } 3196 else { 3197 used = scnprintf(hw_name, len, 3198 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3199 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3200 ah->hw_version.macRev, 3201 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3202 & AR_RADIO_SREV_MAJOR)), 3203 ah->hw_version.phyRev); 3204 } 3205 3206 hw_name[used] = '\0'; 3207 } 3208 EXPORT_SYMBOL(ath9k_hw_name); 3209