1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <asm/unaligned.h> 23 24 #include "hw.h" 25 #include "hw-ops.h" 26 #include "ar9003_mac.h" 27 #include "ar9003_mci.h" 28 #include "ar9003_phy.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 39 { 40 struct ath_common *common = ath9k_hw_common(ah); 41 struct ath9k_channel *chan = ah->curchan; 42 unsigned int clockrate; 43 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 46 clockrate = 117; 47 else if (!chan) /* should really check for CCK instead */ 48 clockrate = ATH9K_CLOCK_RATE_CCK; 49 else if (IS_CHAN_2GHZ(chan)) 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 53 else 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 55 56 if (chan) { 57 if (IS_CHAN_HT40(chan)) 58 clockrate *= 2; 59 if (IS_CHAN_HALF_RATE(chan)) 60 clockrate /= 2; 61 if (IS_CHAN_QUARTER_RATE(chan)) 62 clockrate /= 4; 63 } 64 65 common->clockrate = clockrate; 66 } 67 68 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 69 { 70 struct ath_common *common = ath9k_hw_common(ah); 71 72 return usecs * common->clockrate; 73 } 74 75 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 76 { 77 int i; 78 79 BUG_ON(timeout < AH_TIME_QUANTUM); 80 81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 82 if ((REG_READ(ah, reg) & mask) == val) 83 return true; 84 85 udelay(AH_TIME_QUANTUM); 86 } 87 88 ath_dbg(ath9k_hw_common(ah), ANY, 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 90 timeout, reg, REG_READ(ah, reg), mask, val); 91 92 return false; 93 } 94 EXPORT_SYMBOL(ath9k_hw_wait); 95 96 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 97 int hw_delay) 98 { 99 hw_delay /= 10; 100 101 if (IS_CHAN_HALF_RATE(chan)) 102 hw_delay *= 2; 103 else if (IS_CHAN_QUARTER_RATE(chan)) 104 hw_delay *= 4; 105 106 udelay(hw_delay + BASE_ACTIVATE_DELAY); 107 } 108 109 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 110 int column, unsigned int *writecnt) 111 { 112 int r; 113 114 ENABLE_REGWRITE_BUFFER(ah); 115 for (r = 0; r < array->ia_rows; r++) { 116 REG_WRITE(ah, INI_RA(array, r, 0), 117 INI_RA(array, r, column)); 118 DO_DELAY(*writecnt); 119 } 120 REGWRITE_BUFFER_FLUSH(ah); 121 } 122 123 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 124 { 125 u32 retval; 126 int i; 127 128 for (i = 0, retval = 0; i < n; i++) { 129 retval = (retval << 1) | (val & 1); 130 val >>= 1; 131 } 132 return retval; 133 } 134 135 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 136 u8 phy, int kbps, 137 u32 frameLen, u16 rateix, 138 bool shortPreamble) 139 { 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 141 142 if (kbps == 0) 143 return 0; 144 145 switch (phy) { 146 case WLAN_RC_PHY_CCK: 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 148 if (shortPreamble) 149 phyTime >>= 1; 150 numBits = frameLen << 3; 151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 152 break; 153 case WLAN_RC_PHY_OFDM: 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 156 numBits = OFDM_PLCP_BITS + (frameLen << 3); 157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 158 txTime = OFDM_SIFS_TIME_QUARTER 159 + OFDM_PREAMBLE_TIME_QUARTER 160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 161 } else if (ah->curchan && 162 IS_CHAN_HALF_RATE(ah->curchan)) { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME_HALF + 167 OFDM_PREAMBLE_TIME_HALF 168 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 169 } else { 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 171 numBits = OFDM_PLCP_BITS + (frameLen << 3); 172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 174 + (numSymbols * OFDM_SYMBOL_TIME); 175 } 176 break; 177 default: 178 ath_err(ath9k_hw_common(ah), 179 "Unknown phy %u (rate ix %u)\n", phy, rateix); 180 txTime = 0; 181 break; 182 } 183 184 return txTime; 185 } 186 EXPORT_SYMBOL(ath9k_hw_computetxtime); 187 188 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 189 struct ath9k_channel *chan, 190 struct chan_centers *centers) 191 { 192 int8_t extoff; 193 194 if (!IS_CHAN_HT40(chan)) { 195 centers->ctl_center = centers->ext_center = 196 centers->synth_center = chan->channel; 197 return; 198 } 199 200 if (IS_CHAN_HT40PLUS(chan)) { 201 centers->synth_center = 202 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 203 extoff = 1; 204 } else { 205 centers->synth_center = 206 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 207 extoff = -1; 208 } 209 210 centers->ctl_center = 211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 212 /* 25 MHz spacing is supported by hw but not on upper layers */ 213 centers->ext_center = 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 215 } 216 217 /******************/ 218 /* Chip Revisions */ 219 /******************/ 220 221 static void ath9k_hw_read_revisions(struct ath_hw *ah) 222 { 223 u32 val; 224 225 if (ah->get_mac_revision) 226 ah->hw_version.macRev = ah->get_mac_revision(); 227 228 switch (ah->hw_version.devid) { 229 case AR5416_AR9100_DEVID: 230 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 231 break; 232 case AR9300_DEVID_AR9330: 233 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 234 if (!ah->get_mac_revision) { 235 val = REG_READ(ah, AR_SREV); 236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 237 } 238 return; 239 case AR9300_DEVID_AR9340: 240 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 241 return; 242 case AR9300_DEVID_QCA955X: 243 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 244 return; 245 case AR9300_DEVID_AR953X: 246 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 247 return; 248 } 249 250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 251 252 if (val == 0xFF) { 253 val = REG_READ(ah, AR_SREV); 254 ah->hw_version.macVersion = 255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 257 258 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 259 ah->is_pciexpress = true; 260 else 261 ah->is_pciexpress = (val & 262 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 263 } else { 264 if (!AR_SREV_9100(ah)) 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 266 267 ah->hw_version.macRev = val & AR_SREV_REVISION; 268 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 270 ah->is_pciexpress = true; 271 } 272 } 273 274 /************************************/ 275 /* HW Attach, Detach, Init Routines */ 276 /************************************/ 277 278 static void ath9k_hw_disablepcie(struct ath_hw *ah) 279 { 280 if (!AR_SREV_5416(ah)) 281 return; 282 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 292 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 294 } 295 296 /* This should work for all families including legacy */ 297 static bool ath9k_hw_chip_test(struct ath_hw *ah) 298 { 299 struct ath_common *common = ath9k_hw_common(ah); 300 u32 regAddr[2] = { AR_STA_ID0 }; 301 u32 regHold[2]; 302 static const u32 patternData[4] = { 303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 304 }; 305 int i, j, loop_max; 306 307 if (!AR_SREV_9300_20_OR_LATER(ah)) { 308 loop_max = 2; 309 regAddr[1] = AR_PHY_BASE + (8 << 2); 310 } else 311 loop_max = 1; 312 313 for (i = 0; i < loop_max; i++) { 314 u32 addr = regAddr[i]; 315 u32 wrData, rdData; 316 317 regHold[i] = REG_READ(ah, addr); 318 for (j = 0; j < 0x100; j++) { 319 wrData = (j << 16) | j; 320 REG_WRITE(ah, addr, wrData); 321 rdData = REG_READ(ah, addr); 322 if (rdData != wrData) { 323 ath_err(common, 324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 325 addr, wrData, rdData); 326 return false; 327 } 328 } 329 for (j = 0; j < 4; j++) { 330 wrData = patternData[j]; 331 REG_WRITE(ah, addr, wrData); 332 rdData = REG_READ(ah, addr); 333 if (wrData != rdData) { 334 ath_err(common, 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 336 addr, wrData, rdData); 337 return false; 338 } 339 } 340 REG_WRITE(ah, regAddr[i], regHold[i]); 341 } 342 udelay(100); 343 344 return true; 345 } 346 347 static void ath9k_hw_init_config(struct ath_hw *ah) 348 { 349 struct ath_common *common = ath9k_hw_common(ah); 350 351 ah->config.dma_beacon_response_time = 1; 352 ah->config.sw_beacon_response_time = 6; 353 ah->config.cwm_ignore_extcca = 0; 354 ah->config.analog_shiftreg = 1; 355 356 ah->config.rx_intr_mitigation = true; 357 358 if (AR_SREV_9300_20_OR_LATER(ah)) { 359 ah->config.rimt_last = 500; 360 ah->config.rimt_first = 2000; 361 } else { 362 ah->config.rimt_last = 250; 363 ah->config.rimt_first = 700; 364 } 365 366 /* 367 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 368 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 369 * This means we use it for all AR5416 devices, and the few 370 * minor PCI AR9280 devices out there. 371 * 372 * Serialization is required because these devices do not handle 373 * well the case of two concurrent reads/writes due to the latency 374 * involved. During one read/write another read/write can be issued 375 * on another CPU while the previous read/write may still be working 376 * on our hardware, if we hit this case the hardware poops in a loop. 377 * We prevent this by serializing reads and writes. 378 * 379 * This issue is not present on PCI-Express devices or pre-AR5416 380 * devices (legacy, 802.11abg). 381 */ 382 if (num_possible_cpus() > 1) 383 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 384 385 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 386 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 387 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 388 !ah->is_pciexpress)) { 389 ah->config.serialize_regmode = SER_REG_MODE_ON; 390 } else { 391 ah->config.serialize_regmode = SER_REG_MODE_OFF; 392 } 393 } 394 395 ath_dbg(common, RESET, "serialize_regmode is %d\n", 396 ah->config.serialize_regmode); 397 398 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 399 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 400 else 401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 402 } 403 404 static void ath9k_hw_init_defaults(struct ath_hw *ah) 405 { 406 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 407 408 regulatory->country_code = CTRY_DEFAULT; 409 regulatory->power_limit = MAX_RATE_POWER; 410 411 ah->hw_version.magic = AR5416_MAGIC; 412 ah->hw_version.subvendorid = 0; 413 414 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 415 AR_STA_ID1_MCAST_KSRCH; 416 if (AR_SREV_9100(ah)) 417 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 418 419 ah->slottime = ATH9K_SLOT_TIME_9; 420 ah->globaltxtimeout = (u32) -1; 421 ah->power_mode = ATH9K_PM_UNDEFINED; 422 ah->htc_reset_init = true; 423 424 ah->ani_function = ATH9K_ANI_ALL; 425 if (!AR_SREV_9300_20_OR_LATER(ah)) 426 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 427 428 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 429 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 430 else 431 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 432 } 433 434 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 435 { 436 struct ath_common *common = ath9k_hw_common(ah); 437 u32 sum; 438 int i; 439 u16 eeval; 440 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 441 442 sum = 0; 443 for (i = 0; i < 3; i++) { 444 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 445 sum += eeval; 446 common->macaddr[2 * i] = eeval >> 8; 447 common->macaddr[2 * i + 1] = eeval & 0xff; 448 } 449 if (sum == 0 || sum == 0xffff * 3) 450 return -EADDRNOTAVAIL; 451 452 return 0; 453 } 454 455 static int ath9k_hw_post_init(struct ath_hw *ah) 456 { 457 struct ath_common *common = ath9k_hw_common(ah); 458 int ecode; 459 460 if (common->bus_ops->ath_bus_type != ATH_USB) { 461 if (!ath9k_hw_chip_test(ah)) 462 return -ENODEV; 463 } 464 465 if (!AR_SREV_9300_20_OR_LATER(ah)) { 466 ecode = ar9002_hw_rf_claim(ah); 467 if (ecode != 0) 468 return ecode; 469 } 470 471 ecode = ath9k_hw_eeprom_init(ah); 472 if (ecode != 0) 473 return ecode; 474 475 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 476 ah->eep_ops->get_eeprom_ver(ah), 477 ah->eep_ops->get_eeprom_rev(ah)); 478 479 ath9k_hw_ani_init(ah); 480 481 /* 482 * EEPROM needs to be initialized before we do this. 483 * This is required for regulatory compliance. 484 */ 485 if (AR_SREV_9300_20_OR_LATER(ah)) { 486 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 487 if ((regdmn & 0xF0) == CTL_FCC) { 488 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 489 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 490 } 491 } 492 493 return 0; 494 } 495 496 static int ath9k_hw_attach_ops(struct ath_hw *ah) 497 { 498 if (!AR_SREV_9300_20_OR_LATER(ah)) 499 return ar9002_hw_attach_ops(ah); 500 501 ar9003_hw_attach_ops(ah); 502 return 0; 503 } 504 505 /* Called for all hardware families */ 506 static int __ath9k_hw_init(struct ath_hw *ah) 507 { 508 struct ath_common *common = ath9k_hw_common(ah); 509 int r = 0; 510 511 ath9k_hw_read_revisions(ah); 512 513 switch (ah->hw_version.macVersion) { 514 case AR_SREV_VERSION_5416_PCI: 515 case AR_SREV_VERSION_5416_PCIE: 516 case AR_SREV_VERSION_9160: 517 case AR_SREV_VERSION_9100: 518 case AR_SREV_VERSION_9280: 519 case AR_SREV_VERSION_9285: 520 case AR_SREV_VERSION_9287: 521 case AR_SREV_VERSION_9271: 522 case AR_SREV_VERSION_9300: 523 case AR_SREV_VERSION_9330: 524 case AR_SREV_VERSION_9485: 525 case AR_SREV_VERSION_9340: 526 case AR_SREV_VERSION_9462: 527 case AR_SREV_VERSION_9550: 528 case AR_SREV_VERSION_9565: 529 case AR_SREV_VERSION_9531: 530 break; 531 default: 532 ath_err(common, 533 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 534 ah->hw_version.macVersion, ah->hw_version.macRev); 535 return -EOPNOTSUPP; 536 } 537 538 /* 539 * Read back AR_WA into a permanent copy and set bits 14 and 17. 540 * We need to do this to avoid RMW of this register. We cannot 541 * read the reg when chip is asleep. 542 */ 543 if (AR_SREV_9300_20_OR_LATER(ah)) { 544 ah->WARegVal = REG_READ(ah, AR_WA); 545 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 546 AR_WA_ASPM_TIMER_BASED_DISABLE); 547 } 548 549 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 550 ath_err(common, "Couldn't reset chip\n"); 551 return -EIO; 552 } 553 554 if (AR_SREV_9565(ah)) { 555 ah->WARegVal |= AR_WA_BIT22; 556 REG_WRITE(ah, AR_WA, ah->WARegVal); 557 } 558 559 ath9k_hw_init_defaults(ah); 560 ath9k_hw_init_config(ah); 561 562 r = ath9k_hw_attach_ops(ah); 563 if (r) 564 return r; 565 566 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 567 ath_err(common, "Couldn't wakeup chip\n"); 568 return -EIO; 569 } 570 571 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 572 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 573 ah->is_pciexpress = false; 574 575 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 576 ath9k_hw_init_cal_settings(ah); 577 578 if (!ah->is_pciexpress) 579 ath9k_hw_disablepcie(ah); 580 581 r = ath9k_hw_post_init(ah); 582 if (r) 583 return r; 584 585 ath9k_hw_init_mode_gain_regs(ah); 586 r = ath9k_hw_fill_cap_info(ah); 587 if (r) 588 return r; 589 590 r = ath9k_hw_init_macaddr(ah); 591 if (r) { 592 ath_err(common, "Failed to initialize MAC address\n"); 593 return r; 594 } 595 596 ath9k_hw_init_hang_checks(ah); 597 598 common->state = ATH_HW_INITIALIZED; 599 600 return 0; 601 } 602 603 int ath9k_hw_init(struct ath_hw *ah) 604 { 605 int ret; 606 struct ath_common *common = ath9k_hw_common(ah); 607 608 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 609 switch (ah->hw_version.devid) { 610 case AR5416_DEVID_PCI: 611 case AR5416_DEVID_PCIE: 612 case AR5416_AR9100_DEVID: 613 case AR9160_DEVID_PCI: 614 case AR9280_DEVID_PCI: 615 case AR9280_DEVID_PCIE: 616 case AR9285_DEVID_PCIE: 617 case AR9287_DEVID_PCI: 618 case AR9287_DEVID_PCIE: 619 case AR2427_DEVID_PCIE: 620 case AR9300_DEVID_PCIE: 621 case AR9300_DEVID_AR9485_PCIE: 622 case AR9300_DEVID_AR9330: 623 case AR9300_DEVID_AR9340: 624 case AR9300_DEVID_QCA955X: 625 case AR9300_DEVID_AR9580: 626 case AR9300_DEVID_AR9462: 627 case AR9485_DEVID_AR1111: 628 case AR9300_DEVID_AR9565: 629 case AR9300_DEVID_AR953X: 630 break; 631 default: 632 if (common->bus_ops->ath_bus_type == ATH_USB) 633 break; 634 ath_err(common, "Hardware device ID 0x%04x not supported\n", 635 ah->hw_version.devid); 636 return -EOPNOTSUPP; 637 } 638 639 ret = __ath9k_hw_init(ah); 640 if (ret) { 641 ath_err(common, 642 "Unable to initialize hardware; initialization status: %d\n", 643 ret); 644 return ret; 645 } 646 647 ath_dynack_init(ah); 648 649 return 0; 650 } 651 EXPORT_SYMBOL(ath9k_hw_init); 652 653 static void ath9k_hw_init_qos(struct ath_hw *ah) 654 { 655 ENABLE_REGWRITE_BUFFER(ah); 656 657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 659 660 REG_WRITE(ah, AR_QOS_NO_ACK, 661 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 662 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 663 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 664 665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 670 671 REGWRITE_BUFFER_FLUSH(ah); 672 } 673 674 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 675 { 676 struct ath_common *common = ath9k_hw_common(ah); 677 int i = 0; 678 679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 680 udelay(100); 681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 682 683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 684 685 udelay(100); 686 687 if (WARN_ON_ONCE(i >= 100)) { 688 ath_err(common, "PLL4 meaurement not done\n"); 689 break; 690 } 691 692 i++; 693 } 694 695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 696 } 697 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 698 699 static void ath9k_hw_init_pll(struct ath_hw *ah, 700 struct ath9k_channel *chan) 701 { 702 u32 pll; 703 704 pll = ath9k_hw_compute_pll_control(ah, chan); 705 706 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 707 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 709 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 711 AR_CH0_DPLL2_KD, 0x40); 712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 713 AR_CH0_DPLL2_KI, 0x4); 714 715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 716 AR_CH0_BB_DPLL1_REFDIV, 0x5); 717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 718 AR_CH0_BB_DPLL1_NINI, 0x58); 719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 720 AR_CH0_BB_DPLL1_NFRAC, 0x0); 721 722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 723 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 725 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 727 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 728 729 /* program BB PLL phase_shift to 0x6 */ 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 731 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 732 733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 734 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 735 udelay(1000); 736 } else if (AR_SREV_9330(ah)) { 737 u32 ddr_dpll2, pll_control2, kd; 738 739 if (ah->is_clk_25mhz) { 740 ddr_dpll2 = 0x18e82f01; 741 pll_control2 = 0xe04a3d; 742 kd = 0x1d; 743 } else { 744 ddr_dpll2 = 0x19e82f01; 745 pll_control2 = 0x886666; 746 kd = 0x3d; 747 } 748 749 /* program DDR PLL ki and kd value */ 750 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 751 752 /* program DDR PLL phase_shift */ 753 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 754 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 755 756 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 757 pll | AR_RTC_9300_PLL_BYPASS); 758 udelay(1000); 759 760 /* program refdiv, nint, frac to RTC register */ 761 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 762 763 /* program BB PLL kd and ki value */ 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 766 767 /* program BB PLL phase_shift */ 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 769 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 770 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 771 u32 regval, pll2_divint, pll2_divfrac, refdiv; 772 773 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 774 pll | AR_RTC_9300_SOC_PLL_BYPASS); 775 udelay(1000); 776 777 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 778 udelay(100); 779 780 if (ah->is_clk_25mhz) { 781 if (AR_SREV_9531(ah)) { 782 pll2_divint = 0x1c; 783 pll2_divfrac = 0xa3d2; 784 refdiv = 1; 785 } else { 786 pll2_divint = 0x54; 787 pll2_divfrac = 0x1eb85; 788 refdiv = 3; 789 } 790 } else { 791 if (AR_SREV_9340(ah)) { 792 pll2_divint = 88; 793 pll2_divfrac = 0; 794 refdiv = 5; 795 } else { 796 pll2_divint = 0x11; 797 pll2_divfrac = 798 AR_SREV_9531(ah) ? 0x26665 : 0x26666; 799 refdiv = 1; 800 } 801 } 802 803 regval = REG_READ(ah, AR_PHY_PLL_MODE); 804 if (AR_SREV_9531(ah)) 805 regval |= (0x1 << 22); 806 else 807 regval |= (0x1 << 16); 808 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 809 udelay(100); 810 811 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 812 (pll2_divint << 18) | pll2_divfrac); 813 udelay(100); 814 815 regval = REG_READ(ah, AR_PHY_PLL_MODE); 816 if (AR_SREV_9340(ah)) 817 regval = (regval & 0x80071fff) | 818 (0x1 << 30) | 819 (0x1 << 13) | 820 (0x4 << 26) | 821 (0x18 << 19); 822 else if (AR_SREV_9531(ah)) 823 regval = (regval & 0x01c00fff) | 824 (0x1 << 31) | 825 (0x2 << 29) | 826 (0xa << 25) | 827 (0x1 << 19) | 828 (0x6 << 12); 829 else 830 regval = (regval & 0x80071fff) | 831 (0x3 << 30) | 832 (0x1 << 13) | 833 (0x4 << 26) | 834 (0x60 << 19); 835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 836 837 if (AR_SREV_9531(ah)) 838 REG_WRITE(ah, AR_PHY_PLL_MODE, 839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 840 else 841 REG_WRITE(ah, AR_PHY_PLL_MODE, 842 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 843 844 udelay(1000); 845 } 846 847 if (AR_SREV_9565(ah)) 848 pll |= 0x40000; 849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 850 851 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 852 AR_SREV_9550(ah)) 853 udelay(1000); 854 855 /* Switch the core clock for ar9271 to 117Mhz */ 856 if (AR_SREV_9271(ah)) { 857 udelay(500); 858 REG_WRITE(ah, 0x50040, 0x304); 859 } 860 861 udelay(RTC_PLL_SETTLE_DELAY); 862 863 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 864 865 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 866 if (ah->is_clk_25mhz) { 867 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 868 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 869 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 870 } else { 871 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 872 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 873 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 874 } 875 udelay(100); 876 } 877 } 878 879 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 880 enum nl80211_iftype opmode) 881 { 882 u32 sync_default = AR_INTR_SYNC_DEFAULT; 883 u32 imr_reg = AR_IMR_TXERR | 884 AR_IMR_TXURN | 885 AR_IMR_RXERR | 886 AR_IMR_RXORN | 887 AR_IMR_BCNMISC; 888 889 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 890 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 891 892 if (AR_SREV_9300_20_OR_LATER(ah)) { 893 imr_reg |= AR_IMR_RXOK_HP; 894 if (ah->config.rx_intr_mitigation) 895 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 896 else 897 imr_reg |= AR_IMR_RXOK_LP; 898 899 } else { 900 if (ah->config.rx_intr_mitigation) 901 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 902 else 903 imr_reg |= AR_IMR_RXOK; 904 } 905 906 if (ah->config.tx_intr_mitigation) 907 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 908 else 909 imr_reg |= AR_IMR_TXOK; 910 911 ENABLE_REGWRITE_BUFFER(ah); 912 913 REG_WRITE(ah, AR_IMR, imr_reg); 914 ah->imrs2_reg |= AR_IMR_S2_GTT; 915 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 916 917 if (!AR_SREV_9100(ah)) { 918 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 919 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 920 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 921 } 922 923 REGWRITE_BUFFER_FLUSH(ah); 924 925 if (AR_SREV_9300_20_OR_LATER(ah)) { 926 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 927 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 928 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 929 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 930 } 931 } 932 933 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 934 { 935 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 936 val = min(val, (u32) 0xFFFF); 937 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 938 } 939 940 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 941 { 942 u32 val = ath9k_hw_mac_to_clks(ah, us); 943 val = min(val, (u32) 0xFFFF); 944 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 945 } 946 947 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 948 { 949 u32 val = ath9k_hw_mac_to_clks(ah, us); 950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 952 } 953 954 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 955 { 956 u32 val = ath9k_hw_mac_to_clks(ah, us); 957 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 958 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 959 } 960 961 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 962 { 963 if (tu > 0xFFFF) { 964 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 965 tu); 966 ah->globaltxtimeout = (u32) -1; 967 return false; 968 } else { 969 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 970 ah->globaltxtimeout = tu; 971 return true; 972 } 973 } 974 975 void ath9k_hw_init_global_settings(struct ath_hw *ah) 976 { 977 struct ath_common *common = ath9k_hw_common(ah); 978 const struct ath9k_channel *chan = ah->curchan; 979 int acktimeout, ctstimeout, ack_offset = 0; 980 int slottime; 981 int sifstime; 982 int rx_lat = 0, tx_lat = 0, eifs = 0; 983 u32 reg; 984 985 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 986 ah->misc_mode); 987 988 if (!chan) 989 return; 990 991 if (ah->misc_mode != 0) 992 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 993 994 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 995 rx_lat = 41; 996 else 997 rx_lat = 37; 998 tx_lat = 54; 999 1000 if (IS_CHAN_5GHZ(chan)) 1001 sifstime = 16; 1002 else 1003 sifstime = 10; 1004 1005 if (IS_CHAN_HALF_RATE(chan)) { 1006 eifs = 175; 1007 rx_lat *= 2; 1008 tx_lat *= 2; 1009 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1010 tx_lat += 11; 1011 1012 sifstime = 32; 1013 ack_offset = 16; 1014 slottime = 13; 1015 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1016 eifs = 340; 1017 rx_lat = (rx_lat * 4) - 1; 1018 tx_lat *= 4; 1019 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1020 tx_lat += 22; 1021 1022 sifstime = 64; 1023 ack_offset = 32; 1024 slottime = 21; 1025 } else { 1026 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1027 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1028 reg = AR_USEC_ASYNC_FIFO; 1029 } else { 1030 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1031 common->clockrate; 1032 reg = REG_READ(ah, AR_USEC); 1033 } 1034 rx_lat = MS(reg, AR_USEC_RX_LAT); 1035 tx_lat = MS(reg, AR_USEC_TX_LAT); 1036 1037 slottime = ah->slottime; 1038 } 1039 1040 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1041 slottime += 3 * ah->coverage_class; 1042 acktimeout = slottime + sifstime + ack_offset; 1043 ctstimeout = acktimeout; 1044 1045 /* 1046 * Workaround for early ACK timeouts, add an offset to match the 1047 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1048 * This was initially only meant to work around an issue with delayed 1049 * BA frames in some implementations, but it has been found to fix ACK 1050 * timeout issues in other cases as well. 1051 */ 1052 if (IS_CHAN_2GHZ(chan) && 1053 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1054 acktimeout += 64 - sifstime - ah->slottime; 1055 ctstimeout += 48 - sifstime - ah->slottime; 1056 } 1057 1058 if (ah->dynack.enabled) { 1059 acktimeout = ah->dynack.ackto; 1060 ctstimeout = acktimeout; 1061 slottime = (acktimeout - 3) / 2; 1062 } else { 1063 ah->dynack.ackto = acktimeout; 1064 } 1065 1066 ath9k_hw_set_sifs_time(ah, sifstime); 1067 ath9k_hw_setslottime(ah, slottime); 1068 ath9k_hw_set_ack_timeout(ah, acktimeout); 1069 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1070 if (ah->globaltxtimeout != (u32) -1) 1071 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1072 1073 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1074 REG_RMW(ah, AR_USEC, 1075 (common->clockrate - 1) | 1076 SM(rx_lat, AR_USEC_RX_LAT) | 1077 SM(tx_lat, AR_USEC_TX_LAT), 1078 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1079 1080 } 1081 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1082 1083 void ath9k_hw_deinit(struct ath_hw *ah) 1084 { 1085 struct ath_common *common = ath9k_hw_common(ah); 1086 1087 if (common->state < ATH_HW_INITIALIZED) 1088 return; 1089 1090 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1091 } 1092 EXPORT_SYMBOL(ath9k_hw_deinit); 1093 1094 /*******/ 1095 /* INI */ 1096 /*******/ 1097 1098 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1099 { 1100 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1101 1102 if (IS_CHAN_2GHZ(chan)) 1103 ctl |= CTL_11G; 1104 else 1105 ctl |= CTL_11A; 1106 1107 return ctl; 1108 } 1109 1110 /****************************************/ 1111 /* Reset and Channel Switching Routines */ 1112 /****************************************/ 1113 1114 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1115 { 1116 struct ath_common *common = ath9k_hw_common(ah); 1117 int txbuf_size; 1118 1119 ENABLE_REGWRITE_BUFFER(ah); 1120 1121 /* 1122 * set AHB_MODE not to do cacheline prefetches 1123 */ 1124 if (!AR_SREV_9300_20_OR_LATER(ah)) 1125 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1126 1127 /* 1128 * let mac dma reads be in 128 byte chunks 1129 */ 1130 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1131 1132 REGWRITE_BUFFER_FLUSH(ah); 1133 1134 /* 1135 * Restore TX Trigger Level to its pre-reset value. 1136 * The initial value depends on whether aggregation is enabled, and is 1137 * adjusted whenever underruns are detected. 1138 */ 1139 if (!AR_SREV_9300_20_OR_LATER(ah)) 1140 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1141 1142 ENABLE_REGWRITE_BUFFER(ah); 1143 1144 /* 1145 * let mac dma writes be in 128 byte chunks 1146 */ 1147 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1148 1149 /* 1150 * Setup receive FIFO threshold to hold off TX activities 1151 */ 1152 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1153 1154 if (AR_SREV_9300_20_OR_LATER(ah)) { 1155 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1156 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1157 1158 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1159 ah->caps.rx_status_len); 1160 } 1161 1162 /* 1163 * reduce the number of usable entries in PCU TXBUF to avoid 1164 * wrap around issues. 1165 */ 1166 if (AR_SREV_9285(ah)) { 1167 /* For AR9285 the number of Fifos are reduced to half. 1168 * So set the usable tx buf size also to half to 1169 * avoid data/delimiter underruns 1170 */ 1171 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1172 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1173 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1174 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1175 } else { 1176 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1177 } 1178 1179 if (!AR_SREV_9271(ah)) 1180 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1181 1182 REGWRITE_BUFFER_FLUSH(ah); 1183 1184 if (AR_SREV_9300_20_OR_LATER(ah)) 1185 ath9k_hw_reset_txstatus_ring(ah); 1186 } 1187 1188 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1189 { 1190 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1191 u32 set = AR_STA_ID1_KSRCH_MODE; 1192 1193 switch (opmode) { 1194 case NL80211_IFTYPE_ADHOC: 1195 if (!AR_SREV_9340_13(ah)) { 1196 set |= AR_STA_ID1_ADHOC; 1197 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1198 break; 1199 } 1200 /* fall through */ 1201 case NL80211_IFTYPE_MESH_POINT: 1202 case NL80211_IFTYPE_AP: 1203 set |= AR_STA_ID1_STA_AP; 1204 /* fall through */ 1205 case NL80211_IFTYPE_STATION: 1206 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1207 break; 1208 default: 1209 if (!ah->is_monitoring) 1210 set = 0; 1211 break; 1212 } 1213 REG_RMW(ah, AR_STA_ID1, set, mask); 1214 } 1215 1216 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1217 u32 *coef_mantissa, u32 *coef_exponent) 1218 { 1219 u32 coef_exp, coef_man; 1220 1221 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1222 if ((coef_scaled >> coef_exp) & 0x1) 1223 break; 1224 1225 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1226 1227 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1228 1229 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1230 *coef_exponent = coef_exp - 16; 1231 } 1232 1233 /* AR9330 WAR: 1234 * call external reset function to reset WMAC if: 1235 * - doing a cold reset 1236 * - we have pending frames in the TX queues. 1237 */ 1238 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1239 { 1240 int i, npend = 0; 1241 1242 for (i = 0; i < AR_NUM_QCU; i++) { 1243 npend = ath9k_hw_numtxpending(ah, i); 1244 if (npend) 1245 break; 1246 } 1247 1248 if (ah->external_reset && 1249 (npend || type == ATH9K_RESET_COLD)) { 1250 int reset_err = 0; 1251 1252 ath_dbg(ath9k_hw_common(ah), RESET, 1253 "reset MAC via external reset\n"); 1254 1255 reset_err = ah->external_reset(); 1256 if (reset_err) { 1257 ath_err(ath9k_hw_common(ah), 1258 "External reset failed, err=%d\n", 1259 reset_err); 1260 return false; 1261 } 1262 1263 REG_WRITE(ah, AR_RTC_RESET, 1); 1264 } 1265 1266 return true; 1267 } 1268 1269 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1270 { 1271 u32 rst_flags; 1272 u32 tmpReg; 1273 1274 if (AR_SREV_9100(ah)) { 1275 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1276 AR_RTC_DERIVED_CLK_PERIOD, 1); 1277 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1278 } 1279 1280 ENABLE_REGWRITE_BUFFER(ah); 1281 1282 if (AR_SREV_9300_20_OR_LATER(ah)) { 1283 REG_WRITE(ah, AR_WA, ah->WARegVal); 1284 udelay(10); 1285 } 1286 1287 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1288 AR_RTC_FORCE_WAKE_ON_INT); 1289 1290 if (AR_SREV_9100(ah)) { 1291 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1292 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1293 } else { 1294 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1295 if (AR_SREV_9340(ah)) 1296 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1297 else 1298 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1299 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1300 1301 if (tmpReg) { 1302 u32 val; 1303 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1304 1305 val = AR_RC_HOSTIF; 1306 if (!AR_SREV_9300_20_OR_LATER(ah)) 1307 val |= AR_RC_AHB; 1308 REG_WRITE(ah, AR_RC, val); 1309 1310 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1311 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1312 1313 rst_flags = AR_RTC_RC_MAC_WARM; 1314 if (type == ATH9K_RESET_COLD) 1315 rst_flags |= AR_RTC_RC_MAC_COLD; 1316 } 1317 1318 if (AR_SREV_9330(ah)) { 1319 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1320 return false; 1321 } 1322 1323 if (ath9k_hw_mci_is_enabled(ah)) 1324 ar9003_mci_check_gpm_offset(ah); 1325 1326 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1327 1328 REGWRITE_BUFFER_FLUSH(ah); 1329 1330 if (AR_SREV_9300_20_OR_LATER(ah)) 1331 udelay(50); 1332 else if (AR_SREV_9100(ah)) 1333 mdelay(10); 1334 else 1335 udelay(100); 1336 1337 REG_WRITE(ah, AR_RTC_RC, 0); 1338 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1339 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1340 return false; 1341 } 1342 1343 if (!AR_SREV_9100(ah)) 1344 REG_WRITE(ah, AR_RC, 0); 1345 1346 if (AR_SREV_9100(ah)) 1347 udelay(50); 1348 1349 return true; 1350 } 1351 1352 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1353 { 1354 ENABLE_REGWRITE_BUFFER(ah); 1355 1356 if (AR_SREV_9300_20_OR_LATER(ah)) { 1357 REG_WRITE(ah, AR_WA, ah->WARegVal); 1358 udelay(10); 1359 } 1360 1361 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1362 AR_RTC_FORCE_WAKE_ON_INT); 1363 1364 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1365 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1366 1367 REG_WRITE(ah, AR_RTC_RESET, 0); 1368 1369 REGWRITE_BUFFER_FLUSH(ah); 1370 1371 udelay(2); 1372 1373 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1374 REG_WRITE(ah, AR_RC, 0); 1375 1376 REG_WRITE(ah, AR_RTC_RESET, 1); 1377 1378 if (!ath9k_hw_wait(ah, 1379 AR_RTC_STATUS, 1380 AR_RTC_STATUS_M, 1381 AR_RTC_STATUS_ON, 1382 AH_WAIT_TIMEOUT)) { 1383 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1384 return false; 1385 } 1386 1387 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1388 } 1389 1390 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1391 { 1392 bool ret = false; 1393 1394 if (AR_SREV_9300_20_OR_LATER(ah)) { 1395 REG_WRITE(ah, AR_WA, ah->WARegVal); 1396 udelay(10); 1397 } 1398 1399 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1400 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1401 1402 if (!ah->reset_power_on) 1403 type = ATH9K_RESET_POWER_ON; 1404 1405 switch (type) { 1406 case ATH9K_RESET_POWER_ON: 1407 ret = ath9k_hw_set_reset_power_on(ah); 1408 if (ret) 1409 ah->reset_power_on = true; 1410 break; 1411 case ATH9K_RESET_WARM: 1412 case ATH9K_RESET_COLD: 1413 ret = ath9k_hw_set_reset(ah, type); 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 return ret; 1420 } 1421 1422 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1423 struct ath9k_channel *chan) 1424 { 1425 int reset_type = ATH9K_RESET_WARM; 1426 1427 if (AR_SREV_9280(ah)) { 1428 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1429 reset_type = ATH9K_RESET_POWER_ON; 1430 else 1431 reset_type = ATH9K_RESET_COLD; 1432 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1433 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1434 reset_type = ATH9K_RESET_COLD; 1435 1436 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1437 return false; 1438 1439 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1440 return false; 1441 1442 ah->chip_fullsleep = false; 1443 1444 if (AR_SREV_9330(ah)) 1445 ar9003_hw_internal_regulator_apply(ah); 1446 ath9k_hw_init_pll(ah, chan); 1447 1448 return true; 1449 } 1450 1451 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1452 struct ath9k_channel *chan) 1453 { 1454 struct ath_common *common = ath9k_hw_common(ah); 1455 struct ath9k_hw_capabilities *pCap = &ah->caps; 1456 bool band_switch = false, mode_diff = false; 1457 u8 ini_reloaded = 0; 1458 u32 qnum; 1459 int r; 1460 1461 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1462 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1463 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1464 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1465 } 1466 1467 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1468 if (ath9k_hw_numtxpending(ah, qnum)) { 1469 ath_dbg(common, QUEUE, 1470 "Transmit frames pending on queue %d\n", qnum); 1471 return false; 1472 } 1473 } 1474 1475 if (!ath9k_hw_rfbus_req(ah)) { 1476 ath_err(common, "Could not kill baseband RX\n"); 1477 return false; 1478 } 1479 1480 if (band_switch || mode_diff) { 1481 ath9k_hw_mark_phy_inactive(ah); 1482 udelay(5); 1483 1484 if (band_switch) 1485 ath9k_hw_init_pll(ah, chan); 1486 1487 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1488 ath_err(common, "Failed to do fast channel change\n"); 1489 return false; 1490 } 1491 } 1492 1493 ath9k_hw_set_channel_regs(ah, chan); 1494 1495 r = ath9k_hw_rf_set_freq(ah, chan); 1496 if (r) { 1497 ath_err(common, "Failed to set channel\n"); 1498 return false; 1499 } 1500 ath9k_hw_set_clockrate(ah); 1501 ath9k_hw_apply_txpower(ah, chan, false); 1502 1503 ath9k_hw_set_delta_slope(ah, chan); 1504 ath9k_hw_spur_mitigate_freq(ah, chan); 1505 1506 if (band_switch || ini_reloaded) 1507 ah->eep_ops->set_board_values(ah, chan); 1508 1509 ath9k_hw_init_bb(ah, chan); 1510 ath9k_hw_rfbus_done(ah); 1511 1512 if (band_switch || ini_reloaded) { 1513 ah->ah_flags |= AH_FASTCC; 1514 ath9k_hw_init_cal(ah, chan); 1515 ah->ah_flags &= ~AH_FASTCC; 1516 } 1517 1518 return true; 1519 } 1520 1521 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1522 { 1523 u32 gpio_mask = ah->gpio_mask; 1524 int i; 1525 1526 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1527 if (!(gpio_mask & 1)) 1528 continue; 1529 1530 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1531 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1532 } 1533 } 1534 1535 void ath9k_hw_check_nav(struct ath_hw *ah) 1536 { 1537 struct ath_common *common = ath9k_hw_common(ah); 1538 u32 val; 1539 1540 val = REG_READ(ah, AR_NAV); 1541 if (val != 0xdeadbeef && val > 0x7fff) { 1542 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1543 REG_WRITE(ah, AR_NAV, 0); 1544 } 1545 } 1546 EXPORT_SYMBOL(ath9k_hw_check_nav); 1547 1548 bool ath9k_hw_check_alive(struct ath_hw *ah) 1549 { 1550 int count = 50; 1551 u32 reg, last_val; 1552 1553 if (AR_SREV_9300(ah)) 1554 return !ath9k_hw_detect_mac_hang(ah); 1555 1556 if (AR_SREV_9285_12_OR_LATER(ah)) 1557 return true; 1558 1559 last_val = REG_READ(ah, AR_OBS_BUS_1); 1560 do { 1561 reg = REG_READ(ah, AR_OBS_BUS_1); 1562 if (reg != last_val) 1563 return true; 1564 1565 udelay(1); 1566 last_val = reg; 1567 if ((reg & 0x7E7FFFEF) == 0x00702400) 1568 continue; 1569 1570 switch (reg & 0x7E000B00) { 1571 case 0x1E000000: 1572 case 0x52000B00: 1573 case 0x18000B00: 1574 continue; 1575 default: 1576 return true; 1577 } 1578 } while (count-- > 0); 1579 1580 return false; 1581 } 1582 EXPORT_SYMBOL(ath9k_hw_check_alive); 1583 1584 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1585 { 1586 /* Setup MFP options for CCMP */ 1587 if (AR_SREV_9280_20_OR_LATER(ah)) { 1588 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1589 * frames when constructing CCMP AAD. */ 1590 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1591 0xc7ff); 1592 ah->sw_mgmt_crypto = false; 1593 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1594 /* Disable hardware crypto for management frames */ 1595 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1596 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1597 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1598 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1599 ah->sw_mgmt_crypto = true; 1600 } else { 1601 ah->sw_mgmt_crypto = true; 1602 } 1603 } 1604 1605 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1606 u32 macStaId1, u32 saveDefAntenna) 1607 { 1608 struct ath_common *common = ath9k_hw_common(ah); 1609 1610 ENABLE_REGWRITE_BUFFER(ah); 1611 1612 REG_RMW(ah, AR_STA_ID1, macStaId1 1613 | AR_STA_ID1_RTS_USE_DEF 1614 | ah->sta_id1_defaults, 1615 ~AR_STA_ID1_SADH_MASK); 1616 ath_hw_setbssidmask(common); 1617 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1618 ath9k_hw_write_associd(ah); 1619 REG_WRITE(ah, AR_ISR, ~0); 1620 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1621 1622 REGWRITE_BUFFER_FLUSH(ah); 1623 1624 ath9k_hw_set_operating_mode(ah, ah->opmode); 1625 } 1626 1627 static void ath9k_hw_init_queues(struct ath_hw *ah) 1628 { 1629 int i; 1630 1631 ENABLE_REGWRITE_BUFFER(ah); 1632 1633 for (i = 0; i < AR_NUM_DCU; i++) 1634 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1635 1636 REGWRITE_BUFFER_FLUSH(ah); 1637 1638 ah->intr_txqs = 0; 1639 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1640 ath9k_hw_resettxqueue(ah, i); 1641 } 1642 1643 /* 1644 * For big endian systems turn on swapping for descriptors 1645 */ 1646 static void ath9k_hw_init_desc(struct ath_hw *ah) 1647 { 1648 struct ath_common *common = ath9k_hw_common(ah); 1649 1650 if (AR_SREV_9100(ah)) { 1651 u32 mask; 1652 mask = REG_READ(ah, AR_CFG); 1653 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1654 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1655 mask); 1656 } else { 1657 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1658 REG_WRITE(ah, AR_CFG, mask); 1659 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1660 REG_READ(ah, AR_CFG)); 1661 } 1662 } else { 1663 if (common->bus_ops->ath_bus_type == ATH_USB) { 1664 /* Configure AR9271 target WLAN */ 1665 if (AR_SREV_9271(ah)) 1666 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1667 else 1668 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1669 } 1670 #ifdef __BIG_ENDIAN 1671 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1672 AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1673 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1674 else 1675 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1676 #endif 1677 } 1678 } 1679 1680 /* 1681 * Fast channel change: 1682 * (Change synthesizer based on channel freq without resetting chip) 1683 */ 1684 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1685 { 1686 struct ath_common *common = ath9k_hw_common(ah); 1687 struct ath9k_hw_capabilities *pCap = &ah->caps; 1688 int ret; 1689 1690 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1691 goto fail; 1692 1693 if (ah->chip_fullsleep) 1694 goto fail; 1695 1696 if (!ah->curchan) 1697 goto fail; 1698 1699 if (chan->channel == ah->curchan->channel) 1700 goto fail; 1701 1702 if ((ah->curchan->channelFlags | chan->channelFlags) & 1703 (CHANNEL_HALF | CHANNEL_QUARTER)) 1704 goto fail; 1705 1706 /* 1707 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1708 */ 1709 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1710 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1711 goto fail; 1712 1713 if (!ath9k_hw_check_alive(ah)) 1714 goto fail; 1715 1716 /* 1717 * For AR9462, make sure that calibration data for 1718 * re-using are present. 1719 */ 1720 if (AR_SREV_9462(ah) && (ah->caldata && 1721 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1722 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1723 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1724 goto fail; 1725 1726 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1727 ah->curchan->channel, chan->channel); 1728 1729 ret = ath9k_hw_channel_change(ah, chan); 1730 if (!ret) 1731 goto fail; 1732 1733 if (ath9k_hw_mci_is_enabled(ah)) 1734 ar9003_mci_2g5g_switch(ah, false); 1735 1736 ath9k_hw_loadnf(ah, ah->curchan); 1737 ath9k_hw_start_nfcal(ah, true); 1738 1739 if (AR_SREV_9271(ah)) 1740 ar9002_hw_load_ani_reg(ah, chan); 1741 1742 return 0; 1743 fail: 1744 return -EINVAL; 1745 } 1746 1747 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1748 { 1749 struct timespec ts; 1750 s64 usec; 1751 1752 if (!cur) { 1753 getrawmonotonic(&ts); 1754 cur = &ts; 1755 } 1756 1757 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1758 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1759 1760 return (u32) usec; 1761 } 1762 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1763 1764 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1765 struct ath9k_hw_cal_data *caldata, bool fastcc) 1766 { 1767 struct ath_common *common = ath9k_hw_common(ah); 1768 u32 saveLedState; 1769 u32 saveDefAntenna; 1770 u32 macStaId1; 1771 u64 tsf = 0; 1772 s64 usec = 0; 1773 int r; 1774 bool start_mci_reset = false; 1775 bool save_fullsleep = ah->chip_fullsleep; 1776 1777 if (ath9k_hw_mci_is_enabled(ah)) { 1778 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1779 if (start_mci_reset) 1780 return 0; 1781 } 1782 1783 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1784 return -EIO; 1785 1786 if (ah->curchan && !ah->chip_fullsleep) 1787 ath9k_hw_getnf(ah, ah->curchan); 1788 1789 ah->caldata = caldata; 1790 if (caldata && (chan->channel != caldata->channel || 1791 chan->channelFlags != caldata->channelFlags)) { 1792 /* Operating channel changed, reset channel calibration data */ 1793 memset(caldata, 0, sizeof(*caldata)); 1794 ath9k_init_nfcal_hist_buffer(ah, chan); 1795 } else if (caldata) { 1796 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1797 } 1798 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1799 1800 if (fastcc) { 1801 r = ath9k_hw_do_fastcc(ah, chan); 1802 if (!r) 1803 return r; 1804 } 1805 1806 if (ath9k_hw_mci_is_enabled(ah)) 1807 ar9003_mci_stop_bt(ah, save_fullsleep); 1808 1809 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1810 if (saveDefAntenna == 0) 1811 saveDefAntenna = 1; 1812 1813 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1814 1815 /* Save TSF before chip reset, a cold reset clears it */ 1816 tsf = ath9k_hw_gettsf64(ah); 1817 usec = ktime_to_us(ktime_get_raw()); 1818 1819 saveLedState = REG_READ(ah, AR_CFG_LED) & 1820 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1821 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1822 1823 ath9k_hw_mark_phy_inactive(ah); 1824 1825 ah->paprd_table_write_done = false; 1826 1827 /* Only required on the first reset */ 1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1829 REG_WRITE(ah, 1830 AR9271_RESET_POWER_DOWN_CONTROL, 1831 AR9271_RADIO_RF_RST); 1832 udelay(50); 1833 } 1834 1835 if (!ath9k_hw_chip_reset(ah, chan)) { 1836 ath_err(common, "Chip reset failed\n"); 1837 return -EINVAL; 1838 } 1839 1840 /* Only required on the first reset */ 1841 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1842 ah->htc_reset_init = false; 1843 REG_WRITE(ah, 1844 AR9271_RESET_POWER_DOWN_CONTROL, 1845 AR9271_GATE_MAC_CTL); 1846 udelay(50); 1847 } 1848 1849 /* Restore TSF */ 1850 usec = ktime_to_us(ktime_get_raw()) - usec; 1851 ath9k_hw_settsf64(ah, tsf + usec); 1852 1853 if (AR_SREV_9280_20_OR_LATER(ah)) 1854 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1855 1856 if (!AR_SREV_9300_20_OR_LATER(ah)) 1857 ar9002_hw_enable_async_fifo(ah); 1858 1859 r = ath9k_hw_process_ini(ah, chan); 1860 if (r) 1861 return r; 1862 1863 ath9k_hw_set_rfmode(ah, chan); 1864 1865 if (ath9k_hw_mci_is_enabled(ah)) 1866 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1867 1868 /* 1869 * Some AR91xx SoC devices frequently fail to accept TSF writes 1870 * right after the chip reset. When that happens, write a new 1871 * value after the initvals have been applied, with an offset 1872 * based on measured time difference 1873 */ 1874 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1875 tsf += 1500; 1876 ath9k_hw_settsf64(ah, tsf); 1877 } 1878 1879 ath9k_hw_init_mfp(ah); 1880 1881 ath9k_hw_set_delta_slope(ah, chan); 1882 ath9k_hw_spur_mitigate_freq(ah, chan); 1883 ah->eep_ops->set_board_values(ah, chan); 1884 1885 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1886 1887 r = ath9k_hw_rf_set_freq(ah, chan); 1888 if (r) 1889 return r; 1890 1891 ath9k_hw_set_clockrate(ah); 1892 1893 ath9k_hw_init_queues(ah); 1894 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1895 ath9k_hw_ani_cache_ini_regs(ah); 1896 ath9k_hw_init_qos(ah); 1897 1898 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1899 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1900 1901 ath9k_hw_init_global_settings(ah); 1902 1903 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1904 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1905 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1906 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1907 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1908 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1909 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1910 } 1911 1912 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1913 1914 ath9k_hw_set_dma(ah); 1915 1916 if (!ath9k_hw_mci_is_enabled(ah)) 1917 REG_WRITE(ah, AR_OBS, 8); 1918 1919 if (ah->config.rx_intr_mitigation) { 1920 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1921 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1922 } 1923 1924 if (ah->config.tx_intr_mitigation) { 1925 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1926 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1927 } 1928 1929 ath9k_hw_init_bb(ah, chan); 1930 1931 if (caldata) { 1932 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1933 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1934 } 1935 if (!ath9k_hw_init_cal(ah, chan)) 1936 return -EIO; 1937 1938 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1939 return -EIO; 1940 1941 ENABLE_REGWRITE_BUFFER(ah); 1942 1943 ath9k_hw_restore_chainmask(ah); 1944 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1945 1946 REGWRITE_BUFFER_FLUSH(ah); 1947 1948 ath9k_hw_init_desc(ah); 1949 1950 if (ath9k_hw_btcoex_is_enabled(ah)) 1951 ath9k_hw_btcoex_enable(ah); 1952 1953 if (ath9k_hw_mci_is_enabled(ah)) 1954 ar9003_mci_check_bt(ah); 1955 1956 ath9k_hw_loadnf(ah, chan); 1957 ath9k_hw_start_nfcal(ah, true); 1958 1959 if (AR_SREV_9300_20_OR_LATER(ah)) 1960 ar9003_hw_bb_watchdog_config(ah); 1961 1962 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1963 ar9003_hw_disable_phy_restart(ah); 1964 1965 ath9k_hw_apply_gpio_override(ah); 1966 1967 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1968 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1969 1970 if (ah->hw->conf.radar_enabled) { 1971 /* set HW specific DFS configuration */ 1972 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 1973 ath9k_hw_set_radar_params(ah); 1974 } 1975 1976 return 0; 1977 } 1978 EXPORT_SYMBOL(ath9k_hw_reset); 1979 1980 /******************************/ 1981 /* Power Management (Chipset) */ 1982 /******************************/ 1983 1984 /* 1985 * Notify Power Mgt is disabled in self-generated frames. 1986 * If requested, force chip to sleep. 1987 */ 1988 static void ath9k_set_power_sleep(struct ath_hw *ah) 1989 { 1990 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1991 1992 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1993 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 1994 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 1995 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 1996 /* xxx Required for WLAN only case ? */ 1997 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1998 udelay(100); 1999 } 2000 2001 /* 2002 * Clear the RTC force wake bit to allow the 2003 * mac to go to sleep. 2004 */ 2005 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2006 2007 if (ath9k_hw_mci_is_enabled(ah)) 2008 udelay(100); 2009 2010 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2011 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2012 2013 /* Shutdown chip. Active low */ 2014 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2015 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2016 udelay(2); 2017 } 2018 2019 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2020 if (AR_SREV_9300_20_OR_LATER(ah)) 2021 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2022 } 2023 2024 /* 2025 * Notify Power Management is enabled in self-generating 2026 * frames. If request, set power mode of chip to 2027 * auto/normal. Duration in units of 128us (1/8 TU). 2028 */ 2029 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2030 { 2031 struct ath9k_hw_capabilities *pCap = &ah->caps; 2032 2033 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2034 2035 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2036 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2037 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2038 AR_RTC_FORCE_WAKE_ON_INT); 2039 } else { 2040 2041 /* When chip goes into network sleep, it could be waken 2042 * up by MCI_INT interrupt caused by BT's HW messages 2043 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2044 * rate (~100us). This will cause chip to leave and 2045 * re-enter network sleep mode frequently, which in 2046 * consequence will have WLAN MCI HW to generate lots of 2047 * SYS_WAKING and SYS_SLEEPING messages which will make 2048 * BT CPU to busy to process. 2049 */ 2050 if (ath9k_hw_mci_is_enabled(ah)) 2051 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2052 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2053 /* 2054 * Clear the RTC force wake bit to allow the 2055 * mac to go to sleep. 2056 */ 2057 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2058 2059 if (ath9k_hw_mci_is_enabled(ah)) 2060 udelay(30); 2061 } 2062 2063 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2064 if (AR_SREV_9300_20_OR_LATER(ah)) 2065 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2066 } 2067 2068 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2069 { 2070 u32 val; 2071 int i; 2072 2073 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2074 if (AR_SREV_9300_20_OR_LATER(ah)) { 2075 REG_WRITE(ah, AR_WA, ah->WARegVal); 2076 udelay(10); 2077 } 2078 2079 if ((REG_READ(ah, AR_RTC_STATUS) & 2080 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2081 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2082 return false; 2083 } 2084 if (!AR_SREV_9300_20_OR_LATER(ah)) 2085 ath9k_hw_init_pll(ah, NULL); 2086 } 2087 if (AR_SREV_9100(ah)) 2088 REG_SET_BIT(ah, AR_RTC_RESET, 2089 AR_RTC_RESET_EN); 2090 2091 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2092 AR_RTC_FORCE_WAKE_EN); 2093 if (AR_SREV_9100(ah)) 2094 mdelay(10); 2095 else 2096 udelay(50); 2097 2098 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2099 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2100 if (val == AR_RTC_STATUS_ON) 2101 break; 2102 udelay(50); 2103 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2104 AR_RTC_FORCE_WAKE_EN); 2105 } 2106 if (i == 0) { 2107 ath_err(ath9k_hw_common(ah), 2108 "Failed to wakeup in %uus\n", 2109 POWER_UP_TIME / 20); 2110 return false; 2111 } 2112 2113 if (ath9k_hw_mci_is_enabled(ah)) 2114 ar9003_mci_set_power_awake(ah); 2115 2116 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2117 2118 return true; 2119 } 2120 2121 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2122 { 2123 struct ath_common *common = ath9k_hw_common(ah); 2124 int status = true; 2125 static const char *modes[] = { 2126 "AWAKE", 2127 "FULL-SLEEP", 2128 "NETWORK SLEEP", 2129 "UNDEFINED" 2130 }; 2131 2132 if (ah->power_mode == mode) 2133 return status; 2134 2135 ath_dbg(common, RESET, "%s -> %s\n", 2136 modes[ah->power_mode], modes[mode]); 2137 2138 switch (mode) { 2139 case ATH9K_PM_AWAKE: 2140 status = ath9k_hw_set_power_awake(ah); 2141 break; 2142 case ATH9K_PM_FULL_SLEEP: 2143 if (ath9k_hw_mci_is_enabled(ah)) 2144 ar9003_mci_set_full_sleep(ah); 2145 2146 ath9k_set_power_sleep(ah); 2147 ah->chip_fullsleep = true; 2148 break; 2149 case ATH9K_PM_NETWORK_SLEEP: 2150 ath9k_set_power_network_sleep(ah); 2151 break; 2152 default: 2153 ath_err(common, "Unknown power mode %u\n", mode); 2154 return false; 2155 } 2156 ah->power_mode = mode; 2157 2158 /* 2159 * XXX: If this warning never comes up after a while then 2160 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2161 * ath9k_hw_setpower() return type void. 2162 */ 2163 2164 if (!(ah->ah_flags & AH_UNPLUGGED)) 2165 ATH_DBG_WARN_ON_ONCE(!status); 2166 2167 return status; 2168 } 2169 EXPORT_SYMBOL(ath9k_hw_setpower); 2170 2171 /*******************/ 2172 /* Beacon Handling */ 2173 /*******************/ 2174 2175 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2176 { 2177 int flags = 0; 2178 2179 ENABLE_REGWRITE_BUFFER(ah); 2180 2181 switch (ah->opmode) { 2182 case NL80211_IFTYPE_ADHOC: 2183 REG_SET_BIT(ah, AR_TXCFG, 2184 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2185 case NL80211_IFTYPE_MESH_POINT: 2186 case NL80211_IFTYPE_AP: 2187 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2188 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2189 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2190 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2191 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2192 flags |= 2193 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2194 break; 2195 default: 2196 ath_dbg(ath9k_hw_common(ah), BEACON, 2197 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2198 return; 2199 break; 2200 } 2201 2202 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2203 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2204 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2205 2206 REGWRITE_BUFFER_FLUSH(ah); 2207 2208 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2209 } 2210 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2211 2212 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2213 const struct ath9k_beacon_state *bs) 2214 { 2215 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2216 struct ath9k_hw_capabilities *pCap = &ah->caps; 2217 struct ath_common *common = ath9k_hw_common(ah); 2218 2219 ENABLE_REGWRITE_BUFFER(ah); 2220 2221 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2222 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2223 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2224 2225 REGWRITE_BUFFER_FLUSH(ah); 2226 2227 REG_RMW_FIELD(ah, AR_RSSI_THR, 2228 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2229 2230 beaconintval = bs->bs_intval; 2231 2232 if (bs->bs_sleepduration > beaconintval) 2233 beaconintval = bs->bs_sleepduration; 2234 2235 dtimperiod = bs->bs_dtimperiod; 2236 if (bs->bs_sleepduration > dtimperiod) 2237 dtimperiod = bs->bs_sleepduration; 2238 2239 if (beaconintval == dtimperiod) 2240 nextTbtt = bs->bs_nextdtim; 2241 else 2242 nextTbtt = bs->bs_nexttbtt; 2243 2244 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2245 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2246 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2247 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2248 2249 ENABLE_REGWRITE_BUFFER(ah); 2250 2251 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2252 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2253 2254 REG_WRITE(ah, AR_SLEEP1, 2255 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2256 | AR_SLEEP1_ASSUME_DTIM); 2257 2258 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2259 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2260 else 2261 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2262 2263 REG_WRITE(ah, AR_SLEEP2, 2264 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2265 2266 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2267 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2268 2269 REGWRITE_BUFFER_FLUSH(ah); 2270 2271 REG_SET_BIT(ah, AR_TIMER_MODE, 2272 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2273 AR_DTIM_TIMER_EN); 2274 2275 /* TSF Out of Range Threshold */ 2276 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2277 } 2278 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2279 2280 /*******************/ 2281 /* HW Capabilities */ 2282 /*******************/ 2283 2284 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2285 { 2286 eeprom_chainmask &= chip_chainmask; 2287 if (eeprom_chainmask) 2288 return eeprom_chainmask; 2289 else 2290 return chip_chainmask; 2291 } 2292 2293 /** 2294 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2295 * @ah: the atheros hardware data structure 2296 * 2297 * We enable DFS support upstream on chipsets which have passed a series 2298 * of tests. The testing requirements are going to be documented. Desired 2299 * test requirements are documented at: 2300 * 2301 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2302 * 2303 * Once a new chipset gets properly tested an individual commit can be used 2304 * to document the testing for DFS for that chipset. 2305 */ 2306 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2307 { 2308 2309 switch (ah->hw_version.macVersion) { 2310 /* for temporary testing DFS with 9280 */ 2311 case AR_SREV_VERSION_9280: 2312 /* AR9580 will likely be our first target to get testing on */ 2313 case AR_SREV_VERSION_9580: 2314 return true; 2315 default: 2316 return false; 2317 } 2318 } 2319 2320 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2321 { 2322 struct ath9k_hw_capabilities *pCap = &ah->caps; 2323 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2324 struct ath_common *common = ath9k_hw_common(ah); 2325 unsigned int chip_chainmask; 2326 2327 u16 eeval; 2328 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2329 2330 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2331 regulatory->current_rd = eeval; 2332 2333 if (ah->opmode != NL80211_IFTYPE_AP && 2334 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2335 if (regulatory->current_rd == 0x64 || 2336 regulatory->current_rd == 0x65) 2337 regulatory->current_rd += 5; 2338 else if (regulatory->current_rd == 0x41) 2339 regulatory->current_rd = 0x43; 2340 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2341 regulatory->current_rd); 2342 } 2343 2344 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2345 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2346 ath_err(common, 2347 "no band has been marked as supported in EEPROM\n"); 2348 return -EINVAL; 2349 } 2350 2351 if (eeval & AR5416_OPFLAGS_11A) 2352 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2353 2354 if (eeval & AR5416_OPFLAGS_11G) 2355 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2356 2357 if (AR_SREV_9485(ah) || 2358 AR_SREV_9285(ah) || 2359 AR_SREV_9330(ah) || 2360 AR_SREV_9565(ah)) 2361 chip_chainmask = 1; 2362 else if (AR_SREV_9462(ah)) 2363 chip_chainmask = 3; 2364 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2365 chip_chainmask = 7; 2366 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2367 chip_chainmask = 3; 2368 else 2369 chip_chainmask = 7; 2370 2371 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2372 /* 2373 * For AR9271 we will temporarilly uses the rx chainmax as read from 2374 * the EEPROM. 2375 */ 2376 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2377 !(eeval & AR5416_OPFLAGS_11A) && 2378 !(AR_SREV_9271(ah))) 2379 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2380 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2381 else if (AR_SREV_9100(ah)) 2382 pCap->rx_chainmask = 0x7; 2383 else 2384 /* Use rx_chainmask from EEPROM. */ 2385 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2386 2387 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2388 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2389 ah->txchainmask = pCap->tx_chainmask; 2390 ah->rxchainmask = pCap->rx_chainmask; 2391 2392 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2393 2394 /* enable key search for every frame in an aggregate */ 2395 if (AR_SREV_9300_20_OR_LATER(ah)) 2396 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2397 2398 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2399 2400 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2401 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2402 else 2403 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2404 2405 if (AR_SREV_9271(ah)) 2406 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2407 else if (AR_DEVID_7010(ah)) 2408 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2409 else if (AR_SREV_9300_20_OR_LATER(ah)) 2410 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2411 else if (AR_SREV_9287_11_OR_LATER(ah)) 2412 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2413 else if (AR_SREV_9285_12_OR_LATER(ah)) 2414 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2415 else if (AR_SREV_9280_20_OR_LATER(ah)) 2416 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2417 else 2418 pCap->num_gpio_pins = AR_NUM_GPIO; 2419 2420 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2421 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2422 else 2423 pCap->rts_aggr_limit = (8 * 1024); 2424 2425 #ifdef CONFIG_ATH9K_RFKILL 2426 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2427 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2428 ah->rfkill_gpio = 2429 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2430 ah->rfkill_polarity = 2431 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2432 2433 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2434 } 2435 #endif 2436 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2437 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2438 else 2439 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2440 2441 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2442 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2443 else 2444 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2445 2446 if (AR_SREV_9300_20_OR_LATER(ah)) { 2447 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2448 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2449 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2450 2451 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2452 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2453 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2454 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2455 pCap->txs_len = sizeof(struct ar9003_txs); 2456 } else { 2457 pCap->tx_desc_len = sizeof(struct ath_desc); 2458 if (AR_SREV_9280_20(ah)) 2459 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2460 } 2461 2462 if (AR_SREV_9300_20_OR_LATER(ah)) 2463 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2464 2465 if (AR_SREV_9300_20_OR_LATER(ah)) 2466 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2467 2468 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2469 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2470 2471 if (AR_SREV_9285(ah)) { 2472 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2473 ant_div_ctl1 = 2474 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2475 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2476 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2477 ath_info(common, "Enable LNA combining\n"); 2478 } 2479 } 2480 } 2481 2482 if (AR_SREV_9300_20_OR_LATER(ah)) { 2483 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2484 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2485 } 2486 2487 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2488 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2489 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2490 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2491 ath_info(common, "Enable LNA combining\n"); 2492 } 2493 } 2494 2495 if (ath9k_hw_dfs_tested(ah)) 2496 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2497 2498 tx_chainmask = pCap->tx_chainmask; 2499 rx_chainmask = pCap->rx_chainmask; 2500 while (tx_chainmask || rx_chainmask) { 2501 if (tx_chainmask & BIT(0)) 2502 pCap->max_txchains++; 2503 if (rx_chainmask & BIT(0)) 2504 pCap->max_rxchains++; 2505 2506 tx_chainmask >>= 1; 2507 rx_chainmask >>= 1; 2508 } 2509 2510 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2511 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2512 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2513 2514 if (AR_SREV_9462_20_OR_LATER(ah)) 2515 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2516 } 2517 2518 if (AR_SREV_9462(ah)) 2519 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2520 2521 if (AR_SREV_9300_20_OR_LATER(ah) && 2522 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2523 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2524 2525 return 0; 2526 } 2527 2528 /****************************/ 2529 /* GPIO / RFKILL / Antennae */ 2530 /****************************/ 2531 2532 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2533 u32 gpio, u32 type) 2534 { 2535 int addr; 2536 u32 gpio_shift, tmp; 2537 2538 if (gpio > 11) 2539 addr = AR_GPIO_OUTPUT_MUX3; 2540 else if (gpio > 5) 2541 addr = AR_GPIO_OUTPUT_MUX2; 2542 else 2543 addr = AR_GPIO_OUTPUT_MUX1; 2544 2545 gpio_shift = (gpio % 6) * 5; 2546 2547 if (AR_SREV_9280_20_OR_LATER(ah) 2548 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2549 REG_RMW(ah, addr, (type << gpio_shift), 2550 (0x1f << gpio_shift)); 2551 } else { 2552 tmp = REG_READ(ah, addr); 2553 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2554 tmp &= ~(0x1f << gpio_shift); 2555 tmp |= (type << gpio_shift); 2556 REG_WRITE(ah, addr, tmp); 2557 } 2558 } 2559 2560 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2561 { 2562 u32 gpio_shift; 2563 2564 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2565 2566 if (AR_DEVID_7010(ah)) { 2567 gpio_shift = gpio; 2568 REG_RMW(ah, AR7010_GPIO_OE, 2569 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2570 (AR7010_GPIO_OE_MASK << gpio_shift)); 2571 return; 2572 } 2573 2574 gpio_shift = gpio << 1; 2575 REG_RMW(ah, 2576 AR_GPIO_OE_OUT, 2577 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2578 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2579 } 2580 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2581 2582 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2583 { 2584 #define MS_REG_READ(x, y) \ 2585 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2586 2587 if (gpio >= ah->caps.num_gpio_pins) 2588 return 0xffffffff; 2589 2590 if (AR_DEVID_7010(ah)) { 2591 u32 val; 2592 val = REG_READ(ah, AR7010_GPIO_IN); 2593 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2594 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2595 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2596 AR_GPIO_BIT(gpio)) != 0; 2597 else if (AR_SREV_9271(ah)) 2598 return MS_REG_READ(AR9271, gpio) != 0; 2599 else if (AR_SREV_9287_11_OR_LATER(ah)) 2600 return MS_REG_READ(AR9287, gpio) != 0; 2601 else if (AR_SREV_9285_12_OR_LATER(ah)) 2602 return MS_REG_READ(AR9285, gpio) != 0; 2603 else if (AR_SREV_9280_20_OR_LATER(ah)) 2604 return MS_REG_READ(AR928X, gpio) != 0; 2605 else 2606 return MS_REG_READ(AR, gpio) != 0; 2607 } 2608 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2609 2610 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2611 u32 ah_signal_type) 2612 { 2613 u32 gpio_shift; 2614 2615 if (AR_DEVID_7010(ah)) { 2616 gpio_shift = gpio; 2617 REG_RMW(ah, AR7010_GPIO_OE, 2618 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2619 (AR7010_GPIO_OE_MASK << gpio_shift)); 2620 return; 2621 } 2622 2623 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2624 gpio_shift = 2 * gpio; 2625 REG_RMW(ah, 2626 AR_GPIO_OE_OUT, 2627 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2628 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2629 } 2630 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2631 2632 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2633 { 2634 if (AR_DEVID_7010(ah)) { 2635 val = val ? 0 : 1; 2636 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2637 AR_GPIO_BIT(gpio)); 2638 return; 2639 } 2640 2641 if (AR_SREV_9271(ah)) 2642 val = ~val; 2643 2644 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2645 AR_GPIO_BIT(gpio)); 2646 } 2647 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2648 2649 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2650 { 2651 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2652 } 2653 EXPORT_SYMBOL(ath9k_hw_setantenna); 2654 2655 /*********************/ 2656 /* General Operation */ 2657 /*********************/ 2658 2659 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2660 { 2661 u32 bits = REG_READ(ah, AR_RX_FILTER); 2662 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2663 2664 if (phybits & AR_PHY_ERR_RADAR) 2665 bits |= ATH9K_RX_FILTER_PHYRADAR; 2666 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2667 bits |= ATH9K_RX_FILTER_PHYERR; 2668 2669 return bits; 2670 } 2671 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2672 2673 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2674 { 2675 u32 phybits; 2676 2677 ENABLE_REGWRITE_BUFFER(ah); 2678 2679 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2680 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2681 2682 REG_WRITE(ah, AR_RX_FILTER, bits); 2683 2684 phybits = 0; 2685 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2686 phybits |= AR_PHY_ERR_RADAR; 2687 if (bits & ATH9K_RX_FILTER_PHYERR) 2688 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2689 REG_WRITE(ah, AR_PHY_ERR, phybits); 2690 2691 if (phybits) 2692 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2693 else 2694 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2695 2696 REGWRITE_BUFFER_FLUSH(ah); 2697 } 2698 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2699 2700 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2701 { 2702 if (ath9k_hw_mci_is_enabled(ah)) 2703 ar9003_mci_bt_gain_ctrl(ah); 2704 2705 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2706 return false; 2707 2708 ath9k_hw_init_pll(ah, NULL); 2709 ah->htc_reset_init = true; 2710 return true; 2711 } 2712 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2713 2714 bool ath9k_hw_disable(struct ath_hw *ah) 2715 { 2716 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2717 return false; 2718 2719 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2720 return false; 2721 2722 ath9k_hw_init_pll(ah, NULL); 2723 return true; 2724 } 2725 EXPORT_SYMBOL(ath9k_hw_disable); 2726 2727 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2728 { 2729 enum eeprom_param gain_param; 2730 2731 if (IS_CHAN_2GHZ(chan)) 2732 gain_param = EEP_ANTENNA_GAIN_2G; 2733 else 2734 gain_param = EEP_ANTENNA_GAIN_5G; 2735 2736 return ah->eep_ops->get_eeprom(ah, gain_param); 2737 } 2738 2739 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2740 bool test) 2741 { 2742 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2743 struct ieee80211_channel *channel; 2744 int chan_pwr, new_pwr, max_gain; 2745 int ant_gain, ant_reduction = 0; 2746 2747 if (!chan) 2748 return; 2749 2750 channel = chan->chan; 2751 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2752 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2753 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2754 2755 ant_gain = get_antenna_gain(ah, chan); 2756 if (ant_gain > max_gain) 2757 ant_reduction = ant_gain - max_gain; 2758 2759 ah->eep_ops->set_txpower(ah, chan, 2760 ath9k_regd_get_ctl(reg, chan), 2761 ant_reduction, new_pwr, test); 2762 } 2763 2764 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2765 { 2766 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2767 struct ath9k_channel *chan = ah->curchan; 2768 struct ieee80211_channel *channel = chan->chan; 2769 2770 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2771 if (test) 2772 channel->max_power = MAX_RATE_POWER / 2; 2773 2774 ath9k_hw_apply_txpower(ah, chan, test); 2775 2776 if (test) 2777 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2778 } 2779 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2780 2781 void ath9k_hw_setopmode(struct ath_hw *ah) 2782 { 2783 ath9k_hw_set_operating_mode(ah, ah->opmode); 2784 } 2785 EXPORT_SYMBOL(ath9k_hw_setopmode); 2786 2787 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2788 { 2789 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2790 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2791 } 2792 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2793 2794 void ath9k_hw_write_associd(struct ath_hw *ah) 2795 { 2796 struct ath_common *common = ath9k_hw_common(ah); 2797 2798 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2799 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2800 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2801 } 2802 EXPORT_SYMBOL(ath9k_hw_write_associd); 2803 2804 #define ATH9K_MAX_TSF_READ 10 2805 2806 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2807 { 2808 u32 tsf_lower, tsf_upper1, tsf_upper2; 2809 int i; 2810 2811 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2812 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2813 tsf_lower = REG_READ(ah, AR_TSF_L32); 2814 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2815 if (tsf_upper2 == tsf_upper1) 2816 break; 2817 tsf_upper1 = tsf_upper2; 2818 } 2819 2820 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2821 2822 return (((u64)tsf_upper1 << 32) | tsf_lower); 2823 } 2824 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2825 2826 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2827 { 2828 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2829 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2830 } 2831 EXPORT_SYMBOL(ath9k_hw_settsf64); 2832 2833 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2834 { 2835 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2836 AH_TSF_WRITE_TIMEOUT)) 2837 ath_dbg(ath9k_hw_common(ah), RESET, 2838 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2839 2840 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2841 } 2842 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2843 2844 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2845 { 2846 if (set) 2847 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2848 else 2849 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2850 } 2851 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2852 2853 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2854 { 2855 u32 macmode; 2856 2857 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2858 macmode = AR_2040_JOINED_RX_CLEAR; 2859 else 2860 macmode = 0; 2861 2862 REG_WRITE(ah, AR_2040_MODE, macmode); 2863 } 2864 2865 /* HW Generic timers configuration */ 2866 2867 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2868 { 2869 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2870 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2871 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2872 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2873 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2874 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2875 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2876 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2877 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2878 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2879 AR_NDP2_TIMER_MODE, 0x0002}, 2880 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2881 AR_NDP2_TIMER_MODE, 0x0004}, 2882 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2883 AR_NDP2_TIMER_MODE, 0x0008}, 2884 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2885 AR_NDP2_TIMER_MODE, 0x0010}, 2886 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2887 AR_NDP2_TIMER_MODE, 0x0020}, 2888 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2889 AR_NDP2_TIMER_MODE, 0x0040}, 2890 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2891 AR_NDP2_TIMER_MODE, 0x0080} 2892 }; 2893 2894 /* HW generic timer primitives */ 2895 2896 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2897 { 2898 return REG_READ(ah, AR_TSF_L32); 2899 } 2900 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2901 2902 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2903 void (*trigger)(void *), 2904 void (*overflow)(void *), 2905 void *arg, 2906 u8 timer_index) 2907 { 2908 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2909 struct ath_gen_timer *timer; 2910 2911 if ((timer_index < AR_FIRST_NDP_TIMER) || 2912 (timer_index >= ATH_MAX_GEN_TIMER)) 2913 return NULL; 2914 2915 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2916 if (timer == NULL) 2917 return NULL; 2918 2919 /* allocate a hardware generic timer slot */ 2920 timer_table->timers[timer_index] = timer; 2921 timer->index = timer_index; 2922 timer->trigger = trigger; 2923 timer->overflow = overflow; 2924 timer->arg = arg; 2925 2926 return timer; 2927 } 2928 EXPORT_SYMBOL(ath_gen_timer_alloc); 2929 2930 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2931 struct ath_gen_timer *timer, 2932 u32 timer_next, 2933 u32 timer_period) 2934 { 2935 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2936 u32 mask = 0; 2937 2938 timer_table->timer_mask |= BIT(timer->index); 2939 2940 /* 2941 * Program generic timer registers 2942 */ 2943 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2944 timer_next); 2945 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2946 timer_period); 2947 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2948 gen_tmr_configuration[timer->index].mode_mask); 2949 2950 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2951 /* 2952 * Starting from AR9462, each generic timer can select which tsf 2953 * to use. But we still follow the old rule, 0 - 7 use tsf and 2954 * 8 - 15 use tsf2. 2955 */ 2956 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2957 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2958 (1 << timer->index)); 2959 else 2960 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2961 (1 << timer->index)); 2962 } 2963 2964 if (timer->trigger) 2965 mask |= SM(AR_GENTMR_BIT(timer->index), 2966 AR_IMR_S5_GENTIMER_TRIG); 2967 if (timer->overflow) 2968 mask |= SM(AR_GENTMR_BIT(timer->index), 2969 AR_IMR_S5_GENTIMER_THRESH); 2970 2971 REG_SET_BIT(ah, AR_IMR_S5, mask); 2972 2973 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 2974 ah->imask |= ATH9K_INT_GENTIMER; 2975 ath9k_hw_set_interrupts(ah); 2976 } 2977 } 2978 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2979 2980 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2981 { 2982 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2983 2984 /* Clear generic timer enable bits. */ 2985 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2986 gen_tmr_configuration[timer->index].mode_mask); 2987 2988 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2989 /* 2990 * Need to switch back to TSF if it was using TSF2. 2991 */ 2992 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 2993 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2994 (1 << timer->index)); 2995 } 2996 } 2997 2998 /* Disable both trigger and thresh interrupt masks */ 2999 REG_CLR_BIT(ah, AR_IMR_S5, 3000 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3001 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3002 3003 timer_table->timer_mask &= ~BIT(timer->index); 3004 3005 if (timer_table->timer_mask == 0) { 3006 ah->imask &= ~ATH9K_INT_GENTIMER; 3007 ath9k_hw_set_interrupts(ah); 3008 } 3009 } 3010 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3011 3012 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3013 { 3014 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3015 3016 /* free the hardware generic timer slot */ 3017 timer_table->timers[timer->index] = NULL; 3018 kfree(timer); 3019 } 3020 EXPORT_SYMBOL(ath_gen_timer_free); 3021 3022 /* 3023 * Generic Timer Interrupts handling 3024 */ 3025 void ath_gen_timer_isr(struct ath_hw *ah) 3026 { 3027 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3028 struct ath_gen_timer *timer; 3029 unsigned long trigger_mask, thresh_mask; 3030 unsigned int index; 3031 3032 /* get hardware generic timer interrupt status */ 3033 trigger_mask = ah->intr_gen_timer_trigger; 3034 thresh_mask = ah->intr_gen_timer_thresh; 3035 trigger_mask &= timer_table->timer_mask; 3036 thresh_mask &= timer_table->timer_mask; 3037 3038 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3039 timer = timer_table->timers[index]; 3040 if (!timer) 3041 continue; 3042 if (!timer->overflow) 3043 continue; 3044 3045 trigger_mask &= ~BIT(index); 3046 timer->overflow(timer->arg); 3047 } 3048 3049 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3050 timer = timer_table->timers[index]; 3051 if (!timer) 3052 continue; 3053 if (!timer->trigger) 3054 continue; 3055 timer->trigger(timer->arg); 3056 } 3057 } 3058 EXPORT_SYMBOL(ath_gen_timer_isr); 3059 3060 /********/ 3061 /* HTC */ 3062 /********/ 3063 3064 static struct { 3065 u32 version; 3066 const char * name; 3067 } ath_mac_bb_names[] = { 3068 /* Devices with external radios */ 3069 { AR_SREV_VERSION_5416_PCI, "5416" }, 3070 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3071 { AR_SREV_VERSION_9100, "9100" }, 3072 { AR_SREV_VERSION_9160, "9160" }, 3073 /* Single-chip solutions */ 3074 { AR_SREV_VERSION_9280, "9280" }, 3075 { AR_SREV_VERSION_9285, "9285" }, 3076 { AR_SREV_VERSION_9287, "9287" }, 3077 { AR_SREV_VERSION_9271, "9271" }, 3078 { AR_SREV_VERSION_9300, "9300" }, 3079 { AR_SREV_VERSION_9330, "9330" }, 3080 { AR_SREV_VERSION_9340, "9340" }, 3081 { AR_SREV_VERSION_9485, "9485" }, 3082 { AR_SREV_VERSION_9462, "9462" }, 3083 { AR_SREV_VERSION_9550, "9550" }, 3084 { AR_SREV_VERSION_9565, "9565" }, 3085 { AR_SREV_VERSION_9531, "9531" }, 3086 }; 3087 3088 /* For devices with external radios */ 3089 static struct { 3090 u16 version; 3091 const char * name; 3092 } ath_rf_names[] = { 3093 { 0, "5133" }, 3094 { AR_RAD5133_SREV_MAJOR, "5133" }, 3095 { AR_RAD5122_SREV_MAJOR, "5122" }, 3096 { AR_RAD2133_SREV_MAJOR, "2133" }, 3097 { AR_RAD2122_SREV_MAJOR, "2122" } 3098 }; 3099 3100 /* 3101 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3102 */ 3103 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3104 { 3105 int i; 3106 3107 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3108 if (ath_mac_bb_names[i].version == mac_bb_version) { 3109 return ath_mac_bb_names[i].name; 3110 } 3111 } 3112 3113 return "????"; 3114 } 3115 3116 /* 3117 * Return the RF name. "????" is returned if the RF is unknown. 3118 * Used for devices with external radios. 3119 */ 3120 static const char *ath9k_hw_rf_name(u16 rf_version) 3121 { 3122 int i; 3123 3124 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3125 if (ath_rf_names[i].version == rf_version) { 3126 return ath_rf_names[i].name; 3127 } 3128 } 3129 3130 return "????"; 3131 } 3132 3133 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3134 { 3135 int used; 3136 3137 /* chipsets >= AR9280 are single-chip */ 3138 if (AR_SREV_9280_20_OR_LATER(ah)) { 3139 used = scnprintf(hw_name, len, 3140 "Atheros AR%s Rev:%x", 3141 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3142 ah->hw_version.macRev); 3143 } 3144 else { 3145 used = scnprintf(hw_name, len, 3146 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3147 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3148 ah->hw_version.macRev, 3149 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3150 & AR_RADIO_SREV_MAJOR)), 3151 ah->hw_version.phyRev); 3152 } 3153 3154 hw_name[used] = '\0'; 3155 } 3156 EXPORT_SYMBOL(ath9k_hw_name); 3157