1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 29 30 MODULE_AUTHOR("Atheros Communications"); 31 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 32 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 33 MODULE_LICENSE("Dual BSD/GPL"); 34 35 static int __init ath9k_init(void) 36 { 37 return 0; 38 } 39 module_init(ath9k_init); 40 41 static void __exit ath9k_exit(void) 42 { 43 return; 44 } 45 module_exit(ath9k_exit); 46 47 /* Private hardware callbacks */ 48 49 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 50 { 51 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 52 } 53 54 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 55 { 56 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 57 } 58 59 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 60 struct ath9k_channel *chan) 61 { 62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 63 } 64 65 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 66 { 67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 68 return; 69 70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 71 } 72 73 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 74 { 75 /* You will not have this callback if using the old ANI */ 76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 77 return; 78 79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 80 } 81 82 /********************/ 83 /* Helper Functions */ 84 /********************/ 85 86 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 87 { 88 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 89 struct ath_common *common = ath9k_hw_common(ah); 90 unsigned int clockrate; 91 92 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 93 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 94 clockrate = 117; 95 else if (!ah->curchan) /* should really check for CCK instead */ 96 clockrate = ATH9K_CLOCK_RATE_CCK; 97 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 98 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 99 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 100 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 101 else 102 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 103 104 if (conf_is_ht40(conf)) 105 clockrate *= 2; 106 107 if (ah->curchan) { 108 if (IS_CHAN_HALF_RATE(ah->curchan)) 109 clockrate /= 2; 110 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 111 clockrate /= 4; 112 } 113 114 common->clockrate = clockrate; 115 } 116 117 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 118 { 119 struct ath_common *common = ath9k_hw_common(ah); 120 121 return usecs * common->clockrate; 122 } 123 124 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 125 { 126 int i; 127 128 BUG_ON(timeout < AH_TIME_QUANTUM); 129 130 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 131 if ((REG_READ(ah, reg) & mask) == val) 132 return true; 133 134 udelay(AH_TIME_QUANTUM); 135 } 136 137 ath_dbg(ath9k_hw_common(ah), ANY, 138 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 139 timeout, reg, REG_READ(ah, reg), mask, val); 140 141 return false; 142 } 143 EXPORT_SYMBOL(ath9k_hw_wait); 144 145 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 146 int column, unsigned int *writecnt) 147 { 148 int r; 149 150 ENABLE_REGWRITE_BUFFER(ah); 151 for (r = 0; r < array->ia_rows; r++) { 152 REG_WRITE(ah, INI_RA(array, r, 0), 153 INI_RA(array, r, column)); 154 DO_DELAY(*writecnt); 155 } 156 REGWRITE_BUFFER_FLUSH(ah); 157 } 158 159 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 160 { 161 u32 retval; 162 int i; 163 164 for (i = 0, retval = 0; i < n; i++) { 165 retval = (retval << 1) | (val & 1); 166 val >>= 1; 167 } 168 return retval; 169 } 170 171 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 172 u8 phy, int kbps, 173 u32 frameLen, u16 rateix, 174 bool shortPreamble) 175 { 176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 177 178 if (kbps == 0) 179 return 0; 180 181 switch (phy) { 182 case WLAN_RC_PHY_CCK: 183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 184 if (shortPreamble) 185 phyTime >>= 1; 186 numBits = frameLen << 3; 187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 188 break; 189 case WLAN_RC_PHY_OFDM: 190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 192 numBits = OFDM_PLCP_BITS + (frameLen << 3); 193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 194 txTime = OFDM_SIFS_TIME_QUARTER 195 + OFDM_PREAMBLE_TIME_QUARTER 196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 197 } else if (ah->curchan && 198 IS_CHAN_HALF_RATE(ah->curchan)) { 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 200 numBits = OFDM_PLCP_BITS + (frameLen << 3); 201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 202 txTime = OFDM_SIFS_TIME_HALF + 203 OFDM_PREAMBLE_TIME_HALF 204 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 205 } else { 206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 207 numBits = OFDM_PLCP_BITS + (frameLen << 3); 208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 210 + (numSymbols * OFDM_SYMBOL_TIME); 211 } 212 break; 213 default: 214 ath_err(ath9k_hw_common(ah), 215 "Unknown phy %u (rate ix %u)\n", phy, rateix); 216 txTime = 0; 217 break; 218 } 219 220 return txTime; 221 } 222 EXPORT_SYMBOL(ath9k_hw_computetxtime); 223 224 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 225 struct ath9k_channel *chan, 226 struct chan_centers *centers) 227 { 228 int8_t extoff; 229 230 if (!IS_CHAN_HT40(chan)) { 231 centers->ctl_center = centers->ext_center = 232 centers->synth_center = chan->channel; 233 return; 234 } 235 236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 237 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 238 centers->synth_center = 239 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 240 extoff = 1; 241 } else { 242 centers->synth_center = 243 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 244 extoff = -1; 245 } 246 247 centers->ctl_center = 248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 249 /* 25 MHz spacing is supported by hw but not on upper layers */ 250 centers->ext_center = 251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 252 } 253 254 /******************/ 255 /* Chip Revisions */ 256 /******************/ 257 258 static void ath9k_hw_read_revisions(struct ath_hw *ah) 259 { 260 u32 val; 261 262 switch (ah->hw_version.devid) { 263 case AR5416_AR9100_DEVID: 264 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 265 break; 266 case AR9300_DEVID_AR9330: 267 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 268 if (ah->get_mac_revision) { 269 ah->hw_version.macRev = ah->get_mac_revision(); 270 } else { 271 val = REG_READ(ah, AR_SREV); 272 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 273 } 274 return; 275 case AR9300_DEVID_AR9340: 276 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 277 val = REG_READ(ah, AR_SREV); 278 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 279 return; 280 } 281 282 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 283 284 if (val == 0xFF) { 285 val = REG_READ(ah, AR_SREV); 286 ah->hw_version.macVersion = 287 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 288 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 289 290 if (AR_SREV_9462(ah)) 291 ah->is_pciexpress = true; 292 else 293 ah->is_pciexpress = (val & 294 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 295 } else { 296 if (!AR_SREV_9100(ah)) 297 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 298 299 ah->hw_version.macRev = val & AR_SREV_REVISION; 300 301 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 302 ah->is_pciexpress = true; 303 } 304 } 305 306 /************************************/ 307 /* HW Attach, Detach, Init Routines */ 308 /************************************/ 309 310 static void ath9k_hw_disablepcie(struct ath_hw *ah) 311 { 312 if (!AR_SREV_5416(ah)) 313 return; 314 315 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 317 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 324 325 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 326 } 327 328 static void ath9k_hw_aspm_init(struct ath_hw *ah) 329 { 330 struct ath_common *common = ath9k_hw_common(ah); 331 332 if (common->bus_ops->aspm_init) 333 common->bus_ops->aspm_init(common); 334 } 335 336 /* This should work for all families including legacy */ 337 static bool ath9k_hw_chip_test(struct ath_hw *ah) 338 { 339 struct ath_common *common = ath9k_hw_common(ah); 340 u32 regAddr[2] = { AR_STA_ID0 }; 341 u32 regHold[2]; 342 static const u32 patternData[4] = { 343 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 344 }; 345 int i, j, loop_max; 346 347 if (!AR_SREV_9300_20_OR_LATER(ah)) { 348 loop_max = 2; 349 regAddr[1] = AR_PHY_BASE + (8 << 2); 350 } else 351 loop_max = 1; 352 353 for (i = 0; i < loop_max; i++) { 354 u32 addr = regAddr[i]; 355 u32 wrData, rdData; 356 357 regHold[i] = REG_READ(ah, addr); 358 for (j = 0; j < 0x100; j++) { 359 wrData = (j << 16) | j; 360 REG_WRITE(ah, addr, wrData); 361 rdData = REG_READ(ah, addr); 362 if (rdData != wrData) { 363 ath_err(common, 364 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 365 addr, wrData, rdData); 366 return false; 367 } 368 } 369 for (j = 0; j < 4; j++) { 370 wrData = patternData[j]; 371 REG_WRITE(ah, addr, wrData); 372 rdData = REG_READ(ah, addr); 373 if (wrData != rdData) { 374 ath_err(common, 375 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 376 addr, wrData, rdData); 377 return false; 378 } 379 } 380 REG_WRITE(ah, regAddr[i], regHold[i]); 381 } 382 udelay(100); 383 384 return true; 385 } 386 387 static void ath9k_hw_init_config(struct ath_hw *ah) 388 { 389 int i; 390 391 ah->config.dma_beacon_response_time = 2; 392 ah->config.sw_beacon_response_time = 10; 393 ah->config.additional_swba_backoff = 0; 394 ah->config.ack_6mb = 0x0; 395 ah->config.cwm_ignore_extcca = 0; 396 ah->config.pcie_clock_req = 0; 397 ah->config.pcie_waen = 0; 398 ah->config.analog_shiftreg = 1; 399 ah->config.enable_ani = true; 400 401 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 402 ah->config.spurchans[i][0] = AR_NO_SPUR; 403 ah->config.spurchans[i][1] = AR_NO_SPUR; 404 } 405 406 /* PAPRD needs some more work to be enabled */ 407 ah->config.paprd_disable = 1; 408 409 ah->config.rx_intr_mitigation = true; 410 ah->config.pcieSerDesWrite = true; 411 412 /* 413 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 414 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 415 * This means we use it for all AR5416 devices, and the few 416 * minor PCI AR9280 devices out there. 417 * 418 * Serialization is required because these devices do not handle 419 * well the case of two concurrent reads/writes due to the latency 420 * involved. During one read/write another read/write can be issued 421 * on another CPU while the previous read/write may still be working 422 * on our hardware, if we hit this case the hardware poops in a loop. 423 * We prevent this by serializing reads and writes. 424 * 425 * This issue is not present on PCI-Express devices or pre-AR5416 426 * devices (legacy, 802.11abg). 427 */ 428 if (num_possible_cpus() > 1) 429 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 430 } 431 432 static void ath9k_hw_init_defaults(struct ath_hw *ah) 433 { 434 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 435 436 regulatory->country_code = CTRY_DEFAULT; 437 regulatory->power_limit = MAX_RATE_POWER; 438 439 ah->hw_version.magic = AR5416_MAGIC; 440 ah->hw_version.subvendorid = 0; 441 442 ah->atim_window = 0; 443 ah->sta_id1_defaults = 444 AR_STA_ID1_CRPT_MIC_ENABLE | 445 AR_STA_ID1_MCAST_KSRCH; 446 if (AR_SREV_9100(ah)) 447 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 448 ah->enable_32kHz_clock = DONT_USE_32KHZ; 449 ah->slottime = ATH9K_SLOT_TIME_9; 450 ah->globaltxtimeout = (u32) -1; 451 ah->power_mode = ATH9K_PM_UNDEFINED; 452 ah->htc_reset_init = true; 453 } 454 455 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 456 { 457 struct ath_common *common = ath9k_hw_common(ah); 458 u32 sum; 459 int i; 460 u16 eeval; 461 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 462 463 sum = 0; 464 for (i = 0; i < 3; i++) { 465 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 466 sum += eeval; 467 common->macaddr[2 * i] = eeval >> 8; 468 common->macaddr[2 * i + 1] = eeval & 0xff; 469 } 470 if (sum == 0 || sum == 0xffff * 3) 471 return -EADDRNOTAVAIL; 472 473 return 0; 474 } 475 476 static int ath9k_hw_post_init(struct ath_hw *ah) 477 { 478 struct ath_common *common = ath9k_hw_common(ah); 479 int ecode; 480 481 if (common->bus_ops->ath_bus_type != ATH_USB) { 482 if (!ath9k_hw_chip_test(ah)) 483 return -ENODEV; 484 } 485 486 if (!AR_SREV_9300_20_OR_LATER(ah)) { 487 ecode = ar9002_hw_rf_claim(ah); 488 if (ecode != 0) 489 return ecode; 490 } 491 492 ecode = ath9k_hw_eeprom_init(ah); 493 if (ecode != 0) 494 return ecode; 495 496 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 497 ah->eep_ops->get_eeprom_ver(ah), 498 ah->eep_ops->get_eeprom_rev(ah)); 499 500 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 501 if (ecode) { 502 ath_err(ath9k_hw_common(ah), 503 "Failed allocating banks for external radio\n"); 504 ath9k_hw_rf_free_ext_banks(ah); 505 return ecode; 506 } 507 508 if (ah->config.enable_ani) { 509 ath9k_hw_ani_setup(ah); 510 ath9k_hw_ani_init(ah); 511 } 512 513 return 0; 514 } 515 516 static void ath9k_hw_attach_ops(struct ath_hw *ah) 517 { 518 if (AR_SREV_9300_20_OR_LATER(ah)) 519 ar9003_hw_attach_ops(ah); 520 else 521 ar9002_hw_attach_ops(ah); 522 } 523 524 /* Called for all hardware families */ 525 static int __ath9k_hw_init(struct ath_hw *ah) 526 { 527 struct ath_common *common = ath9k_hw_common(ah); 528 int r = 0; 529 530 ath9k_hw_read_revisions(ah); 531 532 /* 533 * Read back AR_WA into a permanent copy and set bits 14 and 17. 534 * We need to do this to avoid RMW of this register. We cannot 535 * read the reg when chip is asleep. 536 */ 537 ah->WARegVal = REG_READ(ah, AR_WA); 538 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 539 AR_WA_ASPM_TIMER_BASED_DISABLE); 540 541 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 542 ath_err(common, "Couldn't reset chip\n"); 543 return -EIO; 544 } 545 546 if (AR_SREV_9462(ah)) 547 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 548 549 ath9k_hw_init_defaults(ah); 550 ath9k_hw_init_config(ah); 551 552 ath9k_hw_attach_ops(ah); 553 554 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 555 ath_err(common, "Couldn't wakeup chip\n"); 556 return -EIO; 557 } 558 559 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 560 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 561 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 562 !ah->is_pciexpress)) { 563 ah->config.serialize_regmode = 564 SER_REG_MODE_ON; 565 } else { 566 ah->config.serialize_regmode = 567 SER_REG_MODE_OFF; 568 } 569 } 570 571 ath_dbg(common, RESET, "serialize_regmode is %d\n", 572 ah->config.serialize_regmode); 573 574 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 576 else 577 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 578 579 switch (ah->hw_version.macVersion) { 580 case AR_SREV_VERSION_5416_PCI: 581 case AR_SREV_VERSION_5416_PCIE: 582 case AR_SREV_VERSION_9160: 583 case AR_SREV_VERSION_9100: 584 case AR_SREV_VERSION_9280: 585 case AR_SREV_VERSION_9285: 586 case AR_SREV_VERSION_9287: 587 case AR_SREV_VERSION_9271: 588 case AR_SREV_VERSION_9300: 589 case AR_SREV_VERSION_9330: 590 case AR_SREV_VERSION_9485: 591 case AR_SREV_VERSION_9340: 592 case AR_SREV_VERSION_9462: 593 break; 594 default: 595 ath_err(common, 596 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 597 ah->hw_version.macVersion, ah->hw_version.macRev); 598 return -EOPNOTSUPP; 599 } 600 601 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 602 AR_SREV_9330(ah)) 603 ah->is_pciexpress = false; 604 605 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 606 ath9k_hw_init_cal_settings(ah); 607 608 ah->ani_function = ATH9K_ANI_ALL; 609 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 610 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 611 if (!AR_SREV_9300_20_OR_LATER(ah)) 612 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 613 614 /* disable ANI for 9340 */ 615 if (AR_SREV_9340(ah)) 616 ah->config.enable_ani = false; 617 618 ath9k_hw_init_mode_regs(ah); 619 620 if (!ah->is_pciexpress) 621 ath9k_hw_disablepcie(ah); 622 623 r = ath9k_hw_post_init(ah); 624 if (r) 625 return r; 626 627 ath9k_hw_init_mode_gain_regs(ah); 628 r = ath9k_hw_fill_cap_info(ah); 629 if (r) 630 return r; 631 632 if (ah->is_pciexpress) 633 ath9k_hw_aspm_init(ah); 634 635 r = ath9k_hw_init_macaddr(ah); 636 if (r) { 637 ath_err(common, "Failed to initialize MAC address\n"); 638 return r; 639 } 640 641 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 642 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 643 else 644 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 645 646 if (AR_SREV_9330(ah)) 647 ah->bb_watchdog_timeout_ms = 85; 648 else 649 ah->bb_watchdog_timeout_ms = 25; 650 651 common->state = ATH_HW_INITIALIZED; 652 653 return 0; 654 } 655 656 int ath9k_hw_init(struct ath_hw *ah) 657 { 658 int ret; 659 struct ath_common *common = ath9k_hw_common(ah); 660 661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 662 switch (ah->hw_version.devid) { 663 case AR5416_DEVID_PCI: 664 case AR5416_DEVID_PCIE: 665 case AR5416_AR9100_DEVID: 666 case AR9160_DEVID_PCI: 667 case AR9280_DEVID_PCI: 668 case AR9280_DEVID_PCIE: 669 case AR9285_DEVID_PCIE: 670 case AR9287_DEVID_PCI: 671 case AR9287_DEVID_PCIE: 672 case AR2427_DEVID_PCIE: 673 case AR9300_DEVID_PCIE: 674 case AR9300_DEVID_AR9485_PCIE: 675 case AR9300_DEVID_AR9330: 676 case AR9300_DEVID_AR9340: 677 case AR9300_DEVID_AR9580: 678 case AR9300_DEVID_AR9462: 679 break; 680 default: 681 if (common->bus_ops->ath_bus_type == ATH_USB) 682 break; 683 ath_err(common, "Hardware device ID 0x%04x not supported\n", 684 ah->hw_version.devid); 685 return -EOPNOTSUPP; 686 } 687 688 ret = __ath9k_hw_init(ah); 689 if (ret) { 690 ath_err(common, 691 "Unable to initialize hardware; initialization status: %d\n", 692 ret); 693 return ret; 694 } 695 696 return 0; 697 } 698 EXPORT_SYMBOL(ath9k_hw_init); 699 700 static void ath9k_hw_init_qos(struct ath_hw *ah) 701 { 702 ENABLE_REGWRITE_BUFFER(ah); 703 704 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 705 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 706 707 REG_WRITE(ah, AR_QOS_NO_ACK, 708 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 709 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 710 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 711 712 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 713 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 714 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 715 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 716 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 717 718 REGWRITE_BUFFER_FLUSH(ah); 719 } 720 721 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 722 { 723 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 724 udelay(100); 725 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 726 727 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 728 udelay(100); 729 730 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 731 } 732 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 733 734 static void ath9k_hw_init_pll(struct ath_hw *ah, 735 struct ath9k_channel *chan) 736 { 737 u32 pll; 738 739 if (AR_SREV_9485(ah)) { 740 741 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 743 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 745 AR_CH0_DPLL2_KD, 0x40); 746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 747 AR_CH0_DPLL2_KI, 0x4); 748 749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 750 AR_CH0_BB_DPLL1_REFDIV, 0x5); 751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 752 AR_CH0_BB_DPLL1_NINI, 0x58); 753 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 754 AR_CH0_BB_DPLL1_NFRAC, 0x0); 755 756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 757 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 759 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 761 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 762 763 /* program BB PLL phase_shift to 0x6 */ 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 765 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 766 767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 768 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 769 udelay(1000); 770 } else if (AR_SREV_9330(ah)) { 771 u32 ddr_dpll2, pll_control2, kd; 772 773 if (ah->is_clk_25mhz) { 774 ddr_dpll2 = 0x18e82f01; 775 pll_control2 = 0xe04a3d; 776 kd = 0x1d; 777 } else { 778 ddr_dpll2 = 0x19e82f01; 779 pll_control2 = 0x886666; 780 kd = 0x3d; 781 } 782 783 /* program DDR PLL ki and kd value */ 784 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 785 786 /* program DDR PLL phase_shift */ 787 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 788 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 789 790 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 791 udelay(1000); 792 793 /* program refdiv, nint, frac to RTC register */ 794 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 795 796 /* program BB PLL kd and ki value */ 797 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 799 800 /* program BB PLL phase_shift */ 801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 802 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 803 } else if (AR_SREV_9340(ah)) { 804 u32 regval, pll2_divint, pll2_divfrac, refdiv; 805 806 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 807 udelay(1000); 808 809 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 810 udelay(100); 811 812 if (ah->is_clk_25mhz) { 813 pll2_divint = 0x54; 814 pll2_divfrac = 0x1eb85; 815 refdiv = 3; 816 } else { 817 pll2_divint = 88; 818 pll2_divfrac = 0; 819 refdiv = 5; 820 } 821 822 regval = REG_READ(ah, AR_PHY_PLL_MODE); 823 regval |= (0x1 << 16); 824 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 825 udelay(100); 826 827 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 828 (pll2_divint << 18) | pll2_divfrac); 829 udelay(100); 830 831 regval = REG_READ(ah, AR_PHY_PLL_MODE); 832 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 833 (0x4 << 26) | (0x18 << 19); 834 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 835 REG_WRITE(ah, AR_PHY_PLL_MODE, 836 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 837 udelay(1000); 838 } 839 840 pll = ath9k_hw_compute_pll_control(ah, chan); 841 842 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 843 844 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 845 udelay(1000); 846 847 /* Switch the core clock for ar9271 to 117Mhz */ 848 if (AR_SREV_9271(ah)) { 849 udelay(500); 850 REG_WRITE(ah, 0x50040, 0x304); 851 } 852 853 udelay(RTC_PLL_SETTLE_DELAY); 854 855 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 856 857 if (AR_SREV_9340(ah)) { 858 if (ah->is_clk_25mhz) { 859 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 860 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 861 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 862 } else { 863 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 864 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 865 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 866 } 867 udelay(100); 868 } 869 } 870 871 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 872 enum nl80211_iftype opmode) 873 { 874 u32 sync_default = AR_INTR_SYNC_DEFAULT; 875 u32 imr_reg = AR_IMR_TXERR | 876 AR_IMR_TXURN | 877 AR_IMR_RXERR | 878 AR_IMR_RXORN | 879 AR_IMR_BCNMISC; 880 881 if (AR_SREV_9340(ah)) 882 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 883 884 if (AR_SREV_9300_20_OR_LATER(ah)) { 885 imr_reg |= AR_IMR_RXOK_HP; 886 if (ah->config.rx_intr_mitigation) 887 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 888 else 889 imr_reg |= AR_IMR_RXOK_LP; 890 891 } else { 892 if (ah->config.rx_intr_mitigation) 893 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 894 else 895 imr_reg |= AR_IMR_RXOK; 896 } 897 898 if (ah->config.tx_intr_mitigation) 899 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 900 else 901 imr_reg |= AR_IMR_TXOK; 902 903 if (opmode == NL80211_IFTYPE_AP) 904 imr_reg |= AR_IMR_MIB; 905 906 ENABLE_REGWRITE_BUFFER(ah); 907 908 REG_WRITE(ah, AR_IMR, imr_reg); 909 ah->imrs2_reg |= AR_IMR_S2_GTT; 910 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 911 912 if (!AR_SREV_9100(ah)) { 913 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 914 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 915 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 916 } 917 918 REGWRITE_BUFFER_FLUSH(ah); 919 920 if (AR_SREV_9300_20_OR_LATER(ah)) { 921 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 923 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 925 } 926 } 927 928 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 929 { 930 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 931 val = min(val, (u32) 0xFFFF); 932 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 933 } 934 935 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 936 { 937 u32 val = ath9k_hw_mac_to_clks(ah, us); 938 val = min(val, (u32) 0xFFFF); 939 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 940 } 941 942 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 943 { 944 u32 val = ath9k_hw_mac_to_clks(ah, us); 945 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 946 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 947 } 948 949 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 950 { 951 u32 val = ath9k_hw_mac_to_clks(ah, us); 952 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 953 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 954 } 955 956 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 957 { 958 if (tu > 0xFFFF) { 959 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 960 tu); 961 ah->globaltxtimeout = (u32) -1; 962 return false; 963 } else { 964 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 965 ah->globaltxtimeout = tu; 966 return true; 967 } 968 } 969 970 void ath9k_hw_init_global_settings(struct ath_hw *ah) 971 { 972 struct ath_common *common = ath9k_hw_common(ah); 973 struct ieee80211_conf *conf = &common->hw->conf; 974 const struct ath9k_channel *chan = ah->curchan; 975 int acktimeout, ctstimeout; 976 int slottime; 977 int sifstime; 978 int rx_lat = 0, tx_lat = 0, eifs = 0; 979 u32 reg; 980 981 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 982 ah->misc_mode); 983 984 if (!chan) 985 return; 986 987 if (ah->misc_mode != 0) 988 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 989 990 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 991 rx_lat = 41; 992 else 993 rx_lat = 37; 994 tx_lat = 54; 995 996 if (IS_CHAN_HALF_RATE(chan)) { 997 eifs = 175; 998 rx_lat *= 2; 999 tx_lat *= 2; 1000 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1001 tx_lat += 11; 1002 1003 slottime = 13; 1004 sifstime = 32; 1005 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1006 eifs = 340; 1007 rx_lat = (rx_lat * 4) - 1; 1008 tx_lat *= 4; 1009 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1010 tx_lat += 22; 1011 1012 slottime = 21; 1013 sifstime = 64; 1014 } else { 1015 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1016 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1017 reg = AR_USEC_ASYNC_FIFO; 1018 } else { 1019 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1020 common->clockrate; 1021 reg = REG_READ(ah, AR_USEC); 1022 } 1023 rx_lat = MS(reg, AR_USEC_RX_LAT); 1024 tx_lat = MS(reg, AR_USEC_TX_LAT); 1025 1026 slottime = ah->slottime; 1027 if (IS_CHAN_5GHZ(chan)) 1028 sifstime = 16; 1029 else 1030 sifstime = 10; 1031 } 1032 1033 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1034 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1035 ctstimeout = acktimeout; 1036 1037 /* 1038 * Workaround for early ACK timeouts, add an offset to match the 1039 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1040 * This was initially only meant to work around an issue with delayed 1041 * BA frames in some implementations, but it has been found to fix ACK 1042 * timeout issues in other cases as well. 1043 */ 1044 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) { 1045 acktimeout += 64 - sifstime - ah->slottime; 1046 ctstimeout += 48 - sifstime - ah->slottime; 1047 } 1048 1049 1050 ath9k_hw_set_sifs_time(ah, sifstime); 1051 ath9k_hw_setslottime(ah, slottime); 1052 ath9k_hw_set_ack_timeout(ah, acktimeout); 1053 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1054 if (ah->globaltxtimeout != (u32) -1) 1055 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1056 1057 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1058 REG_RMW(ah, AR_USEC, 1059 (common->clockrate - 1) | 1060 SM(rx_lat, AR_USEC_RX_LAT) | 1061 SM(tx_lat, AR_USEC_TX_LAT), 1062 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1063 1064 } 1065 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1066 1067 void ath9k_hw_deinit(struct ath_hw *ah) 1068 { 1069 struct ath_common *common = ath9k_hw_common(ah); 1070 1071 if (common->state < ATH_HW_INITIALIZED) 1072 goto free_hw; 1073 1074 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1075 1076 free_hw: 1077 ath9k_hw_rf_free_ext_banks(ah); 1078 } 1079 EXPORT_SYMBOL(ath9k_hw_deinit); 1080 1081 /*******/ 1082 /* INI */ 1083 /*******/ 1084 1085 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1086 { 1087 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1088 1089 if (IS_CHAN_B(chan)) 1090 ctl |= CTL_11B; 1091 else if (IS_CHAN_G(chan)) 1092 ctl |= CTL_11G; 1093 else 1094 ctl |= CTL_11A; 1095 1096 return ctl; 1097 } 1098 1099 /****************************************/ 1100 /* Reset and Channel Switching Routines */ 1101 /****************************************/ 1102 1103 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1104 { 1105 struct ath_common *common = ath9k_hw_common(ah); 1106 1107 ENABLE_REGWRITE_BUFFER(ah); 1108 1109 /* 1110 * set AHB_MODE not to do cacheline prefetches 1111 */ 1112 if (!AR_SREV_9300_20_OR_LATER(ah)) 1113 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1114 1115 /* 1116 * let mac dma reads be in 128 byte chunks 1117 */ 1118 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1119 1120 REGWRITE_BUFFER_FLUSH(ah); 1121 1122 /* 1123 * Restore TX Trigger Level to its pre-reset value. 1124 * The initial value depends on whether aggregation is enabled, and is 1125 * adjusted whenever underruns are detected. 1126 */ 1127 if (!AR_SREV_9300_20_OR_LATER(ah)) 1128 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1129 1130 ENABLE_REGWRITE_BUFFER(ah); 1131 1132 /* 1133 * let mac dma writes be in 128 byte chunks 1134 */ 1135 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1136 1137 /* 1138 * Setup receive FIFO threshold to hold off TX activities 1139 */ 1140 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1141 1142 if (AR_SREV_9300_20_OR_LATER(ah)) { 1143 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1145 1146 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1147 ah->caps.rx_status_len); 1148 } 1149 1150 /* 1151 * reduce the number of usable entries in PCU TXBUF to avoid 1152 * wrap around issues. 1153 */ 1154 if (AR_SREV_9285(ah)) { 1155 /* For AR9285 the number of Fifos are reduced to half. 1156 * So set the usable tx buf size also to half to 1157 * avoid data/delimiter underruns 1158 */ 1159 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1160 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1161 } else if (!AR_SREV_9271(ah)) { 1162 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1163 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1164 } 1165 1166 REGWRITE_BUFFER_FLUSH(ah); 1167 1168 if (AR_SREV_9300_20_OR_LATER(ah)) 1169 ath9k_hw_reset_txstatus_ring(ah); 1170 } 1171 1172 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1173 { 1174 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1175 u32 set = AR_STA_ID1_KSRCH_MODE; 1176 1177 switch (opmode) { 1178 case NL80211_IFTYPE_ADHOC: 1179 case NL80211_IFTYPE_MESH_POINT: 1180 set |= AR_STA_ID1_ADHOC; 1181 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1182 break; 1183 case NL80211_IFTYPE_AP: 1184 set |= AR_STA_ID1_STA_AP; 1185 /* fall through */ 1186 case NL80211_IFTYPE_STATION: 1187 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1188 break; 1189 default: 1190 if (!ah->is_monitoring) 1191 set = 0; 1192 break; 1193 } 1194 REG_RMW(ah, AR_STA_ID1, set, mask); 1195 } 1196 1197 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1198 u32 *coef_mantissa, u32 *coef_exponent) 1199 { 1200 u32 coef_exp, coef_man; 1201 1202 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1203 if ((coef_scaled >> coef_exp) & 0x1) 1204 break; 1205 1206 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1207 1208 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1209 1210 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1211 *coef_exponent = coef_exp - 16; 1212 } 1213 1214 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1215 { 1216 u32 rst_flags; 1217 u32 tmpReg; 1218 1219 if (AR_SREV_9100(ah)) { 1220 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1221 AR_RTC_DERIVED_CLK_PERIOD, 1); 1222 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1223 } 1224 1225 ENABLE_REGWRITE_BUFFER(ah); 1226 1227 if (AR_SREV_9300_20_OR_LATER(ah)) { 1228 REG_WRITE(ah, AR_WA, ah->WARegVal); 1229 udelay(10); 1230 } 1231 1232 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1233 AR_RTC_FORCE_WAKE_ON_INT); 1234 1235 if (AR_SREV_9100(ah)) { 1236 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1237 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1238 } else { 1239 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1240 if (tmpReg & 1241 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1242 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1243 u32 val; 1244 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1245 1246 val = AR_RC_HOSTIF; 1247 if (!AR_SREV_9300_20_OR_LATER(ah)) 1248 val |= AR_RC_AHB; 1249 REG_WRITE(ah, AR_RC, val); 1250 1251 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1252 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1253 1254 rst_flags = AR_RTC_RC_MAC_WARM; 1255 if (type == ATH9K_RESET_COLD) 1256 rst_flags |= AR_RTC_RC_MAC_COLD; 1257 } 1258 1259 if (AR_SREV_9330(ah)) { 1260 int npend = 0; 1261 int i; 1262 1263 /* AR9330 WAR: 1264 * call external reset function to reset WMAC if: 1265 * - doing a cold reset 1266 * - we have pending frames in the TX queues 1267 */ 1268 1269 for (i = 0; i < AR_NUM_QCU; i++) { 1270 npend = ath9k_hw_numtxpending(ah, i); 1271 if (npend) 1272 break; 1273 } 1274 1275 if (ah->external_reset && 1276 (npend || type == ATH9K_RESET_COLD)) { 1277 int reset_err = 0; 1278 1279 ath_dbg(ath9k_hw_common(ah), RESET, 1280 "reset MAC via external reset\n"); 1281 1282 reset_err = ah->external_reset(); 1283 if (reset_err) { 1284 ath_err(ath9k_hw_common(ah), 1285 "External reset failed, err=%d\n", 1286 reset_err); 1287 return false; 1288 } 1289 1290 REG_WRITE(ah, AR_RTC_RESET, 1); 1291 } 1292 } 1293 1294 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1295 1296 REGWRITE_BUFFER_FLUSH(ah); 1297 1298 udelay(50); 1299 1300 REG_WRITE(ah, AR_RTC_RC, 0); 1301 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1302 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1303 return false; 1304 } 1305 1306 if (!AR_SREV_9100(ah)) 1307 REG_WRITE(ah, AR_RC, 0); 1308 1309 if (AR_SREV_9100(ah)) 1310 udelay(50); 1311 1312 return true; 1313 } 1314 1315 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1316 { 1317 ENABLE_REGWRITE_BUFFER(ah); 1318 1319 if (AR_SREV_9300_20_OR_LATER(ah)) { 1320 REG_WRITE(ah, AR_WA, ah->WARegVal); 1321 udelay(10); 1322 } 1323 1324 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1325 AR_RTC_FORCE_WAKE_ON_INT); 1326 1327 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1328 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1329 1330 REG_WRITE(ah, AR_RTC_RESET, 0); 1331 1332 REGWRITE_BUFFER_FLUSH(ah); 1333 1334 if (!AR_SREV_9300_20_OR_LATER(ah)) 1335 udelay(2); 1336 1337 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1338 REG_WRITE(ah, AR_RC, 0); 1339 1340 REG_WRITE(ah, AR_RTC_RESET, 1); 1341 1342 if (!ath9k_hw_wait(ah, 1343 AR_RTC_STATUS, 1344 AR_RTC_STATUS_M, 1345 AR_RTC_STATUS_ON, 1346 AH_WAIT_TIMEOUT)) { 1347 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1348 return false; 1349 } 1350 1351 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1352 } 1353 1354 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1355 { 1356 bool ret = false; 1357 1358 if (AR_SREV_9300_20_OR_LATER(ah)) { 1359 REG_WRITE(ah, AR_WA, ah->WARegVal); 1360 udelay(10); 1361 } 1362 1363 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1364 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1365 1366 switch (type) { 1367 case ATH9K_RESET_POWER_ON: 1368 ret = ath9k_hw_set_reset_power_on(ah); 1369 break; 1370 case ATH9K_RESET_WARM: 1371 case ATH9K_RESET_COLD: 1372 ret = ath9k_hw_set_reset(ah, type); 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 1379 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1380 1381 return ret; 1382 } 1383 1384 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1385 struct ath9k_channel *chan) 1386 { 1387 int reset_type = ATH9K_RESET_WARM; 1388 1389 if (AR_SREV_9280(ah)) { 1390 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1391 reset_type = ATH9K_RESET_POWER_ON; 1392 else 1393 reset_type = ATH9K_RESET_COLD; 1394 } 1395 1396 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1397 return false; 1398 1399 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1400 return false; 1401 1402 ah->chip_fullsleep = false; 1403 ath9k_hw_init_pll(ah, chan); 1404 ath9k_hw_set_rfmode(ah, chan); 1405 1406 return true; 1407 } 1408 1409 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1410 struct ath9k_channel *chan) 1411 { 1412 struct ath_common *common = ath9k_hw_common(ah); 1413 u32 qnum; 1414 int r; 1415 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1416 bool band_switch, mode_diff; 1417 u8 ini_reloaded; 1418 1419 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1420 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1421 CHANNEL_5GHZ)); 1422 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1423 1424 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1425 if (ath9k_hw_numtxpending(ah, qnum)) { 1426 ath_dbg(common, QUEUE, 1427 "Transmit frames pending on queue %d\n", qnum); 1428 return false; 1429 } 1430 } 1431 1432 if (!ath9k_hw_rfbus_req(ah)) { 1433 ath_err(common, "Could not kill baseband RX\n"); 1434 return false; 1435 } 1436 1437 if (edma && (band_switch || mode_diff)) { 1438 ath9k_hw_mark_phy_inactive(ah); 1439 udelay(5); 1440 1441 ath9k_hw_init_pll(ah, NULL); 1442 1443 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1444 ath_err(common, "Failed to do fast channel change\n"); 1445 return false; 1446 } 1447 } 1448 1449 ath9k_hw_set_channel_regs(ah, chan); 1450 1451 r = ath9k_hw_rf_set_freq(ah, chan); 1452 if (r) { 1453 ath_err(common, "Failed to set channel\n"); 1454 return false; 1455 } 1456 ath9k_hw_set_clockrate(ah); 1457 ath9k_hw_apply_txpower(ah, chan, false); 1458 ath9k_hw_rfbus_done(ah); 1459 1460 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1461 ath9k_hw_set_delta_slope(ah, chan); 1462 1463 ath9k_hw_spur_mitigate_freq(ah, chan); 1464 1465 if (edma && (band_switch || mode_diff)) { 1466 ah->ah_flags |= AH_FASTCC; 1467 if (band_switch || ini_reloaded) 1468 ah->eep_ops->set_board_values(ah, chan); 1469 1470 ath9k_hw_init_bb(ah, chan); 1471 1472 if (band_switch || ini_reloaded) 1473 ath9k_hw_init_cal(ah, chan); 1474 ah->ah_flags &= ~AH_FASTCC; 1475 } 1476 1477 return true; 1478 } 1479 1480 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1481 { 1482 u32 gpio_mask = ah->gpio_mask; 1483 int i; 1484 1485 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1486 if (!(gpio_mask & 1)) 1487 continue; 1488 1489 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1490 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1491 } 1492 } 1493 1494 bool ath9k_hw_check_alive(struct ath_hw *ah) 1495 { 1496 int count = 50; 1497 u32 reg; 1498 1499 if (AR_SREV_9285_12_OR_LATER(ah)) 1500 return true; 1501 1502 do { 1503 reg = REG_READ(ah, AR_OBS_BUS_1); 1504 1505 if ((reg & 0x7E7FFFEF) == 0x00702400) 1506 continue; 1507 1508 switch (reg & 0x7E000B00) { 1509 case 0x1E000000: 1510 case 0x52000B00: 1511 case 0x18000B00: 1512 continue; 1513 default: 1514 return true; 1515 } 1516 } while (count-- > 0); 1517 1518 return false; 1519 } 1520 EXPORT_SYMBOL(ath9k_hw_check_alive); 1521 1522 /* 1523 * Fast channel change: 1524 * (Change synthesizer based on channel freq without resetting chip) 1525 * 1526 * Don't do FCC when 1527 * - Flag is not set 1528 * - Chip is just coming out of full sleep 1529 * - Channel to be set is same as current channel 1530 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1531 */ 1532 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1533 { 1534 struct ath_common *common = ath9k_hw_common(ah); 1535 int ret; 1536 1537 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1538 goto fail; 1539 1540 if (ah->chip_fullsleep) 1541 goto fail; 1542 1543 if (!ah->curchan) 1544 goto fail; 1545 1546 if (chan->channel == ah->curchan->channel) 1547 goto fail; 1548 1549 if ((chan->channelFlags & CHANNEL_ALL) != 1550 (ah->curchan->channelFlags & CHANNEL_ALL)) 1551 goto fail; 1552 1553 if (!ath9k_hw_check_alive(ah)) 1554 goto fail; 1555 1556 /* 1557 * For AR9462, make sure that calibration data for 1558 * re-using are present. 1559 */ 1560 if (AR_SREV_9462(ah) && (!ah->caldata || 1561 !ah->caldata->done_txiqcal_once || 1562 !ah->caldata->done_txclcal_once || 1563 !ah->caldata->rtt_hist.num_readings)) 1564 goto fail; 1565 1566 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1567 ah->curchan->channel, chan->channel); 1568 1569 ret = ath9k_hw_channel_change(ah, chan); 1570 if (!ret) 1571 goto fail; 1572 1573 ath9k_hw_loadnf(ah, ah->curchan); 1574 ath9k_hw_start_nfcal(ah, true); 1575 1576 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah)) 1577 ar9003_mci_2g5g_switch(ah, true); 1578 1579 if (AR_SREV_9271(ah)) 1580 ar9002_hw_load_ani_reg(ah, chan); 1581 1582 return 0; 1583 fail: 1584 return -EINVAL; 1585 } 1586 1587 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1588 struct ath9k_hw_cal_data *caldata, bool fastcc) 1589 { 1590 struct ath_common *common = ath9k_hw_common(ah); 1591 u32 saveLedState; 1592 u32 saveDefAntenna; 1593 u32 macStaId1; 1594 u64 tsf = 0; 1595 int i, r; 1596 bool start_mci_reset = false; 1597 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1598 bool save_fullsleep = ah->chip_fullsleep; 1599 1600 if (mci) { 1601 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1602 if (start_mci_reset) 1603 return 0; 1604 } 1605 1606 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1607 return -EIO; 1608 1609 if (ah->curchan && !ah->chip_fullsleep) 1610 ath9k_hw_getnf(ah, ah->curchan); 1611 1612 ah->caldata = caldata; 1613 if (caldata && 1614 (chan->channel != caldata->channel || 1615 (chan->channelFlags & ~CHANNEL_CW_INT) != 1616 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1617 /* Operating channel changed, reset channel calibration data */ 1618 memset(caldata, 0, sizeof(*caldata)); 1619 ath9k_init_nfcal_hist_buffer(ah, chan); 1620 } 1621 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1622 1623 if (fastcc) { 1624 r = ath9k_hw_do_fastcc(ah, chan); 1625 if (!r) 1626 return r; 1627 } 1628 1629 if (mci) 1630 ar9003_mci_stop_bt(ah, save_fullsleep); 1631 1632 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1633 if (saveDefAntenna == 0) 1634 saveDefAntenna = 1; 1635 1636 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1637 1638 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1639 if (AR_SREV_9100(ah) || 1640 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1641 tsf = ath9k_hw_gettsf64(ah); 1642 1643 saveLedState = REG_READ(ah, AR_CFG_LED) & 1644 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1645 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1646 1647 ath9k_hw_mark_phy_inactive(ah); 1648 1649 ah->paprd_table_write_done = false; 1650 1651 /* Only required on the first reset */ 1652 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1653 REG_WRITE(ah, 1654 AR9271_RESET_POWER_DOWN_CONTROL, 1655 AR9271_RADIO_RF_RST); 1656 udelay(50); 1657 } 1658 1659 if (!ath9k_hw_chip_reset(ah, chan)) { 1660 ath_err(common, "Chip reset failed\n"); 1661 return -EINVAL; 1662 } 1663 1664 /* Only required on the first reset */ 1665 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1666 ah->htc_reset_init = false; 1667 REG_WRITE(ah, 1668 AR9271_RESET_POWER_DOWN_CONTROL, 1669 AR9271_GATE_MAC_CTL); 1670 udelay(50); 1671 } 1672 1673 /* Restore TSF */ 1674 if (tsf) 1675 ath9k_hw_settsf64(ah, tsf); 1676 1677 if (AR_SREV_9280_20_OR_LATER(ah)) 1678 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1679 1680 if (!AR_SREV_9300_20_OR_LATER(ah)) 1681 ar9002_hw_enable_async_fifo(ah); 1682 1683 r = ath9k_hw_process_ini(ah, chan); 1684 if (r) 1685 return r; 1686 1687 if (mci) 1688 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1689 1690 /* 1691 * Some AR91xx SoC devices frequently fail to accept TSF writes 1692 * right after the chip reset. When that happens, write a new 1693 * value after the initvals have been applied, with an offset 1694 * based on measured time difference 1695 */ 1696 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1697 tsf += 1500; 1698 ath9k_hw_settsf64(ah, tsf); 1699 } 1700 1701 /* Setup MFP options for CCMP */ 1702 if (AR_SREV_9280_20_OR_LATER(ah)) { 1703 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1704 * frames when constructing CCMP AAD. */ 1705 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1706 0xc7ff); 1707 ah->sw_mgmt_crypto = false; 1708 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1709 /* Disable hardware crypto for management frames */ 1710 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1711 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1712 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1713 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1714 ah->sw_mgmt_crypto = true; 1715 } else 1716 ah->sw_mgmt_crypto = true; 1717 1718 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1719 ath9k_hw_set_delta_slope(ah, chan); 1720 1721 ath9k_hw_spur_mitigate_freq(ah, chan); 1722 ah->eep_ops->set_board_values(ah, chan); 1723 1724 ENABLE_REGWRITE_BUFFER(ah); 1725 1726 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1727 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1728 | macStaId1 1729 | AR_STA_ID1_RTS_USE_DEF 1730 | (ah->config. 1731 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1732 | ah->sta_id1_defaults); 1733 ath_hw_setbssidmask(common); 1734 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1735 ath9k_hw_write_associd(ah); 1736 REG_WRITE(ah, AR_ISR, ~0); 1737 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1738 1739 REGWRITE_BUFFER_FLUSH(ah); 1740 1741 ath9k_hw_set_operating_mode(ah, ah->opmode); 1742 1743 r = ath9k_hw_rf_set_freq(ah, chan); 1744 if (r) 1745 return r; 1746 1747 ath9k_hw_set_clockrate(ah); 1748 1749 ENABLE_REGWRITE_BUFFER(ah); 1750 1751 for (i = 0; i < AR_NUM_DCU; i++) 1752 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1753 1754 REGWRITE_BUFFER_FLUSH(ah); 1755 1756 ah->intr_txqs = 0; 1757 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1758 ath9k_hw_resettxqueue(ah, i); 1759 1760 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1761 ath9k_hw_ani_cache_ini_regs(ah); 1762 ath9k_hw_init_qos(ah); 1763 1764 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1765 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1766 1767 ath9k_hw_init_global_settings(ah); 1768 1769 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1770 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1771 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1772 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1773 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1774 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1775 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1776 } 1777 1778 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1779 1780 ath9k_hw_set_dma(ah); 1781 1782 REG_WRITE(ah, AR_OBS, 8); 1783 1784 if (ah->config.rx_intr_mitigation) { 1785 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1786 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1787 } 1788 1789 if (ah->config.tx_intr_mitigation) { 1790 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1791 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1792 } 1793 1794 ath9k_hw_init_bb(ah, chan); 1795 1796 if (caldata) { 1797 caldata->done_txiqcal_once = false; 1798 caldata->done_txclcal_once = false; 1799 caldata->rtt_hist.num_readings = 0; 1800 } 1801 if (!ath9k_hw_init_cal(ah, chan)) 1802 return -EIO; 1803 1804 ath9k_hw_loadnf(ah, chan); 1805 ath9k_hw_start_nfcal(ah, true); 1806 1807 if (mci && ar9003_mci_end_reset(ah, chan, caldata)) 1808 return -EIO; 1809 1810 ENABLE_REGWRITE_BUFFER(ah); 1811 1812 ath9k_hw_restore_chainmask(ah); 1813 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1814 1815 REGWRITE_BUFFER_FLUSH(ah); 1816 1817 /* 1818 * For big endian systems turn on swapping for descriptors 1819 */ 1820 if (AR_SREV_9100(ah)) { 1821 u32 mask; 1822 mask = REG_READ(ah, AR_CFG); 1823 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1824 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1825 mask); 1826 } else { 1827 mask = 1828 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1829 REG_WRITE(ah, AR_CFG, mask); 1830 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1831 REG_READ(ah, AR_CFG)); 1832 } 1833 } else { 1834 if (common->bus_ops->ath_bus_type == ATH_USB) { 1835 /* Configure AR9271 target WLAN */ 1836 if (AR_SREV_9271(ah)) 1837 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1838 else 1839 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1840 } 1841 #ifdef __BIG_ENDIAN 1842 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1843 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1844 else 1845 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1846 #endif 1847 } 1848 1849 if (ath9k_hw_btcoex_is_enabled(ah)) 1850 ath9k_hw_btcoex_enable(ah); 1851 1852 if (mci) 1853 ar9003_mci_check_bt(ah); 1854 1855 if (AR_SREV_9300_20_OR_LATER(ah)) { 1856 ar9003_hw_bb_watchdog_config(ah); 1857 1858 ar9003_hw_disable_phy_restart(ah); 1859 } 1860 1861 ath9k_hw_apply_gpio_override(ah); 1862 1863 return 0; 1864 } 1865 EXPORT_SYMBOL(ath9k_hw_reset); 1866 1867 /******************************/ 1868 /* Power Management (Chipset) */ 1869 /******************************/ 1870 1871 /* 1872 * Notify Power Mgt is disabled in self-generated frames. 1873 * If requested, force chip to sleep. 1874 */ 1875 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1876 { 1877 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1878 if (setChip) { 1879 if (AR_SREV_9462(ah)) { 1880 REG_WRITE(ah, AR_TIMER_MODE, 1881 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1882 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1883 AR_NDP2_TIMER_MODE) & 0xFFFFFF00); 1884 REG_WRITE(ah, AR_SLP32_INC, 1885 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); 1886 /* xxx Required for WLAN only case ? */ 1887 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1888 udelay(100); 1889 } 1890 1891 /* 1892 * Clear the RTC force wake bit to allow the 1893 * mac to go to sleep. 1894 */ 1895 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1896 1897 if (AR_SREV_9462(ah)) 1898 udelay(100); 1899 1900 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1901 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1902 1903 /* Shutdown chip. Active low */ 1904 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 1905 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1906 udelay(2); 1907 } 1908 } 1909 1910 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1911 if (AR_SREV_9300_20_OR_LATER(ah)) 1912 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1913 } 1914 1915 /* 1916 * Notify Power Management is enabled in self-generating 1917 * frames. If request, set power mode of chip to 1918 * auto/normal. Duration in units of 128us (1/8 TU). 1919 */ 1920 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1921 { 1922 u32 val; 1923 1924 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1925 if (setChip) { 1926 struct ath9k_hw_capabilities *pCap = &ah->caps; 1927 1928 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1929 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1930 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1931 AR_RTC_FORCE_WAKE_ON_INT); 1932 } else { 1933 1934 /* When chip goes into network sleep, it could be waken 1935 * up by MCI_INT interrupt caused by BT's HW messages 1936 * (LNA_xxx, CONT_xxx) which chould be in a very fast 1937 * rate (~100us). This will cause chip to leave and 1938 * re-enter network sleep mode frequently, which in 1939 * consequence will have WLAN MCI HW to generate lots of 1940 * SYS_WAKING and SYS_SLEEPING messages which will make 1941 * BT CPU to busy to process. 1942 */ 1943 if (AR_SREV_9462(ah)) { 1944 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 1945 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 1946 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 1947 } 1948 /* 1949 * Clear the RTC force wake bit to allow the 1950 * mac to go to sleep. 1951 */ 1952 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1953 AR_RTC_FORCE_WAKE_EN); 1954 1955 if (AR_SREV_9462(ah)) 1956 udelay(30); 1957 } 1958 } 1959 1960 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1961 if (AR_SREV_9300_20_OR_LATER(ah)) 1962 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1963 } 1964 1965 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1966 { 1967 u32 val; 1968 int i; 1969 1970 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1971 if (AR_SREV_9300_20_OR_LATER(ah)) { 1972 REG_WRITE(ah, AR_WA, ah->WARegVal); 1973 udelay(10); 1974 } 1975 1976 if (setChip) { 1977 if ((REG_READ(ah, AR_RTC_STATUS) & 1978 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1979 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 1980 return false; 1981 } 1982 if (!AR_SREV_9300_20_OR_LATER(ah)) 1983 ath9k_hw_init_pll(ah, NULL); 1984 } 1985 if (AR_SREV_9100(ah)) 1986 REG_SET_BIT(ah, AR_RTC_RESET, 1987 AR_RTC_RESET_EN); 1988 1989 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1990 AR_RTC_FORCE_WAKE_EN); 1991 udelay(50); 1992 1993 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1994 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1995 if (val == AR_RTC_STATUS_ON) 1996 break; 1997 udelay(50); 1998 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1999 AR_RTC_FORCE_WAKE_EN); 2000 } 2001 if (i == 0) { 2002 ath_err(ath9k_hw_common(ah), 2003 "Failed to wakeup in %uus\n", 2004 POWER_UP_TIME / 20); 2005 return false; 2006 } 2007 } 2008 2009 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2010 2011 return true; 2012 } 2013 2014 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2015 { 2016 struct ath_common *common = ath9k_hw_common(ah); 2017 int status = true, setChip = true; 2018 static const char *modes[] = { 2019 "AWAKE", 2020 "FULL-SLEEP", 2021 "NETWORK SLEEP", 2022 "UNDEFINED" 2023 }; 2024 2025 if (ah->power_mode == mode) 2026 return status; 2027 2028 ath_dbg(common, RESET, "%s -> %s\n", 2029 modes[ah->power_mode], modes[mode]); 2030 2031 switch (mode) { 2032 case ATH9K_PM_AWAKE: 2033 status = ath9k_hw_set_power_awake(ah, setChip); 2034 2035 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2036 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2037 2038 break; 2039 case ATH9K_PM_FULL_SLEEP: 2040 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2041 ar9003_mci_set_full_sleep(ah); 2042 2043 ath9k_set_power_sleep(ah, setChip); 2044 ah->chip_fullsleep = true; 2045 break; 2046 case ATH9K_PM_NETWORK_SLEEP: 2047 2048 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2049 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2050 2051 ath9k_set_power_network_sleep(ah, setChip); 2052 break; 2053 default: 2054 ath_err(common, "Unknown power mode %u\n", mode); 2055 return false; 2056 } 2057 ah->power_mode = mode; 2058 2059 /* 2060 * XXX: If this warning never comes up after a while then 2061 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2062 * ath9k_hw_setpower() return type void. 2063 */ 2064 2065 if (!(ah->ah_flags & AH_UNPLUGGED)) 2066 ATH_DBG_WARN_ON_ONCE(!status); 2067 2068 return status; 2069 } 2070 EXPORT_SYMBOL(ath9k_hw_setpower); 2071 2072 /*******************/ 2073 /* Beacon Handling */ 2074 /*******************/ 2075 2076 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2077 { 2078 int flags = 0; 2079 2080 ENABLE_REGWRITE_BUFFER(ah); 2081 2082 switch (ah->opmode) { 2083 case NL80211_IFTYPE_ADHOC: 2084 case NL80211_IFTYPE_MESH_POINT: 2085 REG_SET_BIT(ah, AR_TXCFG, 2086 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2087 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2088 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2089 flags |= AR_NDP_TIMER_EN; 2090 case NL80211_IFTYPE_AP: 2091 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2092 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2093 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2094 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2095 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2096 flags |= 2097 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2098 break; 2099 default: 2100 ath_dbg(ath9k_hw_common(ah), BEACON, 2101 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2102 return; 2103 break; 2104 } 2105 2106 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2107 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2108 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2109 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2110 2111 REGWRITE_BUFFER_FLUSH(ah); 2112 2113 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2114 } 2115 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2116 2117 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2118 const struct ath9k_beacon_state *bs) 2119 { 2120 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2121 struct ath9k_hw_capabilities *pCap = &ah->caps; 2122 struct ath_common *common = ath9k_hw_common(ah); 2123 2124 ENABLE_REGWRITE_BUFFER(ah); 2125 2126 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2127 2128 REG_WRITE(ah, AR_BEACON_PERIOD, 2129 TU_TO_USEC(bs->bs_intval)); 2130 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2131 TU_TO_USEC(bs->bs_intval)); 2132 2133 REGWRITE_BUFFER_FLUSH(ah); 2134 2135 REG_RMW_FIELD(ah, AR_RSSI_THR, 2136 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2137 2138 beaconintval = bs->bs_intval; 2139 2140 if (bs->bs_sleepduration > beaconintval) 2141 beaconintval = bs->bs_sleepduration; 2142 2143 dtimperiod = bs->bs_dtimperiod; 2144 if (bs->bs_sleepduration > dtimperiod) 2145 dtimperiod = bs->bs_sleepduration; 2146 2147 if (beaconintval == dtimperiod) 2148 nextTbtt = bs->bs_nextdtim; 2149 else 2150 nextTbtt = bs->bs_nexttbtt; 2151 2152 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2153 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2154 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2155 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2156 2157 ENABLE_REGWRITE_BUFFER(ah); 2158 2159 REG_WRITE(ah, AR_NEXT_DTIM, 2160 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2161 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2162 2163 REG_WRITE(ah, AR_SLEEP1, 2164 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2165 | AR_SLEEP1_ASSUME_DTIM); 2166 2167 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2168 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2169 else 2170 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2171 2172 REG_WRITE(ah, AR_SLEEP2, 2173 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2174 2175 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2176 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2177 2178 REGWRITE_BUFFER_FLUSH(ah); 2179 2180 REG_SET_BIT(ah, AR_TIMER_MODE, 2181 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2182 AR_DTIM_TIMER_EN); 2183 2184 /* TSF Out of Range Threshold */ 2185 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2186 } 2187 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2188 2189 /*******************/ 2190 /* HW Capabilities */ 2191 /*******************/ 2192 2193 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2194 { 2195 eeprom_chainmask &= chip_chainmask; 2196 if (eeprom_chainmask) 2197 return eeprom_chainmask; 2198 else 2199 return chip_chainmask; 2200 } 2201 2202 /** 2203 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2204 * @ah: the atheros hardware data structure 2205 * 2206 * We enable DFS support upstream on chipsets which have passed a series 2207 * of tests. The testing requirements are going to be documented. Desired 2208 * test requirements are documented at: 2209 * 2210 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2211 * 2212 * Once a new chipset gets properly tested an individual commit can be used 2213 * to document the testing for DFS for that chipset. 2214 */ 2215 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2216 { 2217 2218 switch (ah->hw_version.macVersion) { 2219 /* AR9580 will likely be our first target to get testing on */ 2220 case AR_SREV_VERSION_9580: 2221 default: 2222 return false; 2223 } 2224 } 2225 2226 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2227 { 2228 struct ath9k_hw_capabilities *pCap = &ah->caps; 2229 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2230 struct ath_common *common = ath9k_hw_common(ah); 2231 unsigned int chip_chainmask; 2232 2233 u16 eeval; 2234 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2235 2236 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2237 regulatory->current_rd = eeval; 2238 2239 if (ah->opmode != NL80211_IFTYPE_AP && 2240 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2241 if (regulatory->current_rd == 0x64 || 2242 regulatory->current_rd == 0x65) 2243 regulatory->current_rd += 5; 2244 else if (regulatory->current_rd == 0x41) 2245 regulatory->current_rd = 0x43; 2246 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2247 regulatory->current_rd); 2248 } 2249 2250 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2251 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2252 ath_err(common, 2253 "no band has been marked as supported in EEPROM\n"); 2254 return -EINVAL; 2255 } 2256 2257 if (eeval & AR5416_OPFLAGS_11A) 2258 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2259 2260 if (eeval & AR5416_OPFLAGS_11G) 2261 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2262 2263 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2264 chip_chainmask = 1; 2265 else if (AR_SREV_9462(ah)) 2266 chip_chainmask = 3; 2267 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2268 chip_chainmask = 7; 2269 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2270 chip_chainmask = 3; 2271 else 2272 chip_chainmask = 7; 2273 2274 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2275 /* 2276 * For AR9271 we will temporarilly uses the rx chainmax as read from 2277 * the EEPROM. 2278 */ 2279 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2280 !(eeval & AR5416_OPFLAGS_11A) && 2281 !(AR_SREV_9271(ah))) 2282 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2283 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2284 else if (AR_SREV_9100(ah)) 2285 pCap->rx_chainmask = 0x7; 2286 else 2287 /* Use rx_chainmask from EEPROM. */ 2288 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2289 2290 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2291 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2292 ah->txchainmask = pCap->tx_chainmask; 2293 ah->rxchainmask = pCap->rx_chainmask; 2294 2295 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2296 2297 /* enable key search for every frame in an aggregate */ 2298 if (AR_SREV_9300_20_OR_LATER(ah)) 2299 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2300 2301 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2302 2303 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2304 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2305 else 2306 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2307 2308 if (AR_SREV_9271(ah)) 2309 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2310 else if (AR_DEVID_7010(ah)) 2311 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2312 else if (AR_SREV_9300_20_OR_LATER(ah)) 2313 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2314 else if (AR_SREV_9287_11_OR_LATER(ah)) 2315 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2316 else if (AR_SREV_9285_12_OR_LATER(ah)) 2317 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2318 else if (AR_SREV_9280_20_OR_LATER(ah)) 2319 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2320 else 2321 pCap->num_gpio_pins = AR_NUM_GPIO; 2322 2323 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2324 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2325 else 2326 pCap->rts_aggr_limit = (8 * 1024); 2327 2328 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2329 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2330 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2331 ah->rfkill_gpio = 2332 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2333 ah->rfkill_polarity = 2334 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2335 2336 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2337 } 2338 #endif 2339 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2340 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2341 else 2342 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2343 2344 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2345 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2346 else 2347 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2348 2349 if (AR_SREV_9300_20_OR_LATER(ah)) { 2350 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2351 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2352 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2353 2354 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2355 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2356 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2357 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2358 pCap->txs_len = sizeof(struct ar9003_txs); 2359 if (!ah->config.paprd_disable && 2360 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2361 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2362 } else { 2363 pCap->tx_desc_len = sizeof(struct ath_desc); 2364 if (AR_SREV_9280_20(ah)) 2365 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2366 } 2367 2368 if (AR_SREV_9300_20_OR_LATER(ah)) 2369 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2370 2371 if (AR_SREV_9300_20_OR_LATER(ah)) 2372 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2373 2374 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2375 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2376 2377 if (AR_SREV_9285(ah)) 2378 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2379 ant_div_ctl1 = 2380 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2381 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2382 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2383 } 2384 if (AR_SREV_9300_20_OR_LATER(ah)) { 2385 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2386 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2387 } 2388 2389 2390 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2391 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2392 /* 2393 * enable the diversity-combining algorithm only when 2394 * both enable_lna_div and enable_fast_div are set 2395 * Table for Diversity 2396 * ant_div_alt_lnaconf bit 0-1 2397 * ant_div_main_lnaconf bit 2-3 2398 * ant_div_alt_gaintb bit 4 2399 * ant_div_main_gaintb bit 5 2400 * enable_ant_div_lnadiv bit 6 2401 * enable_ant_fast_div bit 7 2402 */ 2403 if ((ant_div_ctl1 >> 0x6) == 0x3) 2404 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2405 } 2406 2407 if (AR_SREV_9485_10(ah)) { 2408 pCap->pcie_lcr_extsync_en = true; 2409 pCap->pcie_lcr_offset = 0x80; 2410 } 2411 2412 if (ath9k_hw_dfs_tested(ah)) 2413 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2414 2415 tx_chainmask = pCap->tx_chainmask; 2416 rx_chainmask = pCap->rx_chainmask; 2417 while (tx_chainmask || rx_chainmask) { 2418 if (tx_chainmask & BIT(0)) 2419 pCap->max_txchains++; 2420 if (rx_chainmask & BIT(0)) 2421 pCap->max_rxchains++; 2422 2423 tx_chainmask >>= 1; 2424 rx_chainmask >>= 1; 2425 } 2426 2427 if (AR_SREV_9300_20_OR_LATER(ah)) { 2428 ah->enabled_cals |= TX_IQ_CAL; 2429 if (AR_SREV_9485_OR_LATER(ah)) 2430 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2431 } 2432 2433 if (AR_SREV_9462(ah)) { 2434 2435 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2436 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2437 2438 if (AR_SREV_9462_20(ah)) 2439 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2440 2441 } 2442 2443 2444 return 0; 2445 } 2446 2447 /****************************/ 2448 /* GPIO / RFKILL / Antennae */ 2449 /****************************/ 2450 2451 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2452 u32 gpio, u32 type) 2453 { 2454 int addr; 2455 u32 gpio_shift, tmp; 2456 2457 if (gpio > 11) 2458 addr = AR_GPIO_OUTPUT_MUX3; 2459 else if (gpio > 5) 2460 addr = AR_GPIO_OUTPUT_MUX2; 2461 else 2462 addr = AR_GPIO_OUTPUT_MUX1; 2463 2464 gpio_shift = (gpio % 6) * 5; 2465 2466 if (AR_SREV_9280_20_OR_LATER(ah) 2467 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2468 REG_RMW(ah, addr, (type << gpio_shift), 2469 (0x1f << gpio_shift)); 2470 } else { 2471 tmp = REG_READ(ah, addr); 2472 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2473 tmp &= ~(0x1f << gpio_shift); 2474 tmp |= (type << gpio_shift); 2475 REG_WRITE(ah, addr, tmp); 2476 } 2477 } 2478 2479 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2480 { 2481 u32 gpio_shift; 2482 2483 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2484 2485 if (AR_DEVID_7010(ah)) { 2486 gpio_shift = gpio; 2487 REG_RMW(ah, AR7010_GPIO_OE, 2488 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2489 (AR7010_GPIO_OE_MASK << gpio_shift)); 2490 return; 2491 } 2492 2493 gpio_shift = gpio << 1; 2494 REG_RMW(ah, 2495 AR_GPIO_OE_OUT, 2496 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2497 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2498 } 2499 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2500 2501 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2502 { 2503 #define MS_REG_READ(x, y) \ 2504 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2505 2506 if (gpio >= ah->caps.num_gpio_pins) 2507 return 0xffffffff; 2508 2509 if (AR_DEVID_7010(ah)) { 2510 u32 val; 2511 val = REG_READ(ah, AR7010_GPIO_IN); 2512 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2513 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2514 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2515 AR_GPIO_BIT(gpio)) != 0; 2516 else if (AR_SREV_9271(ah)) 2517 return MS_REG_READ(AR9271, gpio) != 0; 2518 else if (AR_SREV_9287_11_OR_LATER(ah)) 2519 return MS_REG_READ(AR9287, gpio) != 0; 2520 else if (AR_SREV_9285_12_OR_LATER(ah)) 2521 return MS_REG_READ(AR9285, gpio) != 0; 2522 else if (AR_SREV_9280_20_OR_LATER(ah)) 2523 return MS_REG_READ(AR928X, gpio) != 0; 2524 else 2525 return MS_REG_READ(AR, gpio) != 0; 2526 } 2527 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2528 2529 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2530 u32 ah_signal_type) 2531 { 2532 u32 gpio_shift; 2533 2534 if (AR_DEVID_7010(ah)) { 2535 gpio_shift = gpio; 2536 REG_RMW(ah, AR7010_GPIO_OE, 2537 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2538 (AR7010_GPIO_OE_MASK << gpio_shift)); 2539 return; 2540 } 2541 2542 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2543 gpio_shift = 2 * gpio; 2544 REG_RMW(ah, 2545 AR_GPIO_OE_OUT, 2546 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2547 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2548 } 2549 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2550 2551 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2552 { 2553 if (AR_DEVID_7010(ah)) { 2554 val = val ? 0 : 1; 2555 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2556 AR_GPIO_BIT(gpio)); 2557 return; 2558 } 2559 2560 if (AR_SREV_9271(ah)) 2561 val = ~val; 2562 2563 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2564 AR_GPIO_BIT(gpio)); 2565 } 2566 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2567 2568 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2569 { 2570 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2571 } 2572 EXPORT_SYMBOL(ath9k_hw_setantenna); 2573 2574 /*********************/ 2575 /* General Operation */ 2576 /*********************/ 2577 2578 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2579 { 2580 u32 bits = REG_READ(ah, AR_RX_FILTER); 2581 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2582 2583 if (phybits & AR_PHY_ERR_RADAR) 2584 bits |= ATH9K_RX_FILTER_PHYRADAR; 2585 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2586 bits |= ATH9K_RX_FILTER_PHYERR; 2587 2588 return bits; 2589 } 2590 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2591 2592 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2593 { 2594 u32 phybits; 2595 2596 ENABLE_REGWRITE_BUFFER(ah); 2597 2598 if (AR_SREV_9462(ah)) 2599 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2600 2601 REG_WRITE(ah, AR_RX_FILTER, bits); 2602 2603 phybits = 0; 2604 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2605 phybits |= AR_PHY_ERR_RADAR; 2606 if (bits & ATH9K_RX_FILTER_PHYERR) 2607 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2608 REG_WRITE(ah, AR_PHY_ERR, phybits); 2609 2610 if (phybits) 2611 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2612 else 2613 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2614 2615 REGWRITE_BUFFER_FLUSH(ah); 2616 } 2617 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2618 2619 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2620 { 2621 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2622 return false; 2623 2624 ath9k_hw_init_pll(ah, NULL); 2625 ah->htc_reset_init = true; 2626 return true; 2627 } 2628 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2629 2630 bool ath9k_hw_disable(struct ath_hw *ah) 2631 { 2632 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2633 return false; 2634 2635 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2636 return false; 2637 2638 ath9k_hw_init_pll(ah, NULL); 2639 return true; 2640 } 2641 EXPORT_SYMBOL(ath9k_hw_disable); 2642 2643 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2644 { 2645 enum eeprom_param gain_param; 2646 2647 if (IS_CHAN_2GHZ(chan)) 2648 gain_param = EEP_ANTENNA_GAIN_2G; 2649 else 2650 gain_param = EEP_ANTENNA_GAIN_5G; 2651 2652 return ah->eep_ops->get_eeprom(ah, gain_param); 2653 } 2654 2655 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2656 bool test) 2657 { 2658 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2659 struct ieee80211_channel *channel; 2660 int chan_pwr, new_pwr, max_gain; 2661 int ant_gain, ant_reduction = 0; 2662 2663 if (!chan) 2664 return; 2665 2666 channel = chan->chan; 2667 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2668 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2669 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2670 2671 ant_gain = get_antenna_gain(ah, chan); 2672 if (ant_gain > max_gain) 2673 ant_reduction = ant_gain - max_gain; 2674 2675 ah->eep_ops->set_txpower(ah, chan, 2676 ath9k_regd_get_ctl(reg, chan), 2677 ant_reduction, new_pwr, test); 2678 } 2679 2680 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2681 { 2682 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2683 struct ath9k_channel *chan = ah->curchan; 2684 struct ieee80211_channel *channel = chan->chan; 2685 2686 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2687 if (test) 2688 channel->max_power = MAX_RATE_POWER / 2; 2689 2690 ath9k_hw_apply_txpower(ah, chan, test); 2691 2692 if (test) 2693 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2694 } 2695 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2696 2697 void ath9k_hw_setopmode(struct ath_hw *ah) 2698 { 2699 ath9k_hw_set_operating_mode(ah, ah->opmode); 2700 } 2701 EXPORT_SYMBOL(ath9k_hw_setopmode); 2702 2703 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2704 { 2705 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2706 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2707 } 2708 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2709 2710 void ath9k_hw_write_associd(struct ath_hw *ah) 2711 { 2712 struct ath_common *common = ath9k_hw_common(ah); 2713 2714 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2715 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2716 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2717 } 2718 EXPORT_SYMBOL(ath9k_hw_write_associd); 2719 2720 #define ATH9K_MAX_TSF_READ 10 2721 2722 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2723 { 2724 u32 tsf_lower, tsf_upper1, tsf_upper2; 2725 int i; 2726 2727 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2728 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2729 tsf_lower = REG_READ(ah, AR_TSF_L32); 2730 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2731 if (tsf_upper2 == tsf_upper1) 2732 break; 2733 tsf_upper1 = tsf_upper2; 2734 } 2735 2736 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2737 2738 return (((u64)tsf_upper1 << 32) | tsf_lower); 2739 } 2740 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2741 2742 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2743 { 2744 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2745 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2746 } 2747 EXPORT_SYMBOL(ath9k_hw_settsf64); 2748 2749 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2750 { 2751 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2752 AH_TSF_WRITE_TIMEOUT)) 2753 ath_dbg(ath9k_hw_common(ah), RESET, 2754 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2755 2756 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2757 } 2758 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2759 2760 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2761 { 2762 if (setting) 2763 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2764 else 2765 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2766 } 2767 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2768 2769 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2770 { 2771 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2772 u32 macmode; 2773 2774 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2775 macmode = AR_2040_JOINED_RX_CLEAR; 2776 else 2777 macmode = 0; 2778 2779 REG_WRITE(ah, AR_2040_MODE, macmode); 2780 } 2781 2782 /* HW Generic timers configuration */ 2783 2784 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2785 { 2786 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2787 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2788 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2789 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2790 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2791 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2792 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2793 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2794 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2795 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2796 AR_NDP2_TIMER_MODE, 0x0002}, 2797 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2798 AR_NDP2_TIMER_MODE, 0x0004}, 2799 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2800 AR_NDP2_TIMER_MODE, 0x0008}, 2801 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2802 AR_NDP2_TIMER_MODE, 0x0010}, 2803 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2804 AR_NDP2_TIMER_MODE, 0x0020}, 2805 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2806 AR_NDP2_TIMER_MODE, 0x0040}, 2807 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2808 AR_NDP2_TIMER_MODE, 0x0080} 2809 }; 2810 2811 /* HW generic timer primitives */ 2812 2813 /* compute and clear index of rightmost 1 */ 2814 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2815 { 2816 u32 b; 2817 2818 b = *mask; 2819 b &= (0-b); 2820 *mask &= ~b; 2821 b *= debruijn32; 2822 b >>= 27; 2823 2824 return timer_table->gen_timer_index[b]; 2825 } 2826 2827 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2828 { 2829 return REG_READ(ah, AR_TSF_L32); 2830 } 2831 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2832 2833 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2834 void (*trigger)(void *), 2835 void (*overflow)(void *), 2836 void *arg, 2837 u8 timer_index) 2838 { 2839 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2840 struct ath_gen_timer *timer; 2841 2842 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2843 2844 if (timer == NULL) { 2845 ath_err(ath9k_hw_common(ah), 2846 "Failed to allocate memory for hw timer[%d]\n", 2847 timer_index); 2848 return NULL; 2849 } 2850 2851 /* allocate a hardware generic timer slot */ 2852 timer_table->timers[timer_index] = timer; 2853 timer->index = timer_index; 2854 timer->trigger = trigger; 2855 timer->overflow = overflow; 2856 timer->arg = arg; 2857 2858 return timer; 2859 } 2860 EXPORT_SYMBOL(ath_gen_timer_alloc); 2861 2862 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2863 struct ath_gen_timer *timer, 2864 u32 trig_timeout, 2865 u32 timer_period) 2866 { 2867 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2868 u32 tsf, timer_next; 2869 2870 BUG_ON(!timer_period); 2871 2872 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2873 2874 tsf = ath9k_hw_gettsf32(ah); 2875 2876 timer_next = tsf + trig_timeout; 2877 2878 ath_dbg(ath9k_hw_common(ah), HWTIMER, 2879 "current tsf %x period %x timer_next %x\n", 2880 tsf, timer_period, timer_next); 2881 2882 /* 2883 * Program generic timer registers 2884 */ 2885 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2886 timer_next); 2887 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2888 timer_period); 2889 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2890 gen_tmr_configuration[timer->index].mode_mask); 2891 2892 if (AR_SREV_9462(ah)) { 2893 /* 2894 * Starting from AR9462, each generic timer can select which tsf 2895 * to use. But we still follow the old rule, 0 - 7 use tsf and 2896 * 8 - 15 use tsf2. 2897 */ 2898 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2899 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2900 (1 << timer->index)); 2901 else 2902 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2903 (1 << timer->index)); 2904 } 2905 2906 /* Enable both trigger and thresh interrupt masks */ 2907 REG_SET_BIT(ah, AR_IMR_S5, 2908 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2909 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2910 } 2911 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2912 2913 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2914 { 2915 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2916 2917 if ((timer->index < AR_FIRST_NDP_TIMER) || 2918 (timer->index >= ATH_MAX_GEN_TIMER)) { 2919 return; 2920 } 2921 2922 /* Clear generic timer enable bits. */ 2923 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2924 gen_tmr_configuration[timer->index].mode_mask); 2925 2926 /* Disable both trigger and thresh interrupt masks */ 2927 REG_CLR_BIT(ah, AR_IMR_S5, 2928 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2929 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2930 2931 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2932 } 2933 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2934 2935 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2936 { 2937 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2938 2939 /* free the hardware generic timer slot */ 2940 timer_table->timers[timer->index] = NULL; 2941 kfree(timer); 2942 } 2943 EXPORT_SYMBOL(ath_gen_timer_free); 2944 2945 /* 2946 * Generic Timer Interrupts handling 2947 */ 2948 void ath_gen_timer_isr(struct ath_hw *ah) 2949 { 2950 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2951 struct ath_gen_timer *timer; 2952 struct ath_common *common = ath9k_hw_common(ah); 2953 u32 trigger_mask, thresh_mask, index; 2954 2955 /* get hardware generic timer interrupt status */ 2956 trigger_mask = ah->intr_gen_timer_trigger; 2957 thresh_mask = ah->intr_gen_timer_thresh; 2958 trigger_mask &= timer_table->timer_mask.val; 2959 thresh_mask &= timer_table->timer_mask.val; 2960 2961 trigger_mask &= ~thresh_mask; 2962 2963 while (thresh_mask) { 2964 index = rightmost_index(timer_table, &thresh_mask); 2965 timer = timer_table->timers[index]; 2966 BUG_ON(!timer); 2967 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 2968 index); 2969 timer->overflow(timer->arg); 2970 } 2971 2972 while (trigger_mask) { 2973 index = rightmost_index(timer_table, &trigger_mask); 2974 timer = timer_table->timers[index]; 2975 BUG_ON(!timer); 2976 ath_dbg(common, HWTIMER, 2977 "Gen timer[%d] trigger\n", index); 2978 timer->trigger(timer->arg); 2979 } 2980 } 2981 EXPORT_SYMBOL(ath_gen_timer_isr); 2982 2983 /********/ 2984 /* HTC */ 2985 /********/ 2986 2987 static struct { 2988 u32 version; 2989 const char * name; 2990 } ath_mac_bb_names[] = { 2991 /* Devices with external radios */ 2992 { AR_SREV_VERSION_5416_PCI, "5416" }, 2993 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2994 { AR_SREV_VERSION_9100, "9100" }, 2995 { AR_SREV_VERSION_9160, "9160" }, 2996 /* Single-chip solutions */ 2997 { AR_SREV_VERSION_9280, "9280" }, 2998 { AR_SREV_VERSION_9285, "9285" }, 2999 { AR_SREV_VERSION_9287, "9287" }, 3000 { AR_SREV_VERSION_9271, "9271" }, 3001 { AR_SREV_VERSION_9300, "9300" }, 3002 { AR_SREV_VERSION_9330, "9330" }, 3003 { AR_SREV_VERSION_9340, "9340" }, 3004 { AR_SREV_VERSION_9485, "9485" }, 3005 { AR_SREV_VERSION_9462, "9462" }, 3006 }; 3007 3008 /* For devices with external radios */ 3009 static struct { 3010 u16 version; 3011 const char * name; 3012 } ath_rf_names[] = { 3013 { 0, "5133" }, 3014 { AR_RAD5133_SREV_MAJOR, "5133" }, 3015 { AR_RAD5122_SREV_MAJOR, "5122" }, 3016 { AR_RAD2133_SREV_MAJOR, "2133" }, 3017 { AR_RAD2122_SREV_MAJOR, "2122" } 3018 }; 3019 3020 /* 3021 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3022 */ 3023 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3024 { 3025 int i; 3026 3027 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3028 if (ath_mac_bb_names[i].version == mac_bb_version) { 3029 return ath_mac_bb_names[i].name; 3030 } 3031 } 3032 3033 return "????"; 3034 } 3035 3036 /* 3037 * Return the RF name. "????" is returned if the RF is unknown. 3038 * Used for devices with external radios. 3039 */ 3040 static const char *ath9k_hw_rf_name(u16 rf_version) 3041 { 3042 int i; 3043 3044 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3045 if (ath_rf_names[i].version == rf_version) { 3046 return ath_rf_names[i].name; 3047 } 3048 } 3049 3050 return "????"; 3051 } 3052 3053 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3054 { 3055 int used; 3056 3057 /* chipsets >= AR9280 are single-chip */ 3058 if (AR_SREV_9280_20_OR_LATER(ah)) { 3059 used = snprintf(hw_name, len, 3060 "Atheros AR%s Rev:%x", 3061 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3062 ah->hw_version.macRev); 3063 } 3064 else { 3065 used = snprintf(hw_name, len, 3066 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3067 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3068 ah->hw_version.macRev, 3069 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3070 AR_RADIO_SREV_MAJOR)), 3071 ah->hw_version.phyRev); 3072 } 3073 3074 hw_name[used] = '\0'; 3075 } 3076 EXPORT_SYMBOL(ath9k_hw_name); 3077