1 /* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <asm/unaligned.h> 20 21 #include "hw.h" 22 #include "hw-ops.h" 23 #include "rc.h" 24 #include "ar9003_mac.h" 25 26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28 MODULE_AUTHOR("Atheros Communications"); 29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31 MODULE_LICENSE("Dual BSD/GPL"); 32 33 static int __init ath9k_init(void) 34 { 35 return 0; 36 } 37 module_init(ath9k_init); 38 39 static void __exit ath9k_exit(void) 40 { 41 return; 42 } 43 module_exit(ath9k_exit); 44 45 /* Private hardware callbacks */ 46 47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48 { 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50 } 51 52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55 } 56 57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59 { 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61 } 62 63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64 { 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69 } 70 71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72 { 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78 } 79 80 /********************/ 81 /* Helper Functions */ 82 /********************/ 83 84 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 85 { 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 87 struct ath_common *common = ath9k_hw_common(ah); 88 unsigned int clockrate; 89 90 if (!ah->curchan) /* should really check for CCK instead */ 91 clockrate = ATH9K_CLOCK_RATE_CCK; 92 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 96 else 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 98 99 if (conf_is_ht40(conf)) 100 clockrate *= 2; 101 102 common->clockrate = clockrate; 103 } 104 105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 106 { 107 struct ath_common *common = ath9k_hw_common(ah); 108 109 return usecs * common->clockrate; 110 } 111 112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 113 { 114 int i; 115 116 BUG_ON(timeout < AH_TIME_QUANTUM); 117 118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 119 if ((REG_READ(ah, reg) & mask) == val) 120 return true; 121 122 udelay(AH_TIME_QUANTUM); 123 } 124 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 127 timeout, reg, REG_READ(ah, reg), mask, val); 128 129 return false; 130 } 131 EXPORT_SYMBOL(ath9k_hw_wait); 132 133 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 134 { 135 u32 retval; 136 int i; 137 138 for (i = 0, retval = 0; i < n; i++) { 139 retval = (retval << 1) | (val & 1); 140 val >>= 1; 141 } 142 return retval; 143 } 144 145 bool ath9k_get_channel_edges(struct ath_hw *ah, 146 u16 flags, u16 *low, 147 u16 *high) 148 { 149 struct ath9k_hw_capabilities *pCap = &ah->caps; 150 151 if (flags & CHANNEL_5GHZ) { 152 *low = pCap->low_5ghz_chan; 153 *high = pCap->high_5ghz_chan; 154 return true; 155 } 156 if ((flags & CHANNEL_2GHZ)) { 157 *low = pCap->low_2ghz_chan; 158 *high = pCap->high_2ghz_chan; 159 return true; 160 } 161 return false; 162 } 163 164 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 165 u8 phy, int kbps, 166 u32 frameLen, u16 rateix, 167 bool shortPreamble) 168 { 169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 170 171 if (kbps == 0) 172 return 0; 173 174 switch (phy) { 175 case WLAN_RC_PHY_CCK: 176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 177 if (shortPreamble) 178 phyTime >>= 1; 179 numBits = frameLen << 3; 180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 181 break; 182 case WLAN_RC_PHY_OFDM: 183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 185 numBits = OFDM_PLCP_BITS + (frameLen << 3); 186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 187 txTime = OFDM_SIFS_TIME_QUARTER 188 + OFDM_PREAMBLE_TIME_QUARTER 189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 190 } else if (ah->curchan && 191 IS_CHAN_HALF_RATE(ah->curchan)) { 192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 193 numBits = OFDM_PLCP_BITS + (frameLen << 3); 194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 195 txTime = OFDM_SIFS_TIME_HALF + 196 OFDM_PREAMBLE_TIME_HALF 197 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 198 } else { 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 200 numBits = OFDM_PLCP_BITS + (frameLen << 3); 201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 203 + (numSymbols * OFDM_SYMBOL_TIME); 204 } 205 break; 206 default: 207 ath_err(ath9k_hw_common(ah), 208 "Unknown phy %u (rate ix %u)\n", phy, rateix); 209 txTime = 0; 210 break; 211 } 212 213 return txTime; 214 } 215 EXPORT_SYMBOL(ath9k_hw_computetxtime); 216 217 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 218 struct ath9k_channel *chan, 219 struct chan_centers *centers) 220 { 221 int8_t extoff; 222 223 if (!IS_CHAN_HT40(chan)) { 224 centers->ctl_center = centers->ext_center = 225 centers->synth_center = chan->channel; 226 return; 227 } 228 229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 230 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 231 centers->synth_center = 232 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 233 extoff = 1; 234 } else { 235 centers->synth_center = 236 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 237 extoff = -1; 238 } 239 240 centers->ctl_center = 241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 242 /* 25 MHz spacing is supported by hw but not on upper layers */ 243 centers->ext_center = 244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 245 } 246 247 /******************/ 248 /* Chip Revisions */ 249 /******************/ 250 251 static void ath9k_hw_read_revisions(struct ath_hw *ah) 252 { 253 u32 val; 254 255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 256 257 if (val == 0xFF) { 258 val = REG_READ(ah, AR_SREV); 259 ah->hw_version.macVersion = 260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 263 } else { 264 if (!AR_SREV_9100(ah)) 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 266 267 ah->hw_version.macRev = val & AR_SREV_REVISION; 268 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 270 ah->is_pciexpress = true; 271 } 272 } 273 274 /************************************/ 275 /* HW Attach, Detach, Init Routines */ 276 /************************************/ 277 278 static void ath9k_hw_disablepcie(struct ath_hw *ah) 279 { 280 if (!AR_SREV_5416(ah)) 281 return; 282 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 292 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 294 } 295 296 /* This should work for all families including legacy */ 297 static bool ath9k_hw_chip_test(struct ath_hw *ah) 298 { 299 struct ath_common *common = ath9k_hw_common(ah); 300 u32 regAddr[2] = { AR_STA_ID0 }; 301 u32 regHold[2]; 302 static const u32 patternData[4] = { 303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 304 }; 305 int i, j, loop_max; 306 307 if (!AR_SREV_9300_20_OR_LATER(ah)) { 308 loop_max = 2; 309 regAddr[1] = AR_PHY_BASE + (8 << 2); 310 } else 311 loop_max = 1; 312 313 for (i = 0; i < loop_max; i++) { 314 u32 addr = regAddr[i]; 315 u32 wrData, rdData; 316 317 regHold[i] = REG_READ(ah, addr); 318 for (j = 0; j < 0x100; j++) { 319 wrData = (j << 16) | j; 320 REG_WRITE(ah, addr, wrData); 321 rdData = REG_READ(ah, addr); 322 if (rdData != wrData) { 323 ath_err(common, 324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 325 addr, wrData, rdData); 326 return false; 327 } 328 } 329 for (j = 0; j < 4; j++) { 330 wrData = patternData[j]; 331 REG_WRITE(ah, addr, wrData); 332 rdData = REG_READ(ah, addr); 333 if (wrData != rdData) { 334 ath_err(common, 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 336 addr, wrData, rdData); 337 return false; 338 } 339 } 340 REG_WRITE(ah, regAddr[i], regHold[i]); 341 } 342 udelay(100); 343 344 return true; 345 } 346 347 static void ath9k_hw_init_config(struct ath_hw *ah) 348 { 349 int i; 350 351 ah->config.dma_beacon_response_time = 2; 352 ah->config.sw_beacon_response_time = 10; 353 ah->config.additional_swba_backoff = 0; 354 ah->config.ack_6mb = 0x0; 355 ah->config.cwm_ignore_extcca = 0; 356 ah->config.pcie_powersave_enable = 0; 357 ah->config.pcie_clock_req = 0; 358 ah->config.pcie_waen = 0; 359 ah->config.analog_shiftreg = 1; 360 ah->config.enable_ani = true; 361 362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 363 ah->config.spurchans[i][0] = AR_NO_SPUR; 364 ah->config.spurchans[i][1] = AR_NO_SPUR; 365 } 366 367 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 368 ah->config.ht_enable = 1; 369 else 370 ah->config.ht_enable = 0; 371 372 /* PAPRD needs some more work to be enabled */ 373 ah->config.paprd_disable = 1; 374 375 ah->config.rx_intr_mitigation = true; 376 ah->config.pcieSerDesWrite = true; 377 378 /* 379 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 380 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 381 * This means we use it for all AR5416 devices, and the few 382 * minor PCI AR9280 devices out there. 383 * 384 * Serialization is required because these devices do not handle 385 * well the case of two concurrent reads/writes due to the latency 386 * involved. During one read/write another read/write can be issued 387 * on another CPU while the previous read/write may still be working 388 * on our hardware, if we hit this case the hardware poops in a loop. 389 * We prevent this by serializing reads and writes. 390 * 391 * This issue is not present on PCI-Express devices or pre-AR5416 392 * devices (legacy, 802.11abg). 393 */ 394 if (num_possible_cpus() > 1) 395 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 396 } 397 398 static void ath9k_hw_init_defaults(struct ath_hw *ah) 399 { 400 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 401 402 regulatory->country_code = CTRY_DEFAULT; 403 regulatory->power_limit = MAX_RATE_POWER; 404 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 405 406 ah->hw_version.magic = AR5416_MAGIC; 407 ah->hw_version.subvendorid = 0; 408 409 ah->atim_window = 0; 410 ah->sta_id1_defaults = 411 AR_STA_ID1_CRPT_MIC_ENABLE | 412 AR_STA_ID1_MCAST_KSRCH; 413 ah->enable_32kHz_clock = DONT_USE_32KHZ; 414 ah->slottime = 20; 415 ah->globaltxtimeout = (u32) -1; 416 ah->power_mode = ATH9K_PM_UNDEFINED; 417 } 418 419 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 420 { 421 struct ath_common *common = ath9k_hw_common(ah); 422 u32 sum; 423 int i; 424 u16 eeval; 425 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 426 427 sum = 0; 428 for (i = 0; i < 3; i++) { 429 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 430 sum += eeval; 431 common->macaddr[2 * i] = eeval >> 8; 432 common->macaddr[2 * i + 1] = eeval & 0xff; 433 } 434 if (sum == 0 || sum == 0xffff * 3) 435 return -EADDRNOTAVAIL; 436 437 return 0; 438 } 439 440 static int ath9k_hw_post_init(struct ath_hw *ah) 441 { 442 struct ath_common *common = ath9k_hw_common(ah); 443 int ecode; 444 445 if (common->bus_ops->ath_bus_type != ATH_USB) { 446 if (!ath9k_hw_chip_test(ah)) 447 return -ENODEV; 448 } 449 450 if (!AR_SREV_9300_20_OR_LATER(ah)) { 451 ecode = ar9002_hw_rf_claim(ah); 452 if (ecode != 0) 453 return ecode; 454 } 455 456 ecode = ath9k_hw_eeprom_init(ah); 457 if (ecode != 0) 458 return ecode; 459 460 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 461 "Eeprom VER: %d, REV: %d\n", 462 ah->eep_ops->get_eeprom_ver(ah), 463 ah->eep_ops->get_eeprom_rev(ah)); 464 465 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 466 if (ecode) { 467 ath_err(ath9k_hw_common(ah), 468 "Failed allocating banks for external radio\n"); 469 ath9k_hw_rf_free_ext_banks(ah); 470 return ecode; 471 } 472 473 if (!AR_SREV_9100(ah)) { 474 ath9k_hw_ani_setup(ah); 475 ath9k_hw_ani_init(ah); 476 } 477 478 return 0; 479 } 480 481 static void ath9k_hw_attach_ops(struct ath_hw *ah) 482 { 483 if (AR_SREV_9300_20_OR_LATER(ah)) 484 ar9003_hw_attach_ops(ah); 485 else 486 ar9002_hw_attach_ops(ah); 487 } 488 489 /* Called for all hardware families */ 490 static int __ath9k_hw_init(struct ath_hw *ah) 491 { 492 struct ath_common *common = ath9k_hw_common(ah); 493 int r = 0; 494 495 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 496 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 497 498 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 499 ath_err(common, "Couldn't reset chip\n"); 500 return -EIO; 501 } 502 503 ath9k_hw_init_defaults(ah); 504 ath9k_hw_init_config(ah); 505 506 ath9k_hw_attach_ops(ah); 507 508 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 509 ath_err(common, "Couldn't wakeup chip\n"); 510 return -EIO; 511 } 512 513 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 514 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 515 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 516 !ah->is_pciexpress)) { 517 ah->config.serialize_regmode = 518 SER_REG_MODE_ON; 519 } else { 520 ah->config.serialize_regmode = 521 SER_REG_MODE_OFF; 522 } 523 } 524 525 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 526 ah->config.serialize_regmode); 527 528 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 529 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 530 else 531 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 532 533 switch (ah->hw_version.macVersion) { 534 case AR_SREV_VERSION_5416_PCI: 535 case AR_SREV_VERSION_5416_PCIE: 536 case AR_SREV_VERSION_9160: 537 case AR_SREV_VERSION_9100: 538 case AR_SREV_VERSION_9280: 539 case AR_SREV_VERSION_9285: 540 case AR_SREV_VERSION_9287: 541 case AR_SREV_VERSION_9271: 542 case AR_SREV_VERSION_9300: 543 case AR_SREV_VERSION_9485: 544 break; 545 default: 546 ath_err(common, 547 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 548 ah->hw_version.macVersion, ah->hw_version.macRev); 549 return -EOPNOTSUPP; 550 } 551 552 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 553 ah->is_pciexpress = false; 554 555 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 556 ath9k_hw_init_cal_settings(ah); 557 558 ah->ani_function = ATH9K_ANI_ALL; 559 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 560 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 561 if (!AR_SREV_9300_20_OR_LATER(ah)) 562 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 563 564 ath9k_hw_init_mode_regs(ah); 565 566 /* 567 * Read back AR_WA into a permanent copy and set bits 14 and 17. 568 * We need to do this to avoid RMW of this register. We cannot 569 * read the reg when chip is asleep. 570 */ 571 ah->WARegVal = REG_READ(ah, AR_WA); 572 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 573 AR_WA_ASPM_TIMER_BASED_DISABLE); 574 575 if (ah->is_pciexpress) 576 ath9k_hw_configpcipowersave(ah, 0, 0); 577 else 578 ath9k_hw_disablepcie(ah); 579 580 if (!AR_SREV_9300_20_OR_LATER(ah)) 581 ar9002_hw_cck_chan14_spread(ah); 582 583 r = ath9k_hw_post_init(ah); 584 if (r) 585 return r; 586 587 ath9k_hw_init_mode_gain_regs(ah); 588 r = ath9k_hw_fill_cap_info(ah); 589 if (r) 590 return r; 591 592 r = ath9k_hw_init_macaddr(ah); 593 if (r) { 594 ath_err(common, "Failed to initialize MAC address\n"); 595 return r; 596 } 597 598 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 599 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 600 else 601 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 602 603 ah->bb_watchdog_timeout_ms = 25; 604 605 common->state = ATH_HW_INITIALIZED; 606 607 return 0; 608 } 609 610 int ath9k_hw_init(struct ath_hw *ah) 611 { 612 int ret; 613 struct ath_common *common = ath9k_hw_common(ah); 614 615 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 616 switch (ah->hw_version.devid) { 617 case AR5416_DEVID_PCI: 618 case AR5416_DEVID_PCIE: 619 case AR5416_AR9100_DEVID: 620 case AR9160_DEVID_PCI: 621 case AR9280_DEVID_PCI: 622 case AR9280_DEVID_PCIE: 623 case AR9285_DEVID_PCIE: 624 case AR9287_DEVID_PCI: 625 case AR9287_DEVID_PCIE: 626 case AR2427_DEVID_PCIE: 627 case AR9300_DEVID_PCIE: 628 case AR9300_DEVID_AR9485_PCIE: 629 break; 630 default: 631 if (common->bus_ops->ath_bus_type == ATH_USB) 632 break; 633 ath_err(common, "Hardware device ID 0x%04x not supported\n", 634 ah->hw_version.devid); 635 return -EOPNOTSUPP; 636 } 637 638 ret = __ath9k_hw_init(ah); 639 if (ret) { 640 ath_err(common, 641 "Unable to initialize hardware; initialization status: %d\n", 642 ret); 643 return ret; 644 } 645 646 return 0; 647 } 648 EXPORT_SYMBOL(ath9k_hw_init); 649 650 static void ath9k_hw_init_qos(struct ath_hw *ah) 651 { 652 ENABLE_REGWRITE_BUFFER(ah); 653 654 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 655 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 656 657 REG_WRITE(ah, AR_QOS_NO_ACK, 658 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 659 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 660 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 661 662 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 663 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 664 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 665 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 666 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 667 668 REGWRITE_BUFFER_FLUSH(ah); 669 } 670 671 static void ath9k_hw_init_pll(struct ath_hw *ah, 672 struct ath9k_channel *chan) 673 { 674 u32 pll; 675 676 if (AR_SREV_9485(ah)) 677 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); 678 679 pll = ath9k_hw_compute_pll_control(ah, chan); 680 681 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 682 683 /* Switch the core clock for ar9271 to 117Mhz */ 684 if (AR_SREV_9271(ah)) { 685 udelay(500); 686 REG_WRITE(ah, 0x50040, 0x304); 687 } 688 689 udelay(RTC_PLL_SETTLE_DELAY); 690 691 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 692 } 693 694 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 695 enum nl80211_iftype opmode) 696 { 697 u32 imr_reg = AR_IMR_TXERR | 698 AR_IMR_TXURN | 699 AR_IMR_RXERR | 700 AR_IMR_RXORN | 701 AR_IMR_BCNMISC; 702 703 if (AR_SREV_9300_20_OR_LATER(ah)) { 704 imr_reg |= AR_IMR_RXOK_HP; 705 if (ah->config.rx_intr_mitigation) 706 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 707 else 708 imr_reg |= AR_IMR_RXOK_LP; 709 710 } else { 711 if (ah->config.rx_intr_mitigation) 712 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 713 else 714 imr_reg |= AR_IMR_RXOK; 715 } 716 717 if (ah->config.tx_intr_mitigation) 718 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 719 else 720 imr_reg |= AR_IMR_TXOK; 721 722 if (opmode == NL80211_IFTYPE_AP) 723 imr_reg |= AR_IMR_MIB; 724 725 ENABLE_REGWRITE_BUFFER(ah); 726 727 REG_WRITE(ah, AR_IMR, imr_reg); 728 ah->imrs2_reg |= AR_IMR_S2_GTT; 729 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 730 731 if (!AR_SREV_9100(ah)) { 732 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 733 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 734 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 735 } 736 737 REGWRITE_BUFFER_FLUSH(ah); 738 739 if (AR_SREV_9300_20_OR_LATER(ah)) { 740 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 741 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 742 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 743 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 744 } 745 } 746 747 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 748 { 749 u32 val = ath9k_hw_mac_to_clks(ah, us); 750 val = min(val, (u32) 0xFFFF); 751 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 752 } 753 754 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 755 { 756 u32 val = ath9k_hw_mac_to_clks(ah, us); 757 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 758 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 759 } 760 761 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 762 { 763 u32 val = ath9k_hw_mac_to_clks(ah, us); 764 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 765 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 766 } 767 768 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 769 { 770 if (tu > 0xFFFF) { 771 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 772 "bad global tx timeout %u\n", tu); 773 ah->globaltxtimeout = (u32) -1; 774 return false; 775 } else { 776 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 777 ah->globaltxtimeout = tu; 778 return true; 779 } 780 } 781 782 void ath9k_hw_init_global_settings(struct ath_hw *ah) 783 { 784 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 785 int acktimeout; 786 int slottime; 787 int sifstime; 788 789 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 790 ah->misc_mode); 791 792 if (ah->misc_mode != 0) 793 REG_WRITE(ah, AR_PCU_MISC, 794 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 795 796 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 797 sifstime = 16; 798 else 799 sifstime = 10; 800 801 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 802 slottime = ah->slottime + 3 * ah->coverage_class; 803 acktimeout = slottime + sifstime; 804 805 /* 806 * Workaround for early ACK timeouts, add an offset to match the 807 * initval's 64us ack timeout value. 808 * This was initially only meant to work around an issue with delayed 809 * BA frames in some implementations, but it has been found to fix ACK 810 * timeout issues in other cases as well. 811 */ 812 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 813 acktimeout += 64 - sifstime - ah->slottime; 814 815 ath9k_hw_setslottime(ah, ah->slottime); 816 ath9k_hw_set_ack_timeout(ah, acktimeout); 817 ath9k_hw_set_cts_timeout(ah, acktimeout); 818 if (ah->globaltxtimeout != (u32) -1) 819 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 820 } 821 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 822 823 void ath9k_hw_deinit(struct ath_hw *ah) 824 { 825 struct ath_common *common = ath9k_hw_common(ah); 826 827 if (common->state < ATH_HW_INITIALIZED) 828 goto free_hw; 829 830 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 831 832 free_hw: 833 ath9k_hw_rf_free_ext_banks(ah); 834 } 835 EXPORT_SYMBOL(ath9k_hw_deinit); 836 837 /*******/ 838 /* INI */ 839 /*******/ 840 841 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 842 { 843 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 844 845 if (IS_CHAN_B(chan)) 846 ctl |= CTL_11B; 847 else if (IS_CHAN_G(chan)) 848 ctl |= CTL_11G; 849 else 850 ctl |= CTL_11A; 851 852 return ctl; 853 } 854 855 /****************************************/ 856 /* Reset and Channel Switching Routines */ 857 /****************************************/ 858 859 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 860 { 861 struct ath_common *common = ath9k_hw_common(ah); 862 u32 regval; 863 864 ENABLE_REGWRITE_BUFFER(ah); 865 866 /* 867 * set AHB_MODE not to do cacheline prefetches 868 */ 869 if (!AR_SREV_9300_20_OR_LATER(ah)) { 870 regval = REG_READ(ah, AR_AHB_MODE); 871 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 872 } 873 874 /* 875 * let mac dma reads be in 128 byte chunks 876 */ 877 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 878 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 879 880 REGWRITE_BUFFER_FLUSH(ah); 881 882 /* 883 * Restore TX Trigger Level to its pre-reset value. 884 * The initial value depends on whether aggregation is enabled, and is 885 * adjusted whenever underruns are detected. 886 */ 887 if (!AR_SREV_9300_20_OR_LATER(ah)) 888 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 889 890 ENABLE_REGWRITE_BUFFER(ah); 891 892 /* 893 * let mac dma writes be in 128 byte chunks 894 */ 895 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 896 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 897 898 /* 899 * Setup receive FIFO threshold to hold off TX activities 900 */ 901 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 902 903 if (AR_SREV_9300_20_OR_LATER(ah)) { 904 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 905 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 906 907 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 908 ah->caps.rx_status_len); 909 } 910 911 /* 912 * reduce the number of usable entries in PCU TXBUF to avoid 913 * wrap around issues. 914 */ 915 if (AR_SREV_9285(ah)) { 916 /* For AR9285 the number of Fifos are reduced to half. 917 * So set the usable tx buf size also to half to 918 * avoid data/delimiter underruns 919 */ 920 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 921 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 922 } else if (!AR_SREV_9271(ah)) { 923 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 924 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 925 } 926 927 REGWRITE_BUFFER_FLUSH(ah); 928 929 if (AR_SREV_9300_20_OR_LATER(ah)) 930 ath9k_hw_reset_txstatus_ring(ah); 931 } 932 933 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 934 { 935 u32 val; 936 937 val = REG_READ(ah, AR_STA_ID1); 938 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 939 switch (opmode) { 940 case NL80211_IFTYPE_AP: 941 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 942 | AR_STA_ID1_KSRCH_MODE); 943 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 944 break; 945 case NL80211_IFTYPE_ADHOC: 946 case NL80211_IFTYPE_MESH_POINT: 947 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 948 | AR_STA_ID1_KSRCH_MODE); 949 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 950 break; 951 case NL80211_IFTYPE_STATION: 952 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 953 break; 954 default: 955 if (ah->is_monitoring) 956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 957 break; 958 } 959 } 960 961 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 962 u32 *coef_mantissa, u32 *coef_exponent) 963 { 964 u32 coef_exp, coef_man; 965 966 for (coef_exp = 31; coef_exp > 0; coef_exp--) 967 if ((coef_scaled >> coef_exp) & 0x1) 968 break; 969 970 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 971 972 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 973 974 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 975 *coef_exponent = coef_exp - 16; 976 } 977 978 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 979 { 980 u32 rst_flags; 981 u32 tmpReg; 982 983 if (AR_SREV_9100(ah)) { 984 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 985 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 986 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 987 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 988 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 989 } 990 991 ENABLE_REGWRITE_BUFFER(ah); 992 993 if (AR_SREV_9300_20_OR_LATER(ah)) { 994 REG_WRITE(ah, AR_WA, ah->WARegVal); 995 udelay(10); 996 } 997 998 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 999 AR_RTC_FORCE_WAKE_ON_INT); 1000 1001 if (AR_SREV_9100(ah)) { 1002 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1003 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1004 } else { 1005 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1006 if (tmpReg & 1007 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1008 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1009 u32 val; 1010 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1011 1012 val = AR_RC_HOSTIF; 1013 if (!AR_SREV_9300_20_OR_LATER(ah)) 1014 val |= AR_RC_AHB; 1015 REG_WRITE(ah, AR_RC, val); 1016 1017 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1018 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1019 1020 rst_flags = AR_RTC_RC_MAC_WARM; 1021 if (type == ATH9K_RESET_COLD) 1022 rst_flags |= AR_RTC_RC_MAC_COLD; 1023 } 1024 1025 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1026 1027 REGWRITE_BUFFER_FLUSH(ah); 1028 1029 udelay(50); 1030 1031 REG_WRITE(ah, AR_RTC_RC, 0); 1032 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1033 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1034 "RTC stuck in MAC reset\n"); 1035 return false; 1036 } 1037 1038 if (!AR_SREV_9100(ah)) 1039 REG_WRITE(ah, AR_RC, 0); 1040 1041 if (AR_SREV_9100(ah)) 1042 udelay(50); 1043 1044 return true; 1045 } 1046 1047 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1048 { 1049 ENABLE_REGWRITE_BUFFER(ah); 1050 1051 if (AR_SREV_9300_20_OR_LATER(ah)) { 1052 REG_WRITE(ah, AR_WA, ah->WARegVal); 1053 udelay(10); 1054 } 1055 1056 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1057 AR_RTC_FORCE_WAKE_ON_INT); 1058 1059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1060 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1061 1062 REG_WRITE(ah, AR_RTC_RESET, 0); 1063 udelay(2); 1064 1065 REGWRITE_BUFFER_FLUSH(ah); 1066 1067 if (!AR_SREV_9300_20_OR_LATER(ah)) 1068 udelay(2); 1069 1070 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1071 REG_WRITE(ah, AR_RC, 0); 1072 1073 REG_WRITE(ah, AR_RTC_RESET, 1); 1074 1075 if (!ath9k_hw_wait(ah, 1076 AR_RTC_STATUS, 1077 AR_RTC_STATUS_M, 1078 AR_RTC_STATUS_ON, 1079 AH_WAIT_TIMEOUT)) { 1080 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1081 "RTC not waking up\n"); 1082 return false; 1083 } 1084 1085 ath9k_hw_read_revisions(ah); 1086 1087 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1088 } 1089 1090 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1091 { 1092 if (AR_SREV_9300_20_OR_LATER(ah)) { 1093 REG_WRITE(ah, AR_WA, ah->WARegVal); 1094 udelay(10); 1095 } 1096 1097 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1098 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1099 1100 switch (type) { 1101 case ATH9K_RESET_POWER_ON: 1102 return ath9k_hw_set_reset_power_on(ah); 1103 case ATH9K_RESET_WARM: 1104 case ATH9K_RESET_COLD: 1105 return ath9k_hw_set_reset(ah, type); 1106 default: 1107 return false; 1108 } 1109 } 1110 1111 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1112 struct ath9k_channel *chan) 1113 { 1114 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1115 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1116 return false; 1117 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1118 return false; 1119 1120 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1121 return false; 1122 1123 ah->chip_fullsleep = false; 1124 ath9k_hw_init_pll(ah, chan); 1125 ath9k_hw_set_rfmode(ah, chan); 1126 1127 return true; 1128 } 1129 1130 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1131 struct ath9k_channel *chan) 1132 { 1133 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1134 struct ath_common *common = ath9k_hw_common(ah); 1135 struct ieee80211_channel *channel = chan->chan; 1136 u32 qnum; 1137 int r; 1138 1139 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1140 if (ath9k_hw_numtxpending(ah, qnum)) { 1141 ath_dbg(common, ATH_DBG_QUEUE, 1142 "Transmit frames pending on queue %d\n", qnum); 1143 return false; 1144 } 1145 } 1146 1147 if (!ath9k_hw_rfbus_req(ah)) { 1148 ath_err(common, "Could not kill baseband RX\n"); 1149 return false; 1150 } 1151 1152 ath9k_hw_set_channel_regs(ah, chan); 1153 1154 r = ath9k_hw_rf_set_freq(ah, chan); 1155 if (r) { 1156 ath_err(common, "Failed to set channel\n"); 1157 return false; 1158 } 1159 ath9k_hw_set_clockrate(ah); 1160 1161 ah->eep_ops->set_txpower(ah, chan, 1162 ath9k_regd_get_ctl(regulatory, chan), 1163 channel->max_antenna_gain * 2, 1164 channel->max_power * 2, 1165 min((u32) MAX_RATE_POWER, 1166 (u32) regulatory->power_limit), false); 1167 1168 ath9k_hw_rfbus_done(ah); 1169 1170 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1171 ath9k_hw_set_delta_slope(ah, chan); 1172 1173 ath9k_hw_spur_mitigate_freq(ah, chan); 1174 1175 return true; 1176 } 1177 1178 bool ath9k_hw_check_alive(struct ath_hw *ah) 1179 { 1180 int count = 50; 1181 u32 reg; 1182 1183 if (AR_SREV_9285_12_OR_LATER(ah)) 1184 return true; 1185 1186 do { 1187 reg = REG_READ(ah, AR_OBS_BUS_1); 1188 1189 if ((reg & 0x7E7FFFEF) == 0x00702400) 1190 continue; 1191 1192 switch (reg & 0x7E000B00) { 1193 case 0x1E000000: 1194 case 0x52000B00: 1195 case 0x18000B00: 1196 continue; 1197 default: 1198 return true; 1199 } 1200 } while (count-- > 0); 1201 1202 return false; 1203 } 1204 EXPORT_SYMBOL(ath9k_hw_check_alive); 1205 1206 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1207 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1208 { 1209 struct ath_common *common = ath9k_hw_common(ah); 1210 u32 saveLedState; 1211 struct ath9k_channel *curchan = ah->curchan; 1212 u32 saveDefAntenna; 1213 u32 macStaId1; 1214 u64 tsf = 0; 1215 int i, r; 1216 1217 ah->txchainmask = common->tx_chainmask; 1218 ah->rxchainmask = common->rx_chainmask; 1219 1220 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) { 1221 ath9k_hw_abortpcurecv(ah); 1222 if (!ath9k_hw_stopdmarecv(ah)) { 1223 ath_dbg(common, ATH_DBG_XMIT, 1224 "Failed to stop receive dma\n"); 1225 bChannelChange = false; 1226 } 1227 } 1228 1229 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1230 return -EIO; 1231 1232 if (curchan && !ah->chip_fullsleep) 1233 ath9k_hw_getnf(ah, curchan); 1234 1235 ah->caldata = caldata; 1236 if (caldata && 1237 (chan->channel != caldata->channel || 1238 (chan->channelFlags & ~CHANNEL_CW_INT) != 1239 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1240 /* Operating channel changed, reset channel calibration data */ 1241 memset(caldata, 0, sizeof(*caldata)); 1242 ath9k_init_nfcal_hist_buffer(ah, chan); 1243 } 1244 1245 if (bChannelChange && 1246 (ah->chip_fullsleep != true) && 1247 (ah->curchan != NULL) && 1248 (chan->channel != ah->curchan->channel) && 1249 ((chan->channelFlags & CHANNEL_ALL) == 1250 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1251 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1252 1253 if (ath9k_hw_channel_change(ah, chan)) { 1254 ath9k_hw_loadnf(ah, ah->curchan); 1255 ath9k_hw_start_nfcal(ah, true); 1256 if (AR_SREV_9271(ah)) 1257 ar9002_hw_load_ani_reg(ah, chan); 1258 return 0; 1259 } 1260 } 1261 1262 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1263 if (saveDefAntenna == 0) 1264 saveDefAntenna = 1; 1265 1266 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1267 1268 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1269 if (AR_SREV_9100(ah) || 1270 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1271 tsf = ath9k_hw_gettsf64(ah); 1272 1273 saveLedState = REG_READ(ah, AR_CFG_LED) & 1274 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1275 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1276 1277 ath9k_hw_mark_phy_inactive(ah); 1278 1279 ah->paprd_table_write_done = false; 1280 1281 /* Only required on the first reset */ 1282 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1283 REG_WRITE(ah, 1284 AR9271_RESET_POWER_DOWN_CONTROL, 1285 AR9271_RADIO_RF_RST); 1286 udelay(50); 1287 } 1288 1289 if (!ath9k_hw_chip_reset(ah, chan)) { 1290 ath_err(common, "Chip reset failed\n"); 1291 return -EINVAL; 1292 } 1293 1294 /* Only required on the first reset */ 1295 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1296 ah->htc_reset_init = false; 1297 REG_WRITE(ah, 1298 AR9271_RESET_POWER_DOWN_CONTROL, 1299 AR9271_GATE_MAC_CTL); 1300 udelay(50); 1301 } 1302 1303 /* Restore TSF */ 1304 if (tsf) 1305 ath9k_hw_settsf64(ah, tsf); 1306 1307 if (AR_SREV_9280_20_OR_LATER(ah)) 1308 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1309 1310 if (!AR_SREV_9300_20_OR_LATER(ah)) 1311 ar9002_hw_enable_async_fifo(ah); 1312 1313 r = ath9k_hw_process_ini(ah, chan); 1314 if (r) 1315 return r; 1316 1317 /* 1318 * Some AR91xx SoC devices frequently fail to accept TSF writes 1319 * right after the chip reset. When that happens, write a new 1320 * value after the initvals have been applied, with an offset 1321 * based on measured time difference 1322 */ 1323 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1324 tsf += 1500; 1325 ath9k_hw_settsf64(ah, tsf); 1326 } 1327 1328 /* Setup MFP options for CCMP */ 1329 if (AR_SREV_9280_20_OR_LATER(ah)) { 1330 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1331 * frames when constructing CCMP AAD. */ 1332 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1333 0xc7ff); 1334 ah->sw_mgmt_crypto = false; 1335 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1336 /* Disable hardware crypto for management frames */ 1337 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1338 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1339 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1340 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1341 ah->sw_mgmt_crypto = true; 1342 } else 1343 ah->sw_mgmt_crypto = true; 1344 1345 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1346 ath9k_hw_set_delta_slope(ah, chan); 1347 1348 ath9k_hw_spur_mitigate_freq(ah, chan); 1349 ah->eep_ops->set_board_values(ah, chan); 1350 1351 ath9k_hw_set_operating_mode(ah, ah->opmode); 1352 1353 ENABLE_REGWRITE_BUFFER(ah); 1354 1355 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1356 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1357 | macStaId1 1358 | AR_STA_ID1_RTS_USE_DEF 1359 | (ah->config. 1360 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1361 | ah->sta_id1_defaults); 1362 ath_hw_setbssidmask(common); 1363 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1364 ath9k_hw_write_associd(ah); 1365 REG_WRITE(ah, AR_ISR, ~0); 1366 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1367 1368 REGWRITE_BUFFER_FLUSH(ah); 1369 1370 r = ath9k_hw_rf_set_freq(ah, chan); 1371 if (r) 1372 return r; 1373 1374 ath9k_hw_set_clockrate(ah); 1375 1376 ENABLE_REGWRITE_BUFFER(ah); 1377 1378 for (i = 0; i < AR_NUM_DCU; i++) 1379 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1380 1381 REGWRITE_BUFFER_FLUSH(ah); 1382 1383 ah->intr_txqs = 0; 1384 for (i = 0; i < ah->caps.total_queues; i++) 1385 ath9k_hw_resettxqueue(ah, i); 1386 1387 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1388 ath9k_hw_ani_cache_ini_regs(ah); 1389 ath9k_hw_init_qos(ah); 1390 1391 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1392 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1393 1394 ath9k_hw_init_global_settings(ah); 1395 1396 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1397 ar9002_hw_update_async_fifo(ah); 1398 ar9002_hw_enable_wep_aggregation(ah); 1399 } 1400 1401 REG_WRITE(ah, AR_STA_ID1, 1402 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1403 1404 ath9k_hw_set_dma(ah); 1405 1406 REG_WRITE(ah, AR_OBS, 8); 1407 1408 if (ah->config.rx_intr_mitigation) { 1409 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1410 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1411 } 1412 1413 if (ah->config.tx_intr_mitigation) { 1414 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1415 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1416 } 1417 1418 ath9k_hw_init_bb(ah, chan); 1419 1420 if (!ath9k_hw_init_cal(ah, chan)) 1421 return -EIO; 1422 1423 ENABLE_REGWRITE_BUFFER(ah); 1424 1425 ath9k_hw_restore_chainmask(ah); 1426 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1427 1428 REGWRITE_BUFFER_FLUSH(ah); 1429 1430 /* 1431 * For big endian systems turn on swapping for descriptors 1432 */ 1433 if (AR_SREV_9100(ah)) { 1434 u32 mask; 1435 mask = REG_READ(ah, AR_CFG); 1436 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1437 ath_dbg(common, ATH_DBG_RESET, 1438 "CFG Byte Swap Set 0x%x\n", mask); 1439 } else { 1440 mask = 1441 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1442 REG_WRITE(ah, AR_CFG, mask); 1443 ath_dbg(common, ATH_DBG_RESET, 1444 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1445 } 1446 } else { 1447 if (common->bus_ops->ath_bus_type == ATH_USB) { 1448 /* Configure AR9271 target WLAN */ 1449 if (AR_SREV_9271(ah)) 1450 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1451 else 1452 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1453 } 1454 #ifdef __BIG_ENDIAN 1455 else 1456 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1457 #endif 1458 } 1459 1460 if (ah->btcoex_hw.enabled) 1461 ath9k_hw_btcoex_enable(ah); 1462 1463 if (AR_SREV_9300_20_OR_LATER(ah)) 1464 ar9003_hw_bb_watchdog_config(ah); 1465 1466 return 0; 1467 } 1468 EXPORT_SYMBOL(ath9k_hw_reset); 1469 1470 /******************************/ 1471 /* Power Management (Chipset) */ 1472 /******************************/ 1473 1474 /* 1475 * Notify Power Mgt is disabled in self-generated frames. 1476 * If requested, force chip to sleep. 1477 */ 1478 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1479 { 1480 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1481 if (setChip) { 1482 /* 1483 * Clear the RTC force wake bit to allow the 1484 * mac to go to sleep. 1485 */ 1486 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1487 AR_RTC_FORCE_WAKE_EN); 1488 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1489 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1490 1491 /* Shutdown chip. Active low */ 1492 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1493 REG_CLR_BIT(ah, (AR_RTC_RESET), 1494 AR_RTC_RESET_EN); 1495 } 1496 1497 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1498 if (AR_SREV_9300_20_OR_LATER(ah)) 1499 REG_WRITE(ah, AR_WA, 1500 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1501 } 1502 1503 /* 1504 * Notify Power Management is enabled in self-generating 1505 * frames. If request, set power mode of chip to 1506 * auto/normal. Duration in units of 128us (1/8 TU). 1507 */ 1508 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1509 { 1510 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1511 if (setChip) { 1512 struct ath9k_hw_capabilities *pCap = &ah->caps; 1513 1514 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1515 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1516 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1517 AR_RTC_FORCE_WAKE_ON_INT); 1518 } else { 1519 /* 1520 * Clear the RTC force wake bit to allow the 1521 * mac to go to sleep. 1522 */ 1523 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1524 AR_RTC_FORCE_WAKE_EN); 1525 } 1526 } 1527 1528 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1529 if (AR_SREV_9300_20_OR_LATER(ah)) 1530 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1531 } 1532 1533 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1534 { 1535 u32 val; 1536 int i; 1537 1538 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1539 if (AR_SREV_9300_20_OR_LATER(ah)) { 1540 REG_WRITE(ah, AR_WA, ah->WARegVal); 1541 udelay(10); 1542 } 1543 1544 if (setChip) { 1545 if ((REG_READ(ah, AR_RTC_STATUS) & 1546 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1547 if (ath9k_hw_set_reset_reg(ah, 1548 ATH9K_RESET_POWER_ON) != true) { 1549 return false; 1550 } 1551 if (!AR_SREV_9300_20_OR_LATER(ah)) 1552 ath9k_hw_init_pll(ah, NULL); 1553 } 1554 if (AR_SREV_9100(ah)) 1555 REG_SET_BIT(ah, AR_RTC_RESET, 1556 AR_RTC_RESET_EN); 1557 1558 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1559 AR_RTC_FORCE_WAKE_EN); 1560 udelay(50); 1561 1562 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1563 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1564 if (val == AR_RTC_STATUS_ON) 1565 break; 1566 udelay(50); 1567 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1568 AR_RTC_FORCE_WAKE_EN); 1569 } 1570 if (i == 0) { 1571 ath_err(ath9k_hw_common(ah), 1572 "Failed to wakeup in %uus\n", 1573 POWER_UP_TIME / 20); 1574 return false; 1575 } 1576 } 1577 1578 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1579 1580 return true; 1581 } 1582 1583 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1584 { 1585 struct ath_common *common = ath9k_hw_common(ah); 1586 int status = true, setChip = true; 1587 static const char *modes[] = { 1588 "AWAKE", 1589 "FULL-SLEEP", 1590 "NETWORK SLEEP", 1591 "UNDEFINED" 1592 }; 1593 1594 if (ah->power_mode == mode) 1595 return status; 1596 1597 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1598 modes[ah->power_mode], modes[mode]); 1599 1600 switch (mode) { 1601 case ATH9K_PM_AWAKE: 1602 status = ath9k_hw_set_power_awake(ah, setChip); 1603 break; 1604 case ATH9K_PM_FULL_SLEEP: 1605 ath9k_set_power_sleep(ah, setChip); 1606 ah->chip_fullsleep = true; 1607 break; 1608 case ATH9K_PM_NETWORK_SLEEP: 1609 ath9k_set_power_network_sleep(ah, setChip); 1610 break; 1611 default: 1612 ath_err(common, "Unknown power mode %u\n", mode); 1613 return false; 1614 } 1615 ah->power_mode = mode; 1616 1617 /* 1618 * XXX: If this warning never comes up after a while then 1619 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1620 * ath9k_hw_setpower() return type void. 1621 */ 1622 1623 if (!(ah->ah_flags & AH_UNPLUGGED)) 1624 ATH_DBG_WARN_ON_ONCE(!status); 1625 1626 return status; 1627 } 1628 EXPORT_SYMBOL(ath9k_hw_setpower); 1629 1630 /*******************/ 1631 /* Beacon Handling */ 1632 /*******************/ 1633 1634 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1635 { 1636 int flags = 0; 1637 1638 ENABLE_REGWRITE_BUFFER(ah); 1639 1640 switch (ah->opmode) { 1641 case NL80211_IFTYPE_ADHOC: 1642 case NL80211_IFTYPE_MESH_POINT: 1643 REG_SET_BIT(ah, AR_TXCFG, 1644 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1645 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1646 TU_TO_USEC(next_beacon + 1647 (ah->atim_window ? ah-> 1648 atim_window : 1))); 1649 flags |= AR_NDP_TIMER_EN; 1650 case NL80211_IFTYPE_AP: 1651 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1652 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1653 TU_TO_USEC(next_beacon - 1654 ah->config. 1655 dma_beacon_response_time)); 1656 REG_WRITE(ah, AR_NEXT_SWBA, 1657 TU_TO_USEC(next_beacon - 1658 ah->config. 1659 sw_beacon_response_time)); 1660 flags |= 1661 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1662 break; 1663 default: 1664 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1665 "%s: unsupported opmode: %d\n", 1666 __func__, ah->opmode); 1667 return; 1668 break; 1669 } 1670 1671 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1672 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1673 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1674 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1675 1676 REGWRITE_BUFFER_FLUSH(ah); 1677 1678 beacon_period &= ~ATH9K_BEACON_ENA; 1679 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1680 ath9k_hw_reset_tsf(ah); 1681 } 1682 1683 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1684 } 1685 EXPORT_SYMBOL(ath9k_hw_beaconinit); 1686 1687 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1688 const struct ath9k_beacon_state *bs) 1689 { 1690 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1691 struct ath9k_hw_capabilities *pCap = &ah->caps; 1692 struct ath_common *common = ath9k_hw_common(ah); 1693 1694 ENABLE_REGWRITE_BUFFER(ah); 1695 1696 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1697 1698 REG_WRITE(ah, AR_BEACON_PERIOD, 1699 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1700 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1701 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1702 1703 REGWRITE_BUFFER_FLUSH(ah); 1704 1705 REG_RMW_FIELD(ah, AR_RSSI_THR, 1706 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1707 1708 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1709 1710 if (bs->bs_sleepduration > beaconintval) 1711 beaconintval = bs->bs_sleepduration; 1712 1713 dtimperiod = bs->bs_dtimperiod; 1714 if (bs->bs_sleepduration > dtimperiod) 1715 dtimperiod = bs->bs_sleepduration; 1716 1717 if (beaconintval == dtimperiod) 1718 nextTbtt = bs->bs_nextdtim; 1719 else 1720 nextTbtt = bs->bs_nexttbtt; 1721 1722 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1723 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1724 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1725 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1726 1727 ENABLE_REGWRITE_BUFFER(ah); 1728 1729 REG_WRITE(ah, AR_NEXT_DTIM, 1730 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1731 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1732 1733 REG_WRITE(ah, AR_SLEEP1, 1734 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1735 | AR_SLEEP1_ASSUME_DTIM); 1736 1737 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1738 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1739 else 1740 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1741 1742 REG_WRITE(ah, AR_SLEEP2, 1743 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1744 1745 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1746 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1747 1748 REGWRITE_BUFFER_FLUSH(ah); 1749 1750 REG_SET_BIT(ah, AR_TIMER_MODE, 1751 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1752 AR_DTIM_TIMER_EN); 1753 1754 /* TSF Out of Range Threshold */ 1755 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 1756 } 1757 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 1758 1759 /*******************/ 1760 /* HW Capabilities */ 1761 /*******************/ 1762 1763 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 1764 { 1765 struct ath9k_hw_capabilities *pCap = &ah->caps; 1766 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1767 struct ath_common *common = ath9k_hw_common(ah); 1768 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1769 1770 u16 capField = 0, eeval; 1771 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 1772 1773 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1774 regulatory->current_rd = eeval; 1775 1776 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 1777 if (AR_SREV_9285_12_OR_LATER(ah)) 1778 eeval |= AR9285_RDEXT_DEFAULT; 1779 regulatory->current_rd_ext = eeval; 1780 1781 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 1782 1783 if (ah->opmode != NL80211_IFTYPE_AP && 1784 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 1785 if (regulatory->current_rd == 0x64 || 1786 regulatory->current_rd == 0x65) 1787 regulatory->current_rd += 5; 1788 else if (regulatory->current_rd == 0x41) 1789 regulatory->current_rd = 0x43; 1790 ath_dbg(common, ATH_DBG_REGULATORY, 1791 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1792 } 1793 1794 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1795 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1796 ath_err(common, 1797 "no band has been marked as supported in EEPROM\n"); 1798 return -EINVAL; 1799 } 1800 1801 if (eeval & AR5416_OPFLAGS_11A) 1802 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 1803 1804 if (eeval & AR5416_OPFLAGS_11G) 1805 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 1806 1807 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 1808 /* 1809 * For AR9271 we will temporarilly uses the rx chainmax as read from 1810 * the EEPROM. 1811 */ 1812 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 1813 !(eeval & AR5416_OPFLAGS_11A) && 1814 !(AR_SREV_9271(ah))) 1815 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1816 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1817 else 1818 /* Use rx_chainmask from EEPROM. */ 1819 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1820 1821 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1822 1823 /* enable key search for every frame in an aggregate */ 1824 if (AR_SREV_9300_20_OR_LATER(ah)) 1825 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 1826 1827 pCap->low_2ghz_chan = 2312; 1828 pCap->high_2ghz_chan = 2732; 1829 1830 pCap->low_5ghz_chan = 4920; 1831 pCap->high_5ghz_chan = 6100; 1832 1833 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 1834 1835 if (ah->config.ht_enable) 1836 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1837 else 1838 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1839 1840 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 1841 pCap->total_queues = 1842 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 1843 else 1844 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 1845 1846 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 1847 pCap->keycache_size = 1848 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 1849 else 1850 pCap->keycache_size = AR_KEYTABLE_SIZE; 1851 1852 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 1853 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 1854 else 1855 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 1856 1857 if (AR_SREV_9271(ah)) 1858 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1859 else if (AR_DEVID_7010(ah)) 1860 pCap->num_gpio_pins = AR7010_NUM_GPIO; 1861 else if (AR_SREV_9285_12_OR_LATER(ah)) 1862 pCap->num_gpio_pins = AR9285_NUM_GPIO; 1863 else if (AR_SREV_9280_20_OR_LATER(ah)) 1864 pCap->num_gpio_pins = AR928X_NUM_GPIO; 1865 else 1866 pCap->num_gpio_pins = AR_NUM_GPIO; 1867 1868 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 1869 pCap->hw_caps |= ATH9K_HW_CAP_CST; 1870 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 1871 } else { 1872 pCap->rts_aggr_limit = (8 * 1024); 1873 } 1874 1875 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 1876 1877 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1878 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1879 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1880 ah->rfkill_gpio = 1881 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 1882 ah->rfkill_polarity = 1883 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 1884 1885 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 1886 } 1887 #endif 1888 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 1889 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 1890 else 1891 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 1892 1893 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 1894 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 1895 else 1896 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1897 1898 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 1899 pCap->reg_cap = 1900 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1901 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 1902 AR_EEPROM_EEREGCAP_EN_KK_U2 | 1903 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 1904 } else { 1905 pCap->reg_cap = 1906 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1907 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 1908 } 1909 1910 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 1911 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 1912 AR_SREV_5416(ah)) 1913 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 1914 1915 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { 1916 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1917 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1918 1919 if (AR_SREV_9285(ah)) { 1920 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1921 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 1922 } else { 1923 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 1924 } 1925 } else { 1926 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 1927 } 1928 1929 if (AR_SREV_9300_20_OR_LATER(ah)) { 1930 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 1931 if (!AR_SREV_9485(ah)) 1932 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 1933 1934 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1935 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1936 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1937 pCap->tx_desc_len = sizeof(struct ar9003_txc); 1938 pCap->txs_len = sizeof(struct ar9003_txs); 1939 if (!ah->config.paprd_disable && 1940 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 1941 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 1942 } else { 1943 pCap->tx_desc_len = sizeof(struct ath_desc); 1944 if (AR_SREV_9280_20(ah) && 1945 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 1946 AR5416_EEP_MINOR_VER_16) || 1947 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 1948 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 1949 } 1950 1951 if (AR_SREV_9300_20_OR_LATER(ah)) 1952 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 1953 1954 if (AR_SREV_9300_20_OR_LATER(ah)) 1955 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 1956 1957 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 1958 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 1959 1960 if (AR_SREV_9285(ah)) 1961 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 1962 ant_div_ctl1 = 1963 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1964 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 1965 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 1966 } 1967 if (AR_SREV_9300_20_OR_LATER(ah)) { 1968 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 1969 pCap->hw_caps |= ATH9K_HW_CAP_APM; 1970 } 1971 1972 1973 1974 if (AR_SREV_9485_10(ah)) { 1975 pCap->pcie_lcr_extsync_en = true; 1976 pCap->pcie_lcr_offset = 0x80; 1977 } 1978 1979 tx_chainmask = pCap->tx_chainmask; 1980 rx_chainmask = pCap->rx_chainmask; 1981 while (tx_chainmask || rx_chainmask) { 1982 if (tx_chainmask & BIT(0)) 1983 pCap->max_txchains++; 1984 if (rx_chainmask & BIT(0)) 1985 pCap->max_rxchains++; 1986 1987 tx_chainmask >>= 1; 1988 rx_chainmask >>= 1; 1989 } 1990 1991 return 0; 1992 } 1993 1994 /****************************/ 1995 /* GPIO / RFKILL / Antennae */ 1996 /****************************/ 1997 1998 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 1999 u32 gpio, u32 type) 2000 { 2001 int addr; 2002 u32 gpio_shift, tmp; 2003 2004 if (gpio > 11) 2005 addr = AR_GPIO_OUTPUT_MUX3; 2006 else if (gpio > 5) 2007 addr = AR_GPIO_OUTPUT_MUX2; 2008 else 2009 addr = AR_GPIO_OUTPUT_MUX1; 2010 2011 gpio_shift = (gpio % 6) * 5; 2012 2013 if (AR_SREV_9280_20_OR_LATER(ah) 2014 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2015 REG_RMW(ah, addr, (type << gpio_shift), 2016 (0x1f << gpio_shift)); 2017 } else { 2018 tmp = REG_READ(ah, addr); 2019 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2020 tmp &= ~(0x1f << gpio_shift); 2021 tmp |= (type << gpio_shift); 2022 REG_WRITE(ah, addr, tmp); 2023 } 2024 } 2025 2026 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2027 { 2028 u32 gpio_shift; 2029 2030 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2031 2032 if (AR_DEVID_7010(ah)) { 2033 gpio_shift = gpio; 2034 REG_RMW(ah, AR7010_GPIO_OE, 2035 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2036 (AR7010_GPIO_OE_MASK << gpio_shift)); 2037 return; 2038 } 2039 2040 gpio_shift = gpio << 1; 2041 REG_RMW(ah, 2042 AR_GPIO_OE_OUT, 2043 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2044 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2045 } 2046 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2047 2048 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2049 { 2050 #define MS_REG_READ(x, y) \ 2051 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2052 2053 if (gpio >= ah->caps.num_gpio_pins) 2054 return 0xffffffff; 2055 2056 if (AR_DEVID_7010(ah)) { 2057 u32 val; 2058 val = REG_READ(ah, AR7010_GPIO_IN); 2059 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2060 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2061 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2062 AR_GPIO_BIT(gpio)) != 0; 2063 else if (AR_SREV_9271(ah)) 2064 return MS_REG_READ(AR9271, gpio) != 0; 2065 else if (AR_SREV_9287_11_OR_LATER(ah)) 2066 return MS_REG_READ(AR9287, gpio) != 0; 2067 else if (AR_SREV_9285_12_OR_LATER(ah)) 2068 return MS_REG_READ(AR9285, gpio) != 0; 2069 else if (AR_SREV_9280_20_OR_LATER(ah)) 2070 return MS_REG_READ(AR928X, gpio) != 0; 2071 else 2072 return MS_REG_READ(AR, gpio) != 0; 2073 } 2074 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2075 2076 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2077 u32 ah_signal_type) 2078 { 2079 u32 gpio_shift; 2080 2081 if (AR_DEVID_7010(ah)) { 2082 gpio_shift = gpio; 2083 REG_RMW(ah, AR7010_GPIO_OE, 2084 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2085 (AR7010_GPIO_OE_MASK << gpio_shift)); 2086 return; 2087 } 2088 2089 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2090 gpio_shift = 2 * gpio; 2091 REG_RMW(ah, 2092 AR_GPIO_OE_OUT, 2093 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2094 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2095 } 2096 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2097 2098 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2099 { 2100 if (AR_DEVID_7010(ah)) { 2101 val = val ? 0 : 1; 2102 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2103 AR_GPIO_BIT(gpio)); 2104 return; 2105 } 2106 2107 if (AR_SREV_9271(ah)) 2108 val = ~val; 2109 2110 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2111 AR_GPIO_BIT(gpio)); 2112 } 2113 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2114 2115 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2116 { 2117 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2118 } 2119 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2120 2121 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2122 { 2123 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2124 } 2125 EXPORT_SYMBOL(ath9k_hw_setantenna); 2126 2127 /*********************/ 2128 /* General Operation */ 2129 /*********************/ 2130 2131 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2132 { 2133 u32 bits = REG_READ(ah, AR_RX_FILTER); 2134 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2135 2136 if (phybits & AR_PHY_ERR_RADAR) 2137 bits |= ATH9K_RX_FILTER_PHYRADAR; 2138 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2139 bits |= ATH9K_RX_FILTER_PHYERR; 2140 2141 return bits; 2142 } 2143 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2144 2145 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2146 { 2147 u32 phybits; 2148 2149 ENABLE_REGWRITE_BUFFER(ah); 2150 2151 REG_WRITE(ah, AR_RX_FILTER, bits); 2152 2153 phybits = 0; 2154 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2155 phybits |= AR_PHY_ERR_RADAR; 2156 if (bits & ATH9K_RX_FILTER_PHYERR) 2157 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2158 REG_WRITE(ah, AR_PHY_ERR, phybits); 2159 2160 if (phybits) 2161 REG_WRITE(ah, AR_RXCFG, 2162 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2163 else 2164 REG_WRITE(ah, AR_RXCFG, 2165 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2166 2167 REGWRITE_BUFFER_FLUSH(ah); 2168 } 2169 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2170 2171 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2172 { 2173 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2174 return false; 2175 2176 ath9k_hw_init_pll(ah, NULL); 2177 return true; 2178 } 2179 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2180 2181 bool ath9k_hw_disable(struct ath_hw *ah) 2182 { 2183 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2184 return false; 2185 2186 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2187 return false; 2188 2189 ath9k_hw_init_pll(ah, NULL); 2190 return true; 2191 } 2192 EXPORT_SYMBOL(ath9k_hw_disable); 2193 2194 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2195 { 2196 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2197 struct ath9k_channel *chan = ah->curchan; 2198 struct ieee80211_channel *channel = chan->chan; 2199 2200 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2201 2202 ah->eep_ops->set_txpower(ah, chan, 2203 ath9k_regd_get_ctl(regulatory, chan), 2204 channel->max_antenna_gain * 2, 2205 channel->max_power * 2, 2206 min((u32) MAX_RATE_POWER, 2207 (u32) regulatory->power_limit), test); 2208 } 2209 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2210 2211 void ath9k_hw_setopmode(struct ath_hw *ah) 2212 { 2213 ath9k_hw_set_operating_mode(ah, ah->opmode); 2214 } 2215 EXPORT_SYMBOL(ath9k_hw_setopmode); 2216 2217 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2218 { 2219 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2220 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2221 } 2222 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2223 2224 void ath9k_hw_write_associd(struct ath_hw *ah) 2225 { 2226 struct ath_common *common = ath9k_hw_common(ah); 2227 2228 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2229 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2230 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2231 } 2232 EXPORT_SYMBOL(ath9k_hw_write_associd); 2233 2234 #define ATH9K_MAX_TSF_READ 10 2235 2236 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2237 { 2238 u32 tsf_lower, tsf_upper1, tsf_upper2; 2239 int i; 2240 2241 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2242 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2243 tsf_lower = REG_READ(ah, AR_TSF_L32); 2244 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2245 if (tsf_upper2 == tsf_upper1) 2246 break; 2247 tsf_upper1 = tsf_upper2; 2248 } 2249 2250 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2251 2252 return (((u64)tsf_upper1 << 32) | tsf_lower); 2253 } 2254 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2255 2256 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2257 { 2258 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2259 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2260 } 2261 EXPORT_SYMBOL(ath9k_hw_settsf64); 2262 2263 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2264 { 2265 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2266 AH_TSF_WRITE_TIMEOUT)) 2267 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2268 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2269 2270 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2271 } 2272 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2273 2274 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2275 { 2276 if (setting) 2277 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2278 else 2279 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2280 } 2281 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2282 2283 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2284 { 2285 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2286 u32 macmode; 2287 2288 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2289 macmode = AR_2040_JOINED_RX_CLEAR; 2290 else 2291 macmode = 0; 2292 2293 REG_WRITE(ah, AR_2040_MODE, macmode); 2294 } 2295 2296 /* HW Generic timers configuration */ 2297 2298 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2299 { 2300 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2301 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2302 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2303 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2304 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2305 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2306 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2307 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2308 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2309 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2310 AR_NDP2_TIMER_MODE, 0x0002}, 2311 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2312 AR_NDP2_TIMER_MODE, 0x0004}, 2313 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2314 AR_NDP2_TIMER_MODE, 0x0008}, 2315 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2316 AR_NDP2_TIMER_MODE, 0x0010}, 2317 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2318 AR_NDP2_TIMER_MODE, 0x0020}, 2319 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2320 AR_NDP2_TIMER_MODE, 0x0040}, 2321 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2322 AR_NDP2_TIMER_MODE, 0x0080} 2323 }; 2324 2325 /* HW generic timer primitives */ 2326 2327 /* compute and clear index of rightmost 1 */ 2328 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2329 { 2330 u32 b; 2331 2332 b = *mask; 2333 b &= (0-b); 2334 *mask &= ~b; 2335 b *= debruijn32; 2336 b >>= 27; 2337 2338 return timer_table->gen_timer_index[b]; 2339 } 2340 2341 static u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2342 { 2343 return REG_READ(ah, AR_TSF_L32); 2344 } 2345 2346 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2347 void (*trigger)(void *), 2348 void (*overflow)(void *), 2349 void *arg, 2350 u8 timer_index) 2351 { 2352 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2353 struct ath_gen_timer *timer; 2354 2355 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2356 2357 if (timer == NULL) { 2358 ath_err(ath9k_hw_common(ah), 2359 "Failed to allocate memory for hw timer[%d]\n", 2360 timer_index); 2361 return NULL; 2362 } 2363 2364 /* allocate a hardware generic timer slot */ 2365 timer_table->timers[timer_index] = timer; 2366 timer->index = timer_index; 2367 timer->trigger = trigger; 2368 timer->overflow = overflow; 2369 timer->arg = arg; 2370 2371 return timer; 2372 } 2373 EXPORT_SYMBOL(ath_gen_timer_alloc); 2374 2375 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2376 struct ath_gen_timer *timer, 2377 u32 timer_next, 2378 u32 timer_period) 2379 { 2380 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2381 u32 tsf; 2382 2383 BUG_ON(!timer_period); 2384 2385 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2386 2387 tsf = ath9k_hw_gettsf32(ah); 2388 2389 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2390 "current tsf %x period %x timer_next %x\n", 2391 tsf, timer_period, timer_next); 2392 2393 /* 2394 * Pull timer_next forward if the current TSF already passed it 2395 * because of software latency 2396 */ 2397 if (timer_next < tsf) 2398 timer_next = tsf + timer_period; 2399 2400 /* 2401 * Program generic timer registers 2402 */ 2403 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2404 timer_next); 2405 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2406 timer_period); 2407 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2408 gen_tmr_configuration[timer->index].mode_mask); 2409 2410 /* Enable both trigger and thresh interrupt masks */ 2411 REG_SET_BIT(ah, AR_IMR_S5, 2412 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2413 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2414 } 2415 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2416 2417 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2418 { 2419 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2420 2421 if ((timer->index < AR_FIRST_NDP_TIMER) || 2422 (timer->index >= ATH_MAX_GEN_TIMER)) { 2423 return; 2424 } 2425 2426 /* Clear generic timer enable bits. */ 2427 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2428 gen_tmr_configuration[timer->index].mode_mask); 2429 2430 /* Disable both trigger and thresh interrupt masks */ 2431 REG_CLR_BIT(ah, AR_IMR_S5, 2432 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2433 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2434 2435 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2436 } 2437 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2438 2439 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2440 { 2441 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2442 2443 /* free the hardware generic timer slot */ 2444 timer_table->timers[timer->index] = NULL; 2445 kfree(timer); 2446 } 2447 EXPORT_SYMBOL(ath_gen_timer_free); 2448 2449 /* 2450 * Generic Timer Interrupts handling 2451 */ 2452 void ath_gen_timer_isr(struct ath_hw *ah) 2453 { 2454 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2455 struct ath_gen_timer *timer; 2456 struct ath_common *common = ath9k_hw_common(ah); 2457 u32 trigger_mask, thresh_mask, index; 2458 2459 /* get hardware generic timer interrupt status */ 2460 trigger_mask = ah->intr_gen_timer_trigger; 2461 thresh_mask = ah->intr_gen_timer_thresh; 2462 trigger_mask &= timer_table->timer_mask.val; 2463 thresh_mask &= timer_table->timer_mask.val; 2464 2465 trigger_mask &= ~thresh_mask; 2466 2467 while (thresh_mask) { 2468 index = rightmost_index(timer_table, &thresh_mask); 2469 timer = timer_table->timers[index]; 2470 BUG_ON(!timer); 2471 ath_dbg(common, ATH_DBG_HWTIMER, 2472 "TSF overflow for Gen timer %d\n", index); 2473 timer->overflow(timer->arg); 2474 } 2475 2476 while (trigger_mask) { 2477 index = rightmost_index(timer_table, &trigger_mask); 2478 timer = timer_table->timers[index]; 2479 BUG_ON(!timer); 2480 ath_dbg(common, ATH_DBG_HWTIMER, 2481 "Gen timer[%d] trigger\n", index); 2482 timer->trigger(timer->arg); 2483 } 2484 } 2485 EXPORT_SYMBOL(ath_gen_timer_isr); 2486 2487 /********/ 2488 /* HTC */ 2489 /********/ 2490 2491 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2492 { 2493 ah->htc_reset_init = true; 2494 } 2495 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2496 2497 static struct { 2498 u32 version; 2499 const char * name; 2500 } ath_mac_bb_names[] = { 2501 /* Devices with external radios */ 2502 { AR_SREV_VERSION_5416_PCI, "5416" }, 2503 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2504 { AR_SREV_VERSION_9100, "9100" }, 2505 { AR_SREV_VERSION_9160, "9160" }, 2506 /* Single-chip solutions */ 2507 { AR_SREV_VERSION_9280, "9280" }, 2508 { AR_SREV_VERSION_9285, "9285" }, 2509 { AR_SREV_VERSION_9287, "9287" }, 2510 { AR_SREV_VERSION_9271, "9271" }, 2511 { AR_SREV_VERSION_9300, "9300" }, 2512 }; 2513 2514 /* For devices with external radios */ 2515 static struct { 2516 u16 version; 2517 const char * name; 2518 } ath_rf_names[] = { 2519 { 0, "5133" }, 2520 { AR_RAD5133_SREV_MAJOR, "5133" }, 2521 { AR_RAD5122_SREV_MAJOR, "5122" }, 2522 { AR_RAD2133_SREV_MAJOR, "2133" }, 2523 { AR_RAD2122_SREV_MAJOR, "2122" } 2524 }; 2525 2526 /* 2527 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2528 */ 2529 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2530 { 2531 int i; 2532 2533 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2534 if (ath_mac_bb_names[i].version == mac_bb_version) { 2535 return ath_mac_bb_names[i].name; 2536 } 2537 } 2538 2539 return "????"; 2540 } 2541 2542 /* 2543 * Return the RF name. "????" is returned if the RF is unknown. 2544 * Used for devices with external radios. 2545 */ 2546 static const char *ath9k_hw_rf_name(u16 rf_version) 2547 { 2548 int i; 2549 2550 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2551 if (ath_rf_names[i].version == rf_version) { 2552 return ath_rf_names[i].name; 2553 } 2554 } 2555 2556 return "????"; 2557 } 2558 2559 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2560 { 2561 int used; 2562 2563 /* chipsets >= AR9280 are single-chip */ 2564 if (AR_SREV_9280_20_OR_LATER(ah)) { 2565 used = snprintf(hw_name, len, 2566 "Atheros AR%s Rev:%x", 2567 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2568 ah->hw_version.macRev); 2569 } 2570 else { 2571 used = snprintf(hw_name, len, 2572 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2573 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2574 ah->hw_version.macRev, 2575 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2576 AR_RADIO_SREV_MAJOR)), 2577 ah->hw_version.phyRev); 2578 } 2579 2580 hw_name[used] = '\0'; 2581 } 2582 EXPORT_SYMBOL(ath9k_hw_name); 2583