1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <asm/unaligned.h> 23 24 #include "hw.h" 25 #include "hw-ops.h" 26 #include "ar9003_mac.h" 27 #include "ar9003_mci.h" 28 #include "ar9003_phy.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 39 { 40 struct ath_common *common = ath9k_hw_common(ah); 41 struct ath9k_channel *chan = ah->curchan; 42 unsigned int clockrate; 43 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 46 clockrate = 117; 47 else if (!chan) /* should really check for CCK instead */ 48 clockrate = ATH9K_CLOCK_RATE_CCK; 49 else if (IS_CHAN_2GHZ(chan)) 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 53 else 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 55 56 if (chan) { 57 if (IS_CHAN_HT40(chan)) 58 clockrate *= 2; 59 if (IS_CHAN_HALF_RATE(chan)) 60 clockrate /= 2; 61 if (IS_CHAN_QUARTER_RATE(chan)) 62 clockrate /= 4; 63 } 64 65 common->clockrate = clockrate; 66 } 67 68 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 69 { 70 struct ath_common *common = ath9k_hw_common(ah); 71 72 return usecs * common->clockrate; 73 } 74 75 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 76 { 77 int i; 78 79 BUG_ON(timeout < AH_TIME_QUANTUM); 80 81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 82 if ((REG_READ(ah, reg) & mask) == val) 83 return true; 84 85 udelay(AH_TIME_QUANTUM); 86 } 87 88 ath_dbg(ath9k_hw_common(ah), ANY, 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 90 timeout, reg, REG_READ(ah, reg), mask, val); 91 92 return false; 93 } 94 EXPORT_SYMBOL(ath9k_hw_wait); 95 96 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 97 int hw_delay) 98 { 99 hw_delay /= 10; 100 101 if (IS_CHAN_HALF_RATE(chan)) 102 hw_delay *= 2; 103 else if (IS_CHAN_QUARTER_RATE(chan)) 104 hw_delay *= 4; 105 106 udelay(hw_delay + BASE_ACTIVATE_DELAY); 107 } 108 109 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 110 int column, unsigned int *writecnt) 111 { 112 int r; 113 114 ENABLE_REGWRITE_BUFFER(ah); 115 for (r = 0; r < array->ia_rows; r++) { 116 REG_WRITE(ah, INI_RA(array, r, 0), 117 INI_RA(array, r, column)); 118 DO_DELAY(*writecnt); 119 } 120 REGWRITE_BUFFER_FLUSH(ah); 121 } 122 123 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 124 { 125 u32 retval; 126 int i; 127 128 for (i = 0, retval = 0; i < n; i++) { 129 retval = (retval << 1) | (val & 1); 130 val >>= 1; 131 } 132 return retval; 133 } 134 135 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 136 u8 phy, int kbps, 137 u32 frameLen, u16 rateix, 138 bool shortPreamble) 139 { 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 141 142 if (kbps == 0) 143 return 0; 144 145 switch (phy) { 146 case WLAN_RC_PHY_CCK: 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 148 if (shortPreamble) 149 phyTime >>= 1; 150 numBits = frameLen << 3; 151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 152 break; 153 case WLAN_RC_PHY_OFDM: 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 156 numBits = OFDM_PLCP_BITS + (frameLen << 3); 157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 158 txTime = OFDM_SIFS_TIME_QUARTER 159 + OFDM_PREAMBLE_TIME_QUARTER 160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 161 } else if (ah->curchan && 162 IS_CHAN_HALF_RATE(ah->curchan)) { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME_HALF + 167 OFDM_PREAMBLE_TIME_HALF 168 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 169 } else { 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 171 numBits = OFDM_PLCP_BITS + (frameLen << 3); 172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 174 + (numSymbols * OFDM_SYMBOL_TIME); 175 } 176 break; 177 default: 178 ath_err(ath9k_hw_common(ah), 179 "Unknown phy %u (rate ix %u)\n", phy, rateix); 180 txTime = 0; 181 break; 182 } 183 184 return txTime; 185 } 186 EXPORT_SYMBOL(ath9k_hw_computetxtime); 187 188 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 189 struct ath9k_channel *chan, 190 struct chan_centers *centers) 191 { 192 int8_t extoff; 193 194 if (!IS_CHAN_HT40(chan)) { 195 centers->ctl_center = centers->ext_center = 196 centers->synth_center = chan->channel; 197 return; 198 } 199 200 if (IS_CHAN_HT40PLUS(chan)) { 201 centers->synth_center = 202 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 203 extoff = 1; 204 } else { 205 centers->synth_center = 206 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 207 extoff = -1; 208 } 209 210 centers->ctl_center = 211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 212 /* 25 MHz spacing is supported by hw but not on upper layers */ 213 centers->ext_center = 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 215 } 216 217 /******************/ 218 /* Chip Revisions */ 219 /******************/ 220 221 static void ath9k_hw_read_revisions(struct ath_hw *ah) 222 { 223 u32 val; 224 225 switch (ah->hw_version.devid) { 226 case AR5416_AR9100_DEVID: 227 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 228 break; 229 case AR9300_DEVID_AR9330: 230 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 231 if (ah->get_mac_revision) { 232 ah->hw_version.macRev = ah->get_mac_revision(); 233 } else { 234 val = REG_READ(ah, AR_SREV); 235 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 236 } 237 return; 238 case AR9300_DEVID_AR9340: 239 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 240 val = REG_READ(ah, AR_SREV); 241 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 242 return; 243 case AR9300_DEVID_QCA955X: 244 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 245 return; 246 case AR9300_DEVID_AR953X: 247 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 248 if (ah->get_mac_revision) 249 ah->hw_version.macRev = ah->get_mac_revision(); 250 return; 251 } 252 253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 254 255 if (val == 0xFF) { 256 val = REG_READ(ah, AR_SREV); 257 ah->hw_version.macVersion = 258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 260 261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 262 ah->is_pciexpress = true; 263 else 264 ah->is_pciexpress = (val & 265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 266 } else { 267 if (!AR_SREV_9100(ah)) 268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 269 270 ah->hw_version.macRev = val & AR_SREV_REVISION; 271 272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 273 ah->is_pciexpress = true; 274 } 275 } 276 277 /************************************/ 278 /* HW Attach, Detach, Init Routines */ 279 /************************************/ 280 281 static void ath9k_hw_disablepcie(struct ath_hw *ah) 282 { 283 if (!AR_SREV_5416(ah)) 284 return; 285 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 295 296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 297 } 298 299 /* This should work for all families including legacy */ 300 static bool ath9k_hw_chip_test(struct ath_hw *ah) 301 { 302 struct ath_common *common = ath9k_hw_common(ah); 303 u32 regAddr[2] = { AR_STA_ID0 }; 304 u32 regHold[2]; 305 static const u32 patternData[4] = { 306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 307 }; 308 int i, j, loop_max; 309 310 if (!AR_SREV_9300_20_OR_LATER(ah)) { 311 loop_max = 2; 312 regAddr[1] = AR_PHY_BASE + (8 << 2); 313 } else 314 loop_max = 1; 315 316 for (i = 0; i < loop_max; i++) { 317 u32 addr = regAddr[i]; 318 u32 wrData, rdData; 319 320 regHold[i] = REG_READ(ah, addr); 321 for (j = 0; j < 0x100; j++) { 322 wrData = (j << 16) | j; 323 REG_WRITE(ah, addr, wrData); 324 rdData = REG_READ(ah, addr); 325 if (rdData != wrData) { 326 ath_err(common, 327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 328 addr, wrData, rdData); 329 return false; 330 } 331 } 332 for (j = 0; j < 4; j++) { 333 wrData = patternData[j]; 334 REG_WRITE(ah, addr, wrData); 335 rdData = REG_READ(ah, addr); 336 if (wrData != rdData) { 337 ath_err(common, 338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 339 addr, wrData, rdData); 340 return false; 341 } 342 } 343 REG_WRITE(ah, regAddr[i], regHold[i]); 344 } 345 udelay(100); 346 347 return true; 348 } 349 350 static void ath9k_hw_init_config(struct ath_hw *ah) 351 { 352 struct ath_common *common = ath9k_hw_common(ah); 353 354 ah->config.dma_beacon_response_time = 1; 355 ah->config.sw_beacon_response_time = 6; 356 ah->config.cwm_ignore_extcca = 0; 357 ah->config.analog_shiftreg = 1; 358 359 ah->config.rx_intr_mitigation = true; 360 361 if (AR_SREV_9300_20_OR_LATER(ah)) { 362 ah->config.rimt_last = 500; 363 ah->config.rimt_first = 2000; 364 } else { 365 ah->config.rimt_last = 250; 366 ah->config.rimt_first = 700; 367 } 368 369 /* 370 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 372 * This means we use it for all AR5416 devices, and the few 373 * minor PCI AR9280 devices out there. 374 * 375 * Serialization is required because these devices do not handle 376 * well the case of two concurrent reads/writes due to the latency 377 * involved. During one read/write another read/write can be issued 378 * on another CPU while the previous read/write may still be working 379 * on our hardware, if we hit this case the hardware poops in a loop. 380 * We prevent this by serializing reads and writes. 381 * 382 * This issue is not present on PCI-Express devices or pre-AR5416 383 * devices (legacy, 802.11abg). 384 */ 385 if (num_possible_cpus() > 1) 386 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 387 388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 391 !ah->is_pciexpress)) { 392 ah->config.serialize_regmode = SER_REG_MODE_ON; 393 } else { 394 ah->config.serialize_regmode = SER_REG_MODE_OFF; 395 } 396 } 397 398 ath_dbg(common, RESET, "serialize_regmode is %d\n", 399 ah->config.serialize_regmode); 400 401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 403 else 404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 405 } 406 407 static void ath9k_hw_init_defaults(struct ath_hw *ah) 408 { 409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 410 411 regulatory->country_code = CTRY_DEFAULT; 412 regulatory->power_limit = MAX_RATE_POWER; 413 414 ah->hw_version.magic = AR5416_MAGIC; 415 ah->hw_version.subvendorid = 0; 416 417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 418 AR_STA_ID1_MCAST_KSRCH; 419 if (AR_SREV_9100(ah)) 420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 421 422 ah->slottime = ATH9K_SLOT_TIME_9; 423 ah->globaltxtimeout = (u32) -1; 424 ah->power_mode = ATH9K_PM_UNDEFINED; 425 ah->htc_reset_init = true; 426 427 ah->ani_function = ATH9K_ANI_ALL; 428 if (!AR_SREV_9300_20_OR_LATER(ah)) 429 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 430 431 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 432 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 433 else 434 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 435 } 436 437 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 438 { 439 struct ath_common *common = ath9k_hw_common(ah); 440 u32 sum; 441 int i; 442 u16 eeval; 443 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 444 445 sum = 0; 446 for (i = 0; i < 3; i++) { 447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 448 sum += eeval; 449 common->macaddr[2 * i] = eeval >> 8; 450 common->macaddr[2 * i + 1] = eeval & 0xff; 451 } 452 if (sum == 0 || sum == 0xffff * 3) 453 return -EADDRNOTAVAIL; 454 455 return 0; 456 } 457 458 static int ath9k_hw_post_init(struct ath_hw *ah) 459 { 460 struct ath_common *common = ath9k_hw_common(ah); 461 int ecode; 462 463 if (common->bus_ops->ath_bus_type != ATH_USB) { 464 if (!ath9k_hw_chip_test(ah)) 465 return -ENODEV; 466 } 467 468 if (!AR_SREV_9300_20_OR_LATER(ah)) { 469 ecode = ar9002_hw_rf_claim(ah); 470 if (ecode != 0) 471 return ecode; 472 } 473 474 ecode = ath9k_hw_eeprom_init(ah); 475 if (ecode != 0) 476 return ecode; 477 478 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 479 ah->eep_ops->get_eeprom_ver(ah), 480 ah->eep_ops->get_eeprom_rev(ah)); 481 482 ath9k_hw_ani_init(ah); 483 484 /* 485 * EEPROM needs to be initialized before we do this. 486 * This is required for regulatory compliance. 487 */ 488 if (AR_SREV_9300_20_OR_LATER(ah)) { 489 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 490 if ((regdmn & 0xF0) == CTL_FCC) { 491 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 492 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 493 } 494 } 495 496 return 0; 497 } 498 499 static int ath9k_hw_attach_ops(struct ath_hw *ah) 500 { 501 if (!AR_SREV_9300_20_OR_LATER(ah)) 502 return ar9002_hw_attach_ops(ah); 503 504 ar9003_hw_attach_ops(ah); 505 return 0; 506 } 507 508 /* Called for all hardware families */ 509 static int __ath9k_hw_init(struct ath_hw *ah) 510 { 511 struct ath_common *common = ath9k_hw_common(ah); 512 int r = 0; 513 514 ath9k_hw_read_revisions(ah); 515 516 switch (ah->hw_version.macVersion) { 517 case AR_SREV_VERSION_5416_PCI: 518 case AR_SREV_VERSION_5416_PCIE: 519 case AR_SREV_VERSION_9160: 520 case AR_SREV_VERSION_9100: 521 case AR_SREV_VERSION_9280: 522 case AR_SREV_VERSION_9285: 523 case AR_SREV_VERSION_9287: 524 case AR_SREV_VERSION_9271: 525 case AR_SREV_VERSION_9300: 526 case AR_SREV_VERSION_9330: 527 case AR_SREV_VERSION_9485: 528 case AR_SREV_VERSION_9340: 529 case AR_SREV_VERSION_9462: 530 case AR_SREV_VERSION_9550: 531 case AR_SREV_VERSION_9565: 532 case AR_SREV_VERSION_9531: 533 break; 534 default: 535 ath_err(common, 536 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 537 ah->hw_version.macVersion, ah->hw_version.macRev); 538 return -EOPNOTSUPP; 539 } 540 541 /* 542 * Read back AR_WA into a permanent copy and set bits 14 and 17. 543 * We need to do this to avoid RMW of this register. We cannot 544 * read the reg when chip is asleep. 545 */ 546 if (AR_SREV_9300_20_OR_LATER(ah)) { 547 ah->WARegVal = REG_READ(ah, AR_WA); 548 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 549 AR_WA_ASPM_TIMER_BASED_DISABLE); 550 } 551 552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 553 ath_err(common, "Couldn't reset chip\n"); 554 return -EIO; 555 } 556 557 if (AR_SREV_9565(ah)) { 558 ah->WARegVal |= AR_WA_BIT22; 559 REG_WRITE(ah, AR_WA, ah->WARegVal); 560 } 561 562 ath9k_hw_init_defaults(ah); 563 ath9k_hw_init_config(ah); 564 565 r = ath9k_hw_attach_ops(ah); 566 if (r) 567 return r; 568 569 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 570 ath_err(common, "Couldn't wakeup chip\n"); 571 return -EIO; 572 } 573 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 575 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 576 ah->is_pciexpress = false; 577 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 579 ath9k_hw_init_cal_settings(ah); 580 581 if (!ah->is_pciexpress) 582 ath9k_hw_disablepcie(ah); 583 584 r = ath9k_hw_post_init(ah); 585 if (r) 586 return r; 587 588 ath9k_hw_init_mode_gain_regs(ah); 589 r = ath9k_hw_fill_cap_info(ah); 590 if (r) 591 return r; 592 593 r = ath9k_hw_init_macaddr(ah); 594 if (r) { 595 ath_err(common, "Failed to initialize MAC address\n"); 596 return r; 597 } 598 599 ath9k_hw_init_hang_checks(ah); 600 601 common->state = ATH_HW_INITIALIZED; 602 603 return 0; 604 } 605 606 int ath9k_hw_init(struct ath_hw *ah) 607 { 608 int ret; 609 struct ath_common *common = ath9k_hw_common(ah); 610 611 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 612 switch (ah->hw_version.devid) { 613 case AR5416_DEVID_PCI: 614 case AR5416_DEVID_PCIE: 615 case AR5416_AR9100_DEVID: 616 case AR9160_DEVID_PCI: 617 case AR9280_DEVID_PCI: 618 case AR9280_DEVID_PCIE: 619 case AR9285_DEVID_PCIE: 620 case AR9287_DEVID_PCI: 621 case AR9287_DEVID_PCIE: 622 case AR2427_DEVID_PCIE: 623 case AR9300_DEVID_PCIE: 624 case AR9300_DEVID_AR9485_PCIE: 625 case AR9300_DEVID_AR9330: 626 case AR9300_DEVID_AR9340: 627 case AR9300_DEVID_QCA955X: 628 case AR9300_DEVID_AR9580: 629 case AR9300_DEVID_AR9462: 630 case AR9485_DEVID_AR1111: 631 case AR9300_DEVID_AR9565: 632 case AR9300_DEVID_AR953X: 633 break; 634 default: 635 if (common->bus_ops->ath_bus_type == ATH_USB) 636 break; 637 ath_err(common, "Hardware device ID 0x%04x not supported\n", 638 ah->hw_version.devid); 639 return -EOPNOTSUPP; 640 } 641 642 ret = __ath9k_hw_init(ah); 643 if (ret) { 644 ath_err(common, 645 "Unable to initialize hardware; initialization status: %d\n", 646 ret); 647 return ret; 648 } 649 650 return 0; 651 } 652 EXPORT_SYMBOL(ath9k_hw_init); 653 654 static void ath9k_hw_init_qos(struct ath_hw *ah) 655 { 656 ENABLE_REGWRITE_BUFFER(ah); 657 658 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 659 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 660 661 REG_WRITE(ah, AR_QOS_NO_ACK, 662 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 663 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 664 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 665 666 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 667 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 668 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 669 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 670 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 671 672 REGWRITE_BUFFER_FLUSH(ah); 673 } 674 675 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 676 { 677 struct ath_common *common = ath9k_hw_common(ah); 678 int i = 0; 679 680 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 681 udelay(100); 682 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 683 684 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 685 686 udelay(100); 687 688 if (WARN_ON_ONCE(i >= 100)) { 689 ath_err(common, "PLL4 meaurement not done\n"); 690 break; 691 } 692 693 i++; 694 } 695 696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 697 } 698 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 699 700 static void ath9k_hw_init_pll(struct ath_hw *ah, 701 struct ath9k_channel *chan) 702 { 703 u32 pll; 704 705 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 706 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 708 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 710 AR_CH0_DPLL2_KD, 0x40); 711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 712 AR_CH0_DPLL2_KI, 0x4); 713 714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 715 AR_CH0_BB_DPLL1_REFDIV, 0x5); 716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 717 AR_CH0_BB_DPLL1_NINI, 0x58); 718 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 719 AR_CH0_BB_DPLL1_NFRAC, 0x0); 720 721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 722 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 724 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 726 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 727 728 /* program BB PLL phase_shift to 0x6 */ 729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 730 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 731 732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 733 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 734 udelay(1000); 735 } else if (AR_SREV_9330(ah)) { 736 u32 ddr_dpll2, pll_control2, kd; 737 738 if (ah->is_clk_25mhz) { 739 ddr_dpll2 = 0x18e82f01; 740 pll_control2 = 0xe04a3d; 741 kd = 0x1d; 742 } else { 743 ddr_dpll2 = 0x19e82f01; 744 pll_control2 = 0x886666; 745 kd = 0x3d; 746 } 747 748 /* program DDR PLL ki and kd value */ 749 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 750 751 /* program DDR PLL phase_shift */ 752 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 753 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 754 755 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 756 udelay(1000); 757 758 /* program refdiv, nint, frac to RTC register */ 759 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 760 761 /* program BB PLL kd and ki value */ 762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 764 765 /* program BB PLL phase_shift */ 766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 767 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 768 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 769 u32 regval, pll2_divint, pll2_divfrac, refdiv; 770 771 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 772 udelay(1000); 773 774 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 775 udelay(100); 776 777 if (ah->is_clk_25mhz) { 778 if (AR_SREV_9531(ah)) { 779 pll2_divint = 0x1c; 780 pll2_divfrac = 0xa3d2; 781 refdiv = 1; 782 } else { 783 pll2_divint = 0x54; 784 pll2_divfrac = 0x1eb85; 785 refdiv = 3; 786 } 787 } else { 788 if (AR_SREV_9340(ah)) { 789 pll2_divint = 88; 790 pll2_divfrac = 0; 791 refdiv = 5; 792 } else { 793 pll2_divint = 0x11; 794 pll2_divfrac = 795 AR_SREV_9531(ah) ? 0x26665 : 0x26666; 796 refdiv = 1; 797 } 798 } 799 800 regval = REG_READ(ah, AR_PHY_PLL_MODE); 801 if (AR_SREV_9531(ah)) 802 regval |= (0x1 << 22); 803 else 804 regval |= (0x1 << 16); 805 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 806 udelay(100); 807 808 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 809 (pll2_divint << 18) | pll2_divfrac); 810 udelay(100); 811 812 regval = REG_READ(ah, AR_PHY_PLL_MODE); 813 if (AR_SREV_9340(ah)) 814 regval = (regval & 0x80071fff) | 815 (0x1 << 30) | 816 (0x1 << 13) | 817 (0x4 << 26) | 818 (0x18 << 19); 819 else if (AR_SREV_9531(ah)) 820 regval = (regval & 0x01c00fff) | 821 (0x1 << 31) | 822 (0x2 << 29) | 823 (0xa << 25) | 824 (0x1 << 19) | 825 (0x6 << 12); 826 else 827 regval = (regval & 0x80071fff) | 828 (0x3 << 30) | 829 (0x1 << 13) | 830 (0x4 << 26) | 831 (0x60 << 19); 832 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 833 834 if (AR_SREV_9531(ah)) 835 REG_WRITE(ah, AR_PHY_PLL_MODE, 836 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 837 else 838 REG_WRITE(ah, AR_PHY_PLL_MODE, 839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 840 841 udelay(1000); 842 } 843 844 pll = ath9k_hw_compute_pll_control(ah, chan); 845 if (AR_SREV_9565(ah)) 846 pll |= 0x40000; 847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 848 849 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 850 AR_SREV_9550(ah)) 851 udelay(1000); 852 853 /* Switch the core clock for ar9271 to 117Mhz */ 854 if (AR_SREV_9271(ah)) { 855 udelay(500); 856 REG_WRITE(ah, 0x50040, 0x304); 857 } 858 859 udelay(RTC_PLL_SETTLE_DELAY); 860 861 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 862 863 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 864 if (ah->is_clk_25mhz) { 865 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 866 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 867 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 868 } else { 869 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 870 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 871 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 872 } 873 udelay(100); 874 } 875 } 876 877 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 878 enum nl80211_iftype opmode) 879 { 880 u32 sync_default = AR_INTR_SYNC_DEFAULT; 881 u32 imr_reg = AR_IMR_TXERR | 882 AR_IMR_TXURN | 883 AR_IMR_RXERR | 884 AR_IMR_RXORN | 885 AR_IMR_BCNMISC; 886 887 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 888 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 889 890 if (AR_SREV_9300_20_OR_LATER(ah)) { 891 imr_reg |= AR_IMR_RXOK_HP; 892 if (ah->config.rx_intr_mitigation) 893 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 894 else 895 imr_reg |= AR_IMR_RXOK_LP; 896 897 } else { 898 if (ah->config.rx_intr_mitigation) 899 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 900 else 901 imr_reg |= AR_IMR_RXOK; 902 } 903 904 if (ah->config.tx_intr_mitigation) 905 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 906 else 907 imr_reg |= AR_IMR_TXOK; 908 909 ENABLE_REGWRITE_BUFFER(ah); 910 911 REG_WRITE(ah, AR_IMR, imr_reg); 912 ah->imrs2_reg |= AR_IMR_S2_GTT; 913 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 914 915 if (!AR_SREV_9100(ah)) { 916 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 917 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 918 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 919 } 920 921 REGWRITE_BUFFER_FLUSH(ah); 922 923 if (AR_SREV_9300_20_OR_LATER(ah)) { 924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 925 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 927 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 928 } 929 } 930 931 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 932 { 933 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 934 val = min(val, (u32) 0xFFFF); 935 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 936 } 937 938 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 939 { 940 u32 val = ath9k_hw_mac_to_clks(ah, us); 941 val = min(val, (u32) 0xFFFF); 942 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 943 } 944 945 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 946 { 947 u32 val = ath9k_hw_mac_to_clks(ah, us); 948 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 949 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 950 } 951 952 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 953 { 954 u32 val = ath9k_hw_mac_to_clks(ah, us); 955 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 956 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 957 } 958 959 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 960 { 961 if (tu > 0xFFFF) { 962 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 963 tu); 964 ah->globaltxtimeout = (u32) -1; 965 return false; 966 } else { 967 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 968 ah->globaltxtimeout = tu; 969 return true; 970 } 971 } 972 973 void ath9k_hw_init_global_settings(struct ath_hw *ah) 974 { 975 struct ath_common *common = ath9k_hw_common(ah); 976 const struct ath9k_channel *chan = ah->curchan; 977 int acktimeout, ctstimeout, ack_offset = 0; 978 int slottime; 979 int sifstime; 980 int rx_lat = 0, tx_lat = 0, eifs = 0; 981 u32 reg; 982 983 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 984 ah->misc_mode); 985 986 if (!chan) 987 return; 988 989 if (ah->misc_mode != 0) 990 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 991 992 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 993 rx_lat = 41; 994 else 995 rx_lat = 37; 996 tx_lat = 54; 997 998 if (IS_CHAN_5GHZ(chan)) 999 sifstime = 16; 1000 else 1001 sifstime = 10; 1002 1003 if (IS_CHAN_HALF_RATE(chan)) { 1004 eifs = 175; 1005 rx_lat *= 2; 1006 tx_lat *= 2; 1007 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1008 tx_lat += 11; 1009 1010 sifstime = 32; 1011 ack_offset = 16; 1012 slottime = 13; 1013 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1014 eifs = 340; 1015 rx_lat = (rx_lat * 4) - 1; 1016 tx_lat *= 4; 1017 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1018 tx_lat += 22; 1019 1020 sifstime = 64; 1021 ack_offset = 32; 1022 slottime = 21; 1023 } else { 1024 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1025 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1026 reg = AR_USEC_ASYNC_FIFO; 1027 } else { 1028 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1029 common->clockrate; 1030 reg = REG_READ(ah, AR_USEC); 1031 } 1032 rx_lat = MS(reg, AR_USEC_RX_LAT); 1033 tx_lat = MS(reg, AR_USEC_TX_LAT); 1034 1035 slottime = ah->slottime; 1036 } 1037 1038 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1039 slottime += 3 * ah->coverage_class; 1040 acktimeout = slottime + sifstime + ack_offset; 1041 ctstimeout = acktimeout; 1042 1043 /* 1044 * Workaround for early ACK timeouts, add an offset to match the 1045 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1046 * This was initially only meant to work around an issue with delayed 1047 * BA frames in some implementations, but it has been found to fix ACK 1048 * timeout issues in other cases as well. 1049 */ 1050 if (IS_CHAN_2GHZ(chan) && 1051 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1052 acktimeout += 64 - sifstime - ah->slottime; 1053 ctstimeout += 48 - sifstime - ah->slottime; 1054 } 1055 1056 ath9k_hw_set_sifs_time(ah, sifstime); 1057 ath9k_hw_setslottime(ah, slottime); 1058 ath9k_hw_set_ack_timeout(ah, acktimeout); 1059 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1060 if (ah->globaltxtimeout != (u32) -1) 1061 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1062 1063 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1064 REG_RMW(ah, AR_USEC, 1065 (common->clockrate - 1) | 1066 SM(rx_lat, AR_USEC_RX_LAT) | 1067 SM(tx_lat, AR_USEC_TX_LAT), 1068 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1069 1070 } 1071 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1072 1073 void ath9k_hw_deinit(struct ath_hw *ah) 1074 { 1075 struct ath_common *common = ath9k_hw_common(ah); 1076 1077 if (common->state < ATH_HW_INITIALIZED) 1078 return; 1079 1080 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1081 } 1082 EXPORT_SYMBOL(ath9k_hw_deinit); 1083 1084 /*******/ 1085 /* INI */ 1086 /*******/ 1087 1088 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1089 { 1090 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1091 1092 if (IS_CHAN_2GHZ(chan)) 1093 ctl |= CTL_11G; 1094 else 1095 ctl |= CTL_11A; 1096 1097 return ctl; 1098 } 1099 1100 /****************************************/ 1101 /* Reset and Channel Switching Routines */ 1102 /****************************************/ 1103 1104 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1105 { 1106 struct ath_common *common = ath9k_hw_common(ah); 1107 int txbuf_size; 1108 1109 ENABLE_REGWRITE_BUFFER(ah); 1110 1111 /* 1112 * set AHB_MODE not to do cacheline prefetches 1113 */ 1114 if (!AR_SREV_9300_20_OR_LATER(ah)) 1115 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1116 1117 /* 1118 * let mac dma reads be in 128 byte chunks 1119 */ 1120 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1121 1122 REGWRITE_BUFFER_FLUSH(ah); 1123 1124 /* 1125 * Restore TX Trigger Level to its pre-reset value. 1126 * The initial value depends on whether aggregation is enabled, and is 1127 * adjusted whenever underruns are detected. 1128 */ 1129 if (!AR_SREV_9300_20_OR_LATER(ah)) 1130 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1131 1132 ENABLE_REGWRITE_BUFFER(ah); 1133 1134 /* 1135 * let mac dma writes be in 128 byte chunks 1136 */ 1137 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1138 1139 /* 1140 * Setup receive FIFO threshold to hold off TX activities 1141 */ 1142 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1143 1144 if (AR_SREV_9300_20_OR_LATER(ah)) { 1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1146 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1147 1148 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1149 ah->caps.rx_status_len); 1150 } 1151 1152 /* 1153 * reduce the number of usable entries in PCU TXBUF to avoid 1154 * wrap around issues. 1155 */ 1156 if (AR_SREV_9285(ah)) { 1157 /* For AR9285 the number of Fifos are reduced to half. 1158 * So set the usable tx buf size also to half to 1159 * avoid data/delimiter underruns 1160 */ 1161 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1162 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1163 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1164 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1165 } else { 1166 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1167 } 1168 1169 if (!AR_SREV_9271(ah)) 1170 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1171 1172 REGWRITE_BUFFER_FLUSH(ah); 1173 1174 if (AR_SREV_9300_20_OR_LATER(ah)) 1175 ath9k_hw_reset_txstatus_ring(ah); 1176 } 1177 1178 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1179 { 1180 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1181 u32 set = AR_STA_ID1_KSRCH_MODE; 1182 1183 switch (opmode) { 1184 case NL80211_IFTYPE_ADHOC: 1185 set |= AR_STA_ID1_ADHOC; 1186 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1187 break; 1188 case NL80211_IFTYPE_MESH_POINT: 1189 case NL80211_IFTYPE_AP: 1190 set |= AR_STA_ID1_STA_AP; 1191 /* fall through */ 1192 case NL80211_IFTYPE_STATION: 1193 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1194 break; 1195 default: 1196 if (!ah->is_monitoring) 1197 set = 0; 1198 break; 1199 } 1200 REG_RMW(ah, AR_STA_ID1, set, mask); 1201 } 1202 1203 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1204 u32 *coef_mantissa, u32 *coef_exponent) 1205 { 1206 u32 coef_exp, coef_man; 1207 1208 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1209 if ((coef_scaled >> coef_exp) & 0x1) 1210 break; 1211 1212 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1213 1214 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1215 1216 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1217 *coef_exponent = coef_exp - 16; 1218 } 1219 1220 /* AR9330 WAR: 1221 * call external reset function to reset WMAC if: 1222 * - doing a cold reset 1223 * - we have pending frames in the TX queues. 1224 */ 1225 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1226 { 1227 int i, npend = 0; 1228 1229 for (i = 0; i < AR_NUM_QCU; i++) { 1230 npend = ath9k_hw_numtxpending(ah, i); 1231 if (npend) 1232 break; 1233 } 1234 1235 if (ah->external_reset && 1236 (npend || type == ATH9K_RESET_COLD)) { 1237 int reset_err = 0; 1238 1239 ath_dbg(ath9k_hw_common(ah), RESET, 1240 "reset MAC via external reset\n"); 1241 1242 reset_err = ah->external_reset(); 1243 if (reset_err) { 1244 ath_err(ath9k_hw_common(ah), 1245 "External reset failed, err=%d\n", 1246 reset_err); 1247 return false; 1248 } 1249 1250 REG_WRITE(ah, AR_RTC_RESET, 1); 1251 } 1252 1253 return true; 1254 } 1255 1256 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1257 { 1258 u32 rst_flags; 1259 u32 tmpReg; 1260 1261 if (AR_SREV_9100(ah)) { 1262 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1263 AR_RTC_DERIVED_CLK_PERIOD, 1); 1264 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1265 } 1266 1267 ENABLE_REGWRITE_BUFFER(ah); 1268 1269 if (AR_SREV_9300_20_OR_LATER(ah)) { 1270 REG_WRITE(ah, AR_WA, ah->WARegVal); 1271 udelay(10); 1272 } 1273 1274 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1275 AR_RTC_FORCE_WAKE_ON_INT); 1276 1277 if (AR_SREV_9100(ah)) { 1278 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1279 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1280 } else { 1281 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1282 if (AR_SREV_9340(ah)) 1283 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1284 else 1285 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1286 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1287 1288 if (tmpReg) { 1289 u32 val; 1290 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1291 1292 val = AR_RC_HOSTIF; 1293 if (!AR_SREV_9300_20_OR_LATER(ah)) 1294 val |= AR_RC_AHB; 1295 REG_WRITE(ah, AR_RC, val); 1296 1297 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1298 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1299 1300 rst_flags = AR_RTC_RC_MAC_WARM; 1301 if (type == ATH9K_RESET_COLD) 1302 rst_flags |= AR_RTC_RC_MAC_COLD; 1303 } 1304 1305 if (AR_SREV_9330(ah)) { 1306 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1307 return false; 1308 } 1309 1310 if (ath9k_hw_mci_is_enabled(ah)) 1311 ar9003_mci_check_gpm_offset(ah); 1312 1313 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1314 1315 REGWRITE_BUFFER_FLUSH(ah); 1316 1317 if (AR_SREV_9300_20_OR_LATER(ah)) 1318 udelay(50); 1319 else if (AR_SREV_9100(ah)) 1320 mdelay(10); 1321 else 1322 udelay(100); 1323 1324 REG_WRITE(ah, AR_RTC_RC, 0); 1325 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1326 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1327 return false; 1328 } 1329 1330 if (!AR_SREV_9100(ah)) 1331 REG_WRITE(ah, AR_RC, 0); 1332 1333 if (AR_SREV_9100(ah)) 1334 udelay(50); 1335 1336 return true; 1337 } 1338 1339 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1340 { 1341 ENABLE_REGWRITE_BUFFER(ah); 1342 1343 if (AR_SREV_9300_20_OR_LATER(ah)) { 1344 REG_WRITE(ah, AR_WA, ah->WARegVal); 1345 udelay(10); 1346 } 1347 1348 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1349 AR_RTC_FORCE_WAKE_ON_INT); 1350 1351 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1352 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1353 1354 REG_WRITE(ah, AR_RTC_RESET, 0); 1355 1356 REGWRITE_BUFFER_FLUSH(ah); 1357 1358 udelay(2); 1359 1360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1361 REG_WRITE(ah, AR_RC, 0); 1362 1363 REG_WRITE(ah, AR_RTC_RESET, 1); 1364 1365 if (!ath9k_hw_wait(ah, 1366 AR_RTC_STATUS, 1367 AR_RTC_STATUS_M, 1368 AR_RTC_STATUS_ON, 1369 AH_WAIT_TIMEOUT)) { 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1371 return false; 1372 } 1373 1374 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1375 } 1376 1377 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1378 { 1379 bool ret = false; 1380 1381 if (AR_SREV_9300_20_OR_LATER(ah)) { 1382 REG_WRITE(ah, AR_WA, ah->WARegVal); 1383 udelay(10); 1384 } 1385 1386 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1387 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1388 1389 if (!ah->reset_power_on) 1390 type = ATH9K_RESET_POWER_ON; 1391 1392 switch (type) { 1393 case ATH9K_RESET_POWER_ON: 1394 ret = ath9k_hw_set_reset_power_on(ah); 1395 if (ret) 1396 ah->reset_power_on = true; 1397 break; 1398 case ATH9K_RESET_WARM: 1399 case ATH9K_RESET_COLD: 1400 ret = ath9k_hw_set_reset(ah, type); 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 return ret; 1407 } 1408 1409 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1410 struct ath9k_channel *chan) 1411 { 1412 int reset_type = ATH9K_RESET_WARM; 1413 1414 if (AR_SREV_9280(ah)) { 1415 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1416 reset_type = ATH9K_RESET_POWER_ON; 1417 else 1418 reset_type = ATH9K_RESET_COLD; 1419 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1420 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1421 reset_type = ATH9K_RESET_COLD; 1422 1423 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1424 return false; 1425 1426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1427 return false; 1428 1429 ah->chip_fullsleep = false; 1430 1431 if (AR_SREV_9330(ah)) 1432 ar9003_hw_internal_regulator_apply(ah); 1433 ath9k_hw_init_pll(ah, chan); 1434 1435 return true; 1436 } 1437 1438 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1439 struct ath9k_channel *chan) 1440 { 1441 struct ath_common *common = ath9k_hw_common(ah); 1442 struct ath9k_hw_capabilities *pCap = &ah->caps; 1443 bool band_switch = false, mode_diff = false; 1444 u8 ini_reloaded = 0; 1445 u32 qnum; 1446 int r; 1447 1448 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1449 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1450 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1451 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1452 } 1453 1454 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1455 if (ath9k_hw_numtxpending(ah, qnum)) { 1456 ath_dbg(common, QUEUE, 1457 "Transmit frames pending on queue %d\n", qnum); 1458 return false; 1459 } 1460 } 1461 1462 if (!ath9k_hw_rfbus_req(ah)) { 1463 ath_err(common, "Could not kill baseband RX\n"); 1464 return false; 1465 } 1466 1467 if (band_switch || mode_diff) { 1468 ath9k_hw_mark_phy_inactive(ah); 1469 udelay(5); 1470 1471 if (band_switch) 1472 ath9k_hw_init_pll(ah, chan); 1473 1474 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1475 ath_err(common, "Failed to do fast channel change\n"); 1476 return false; 1477 } 1478 } 1479 1480 ath9k_hw_set_channel_regs(ah, chan); 1481 1482 r = ath9k_hw_rf_set_freq(ah, chan); 1483 if (r) { 1484 ath_err(common, "Failed to set channel\n"); 1485 return false; 1486 } 1487 ath9k_hw_set_clockrate(ah); 1488 ath9k_hw_apply_txpower(ah, chan, false); 1489 1490 ath9k_hw_set_delta_slope(ah, chan); 1491 ath9k_hw_spur_mitigate_freq(ah, chan); 1492 1493 if (band_switch || ini_reloaded) 1494 ah->eep_ops->set_board_values(ah, chan); 1495 1496 ath9k_hw_init_bb(ah, chan); 1497 ath9k_hw_rfbus_done(ah); 1498 1499 if (band_switch || ini_reloaded) { 1500 ah->ah_flags |= AH_FASTCC; 1501 ath9k_hw_init_cal(ah, chan); 1502 ah->ah_flags &= ~AH_FASTCC; 1503 } 1504 1505 return true; 1506 } 1507 1508 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1509 { 1510 u32 gpio_mask = ah->gpio_mask; 1511 int i; 1512 1513 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1514 if (!(gpio_mask & 1)) 1515 continue; 1516 1517 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1518 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1519 } 1520 } 1521 1522 void ath9k_hw_check_nav(struct ath_hw *ah) 1523 { 1524 struct ath_common *common = ath9k_hw_common(ah); 1525 u32 val; 1526 1527 val = REG_READ(ah, AR_NAV); 1528 if (val != 0xdeadbeef && val > 0x7fff) { 1529 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1530 REG_WRITE(ah, AR_NAV, 0); 1531 } 1532 } 1533 EXPORT_SYMBOL(ath9k_hw_check_nav); 1534 1535 bool ath9k_hw_check_alive(struct ath_hw *ah) 1536 { 1537 int count = 50; 1538 u32 reg, last_val; 1539 1540 if (AR_SREV_9300(ah)) 1541 return !ath9k_hw_detect_mac_hang(ah); 1542 1543 if (AR_SREV_9285_12_OR_LATER(ah)) 1544 return true; 1545 1546 last_val = REG_READ(ah, AR_OBS_BUS_1); 1547 do { 1548 reg = REG_READ(ah, AR_OBS_BUS_1); 1549 if (reg != last_val) 1550 return true; 1551 1552 udelay(1); 1553 last_val = reg; 1554 if ((reg & 0x7E7FFFEF) == 0x00702400) 1555 continue; 1556 1557 switch (reg & 0x7E000B00) { 1558 case 0x1E000000: 1559 case 0x52000B00: 1560 case 0x18000B00: 1561 continue; 1562 default: 1563 return true; 1564 } 1565 } while (count-- > 0); 1566 1567 return false; 1568 } 1569 EXPORT_SYMBOL(ath9k_hw_check_alive); 1570 1571 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1572 { 1573 /* Setup MFP options for CCMP */ 1574 if (AR_SREV_9280_20_OR_LATER(ah)) { 1575 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1576 * frames when constructing CCMP AAD. */ 1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1578 0xc7ff); 1579 ah->sw_mgmt_crypto = false; 1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1581 /* Disable hardware crypto for management frames */ 1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1583 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1585 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1586 ah->sw_mgmt_crypto = true; 1587 } else { 1588 ah->sw_mgmt_crypto = true; 1589 } 1590 } 1591 1592 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1593 u32 macStaId1, u32 saveDefAntenna) 1594 { 1595 struct ath_common *common = ath9k_hw_common(ah); 1596 1597 ENABLE_REGWRITE_BUFFER(ah); 1598 1599 REG_RMW(ah, AR_STA_ID1, macStaId1 1600 | AR_STA_ID1_RTS_USE_DEF 1601 | ah->sta_id1_defaults, 1602 ~AR_STA_ID1_SADH_MASK); 1603 ath_hw_setbssidmask(common); 1604 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1605 ath9k_hw_write_associd(ah); 1606 REG_WRITE(ah, AR_ISR, ~0); 1607 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1608 1609 REGWRITE_BUFFER_FLUSH(ah); 1610 1611 ath9k_hw_set_operating_mode(ah, ah->opmode); 1612 } 1613 1614 static void ath9k_hw_init_queues(struct ath_hw *ah) 1615 { 1616 int i; 1617 1618 ENABLE_REGWRITE_BUFFER(ah); 1619 1620 for (i = 0; i < AR_NUM_DCU; i++) 1621 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1622 1623 REGWRITE_BUFFER_FLUSH(ah); 1624 1625 ah->intr_txqs = 0; 1626 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1627 ath9k_hw_resettxqueue(ah, i); 1628 } 1629 1630 /* 1631 * For big endian systems turn on swapping for descriptors 1632 */ 1633 static void ath9k_hw_init_desc(struct ath_hw *ah) 1634 { 1635 struct ath_common *common = ath9k_hw_common(ah); 1636 1637 if (AR_SREV_9100(ah)) { 1638 u32 mask; 1639 mask = REG_READ(ah, AR_CFG); 1640 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1641 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1642 mask); 1643 } else { 1644 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1645 REG_WRITE(ah, AR_CFG, mask); 1646 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1647 REG_READ(ah, AR_CFG)); 1648 } 1649 } else { 1650 if (common->bus_ops->ath_bus_type == ATH_USB) { 1651 /* Configure AR9271 target WLAN */ 1652 if (AR_SREV_9271(ah)) 1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1654 else 1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1656 } 1657 #ifdef __BIG_ENDIAN 1658 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1659 AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1660 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1661 else 1662 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1663 #endif 1664 } 1665 } 1666 1667 /* 1668 * Fast channel change: 1669 * (Change synthesizer based on channel freq without resetting chip) 1670 */ 1671 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1672 { 1673 struct ath_common *common = ath9k_hw_common(ah); 1674 struct ath9k_hw_capabilities *pCap = &ah->caps; 1675 int ret; 1676 1677 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1678 goto fail; 1679 1680 if (ah->chip_fullsleep) 1681 goto fail; 1682 1683 if (!ah->curchan) 1684 goto fail; 1685 1686 if (chan->channel == ah->curchan->channel) 1687 goto fail; 1688 1689 if ((ah->curchan->channelFlags | chan->channelFlags) & 1690 (CHANNEL_HALF | CHANNEL_QUARTER)) 1691 goto fail; 1692 1693 /* 1694 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1695 */ 1696 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1697 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1698 goto fail; 1699 1700 if (!ath9k_hw_check_alive(ah)) 1701 goto fail; 1702 1703 /* 1704 * For AR9462, make sure that calibration data for 1705 * re-using are present. 1706 */ 1707 if (AR_SREV_9462(ah) && (ah->caldata && 1708 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1709 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1710 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1711 goto fail; 1712 1713 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1714 ah->curchan->channel, chan->channel); 1715 1716 ret = ath9k_hw_channel_change(ah, chan); 1717 if (!ret) 1718 goto fail; 1719 1720 if (ath9k_hw_mci_is_enabled(ah)) 1721 ar9003_mci_2g5g_switch(ah, false); 1722 1723 ath9k_hw_loadnf(ah, ah->curchan); 1724 ath9k_hw_start_nfcal(ah, true); 1725 1726 if (AR_SREV_9271(ah)) 1727 ar9002_hw_load_ani_reg(ah, chan); 1728 1729 return 0; 1730 fail: 1731 return -EINVAL; 1732 } 1733 1734 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1735 { 1736 struct timespec ts; 1737 s64 usec; 1738 1739 if (!cur) { 1740 getrawmonotonic(&ts); 1741 cur = &ts; 1742 } 1743 1744 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1745 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1746 1747 return (u32) usec; 1748 } 1749 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1750 1751 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1752 struct ath9k_hw_cal_data *caldata, bool fastcc) 1753 { 1754 struct ath_common *common = ath9k_hw_common(ah); 1755 u32 saveLedState; 1756 u32 saveDefAntenna; 1757 u32 macStaId1; 1758 u64 tsf = 0; 1759 s64 usec = 0; 1760 int r; 1761 bool start_mci_reset = false; 1762 bool save_fullsleep = ah->chip_fullsleep; 1763 1764 if (ath9k_hw_mci_is_enabled(ah)) { 1765 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1766 if (start_mci_reset) 1767 return 0; 1768 } 1769 1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1771 return -EIO; 1772 1773 if (ah->curchan && !ah->chip_fullsleep) 1774 ath9k_hw_getnf(ah, ah->curchan); 1775 1776 ah->caldata = caldata; 1777 if (caldata && (chan->channel != caldata->channel || 1778 chan->channelFlags != caldata->channelFlags)) { 1779 /* Operating channel changed, reset channel calibration data */ 1780 memset(caldata, 0, sizeof(*caldata)); 1781 ath9k_init_nfcal_hist_buffer(ah, chan); 1782 } else if (caldata) { 1783 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1784 } 1785 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1786 1787 if (fastcc) { 1788 r = ath9k_hw_do_fastcc(ah, chan); 1789 if (!r) 1790 return r; 1791 } 1792 1793 if (ath9k_hw_mci_is_enabled(ah)) 1794 ar9003_mci_stop_bt(ah, save_fullsleep); 1795 1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1797 if (saveDefAntenna == 0) 1798 saveDefAntenna = 1; 1799 1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1801 1802 /* Save TSF before chip reset, a cold reset clears it */ 1803 tsf = ath9k_hw_gettsf64(ah); 1804 usec = ktime_to_us(ktime_get_raw()); 1805 1806 saveLedState = REG_READ(ah, AR_CFG_LED) & 1807 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1808 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1809 1810 ath9k_hw_mark_phy_inactive(ah); 1811 1812 ah->paprd_table_write_done = false; 1813 1814 /* Only required on the first reset */ 1815 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1816 REG_WRITE(ah, 1817 AR9271_RESET_POWER_DOWN_CONTROL, 1818 AR9271_RADIO_RF_RST); 1819 udelay(50); 1820 } 1821 1822 if (!ath9k_hw_chip_reset(ah, chan)) { 1823 ath_err(common, "Chip reset failed\n"); 1824 return -EINVAL; 1825 } 1826 1827 /* Only required on the first reset */ 1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1829 ah->htc_reset_init = false; 1830 REG_WRITE(ah, 1831 AR9271_RESET_POWER_DOWN_CONTROL, 1832 AR9271_GATE_MAC_CTL); 1833 udelay(50); 1834 } 1835 1836 /* Restore TSF */ 1837 usec = ktime_to_us(ktime_get_raw()) - usec; 1838 ath9k_hw_settsf64(ah, tsf + usec); 1839 1840 if (AR_SREV_9280_20_OR_LATER(ah)) 1841 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1842 1843 if (!AR_SREV_9300_20_OR_LATER(ah)) 1844 ar9002_hw_enable_async_fifo(ah); 1845 1846 r = ath9k_hw_process_ini(ah, chan); 1847 if (r) 1848 return r; 1849 1850 ath9k_hw_set_rfmode(ah, chan); 1851 1852 if (ath9k_hw_mci_is_enabled(ah)) 1853 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1854 1855 /* 1856 * Some AR91xx SoC devices frequently fail to accept TSF writes 1857 * right after the chip reset. When that happens, write a new 1858 * value after the initvals have been applied, with an offset 1859 * based on measured time difference 1860 */ 1861 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1862 tsf += 1500; 1863 ath9k_hw_settsf64(ah, tsf); 1864 } 1865 1866 ath9k_hw_init_mfp(ah); 1867 1868 ath9k_hw_set_delta_slope(ah, chan); 1869 ath9k_hw_spur_mitigate_freq(ah, chan); 1870 ah->eep_ops->set_board_values(ah, chan); 1871 1872 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1873 1874 r = ath9k_hw_rf_set_freq(ah, chan); 1875 if (r) 1876 return r; 1877 1878 ath9k_hw_set_clockrate(ah); 1879 1880 ath9k_hw_init_queues(ah); 1881 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1882 ath9k_hw_ani_cache_ini_regs(ah); 1883 ath9k_hw_init_qos(ah); 1884 1885 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1886 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1887 1888 ath9k_hw_init_global_settings(ah); 1889 1890 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1891 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1892 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1893 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1894 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1895 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1896 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1897 } 1898 1899 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1900 1901 ath9k_hw_set_dma(ah); 1902 1903 if (!ath9k_hw_mci_is_enabled(ah)) 1904 REG_WRITE(ah, AR_OBS, 8); 1905 1906 if (ah->config.rx_intr_mitigation) { 1907 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1908 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1909 } 1910 1911 if (ah->config.tx_intr_mitigation) { 1912 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1913 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1914 } 1915 1916 ath9k_hw_init_bb(ah, chan); 1917 1918 if (caldata) { 1919 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1920 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1921 } 1922 if (!ath9k_hw_init_cal(ah, chan)) 1923 return -EIO; 1924 1925 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1926 return -EIO; 1927 1928 ENABLE_REGWRITE_BUFFER(ah); 1929 1930 ath9k_hw_restore_chainmask(ah); 1931 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1932 1933 REGWRITE_BUFFER_FLUSH(ah); 1934 1935 ath9k_hw_init_desc(ah); 1936 1937 if (ath9k_hw_btcoex_is_enabled(ah)) 1938 ath9k_hw_btcoex_enable(ah); 1939 1940 if (ath9k_hw_mci_is_enabled(ah)) 1941 ar9003_mci_check_bt(ah); 1942 1943 ath9k_hw_loadnf(ah, chan); 1944 ath9k_hw_start_nfcal(ah, true); 1945 1946 if (AR_SREV_9300_20_OR_LATER(ah)) 1947 ar9003_hw_bb_watchdog_config(ah); 1948 1949 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1950 ar9003_hw_disable_phy_restart(ah); 1951 1952 ath9k_hw_apply_gpio_override(ah); 1953 1954 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1955 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1956 1957 return 0; 1958 } 1959 EXPORT_SYMBOL(ath9k_hw_reset); 1960 1961 /******************************/ 1962 /* Power Management (Chipset) */ 1963 /******************************/ 1964 1965 /* 1966 * Notify Power Mgt is disabled in self-generated frames. 1967 * If requested, force chip to sleep. 1968 */ 1969 static void ath9k_set_power_sleep(struct ath_hw *ah) 1970 { 1971 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1972 1973 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1974 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 1975 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 1976 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 1977 /* xxx Required for WLAN only case ? */ 1978 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1979 udelay(100); 1980 } 1981 1982 /* 1983 * Clear the RTC force wake bit to allow the 1984 * mac to go to sleep. 1985 */ 1986 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1987 1988 if (ath9k_hw_mci_is_enabled(ah)) 1989 udelay(100); 1990 1991 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1992 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1993 1994 /* Shutdown chip. Active low */ 1995 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 1996 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1997 udelay(2); 1998 } 1999 2000 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2001 if (AR_SREV_9300_20_OR_LATER(ah)) 2002 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2003 } 2004 2005 /* 2006 * Notify Power Management is enabled in self-generating 2007 * frames. If request, set power mode of chip to 2008 * auto/normal. Duration in units of 128us (1/8 TU). 2009 */ 2010 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2011 { 2012 struct ath9k_hw_capabilities *pCap = &ah->caps; 2013 2014 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2015 2016 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2017 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2018 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2019 AR_RTC_FORCE_WAKE_ON_INT); 2020 } else { 2021 2022 /* When chip goes into network sleep, it could be waken 2023 * up by MCI_INT interrupt caused by BT's HW messages 2024 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2025 * rate (~100us). This will cause chip to leave and 2026 * re-enter network sleep mode frequently, which in 2027 * consequence will have WLAN MCI HW to generate lots of 2028 * SYS_WAKING and SYS_SLEEPING messages which will make 2029 * BT CPU to busy to process. 2030 */ 2031 if (ath9k_hw_mci_is_enabled(ah)) 2032 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2033 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2034 /* 2035 * Clear the RTC force wake bit to allow the 2036 * mac to go to sleep. 2037 */ 2038 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2039 2040 if (ath9k_hw_mci_is_enabled(ah)) 2041 udelay(30); 2042 } 2043 2044 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2045 if (AR_SREV_9300_20_OR_LATER(ah)) 2046 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2047 } 2048 2049 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2050 { 2051 u32 val; 2052 int i; 2053 2054 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2055 if (AR_SREV_9300_20_OR_LATER(ah)) { 2056 REG_WRITE(ah, AR_WA, ah->WARegVal); 2057 udelay(10); 2058 } 2059 2060 if ((REG_READ(ah, AR_RTC_STATUS) & 2061 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2062 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2063 return false; 2064 } 2065 if (!AR_SREV_9300_20_OR_LATER(ah)) 2066 ath9k_hw_init_pll(ah, NULL); 2067 } 2068 if (AR_SREV_9100(ah)) 2069 REG_SET_BIT(ah, AR_RTC_RESET, 2070 AR_RTC_RESET_EN); 2071 2072 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2073 AR_RTC_FORCE_WAKE_EN); 2074 if (AR_SREV_9100(ah)) 2075 mdelay(10); 2076 else 2077 udelay(50); 2078 2079 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2080 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2081 if (val == AR_RTC_STATUS_ON) 2082 break; 2083 udelay(50); 2084 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2085 AR_RTC_FORCE_WAKE_EN); 2086 } 2087 if (i == 0) { 2088 ath_err(ath9k_hw_common(ah), 2089 "Failed to wakeup in %uus\n", 2090 POWER_UP_TIME / 20); 2091 return false; 2092 } 2093 2094 if (ath9k_hw_mci_is_enabled(ah)) 2095 ar9003_mci_set_power_awake(ah); 2096 2097 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2098 2099 return true; 2100 } 2101 2102 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2103 { 2104 struct ath_common *common = ath9k_hw_common(ah); 2105 int status = true; 2106 static const char *modes[] = { 2107 "AWAKE", 2108 "FULL-SLEEP", 2109 "NETWORK SLEEP", 2110 "UNDEFINED" 2111 }; 2112 2113 if (ah->power_mode == mode) 2114 return status; 2115 2116 ath_dbg(common, RESET, "%s -> %s\n", 2117 modes[ah->power_mode], modes[mode]); 2118 2119 switch (mode) { 2120 case ATH9K_PM_AWAKE: 2121 status = ath9k_hw_set_power_awake(ah); 2122 break; 2123 case ATH9K_PM_FULL_SLEEP: 2124 if (ath9k_hw_mci_is_enabled(ah)) 2125 ar9003_mci_set_full_sleep(ah); 2126 2127 ath9k_set_power_sleep(ah); 2128 ah->chip_fullsleep = true; 2129 break; 2130 case ATH9K_PM_NETWORK_SLEEP: 2131 ath9k_set_power_network_sleep(ah); 2132 break; 2133 default: 2134 ath_err(common, "Unknown power mode %u\n", mode); 2135 return false; 2136 } 2137 ah->power_mode = mode; 2138 2139 /* 2140 * XXX: If this warning never comes up after a while then 2141 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2142 * ath9k_hw_setpower() return type void. 2143 */ 2144 2145 if (!(ah->ah_flags & AH_UNPLUGGED)) 2146 ATH_DBG_WARN_ON_ONCE(!status); 2147 2148 return status; 2149 } 2150 EXPORT_SYMBOL(ath9k_hw_setpower); 2151 2152 /*******************/ 2153 /* Beacon Handling */ 2154 /*******************/ 2155 2156 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2157 { 2158 int flags = 0; 2159 2160 ENABLE_REGWRITE_BUFFER(ah); 2161 2162 switch (ah->opmode) { 2163 case NL80211_IFTYPE_ADHOC: 2164 REG_SET_BIT(ah, AR_TXCFG, 2165 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2166 case NL80211_IFTYPE_MESH_POINT: 2167 case NL80211_IFTYPE_AP: 2168 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2169 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2170 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2171 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2172 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2173 flags |= 2174 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2175 break; 2176 default: 2177 ath_dbg(ath9k_hw_common(ah), BEACON, 2178 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2179 return; 2180 break; 2181 } 2182 2183 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2184 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2185 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2186 2187 REGWRITE_BUFFER_FLUSH(ah); 2188 2189 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2190 } 2191 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2192 2193 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2194 const struct ath9k_beacon_state *bs) 2195 { 2196 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2197 struct ath9k_hw_capabilities *pCap = &ah->caps; 2198 struct ath_common *common = ath9k_hw_common(ah); 2199 2200 ENABLE_REGWRITE_BUFFER(ah); 2201 2202 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2203 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2204 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2205 2206 REGWRITE_BUFFER_FLUSH(ah); 2207 2208 REG_RMW_FIELD(ah, AR_RSSI_THR, 2209 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2210 2211 beaconintval = bs->bs_intval; 2212 2213 if (bs->bs_sleepduration > beaconintval) 2214 beaconintval = bs->bs_sleepduration; 2215 2216 dtimperiod = bs->bs_dtimperiod; 2217 if (bs->bs_sleepduration > dtimperiod) 2218 dtimperiod = bs->bs_sleepduration; 2219 2220 if (beaconintval == dtimperiod) 2221 nextTbtt = bs->bs_nextdtim; 2222 else 2223 nextTbtt = bs->bs_nexttbtt; 2224 2225 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2226 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2227 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2228 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2229 2230 ENABLE_REGWRITE_BUFFER(ah); 2231 2232 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2233 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2234 2235 REG_WRITE(ah, AR_SLEEP1, 2236 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2237 | AR_SLEEP1_ASSUME_DTIM); 2238 2239 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2240 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2241 else 2242 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2243 2244 REG_WRITE(ah, AR_SLEEP2, 2245 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2246 2247 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2248 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2249 2250 REGWRITE_BUFFER_FLUSH(ah); 2251 2252 REG_SET_BIT(ah, AR_TIMER_MODE, 2253 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2254 AR_DTIM_TIMER_EN); 2255 2256 /* TSF Out of Range Threshold */ 2257 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2258 } 2259 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2260 2261 /*******************/ 2262 /* HW Capabilities */ 2263 /*******************/ 2264 2265 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2266 { 2267 eeprom_chainmask &= chip_chainmask; 2268 if (eeprom_chainmask) 2269 return eeprom_chainmask; 2270 else 2271 return chip_chainmask; 2272 } 2273 2274 /** 2275 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2276 * @ah: the atheros hardware data structure 2277 * 2278 * We enable DFS support upstream on chipsets which have passed a series 2279 * of tests. The testing requirements are going to be documented. Desired 2280 * test requirements are documented at: 2281 * 2282 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2283 * 2284 * Once a new chipset gets properly tested an individual commit can be used 2285 * to document the testing for DFS for that chipset. 2286 */ 2287 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2288 { 2289 2290 switch (ah->hw_version.macVersion) { 2291 /* for temporary testing DFS with 9280 */ 2292 case AR_SREV_VERSION_9280: 2293 /* AR9580 will likely be our first target to get testing on */ 2294 case AR_SREV_VERSION_9580: 2295 return true; 2296 default: 2297 return false; 2298 } 2299 } 2300 2301 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2302 { 2303 struct ath9k_hw_capabilities *pCap = &ah->caps; 2304 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2305 struct ath_common *common = ath9k_hw_common(ah); 2306 unsigned int chip_chainmask; 2307 2308 u16 eeval; 2309 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2310 2311 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2312 regulatory->current_rd = eeval; 2313 2314 if (ah->opmode != NL80211_IFTYPE_AP && 2315 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2316 if (regulatory->current_rd == 0x64 || 2317 regulatory->current_rd == 0x65) 2318 regulatory->current_rd += 5; 2319 else if (regulatory->current_rd == 0x41) 2320 regulatory->current_rd = 0x43; 2321 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2322 regulatory->current_rd); 2323 } 2324 2325 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2326 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2327 ath_err(common, 2328 "no band has been marked as supported in EEPROM\n"); 2329 return -EINVAL; 2330 } 2331 2332 if (eeval & AR5416_OPFLAGS_11A) 2333 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2334 2335 if (eeval & AR5416_OPFLAGS_11G) 2336 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2337 2338 if (AR_SREV_9485(ah) || 2339 AR_SREV_9285(ah) || 2340 AR_SREV_9330(ah) || 2341 AR_SREV_9565(ah)) 2342 chip_chainmask = 1; 2343 else if (AR_SREV_9462(ah)) 2344 chip_chainmask = 3; 2345 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2346 chip_chainmask = 7; 2347 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2348 chip_chainmask = 3; 2349 else 2350 chip_chainmask = 7; 2351 2352 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2353 /* 2354 * For AR9271 we will temporarilly uses the rx chainmax as read from 2355 * the EEPROM. 2356 */ 2357 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2358 !(eeval & AR5416_OPFLAGS_11A) && 2359 !(AR_SREV_9271(ah))) 2360 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2361 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2362 else if (AR_SREV_9100(ah)) 2363 pCap->rx_chainmask = 0x7; 2364 else 2365 /* Use rx_chainmask from EEPROM. */ 2366 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2367 2368 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2369 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2370 ah->txchainmask = pCap->tx_chainmask; 2371 ah->rxchainmask = pCap->rx_chainmask; 2372 2373 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2374 2375 /* enable key search for every frame in an aggregate */ 2376 if (AR_SREV_9300_20_OR_LATER(ah)) 2377 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2378 2379 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2380 2381 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2382 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2383 else 2384 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2385 2386 if (AR_SREV_9271(ah)) 2387 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2388 else if (AR_DEVID_7010(ah)) 2389 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2390 else if (AR_SREV_9300_20_OR_LATER(ah)) 2391 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2392 else if (AR_SREV_9287_11_OR_LATER(ah)) 2393 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2394 else if (AR_SREV_9285_12_OR_LATER(ah)) 2395 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2396 else if (AR_SREV_9280_20_OR_LATER(ah)) 2397 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2398 else 2399 pCap->num_gpio_pins = AR_NUM_GPIO; 2400 2401 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2402 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2403 else 2404 pCap->rts_aggr_limit = (8 * 1024); 2405 2406 #ifdef CONFIG_ATH9K_RFKILL 2407 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2408 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2409 ah->rfkill_gpio = 2410 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2411 ah->rfkill_polarity = 2412 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2413 2414 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2415 } 2416 #endif 2417 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2418 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2419 else 2420 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2421 2422 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2423 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2424 else 2425 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2426 2427 if (AR_SREV_9300_20_OR_LATER(ah)) { 2428 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2429 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2430 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2431 2432 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2433 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2434 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2435 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2436 pCap->txs_len = sizeof(struct ar9003_txs); 2437 } else { 2438 pCap->tx_desc_len = sizeof(struct ath_desc); 2439 if (AR_SREV_9280_20(ah)) 2440 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2441 } 2442 2443 if (AR_SREV_9300_20_OR_LATER(ah)) 2444 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2445 2446 if (AR_SREV_9300_20_OR_LATER(ah)) 2447 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2448 2449 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2450 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2451 2452 if (AR_SREV_9285(ah)) { 2453 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2454 ant_div_ctl1 = 2455 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2456 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2457 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2458 ath_info(common, "Enable LNA combining\n"); 2459 } 2460 } 2461 } 2462 2463 if (AR_SREV_9300_20_OR_LATER(ah)) { 2464 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2465 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2466 } 2467 2468 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2469 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2470 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2471 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2472 ath_info(common, "Enable LNA combining\n"); 2473 } 2474 } 2475 2476 if (ath9k_hw_dfs_tested(ah)) 2477 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2478 2479 tx_chainmask = pCap->tx_chainmask; 2480 rx_chainmask = pCap->rx_chainmask; 2481 while (tx_chainmask || rx_chainmask) { 2482 if (tx_chainmask & BIT(0)) 2483 pCap->max_txchains++; 2484 if (rx_chainmask & BIT(0)) 2485 pCap->max_rxchains++; 2486 2487 tx_chainmask >>= 1; 2488 rx_chainmask >>= 1; 2489 } 2490 2491 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2492 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2493 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2494 2495 if (AR_SREV_9462_20_OR_LATER(ah)) 2496 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2497 } 2498 2499 if (AR_SREV_9462(ah)) 2500 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2501 2502 if (AR_SREV_9300_20_OR_LATER(ah) && 2503 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2504 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2505 2506 return 0; 2507 } 2508 2509 /****************************/ 2510 /* GPIO / RFKILL / Antennae */ 2511 /****************************/ 2512 2513 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2514 u32 gpio, u32 type) 2515 { 2516 int addr; 2517 u32 gpio_shift, tmp; 2518 2519 if (gpio > 11) 2520 addr = AR_GPIO_OUTPUT_MUX3; 2521 else if (gpio > 5) 2522 addr = AR_GPIO_OUTPUT_MUX2; 2523 else 2524 addr = AR_GPIO_OUTPUT_MUX1; 2525 2526 gpio_shift = (gpio % 6) * 5; 2527 2528 if (AR_SREV_9280_20_OR_LATER(ah) 2529 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2530 REG_RMW(ah, addr, (type << gpio_shift), 2531 (0x1f << gpio_shift)); 2532 } else { 2533 tmp = REG_READ(ah, addr); 2534 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2535 tmp &= ~(0x1f << gpio_shift); 2536 tmp |= (type << gpio_shift); 2537 REG_WRITE(ah, addr, tmp); 2538 } 2539 } 2540 2541 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2542 { 2543 u32 gpio_shift; 2544 2545 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2546 2547 if (AR_DEVID_7010(ah)) { 2548 gpio_shift = gpio; 2549 REG_RMW(ah, AR7010_GPIO_OE, 2550 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2551 (AR7010_GPIO_OE_MASK << gpio_shift)); 2552 return; 2553 } 2554 2555 gpio_shift = gpio << 1; 2556 REG_RMW(ah, 2557 AR_GPIO_OE_OUT, 2558 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2559 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2560 } 2561 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2562 2563 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2564 { 2565 #define MS_REG_READ(x, y) \ 2566 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2567 2568 if (gpio >= ah->caps.num_gpio_pins) 2569 return 0xffffffff; 2570 2571 if (AR_DEVID_7010(ah)) { 2572 u32 val; 2573 val = REG_READ(ah, AR7010_GPIO_IN); 2574 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2575 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2576 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2577 AR_GPIO_BIT(gpio)) != 0; 2578 else if (AR_SREV_9271(ah)) 2579 return MS_REG_READ(AR9271, gpio) != 0; 2580 else if (AR_SREV_9287_11_OR_LATER(ah)) 2581 return MS_REG_READ(AR9287, gpio) != 0; 2582 else if (AR_SREV_9285_12_OR_LATER(ah)) 2583 return MS_REG_READ(AR9285, gpio) != 0; 2584 else if (AR_SREV_9280_20_OR_LATER(ah)) 2585 return MS_REG_READ(AR928X, gpio) != 0; 2586 else 2587 return MS_REG_READ(AR, gpio) != 0; 2588 } 2589 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2590 2591 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2592 u32 ah_signal_type) 2593 { 2594 u32 gpio_shift; 2595 2596 if (AR_DEVID_7010(ah)) { 2597 gpio_shift = gpio; 2598 REG_RMW(ah, AR7010_GPIO_OE, 2599 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2600 (AR7010_GPIO_OE_MASK << gpio_shift)); 2601 return; 2602 } 2603 2604 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2605 gpio_shift = 2 * gpio; 2606 REG_RMW(ah, 2607 AR_GPIO_OE_OUT, 2608 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2609 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2610 } 2611 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2612 2613 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2614 { 2615 if (AR_DEVID_7010(ah)) { 2616 val = val ? 0 : 1; 2617 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2618 AR_GPIO_BIT(gpio)); 2619 return; 2620 } 2621 2622 if (AR_SREV_9271(ah)) 2623 val = ~val; 2624 2625 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2626 AR_GPIO_BIT(gpio)); 2627 } 2628 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2629 2630 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2631 { 2632 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2633 } 2634 EXPORT_SYMBOL(ath9k_hw_setantenna); 2635 2636 /*********************/ 2637 /* General Operation */ 2638 /*********************/ 2639 2640 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2641 { 2642 u32 bits = REG_READ(ah, AR_RX_FILTER); 2643 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2644 2645 if (phybits & AR_PHY_ERR_RADAR) 2646 bits |= ATH9K_RX_FILTER_PHYRADAR; 2647 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2648 bits |= ATH9K_RX_FILTER_PHYERR; 2649 2650 return bits; 2651 } 2652 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2653 2654 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2655 { 2656 u32 phybits; 2657 2658 ENABLE_REGWRITE_BUFFER(ah); 2659 2660 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2661 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2662 2663 REG_WRITE(ah, AR_RX_FILTER, bits); 2664 2665 phybits = 0; 2666 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2667 phybits |= AR_PHY_ERR_RADAR; 2668 if (bits & ATH9K_RX_FILTER_PHYERR) 2669 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2670 REG_WRITE(ah, AR_PHY_ERR, phybits); 2671 2672 if (phybits) 2673 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2674 else 2675 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2676 2677 REGWRITE_BUFFER_FLUSH(ah); 2678 } 2679 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2680 2681 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2682 { 2683 if (ath9k_hw_mci_is_enabled(ah)) 2684 ar9003_mci_bt_gain_ctrl(ah); 2685 2686 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2687 return false; 2688 2689 ath9k_hw_init_pll(ah, NULL); 2690 ah->htc_reset_init = true; 2691 return true; 2692 } 2693 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2694 2695 bool ath9k_hw_disable(struct ath_hw *ah) 2696 { 2697 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2698 return false; 2699 2700 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2701 return false; 2702 2703 ath9k_hw_init_pll(ah, NULL); 2704 return true; 2705 } 2706 EXPORT_SYMBOL(ath9k_hw_disable); 2707 2708 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2709 { 2710 enum eeprom_param gain_param; 2711 2712 if (IS_CHAN_2GHZ(chan)) 2713 gain_param = EEP_ANTENNA_GAIN_2G; 2714 else 2715 gain_param = EEP_ANTENNA_GAIN_5G; 2716 2717 return ah->eep_ops->get_eeprom(ah, gain_param); 2718 } 2719 2720 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2721 bool test) 2722 { 2723 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2724 struct ieee80211_channel *channel; 2725 int chan_pwr, new_pwr, max_gain; 2726 int ant_gain, ant_reduction = 0; 2727 2728 if (!chan) 2729 return; 2730 2731 channel = chan->chan; 2732 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2733 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2734 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2735 2736 ant_gain = get_antenna_gain(ah, chan); 2737 if (ant_gain > max_gain) 2738 ant_reduction = ant_gain - max_gain; 2739 2740 ah->eep_ops->set_txpower(ah, chan, 2741 ath9k_regd_get_ctl(reg, chan), 2742 ant_reduction, new_pwr, test); 2743 } 2744 2745 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2746 { 2747 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2748 struct ath9k_channel *chan = ah->curchan; 2749 struct ieee80211_channel *channel = chan->chan; 2750 2751 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2752 if (test) 2753 channel->max_power = MAX_RATE_POWER / 2; 2754 2755 ath9k_hw_apply_txpower(ah, chan, test); 2756 2757 if (test) 2758 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2759 } 2760 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2761 2762 void ath9k_hw_setopmode(struct ath_hw *ah) 2763 { 2764 ath9k_hw_set_operating_mode(ah, ah->opmode); 2765 } 2766 EXPORT_SYMBOL(ath9k_hw_setopmode); 2767 2768 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2769 { 2770 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2771 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2772 } 2773 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2774 2775 void ath9k_hw_write_associd(struct ath_hw *ah) 2776 { 2777 struct ath_common *common = ath9k_hw_common(ah); 2778 2779 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2780 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2781 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2782 } 2783 EXPORT_SYMBOL(ath9k_hw_write_associd); 2784 2785 #define ATH9K_MAX_TSF_READ 10 2786 2787 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2788 { 2789 u32 tsf_lower, tsf_upper1, tsf_upper2; 2790 int i; 2791 2792 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2793 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2794 tsf_lower = REG_READ(ah, AR_TSF_L32); 2795 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2796 if (tsf_upper2 == tsf_upper1) 2797 break; 2798 tsf_upper1 = tsf_upper2; 2799 } 2800 2801 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2802 2803 return (((u64)tsf_upper1 << 32) | tsf_lower); 2804 } 2805 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2806 2807 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2808 { 2809 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2810 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2811 } 2812 EXPORT_SYMBOL(ath9k_hw_settsf64); 2813 2814 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2815 { 2816 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2817 AH_TSF_WRITE_TIMEOUT)) 2818 ath_dbg(ath9k_hw_common(ah), RESET, 2819 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2820 2821 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2822 } 2823 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2824 2825 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2826 { 2827 if (set) 2828 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2829 else 2830 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2831 } 2832 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2833 2834 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2835 { 2836 u32 macmode; 2837 2838 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2839 macmode = AR_2040_JOINED_RX_CLEAR; 2840 else 2841 macmode = 0; 2842 2843 REG_WRITE(ah, AR_2040_MODE, macmode); 2844 } 2845 2846 /* HW Generic timers configuration */ 2847 2848 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2849 { 2850 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2851 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2852 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2853 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2854 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2855 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2856 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2858 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2859 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2860 AR_NDP2_TIMER_MODE, 0x0002}, 2861 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2862 AR_NDP2_TIMER_MODE, 0x0004}, 2863 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2864 AR_NDP2_TIMER_MODE, 0x0008}, 2865 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2866 AR_NDP2_TIMER_MODE, 0x0010}, 2867 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2868 AR_NDP2_TIMER_MODE, 0x0020}, 2869 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2870 AR_NDP2_TIMER_MODE, 0x0040}, 2871 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2872 AR_NDP2_TIMER_MODE, 0x0080} 2873 }; 2874 2875 /* HW generic timer primitives */ 2876 2877 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2878 { 2879 return REG_READ(ah, AR_TSF_L32); 2880 } 2881 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2882 2883 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2884 void (*trigger)(void *), 2885 void (*overflow)(void *), 2886 void *arg, 2887 u8 timer_index) 2888 { 2889 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2890 struct ath_gen_timer *timer; 2891 2892 if ((timer_index < AR_FIRST_NDP_TIMER) || 2893 (timer_index >= ATH_MAX_GEN_TIMER)) 2894 return NULL; 2895 2896 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2897 if (timer == NULL) 2898 return NULL; 2899 2900 /* allocate a hardware generic timer slot */ 2901 timer_table->timers[timer_index] = timer; 2902 timer->index = timer_index; 2903 timer->trigger = trigger; 2904 timer->overflow = overflow; 2905 timer->arg = arg; 2906 2907 return timer; 2908 } 2909 EXPORT_SYMBOL(ath_gen_timer_alloc); 2910 2911 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2912 struct ath_gen_timer *timer, 2913 u32 timer_next, 2914 u32 timer_period) 2915 { 2916 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2917 u32 mask = 0; 2918 2919 timer_table->timer_mask |= BIT(timer->index); 2920 2921 /* 2922 * Program generic timer registers 2923 */ 2924 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2925 timer_next); 2926 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2927 timer_period); 2928 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2929 gen_tmr_configuration[timer->index].mode_mask); 2930 2931 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2932 /* 2933 * Starting from AR9462, each generic timer can select which tsf 2934 * to use. But we still follow the old rule, 0 - 7 use tsf and 2935 * 8 - 15 use tsf2. 2936 */ 2937 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2938 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2939 (1 << timer->index)); 2940 else 2941 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2942 (1 << timer->index)); 2943 } 2944 2945 if (timer->trigger) 2946 mask |= SM(AR_GENTMR_BIT(timer->index), 2947 AR_IMR_S5_GENTIMER_TRIG); 2948 if (timer->overflow) 2949 mask |= SM(AR_GENTMR_BIT(timer->index), 2950 AR_IMR_S5_GENTIMER_THRESH); 2951 2952 REG_SET_BIT(ah, AR_IMR_S5, mask); 2953 2954 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 2955 ah->imask |= ATH9K_INT_GENTIMER; 2956 ath9k_hw_set_interrupts(ah); 2957 } 2958 } 2959 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2960 2961 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2962 { 2963 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2964 2965 /* Clear generic timer enable bits. */ 2966 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2967 gen_tmr_configuration[timer->index].mode_mask); 2968 2969 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2970 /* 2971 * Need to switch back to TSF if it was using TSF2. 2972 */ 2973 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 2974 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2975 (1 << timer->index)); 2976 } 2977 } 2978 2979 /* Disable both trigger and thresh interrupt masks */ 2980 REG_CLR_BIT(ah, AR_IMR_S5, 2981 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2982 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2983 2984 timer_table->timer_mask &= ~BIT(timer->index); 2985 2986 if (timer_table->timer_mask == 0) { 2987 ah->imask &= ~ATH9K_INT_GENTIMER; 2988 ath9k_hw_set_interrupts(ah); 2989 } 2990 } 2991 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2992 2993 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2994 { 2995 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2996 2997 /* free the hardware generic timer slot */ 2998 timer_table->timers[timer->index] = NULL; 2999 kfree(timer); 3000 } 3001 EXPORT_SYMBOL(ath_gen_timer_free); 3002 3003 /* 3004 * Generic Timer Interrupts handling 3005 */ 3006 void ath_gen_timer_isr(struct ath_hw *ah) 3007 { 3008 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3009 struct ath_gen_timer *timer; 3010 unsigned long trigger_mask, thresh_mask; 3011 unsigned int index; 3012 3013 /* get hardware generic timer interrupt status */ 3014 trigger_mask = ah->intr_gen_timer_trigger; 3015 thresh_mask = ah->intr_gen_timer_thresh; 3016 trigger_mask &= timer_table->timer_mask; 3017 thresh_mask &= timer_table->timer_mask; 3018 3019 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3020 timer = timer_table->timers[index]; 3021 if (!timer) 3022 continue; 3023 if (!timer->overflow) 3024 continue; 3025 3026 trigger_mask &= ~BIT(index); 3027 timer->overflow(timer->arg); 3028 } 3029 3030 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3031 timer = timer_table->timers[index]; 3032 if (!timer) 3033 continue; 3034 if (!timer->trigger) 3035 continue; 3036 timer->trigger(timer->arg); 3037 } 3038 } 3039 EXPORT_SYMBOL(ath_gen_timer_isr); 3040 3041 /********/ 3042 /* HTC */ 3043 /********/ 3044 3045 static struct { 3046 u32 version; 3047 const char * name; 3048 } ath_mac_bb_names[] = { 3049 /* Devices with external radios */ 3050 { AR_SREV_VERSION_5416_PCI, "5416" }, 3051 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3052 { AR_SREV_VERSION_9100, "9100" }, 3053 { AR_SREV_VERSION_9160, "9160" }, 3054 /* Single-chip solutions */ 3055 { AR_SREV_VERSION_9280, "9280" }, 3056 { AR_SREV_VERSION_9285, "9285" }, 3057 { AR_SREV_VERSION_9287, "9287" }, 3058 { AR_SREV_VERSION_9271, "9271" }, 3059 { AR_SREV_VERSION_9300, "9300" }, 3060 { AR_SREV_VERSION_9330, "9330" }, 3061 { AR_SREV_VERSION_9340, "9340" }, 3062 { AR_SREV_VERSION_9485, "9485" }, 3063 { AR_SREV_VERSION_9462, "9462" }, 3064 { AR_SREV_VERSION_9550, "9550" }, 3065 { AR_SREV_VERSION_9565, "9565" }, 3066 { AR_SREV_VERSION_9531, "9531" }, 3067 }; 3068 3069 /* For devices with external radios */ 3070 static struct { 3071 u16 version; 3072 const char * name; 3073 } ath_rf_names[] = { 3074 { 0, "5133" }, 3075 { AR_RAD5133_SREV_MAJOR, "5133" }, 3076 { AR_RAD5122_SREV_MAJOR, "5122" }, 3077 { AR_RAD2133_SREV_MAJOR, "2133" }, 3078 { AR_RAD2122_SREV_MAJOR, "2122" } 3079 }; 3080 3081 /* 3082 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3083 */ 3084 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3085 { 3086 int i; 3087 3088 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3089 if (ath_mac_bb_names[i].version == mac_bb_version) { 3090 return ath_mac_bb_names[i].name; 3091 } 3092 } 3093 3094 return "????"; 3095 } 3096 3097 /* 3098 * Return the RF name. "????" is returned if the RF is unknown. 3099 * Used for devices with external radios. 3100 */ 3101 static const char *ath9k_hw_rf_name(u16 rf_version) 3102 { 3103 int i; 3104 3105 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3106 if (ath_rf_names[i].version == rf_version) { 3107 return ath_rf_names[i].name; 3108 } 3109 } 3110 3111 return "????"; 3112 } 3113 3114 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3115 { 3116 int used; 3117 3118 /* chipsets >= AR9280 are single-chip */ 3119 if (AR_SREV_9280_20_OR_LATER(ah)) { 3120 used = scnprintf(hw_name, len, 3121 "Atheros AR%s Rev:%x", 3122 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3123 ah->hw_version.macRev); 3124 } 3125 else { 3126 used = scnprintf(hw_name, len, 3127 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3128 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3129 ah->hw_version.macRev, 3130 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3131 & AR_RADIO_SREV_MAJOR)), 3132 ah->hw_version.phyRev); 3133 } 3134 3135 hw_name[used] = '\0'; 3136 } 3137 EXPORT_SYMBOL(ath9k_hw_name); 3138