1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <linux/gpio.h> 24 #include <asm/unaligned.h> 25 26 #include "hw.h" 27 #include "hw-ops.h" 28 #include "ar9003_mac.h" 29 #include "ar9003_mci.h" 30 #include "ar9003_phy.h" 31 #include "ath9k.h" 32 33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 41 { 42 struct ath_common *common = ath9k_hw_common(ah); 43 struct ath9k_channel *chan = ah->curchan; 44 unsigned int clockrate; 45 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 48 clockrate = 117; 49 else if (!chan) /* should really check for CCK instead */ 50 clockrate = ATH9K_CLOCK_RATE_CCK; 51 else if (IS_CHAN_2GHZ(chan)) 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 55 else 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 57 58 if (chan) { 59 if (IS_CHAN_HT40(chan)) 60 clockrate *= 2; 61 if (IS_CHAN_HALF_RATE(chan)) 62 clockrate /= 2; 63 if (IS_CHAN_QUARTER_RATE(chan)) 64 clockrate /= 4; 65 } 66 67 common->clockrate = clockrate; 68 } 69 70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 71 { 72 struct ath_common *common = ath9k_hw_common(ah); 73 74 return usecs * common->clockrate; 75 } 76 77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 78 { 79 int i; 80 81 BUG_ON(timeout < AH_TIME_QUANTUM); 82 83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 84 if ((REG_READ(ah, reg) & mask) == val) 85 return true; 86 87 udelay(AH_TIME_QUANTUM); 88 } 89 90 ath_dbg(ath9k_hw_common(ah), ANY, 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 92 timeout, reg, REG_READ(ah, reg), mask, val); 93 94 return false; 95 } 96 EXPORT_SYMBOL(ath9k_hw_wait); 97 98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 99 int hw_delay) 100 { 101 hw_delay /= 10; 102 103 if (IS_CHAN_HALF_RATE(chan)) 104 hw_delay *= 2; 105 else if (IS_CHAN_QUARTER_RATE(chan)) 106 hw_delay *= 4; 107 108 udelay(hw_delay + BASE_ACTIVATE_DELAY); 109 } 110 111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 112 int column, unsigned int *writecnt) 113 { 114 int r; 115 116 ENABLE_REGWRITE_BUFFER(ah); 117 for (r = 0; r < array->ia_rows; r++) { 118 REG_WRITE(ah, INI_RA(array, r, 0), 119 INI_RA(array, r, column)); 120 DO_DELAY(*writecnt); 121 } 122 REGWRITE_BUFFER_FLUSH(ah); 123 } 124 125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) 126 { 127 u32 *tmp_reg_list, *tmp_data; 128 int i; 129 130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL); 131 if (!tmp_reg_list) { 132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); 133 return; 134 } 135 136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL); 137 if (!tmp_data) { 138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); 139 goto error_tmp_data; 140 } 141 142 for (i = 0; i < size; i++) 143 tmp_reg_list[i] = array[i][0]; 144 145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); 146 147 for (i = 0; i < size; i++) 148 array[i][1] = tmp_data[i]; 149 150 kfree(tmp_data); 151 error_tmp_data: 152 kfree(tmp_reg_list); 153 } 154 155 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 156 { 157 u32 retval; 158 int i; 159 160 for (i = 0, retval = 0; i < n; i++) { 161 retval = (retval << 1) | (val & 1); 162 val >>= 1; 163 } 164 return retval; 165 } 166 167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 168 u8 phy, int kbps, 169 u32 frameLen, u16 rateix, 170 bool shortPreamble) 171 { 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 173 174 if (kbps == 0) 175 return 0; 176 177 switch (phy) { 178 case WLAN_RC_PHY_CCK: 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 180 if (shortPreamble) 181 phyTime >>= 1; 182 numBits = frameLen << 3; 183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 184 break; 185 case WLAN_RC_PHY_OFDM: 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 188 numBits = OFDM_PLCP_BITS + (frameLen << 3); 189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 190 txTime = OFDM_SIFS_TIME_QUARTER 191 + OFDM_PREAMBLE_TIME_QUARTER 192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 193 } else if (ah->curchan && 194 IS_CHAN_HALF_RATE(ah->curchan)) { 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 196 numBits = OFDM_PLCP_BITS + (frameLen << 3); 197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 198 txTime = OFDM_SIFS_TIME_HALF + 199 OFDM_PREAMBLE_TIME_HALF 200 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 201 } else { 202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 203 numBits = OFDM_PLCP_BITS + (frameLen << 3); 204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 206 + (numSymbols * OFDM_SYMBOL_TIME); 207 } 208 break; 209 default: 210 ath_err(ath9k_hw_common(ah), 211 "Unknown phy %u (rate ix %u)\n", phy, rateix); 212 txTime = 0; 213 break; 214 } 215 216 return txTime; 217 } 218 EXPORT_SYMBOL(ath9k_hw_computetxtime); 219 220 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 221 struct ath9k_channel *chan, 222 struct chan_centers *centers) 223 { 224 int8_t extoff; 225 226 if (!IS_CHAN_HT40(chan)) { 227 centers->ctl_center = centers->ext_center = 228 centers->synth_center = chan->channel; 229 return; 230 } 231 232 if (IS_CHAN_HT40PLUS(chan)) { 233 centers->synth_center = 234 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 235 extoff = 1; 236 } else { 237 centers->synth_center = 238 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 239 extoff = -1; 240 } 241 242 centers->ctl_center = 243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 244 /* 25 MHz spacing is supported by hw but not on upper layers */ 245 centers->ext_center = 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 247 } 248 249 /******************/ 250 /* Chip Revisions */ 251 /******************/ 252 253 static void ath9k_hw_read_revisions(struct ath_hw *ah) 254 { 255 u32 val; 256 257 if (ah->get_mac_revision) 258 ah->hw_version.macRev = ah->get_mac_revision(); 259 260 switch (ah->hw_version.devid) { 261 case AR5416_AR9100_DEVID: 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 263 break; 264 case AR9300_DEVID_AR9330: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 266 if (!ah->get_mac_revision) { 267 val = REG_READ(ah, AR_SREV); 268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 269 } 270 return; 271 case AR9300_DEVID_AR9340: 272 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 273 return; 274 case AR9300_DEVID_QCA955X: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 276 return; 277 case AR9300_DEVID_AR953X: 278 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 279 return; 280 case AR9300_DEVID_QCA956X: 281 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 282 return; 283 } 284 285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 286 287 if (val == 0xFF) { 288 val = REG_READ(ah, AR_SREV); 289 ah->hw_version.macVersion = 290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 292 293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 294 ah->is_pciexpress = true; 295 else 296 ah->is_pciexpress = (val & 297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 298 } else { 299 if (!AR_SREV_9100(ah)) 300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 301 302 ah->hw_version.macRev = val & AR_SREV_REVISION; 303 304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 305 ah->is_pciexpress = true; 306 } 307 } 308 309 /************************************/ 310 /* HW Attach, Detach, Init Routines */ 311 /************************************/ 312 313 static void ath9k_hw_disablepcie(struct ath_hw *ah) 314 { 315 if (!AR_SREV_5416(ah)) 316 return; 317 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 327 328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 329 } 330 331 /* This should work for all families including legacy */ 332 static bool ath9k_hw_chip_test(struct ath_hw *ah) 333 { 334 struct ath_common *common = ath9k_hw_common(ah); 335 u32 regAddr[2] = { AR_STA_ID0 }; 336 u32 regHold[2]; 337 static const u32 patternData[4] = { 338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 339 }; 340 int i, j, loop_max; 341 342 if (!AR_SREV_9300_20_OR_LATER(ah)) { 343 loop_max = 2; 344 regAddr[1] = AR_PHY_BASE + (8 << 2); 345 } else 346 loop_max = 1; 347 348 for (i = 0; i < loop_max; i++) { 349 u32 addr = regAddr[i]; 350 u32 wrData, rdData; 351 352 regHold[i] = REG_READ(ah, addr); 353 for (j = 0; j < 0x100; j++) { 354 wrData = (j << 16) | j; 355 REG_WRITE(ah, addr, wrData); 356 rdData = REG_READ(ah, addr); 357 if (rdData != wrData) { 358 ath_err(common, 359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 360 addr, wrData, rdData); 361 return false; 362 } 363 } 364 for (j = 0; j < 4; j++) { 365 wrData = patternData[j]; 366 REG_WRITE(ah, addr, wrData); 367 rdData = REG_READ(ah, addr); 368 if (wrData != rdData) { 369 ath_err(common, 370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 371 addr, wrData, rdData); 372 return false; 373 } 374 } 375 REG_WRITE(ah, regAddr[i], regHold[i]); 376 } 377 udelay(100); 378 379 return true; 380 } 381 382 static void ath9k_hw_init_config(struct ath_hw *ah) 383 { 384 struct ath_common *common = ath9k_hw_common(ah); 385 386 ah->config.dma_beacon_response_time = 1; 387 ah->config.sw_beacon_response_time = 6; 388 ah->config.cwm_ignore_extcca = false; 389 ah->config.analog_shiftreg = 1; 390 391 ah->config.rx_intr_mitigation = true; 392 393 if (AR_SREV_9300_20_OR_LATER(ah)) { 394 ah->config.rimt_last = 500; 395 ah->config.rimt_first = 2000; 396 } else { 397 ah->config.rimt_last = 250; 398 ah->config.rimt_first = 700; 399 } 400 401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 402 ah->config.pll_pwrsave = 7; 403 404 /* 405 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 407 * This means we use it for all AR5416 devices, and the few 408 * minor PCI AR9280 devices out there. 409 * 410 * Serialization is required because these devices do not handle 411 * well the case of two concurrent reads/writes due to the latency 412 * involved. During one read/write another read/write can be issued 413 * on another CPU while the previous read/write may still be working 414 * on our hardware, if we hit this case the hardware poops in a loop. 415 * We prevent this by serializing reads and writes. 416 * 417 * This issue is not present on PCI-Express devices or pre-AR5416 418 * devices (legacy, 802.11abg). 419 */ 420 if (num_possible_cpus() > 1) 421 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 422 423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 426 !ah->is_pciexpress)) { 427 ah->config.serialize_regmode = SER_REG_MODE_ON; 428 } else { 429 ah->config.serialize_regmode = SER_REG_MODE_OFF; 430 } 431 } 432 433 ath_dbg(common, RESET, "serialize_regmode is %d\n", 434 ah->config.serialize_regmode); 435 436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 438 else 439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 440 } 441 442 static void ath9k_hw_init_defaults(struct ath_hw *ah) 443 { 444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 445 446 regulatory->country_code = CTRY_DEFAULT; 447 regulatory->power_limit = MAX_RATE_POWER; 448 449 ah->hw_version.magic = AR5416_MAGIC; 450 ah->hw_version.subvendorid = 0; 451 452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 453 AR_STA_ID1_MCAST_KSRCH; 454 if (AR_SREV_9100(ah)) 455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 456 457 ah->slottime = ATH9K_SLOT_TIME_9; 458 ah->globaltxtimeout = (u32) -1; 459 ah->power_mode = ATH9K_PM_UNDEFINED; 460 ah->htc_reset_init = true; 461 462 ah->tpc_enabled = false; 463 464 ah->ani_function = ATH9K_ANI_ALL; 465 if (!AR_SREV_9300_20_OR_LATER(ah)) 466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 467 468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 470 else 471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 472 } 473 474 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 475 { 476 struct ath_common *common = ath9k_hw_common(ah); 477 u32 sum; 478 int i; 479 u16 eeval; 480 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 481 482 sum = 0; 483 for (i = 0; i < 3; i++) { 484 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 485 sum += eeval; 486 common->macaddr[2 * i] = eeval >> 8; 487 common->macaddr[2 * i + 1] = eeval & 0xff; 488 } 489 if (!is_valid_ether_addr(common->macaddr)) { 490 ath_err(common, 491 "eeprom contains invalid mac address: %pM\n", 492 common->macaddr); 493 494 random_ether_addr(common->macaddr); 495 ath_err(common, 496 "random mac address will be used: %pM\n", 497 common->macaddr); 498 } 499 500 return 0; 501 } 502 503 static int ath9k_hw_post_init(struct ath_hw *ah) 504 { 505 struct ath_common *common = ath9k_hw_common(ah); 506 int ecode; 507 508 if (common->bus_ops->ath_bus_type != ATH_USB) { 509 if (!ath9k_hw_chip_test(ah)) 510 return -ENODEV; 511 } 512 513 if (!AR_SREV_9300_20_OR_LATER(ah)) { 514 ecode = ar9002_hw_rf_claim(ah); 515 if (ecode != 0) 516 return ecode; 517 } 518 519 ecode = ath9k_hw_eeprom_init(ah); 520 if (ecode != 0) 521 return ecode; 522 523 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 524 ah->eep_ops->get_eeprom_ver(ah), 525 ah->eep_ops->get_eeprom_rev(ah)); 526 527 ath9k_hw_ani_init(ah); 528 529 /* 530 * EEPROM needs to be initialized before we do this. 531 * This is required for regulatory compliance. 532 */ 533 if (AR_SREV_9300_20_OR_LATER(ah)) { 534 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 535 if ((regdmn & 0xF0) == CTL_FCC) { 536 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 537 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 538 } 539 } 540 541 return 0; 542 } 543 544 static int ath9k_hw_attach_ops(struct ath_hw *ah) 545 { 546 if (!AR_SREV_9300_20_OR_LATER(ah)) 547 return ar9002_hw_attach_ops(ah); 548 549 ar9003_hw_attach_ops(ah); 550 return 0; 551 } 552 553 /* Called for all hardware families */ 554 static int __ath9k_hw_init(struct ath_hw *ah) 555 { 556 struct ath_common *common = ath9k_hw_common(ah); 557 int r = 0; 558 559 ath9k_hw_read_revisions(ah); 560 561 switch (ah->hw_version.macVersion) { 562 case AR_SREV_VERSION_5416_PCI: 563 case AR_SREV_VERSION_5416_PCIE: 564 case AR_SREV_VERSION_9160: 565 case AR_SREV_VERSION_9100: 566 case AR_SREV_VERSION_9280: 567 case AR_SREV_VERSION_9285: 568 case AR_SREV_VERSION_9287: 569 case AR_SREV_VERSION_9271: 570 case AR_SREV_VERSION_9300: 571 case AR_SREV_VERSION_9330: 572 case AR_SREV_VERSION_9485: 573 case AR_SREV_VERSION_9340: 574 case AR_SREV_VERSION_9462: 575 case AR_SREV_VERSION_9550: 576 case AR_SREV_VERSION_9565: 577 case AR_SREV_VERSION_9531: 578 case AR_SREV_VERSION_9561: 579 break; 580 default: 581 ath_err(common, 582 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 583 ah->hw_version.macVersion, ah->hw_version.macRev); 584 return -EOPNOTSUPP; 585 } 586 587 /* 588 * Read back AR_WA into a permanent copy and set bits 14 and 17. 589 * We need to do this to avoid RMW of this register. We cannot 590 * read the reg when chip is asleep. 591 */ 592 if (AR_SREV_9300_20_OR_LATER(ah)) { 593 ah->WARegVal = REG_READ(ah, AR_WA); 594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 595 AR_WA_ASPM_TIMER_BASED_DISABLE); 596 } 597 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 599 ath_err(common, "Couldn't reset chip\n"); 600 return -EIO; 601 } 602 603 if (AR_SREV_9565(ah)) { 604 ah->WARegVal |= AR_WA_BIT22; 605 REG_WRITE(ah, AR_WA, ah->WARegVal); 606 } 607 608 ath9k_hw_init_defaults(ah); 609 ath9k_hw_init_config(ah); 610 611 r = ath9k_hw_attach_ops(ah); 612 if (r) 613 return r; 614 615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 616 ath_err(common, "Couldn't wakeup chip\n"); 617 return -EIO; 618 } 619 620 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 621 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 622 ah->is_pciexpress = false; 623 624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 625 ath9k_hw_init_cal_settings(ah); 626 627 if (!ah->is_pciexpress) 628 ath9k_hw_disablepcie(ah); 629 630 r = ath9k_hw_post_init(ah); 631 if (r) 632 return r; 633 634 ath9k_hw_init_mode_gain_regs(ah); 635 r = ath9k_hw_fill_cap_info(ah); 636 if (r) 637 return r; 638 639 r = ath9k_hw_init_macaddr(ah); 640 if (r) { 641 ath_err(common, "Failed to initialize MAC address\n"); 642 return r; 643 } 644 645 ath9k_hw_init_hang_checks(ah); 646 647 common->state = ATH_HW_INITIALIZED; 648 649 return 0; 650 } 651 652 int ath9k_hw_init(struct ath_hw *ah) 653 { 654 int ret; 655 struct ath_common *common = ath9k_hw_common(ah); 656 657 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 658 switch (ah->hw_version.devid) { 659 case AR5416_DEVID_PCI: 660 case AR5416_DEVID_PCIE: 661 case AR5416_AR9100_DEVID: 662 case AR9160_DEVID_PCI: 663 case AR9280_DEVID_PCI: 664 case AR9280_DEVID_PCIE: 665 case AR9285_DEVID_PCIE: 666 case AR9287_DEVID_PCI: 667 case AR9287_DEVID_PCIE: 668 case AR2427_DEVID_PCIE: 669 case AR9300_DEVID_PCIE: 670 case AR9300_DEVID_AR9485_PCIE: 671 case AR9300_DEVID_AR9330: 672 case AR9300_DEVID_AR9340: 673 case AR9300_DEVID_QCA955X: 674 case AR9300_DEVID_AR9580: 675 case AR9300_DEVID_AR9462: 676 case AR9485_DEVID_AR1111: 677 case AR9300_DEVID_AR9565: 678 case AR9300_DEVID_AR953X: 679 case AR9300_DEVID_QCA956X: 680 break; 681 default: 682 if (common->bus_ops->ath_bus_type == ATH_USB) 683 break; 684 ath_err(common, "Hardware device ID 0x%04x not supported\n", 685 ah->hw_version.devid); 686 return -EOPNOTSUPP; 687 } 688 689 ret = __ath9k_hw_init(ah); 690 if (ret) { 691 ath_err(common, 692 "Unable to initialize hardware; initialization status: %d\n", 693 ret); 694 return ret; 695 } 696 697 ath_dynack_init(ah); 698 699 return 0; 700 } 701 EXPORT_SYMBOL(ath9k_hw_init); 702 703 static void ath9k_hw_init_qos(struct ath_hw *ah) 704 { 705 ENABLE_REGWRITE_BUFFER(ah); 706 707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 709 710 REG_WRITE(ah, AR_QOS_NO_ACK, 711 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 712 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 713 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 714 715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 720 721 REGWRITE_BUFFER_FLUSH(ah); 722 } 723 724 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 725 { 726 struct ath_common *common = ath9k_hw_common(ah); 727 int i = 0; 728 729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 730 udelay(100); 731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 732 733 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 734 735 udelay(100); 736 737 if (WARN_ON_ONCE(i >= 100)) { 738 ath_err(common, "PLL4 meaurement not done\n"); 739 break; 740 } 741 742 i++; 743 } 744 745 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 746 } 747 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 748 749 static void ath9k_hw_init_pll(struct ath_hw *ah, 750 struct ath9k_channel *chan) 751 { 752 u32 pll; 753 754 pll = ath9k_hw_compute_pll_control(ah, chan); 755 756 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 757 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 759 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 761 AR_CH0_DPLL2_KD, 0x40); 762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 763 AR_CH0_DPLL2_KI, 0x4); 764 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 766 AR_CH0_BB_DPLL1_REFDIV, 0x5); 767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 768 AR_CH0_BB_DPLL1_NINI, 0x58); 769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 770 AR_CH0_BB_DPLL1_NFRAC, 0x0); 771 772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 773 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 775 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 777 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 778 779 /* program BB PLL phase_shift to 0x6 */ 780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 781 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 782 783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 784 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 785 udelay(1000); 786 } else if (AR_SREV_9330(ah)) { 787 u32 ddr_dpll2, pll_control2, kd; 788 789 if (ah->is_clk_25mhz) { 790 ddr_dpll2 = 0x18e82f01; 791 pll_control2 = 0xe04a3d; 792 kd = 0x1d; 793 } else { 794 ddr_dpll2 = 0x19e82f01; 795 pll_control2 = 0x886666; 796 kd = 0x3d; 797 } 798 799 /* program DDR PLL ki and kd value */ 800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 801 802 /* program DDR PLL phase_shift */ 803 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 804 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 805 806 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 807 pll | AR_RTC_9300_PLL_BYPASS); 808 udelay(1000); 809 810 /* program refdiv, nint, frac to RTC register */ 811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 812 813 /* program BB PLL kd and ki value */ 814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 816 817 /* program BB PLL phase_shift */ 818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 819 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 820 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 821 AR_SREV_9561(ah)) { 822 u32 regval, pll2_divint, pll2_divfrac, refdiv; 823 824 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 825 pll | AR_RTC_9300_SOC_PLL_BYPASS); 826 udelay(1000); 827 828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 829 udelay(100); 830 831 if (ah->is_clk_25mhz) { 832 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 833 pll2_divint = 0x1c; 834 pll2_divfrac = 0xa3d2; 835 refdiv = 1; 836 } else { 837 pll2_divint = 0x54; 838 pll2_divfrac = 0x1eb85; 839 refdiv = 3; 840 } 841 } else { 842 if (AR_SREV_9340(ah)) { 843 pll2_divint = 88; 844 pll2_divfrac = 0; 845 refdiv = 5; 846 } else { 847 pll2_divint = 0x11; 848 pll2_divfrac = (AR_SREV_9531(ah) || 849 AR_SREV_9561(ah)) ? 850 0x26665 : 0x26666; 851 refdiv = 1; 852 } 853 } 854 855 regval = REG_READ(ah, AR_PHY_PLL_MODE); 856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 857 regval |= (0x1 << 22); 858 else 859 regval |= (0x1 << 16); 860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 861 udelay(100); 862 863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 864 (pll2_divint << 18) | pll2_divfrac); 865 udelay(100); 866 867 regval = REG_READ(ah, AR_PHY_PLL_MODE); 868 if (AR_SREV_9340(ah)) 869 regval = (regval & 0x80071fff) | 870 (0x1 << 30) | 871 (0x1 << 13) | 872 (0x4 << 26) | 873 (0x18 << 19); 874 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 875 regval = (regval & 0x01c00fff) | 876 (0x1 << 31) | 877 (0x2 << 29) | 878 (0xa << 25) | 879 (0x1 << 19); 880 881 if (AR_SREV_9531(ah)) 882 regval |= (0x6 << 12); 883 } else 884 regval = (regval & 0x80071fff) | 885 (0x3 << 30) | 886 (0x1 << 13) | 887 (0x4 << 26) | 888 (0x60 << 19); 889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 890 891 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 892 REG_WRITE(ah, AR_PHY_PLL_MODE, 893 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 894 else 895 REG_WRITE(ah, AR_PHY_PLL_MODE, 896 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 897 898 udelay(1000); 899 } 900 901 if (AR_SREV_9565(ah)) 902 pll |= 0x40000; 903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 904 905 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 906 AR_SREV_9550(ah)) 907 udelay(1000); 908 909 /* Switch the core clock for ar9271 to 117Mhz */ 910 if (AR_SREV_9271(ah)) { 911 udelay(500); 912 REG_WRITE(ah, 0x50040, 0x304); 913 } 914 915 udelay(RTC_PLL_SETTLE_DELAY); 916 917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 918 } 919 920 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 921 enum nl80211_iftype opmode) 922 { 923 u32 sync_default = AR_INTR_SYNC_DEFAULT; 924 u32 imr_reg = AR_IMR_TXERR | 925 AR_IMR_TXURN | 926 AR_IMR_RXERR | 927 AR_IMR_RXORN | 928 AR_IMR_BCNMISC; 929 930 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 931 AR_SREV_9561(ah)) 932 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 933 934 if (AR_SREV_9300_20_OR_LATER(ah)) { 935 imr_reg |= AR_IMR_RXOK_HP; 936 if (ah->config.rx_intr_mitigation) 937 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 938 else 939 imr_reg |= AR_IMR_RXOK_LP; 940 941 } else { 942 if (ah->config.rx_intr_mitigation) 943 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 944 else 945 imr_reg |= AR_IMR_RXOK; 946 } 947 948 if (ah->config.tx_intr_mitigation) 949 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 950 else 951 imr_reg |= AR_IMR_TXOK; 952 953 ENABLE_REGWRITE_BUFFER(ah); 954 955 REG_WRITE(ah, AR_IMR, imr_reg); 956 ah->imrs2_reg |= AR_IMR_S2_GTT; 957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 958 959 if (!AR_SREV_9100(ah)) { 960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 963 } 964 965 REGWRITE_BUFFER_FLUSH(ah); 966 967 if (AR_SREV_9300_20_OR_LATER(ah)) { 968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 972 } 973 } 974 975 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 976 { 977 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 978 val = min(val, (u32) 0xFFFF); 979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 980 } 981 982 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 983 { 984 u32 val = ath9k_hw_mac_to_clks(ah, us); 985 val = min(val, (u32) 0xFFFF); 986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 987 } 988 989 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 990 { 991 u32 val = ath9k_hw_mac_to_clks(ah, us); 992 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 993 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 994 } 995 996 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 997 { 998 u32 val = ath9k_hw_mac_to_clks(ah, us); 999 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1000 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1001 } 1002 1003 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1004 { 1005 if (tu > 0xFFFF) { 1006 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1007 tu); 1008 ah->globaltxtimeout = (u32) -1; 1009 return false; 1010 } else { 1011 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1012 ah->globaltxtimeout = tu; 1013 return true; 1014 } 1015 } 1016 1017 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1018 { 1019 struct ath_common *common = ath9k_hw_common(ah); 1020 const struct ath9k_channel *chan = ah->curchan; 1021 int acktimeout, ctstimeout, ack_offset = 0; 1022 int slottime; 1023 int sifstime; 1024 int rx_lat = 0, tx_lat = 0, eifs = 0; 1025 u32 reg; 1026 1027 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1028 ah->misc_mode); 1029 1030 if (!chan) 1031 return; 1032 1033 if (ah->misc_mode != 0) 1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1035 1036 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1037 rx_lat = 41; 1038 else 1039 rx_lat = 37; 1040 tx_lat = 54; 1041 1042 if (IS_CHAN_5GHZ(chan)) 1043 sifstime = 16; 1044 else 1045 sifstime = 10; 1046 1047 if (IS_CHAN_HALF_RATE(chan)) { 1048 eifs = 175; 1049 rx_lat *= 2; 1050 tx_lat *= 2; 1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1052 tx_lat += 11; 1053 1054 sifstime = 32; 1055 ack_offset = 16; 1056 slottime = 13; 1057 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1058 eifs = 340; 1059 rx_lat = (rx_lat * 4) - 1; 1060 tx_lat *= 4; 1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1062 tx_lat += 22; 1063 1064 sifstime = 64; 1065 ack_offset = 32; 1066 slottime = 21; 1067 } else { 1068 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1069 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1070 reg = AR_USEC_ASYNC_FIFO; 1071 } else { 1072 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1073 common->clockrate; 1074 reg = REG_READ(ah, AR_USEC); 1075 } 1076 rx_lat = MS(reg, AR_USEC_RX_LAT); 1077 tx_lat = MS(reg, AR_USEC_TX_LAT); 1078 1079 slottime = ah->slottime; 1080 } 1081 1082 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1083 slottime += 3 * ah->coverage_class; 1084 acktimeout = slottime + sifstime + ack_offset; 1085 ctstimeout = acktimeout; 1086 1087 /* 1088 * Workaround for early ACK timeouts, add an offset to match the 1089 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1090 * This was initially only meant to work around an issue with delayed 1091 * BA frames in some implementations, but it has been found to fix ACK 1092 * timeout issues in other cases as well. 1093 */ 1094 if (IS_CHAN_2GHZ(chan) && 1095 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1096 acktimeout += 64 - sifstime - ah->slottime; 1097 ctstimeout += 48 - sifstime - ah->slottime; 1098 } 1099 1100 if (ah->dynack.enabled) { 1101 acktimeout = ah->dynack.ackto; 1102 ctstimeout = acktimeout; 1103 slottime = (acktimeout - 3) / 2; 1104 } else { 1105 ah->dynack.ackto = acktimeout; 1106 } 1107 1108 ath9k_hw_set_sifs_time(ah, sifstime); 1109 ath9k_hw_setslottime(ah, slottime); 1110 ath9k_hw_set_ack_timeout(ah, acktimeout); 1111 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1112 if (ah->globaltxtimeout != (u32) -1) 1113 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1114 1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1116 REG_RMW(ah, AR_USEC, 1117 (common->clockrate - 1) | 1118 SM(rx_lat, AR_USEC_RX_LAT) | 1119 SM(tx_lat, AR_USEC_TX_LAT), 1120 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1121 1122 } 1123 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1124 1125 void ath9k_hw_deinit(struct ath_hw *ah) 1126 { 1127 struct ath_common *common = ath9k_hw_common(ah); 1128 1129 if (common->state < ATH_HW_INITIALIZED) 1130 return; 1131 1132 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1133 } 1134 EXPORT_SYMBOL(ath9k_hw_deinit); 1135 1136 /*******/ 1137 /* INI */ 1138 /*******/ 1139 1140 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1141 { 1142 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1143 1144 if (IS_CHAN_2GHZ(chan)) 1145 ctl |= CTL_11G; 1146 else 1147 ctl |= CTL_11A; 1148 1149 return ctl; 1150 } 1151 1152 /****************************************/ 1153 /* Reset and Channel Switching Routines */ 1154 /****************************************/ 1155 1156 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1157 { 1158 struct ath_common *common = ath9k_hw_common(ah); 1159 int txbuf_size; 1160 1161 ENABLE_REGWRITE_BUFFER(ah); 1162 1163 /* 1164 * set AHB_MODE not to do cacheline prefetches 1165 */ 1166 if (!AR_SREV_9300_20_OR_LATER(ah)) 1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1168 1169 /* 1170 * let mac dma reads be in 128 byte chunks 1171 */ 1172 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1173 1174 REGWRITE_BUFFER_FLUSH(ah); 1175 1176 /* 1177 * Restore TX Trigger Level to its pre-reset value. 1178 * The initial value depends on whether aggregation is enabled, and is 1179 * adjusted whenever underruns are detected. 1180 */ 1181 if (!AR_SREV_9300_20_OR_LATER(ah)) 1182 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1183 1184 ENABLE_REGWRITE_BUFFER(ah); 1185 1186 /* 1187 * let mac dma writes be in 128 byte chunks 1188 */ 1189 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1190 1191 /* 1192 * Setup receive FIFO threshold to hold off TX activities 1193 */ 1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1195 1196 if (AR_SREV_9300_20_OR_LATER(ah)) { 1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1198 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1199 1200 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1201 ah->caps.rx_status_len); 1202 } 1203 1204 /* 1205 * reduce the number of usable entries in PCU TXBUF to avoid 1206 * wrap around issues. 1207 */ 1208 if (AR_SREV_9285(ah)) { 1209 /* For AR9285 the number of Fifos are reduced to half. 1210 * So set the usable tx buf size also to half to 1211 * avoid data/delimiter underruns 1212 */ 1213 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1214 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1215 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1216 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1217 } else { 1218 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1219 } 1220 1221 if (!AR_SREV_9271(ah)) 1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1223 1224 REGWRITE_BUFFER_FLUSH(ah); 1225 1226 if (AR_SREV_9300_20_OR_LATER(ah)) 1227 ath9k_hw_reset_txstatus_ring(ah); 1228 } 1229 1230 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1231 { 1232 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1233 u32 set = AR_STA_ID1_KSRCH_MODE; 1234 1235 ENABLE_REG_RMW_BUFFER(ah); 1236 switch (opmode) { 1237 case NL80211_IFTYPE_ADHOC: 1238 if (!AR_SREV_9340_13(ah)) { 1239 set |= AR_STA_ID1_ADHOC; 1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1241 break; 1242 } 1243 /* fall through */ 1244 case NL80211_IFTYPE_OCB: 1245 case NL80211_IFTYPE_MESH_POINT: 1246 case NL80211_IFTYPE_AP: 1247 set |= AR_STA_ID1_STA_AP; 1248 /* fall through */ 1249 case NL80211_IFTYPE_STATION: 1250 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1251 break; 1252 default: 1253 if (!ah->is_monitoring) 1254 set = 0; 1255 break; 1256 } 1257 REG_RMW(ah, AR_STA_ID1, set, mask); 1258 REG_RMW_BUFFER_FLUSH(ah); 1259 } 1260 1261 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1262 u32 *coef_mantissa, u32 *coef_exponent) 1263 { 1264 u32 coef_exp, coef_man; 1265 1266 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1267 if ((coef_scaled >> coef_exp) & 0x1) 1268 break; 1269 1270 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1271 1272 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1273 1274 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1275 *coef_exponent = coef_exp - 16; 1276 } 1277 1278 /* AR9330 WAR: 1279 * call external reset function to reset WMAC if: 1280 * - doing a cold reset 1281 * - we have pending frames in the TX queues. 1282 */ 1283 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1284 { 1285 int i, npend = 0; 1286 1287 for (i = 0; i < AR_NUM_QCU; i++) { 1288 npend = ath9k_hw_numtxpending(ah, i); 1289 if (npend) 1290 break; 1291 } 1292 1293 if (ah->external_reset && 1294 (npend || type == ATH9K_RESET_COLD)) { 1295 int reset_err = 0; 1296 1297 ath_dbg(ath9k_hw_common(ah), RESET, 1298 "reset MAC via external reset\n"); 1299 1300 reset_err = ah->external_reset(); 1301 if (reset_err) { 1302 ath_err(ath9k_hw_common(ah), 1303 "External reset failed, err=%d\n", 1304 reset_err); 1305 return false; 1306 } 1307 1308 REG_WRITE(ah, AR_RTC_RESET, 1); 1309 } 1310 1311 return true; 1312 } 1313 1314 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1315 { 1316 u32 rst_flags; 1317 u32 tmpReg; 1318 1319 if (AR_SREV_9100(ah)) { 1320 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1321 AR_RTC_DERIVED_CLK_PERIOD, 1); 1322 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1323 } 1324 1325 ENABLE_REGWRITE_BUFFER(ah); 1326 1327 if (AR_SREV_9300_20_OR_LATER(ah)) { 1328 REG_WRITE(ah, AR_WA, ah->WARegVal); 1329 udelay(10); 1330 } 1331 1332 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1333 AR_RTC_FORCE_WAKE_ON_INT); 1334 1335 if (AR_SREV_9100(ah)) { 1336 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1337 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1338 } else { 1339 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1340 if (AR_SREV_9340(ah)) 1341 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1342 else 1343 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1344 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1345 1346 if (tmpReg) { 1347 u32 val; 1348 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1349 1350 val = AR_RC_HOSTIF; 1351 if (!AR_SREV_9300_20_OR_LATER(ah)) 1352 val |= AR_RC_AHB; 1353 REG_WRITE(ah, AR_RC, val); 1354 1355 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1356 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1357 1358 rst_flags = AR_RTC_RC_MAC_WARM; 1359 if (type == ATH9K_RESET_COLD) 1360 rst_flags |= AR_RTC_RC_MAC_COLD; 1361 } 1362 1363 if (AR_SREV_9330(ah)) { 1364 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1365 return false; 1366 } 1367 1368 if (ath9k_hw_mci_is_enabled(ah)) 1369 ar9003_mci_check_gpm_offset(ah); 1370 1371 /* DMA HALT added to resolve ar9300 and ar9580 bus error during 1372 * RTC_RC reg read 1373 */ 1374 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { 1375 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1376 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, 1377 20 * AH_WAIT_TIMEOUT); 1378 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1379 } 1380 1381 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1382 1383 REGWRITE_BUFFER_FLUSH(ah); 1384 1385 if (AR_SREV_9300_20_OR_LATER(ah)) 1386 udelay(50); 1387 else if (AR_SREV_9100(ah)) 1388 mdelay(10); 1389 else 1390 udelay(100); 1391 1392 REG_WRITE(ah, AR_RTC_RC, 0); 1393 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1394 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1395 return false; 1396 } 1397 1398 if (!AR_SREV_9100(ah)) 1399 REG_WRITE(ah, AR_RC, 0); 1400 1401 if (AR_SREV_9100(ah)) 1402 udelay(50); 1403 1404 return true; 1405 } 1406 1407 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1408 { 1409 ENABLE_REGWRITE_BUFFER(ah); 1410 1411 if (AR_SREV_9300_20_OR_LATER(ah)) { 1412 REG_WRITE(ah, AR_WA, ah->WARegVal); 1413 udelay(10); 1414 } 1415 1416 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1417 AR_RTC_FORCE_WAKE_ON_INT); 1418 1419 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1420 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1421 1422 REG_WRITE(ah, AR_RTC_RESET, 0); 1423 1424 REGWRITE_BUFFER_FLUSH(ah); 1425 1426 udelay(2); 1427 1428 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1429 REG_WRITE(ah, AR_RC, 0); 1430 1431 REG_WRITE(ah, AR_RTC_RESET, 1); 1432 1433 if (!ath9k_hw_wait(ah, 1434 AR_RTC_STATUS, 1435 AR_RTC_STATUS_M, 1436 AR_RTC_STATUS_ON, 1437 AH_WAIT_TIMEOUT)) { 1438 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1439 return false; 1440 } 1441 1442 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1443 } 1444 1445 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1446 { 1447 bool ret = false; 1448 1449 if (AR_SREV_9300_20_OR_LATER(ah)) { 1450 REG_WRITE(ah, AR_WA, ah->WARegVal); 1451 udelay(10); 1452 } 1453 1454 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1455 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1456 1457 if (!ah->reset_power_on) 1458 type = ATH9K_RESET_POWER_ON; 1459 1460 switch (type) { 1461 case ATH9K_RESET_POWER_ON: 1462 ret = ath9k_hw_set_reset_power_on(ah); 1463 if (ret) 1464 ah->reset_power_on = true; 1465 break; 1466 case ATH9K_RESET_WARM: 1467 case ATH9K_RESET_COLD: 1468 ret = ath9k_hw_set_reset(ah, type); 1469 break; 1470 default: 1471 break; 1472 } 1473 1474 return ret; 1475 } 1476 1477 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1478 struct ath9k_channel *chan) 1479 { 1480 int reset_type = ATH9K_RESET_WARM; 1481 1482 if (AR_SREV_9280(ah)) { 1483 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1484 reset_type = ATH9K_RESET_POWER_ON; 1485 else 1486 reset_type = ATH9K_RESET_COLD; 1487 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1488 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1489 reset_type = ATH9K_RESET_COLD; 1490 1491 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1492 return false; 1493 1494 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1495 return false; 1496 1497 ah->chip_fullsleep = false; 1498 1499 if (AR_SREV_9330(ah)) 1500 ar9003_hw_internal_regulator_apply(ah); 1501 ath9k_hw_init_pll(ah, chan); 1502 1503 return true; 1504 } 1505 1506 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1507 struct ath9k_channel *chan) 1508 { 1509 struct ath_common *common = ath9k_hw_common(ah); 1510 struct ath9k_hw_capabilities *pCap = &ah->caps; 1511 bool band_switch = false, mode_diff = false; 1512 u8 ini_reloaded = 0; 1513 u32 qnum; 1514 int r; 1515 1516 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1517 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1518 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1519 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1520 } 1521 1522 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1523 if (ath9k_hw_numtxpending(ah, qnum)) { 1524 ath_dbg(common, QUEUE, 1525 "Transmit frames pending on queue %d\n", qnum); 1526 return false; 1527 } 1528 } 1529 1530 if (!ath9k_hw_rfbus_req(ah)) { 1531 ath_err(common, "Could not kill baseband RX\n"); 1532 return false; 1533 } 1534 1535 if (band_switch || mode_diff) { 1536 ath9k_hw_mark_phy_inactive(ah); 1537 udelay(5); 1538 1539 if (band_switch) 1540 ath9k_hw_init_pll(ah, chan); 1541 1542 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1543 ath_err(common, "Failed to do fast channel change\n"); 1544 return false; 1545 } 1546 } 1547 1548 ath9k_hw_set_channel_regs(ah, chan); 1549 1550 r = ath9k_hw_rf_set_freq(ah, chan); 1551 if (r) { 1552 ath_err(common, "Failed to set channel\n"); 1553 return false; 1554 } 1555 ath9k_hw_set_clockrate(ah); 1556 ath9k_hw_apply_txpower(ah, chan, false); 1557 1558 ath9k_hw_set_delta_slope(ah, chan); 1559 ath9k_hw_spur_mitigate_freq(ah, chan); 1560 1561 if (band_switch || ini_reloaded) 1562 ah->eep_ops->set_board_values(ah, chan); 1563 1564 ath9k_hw_init_bb(ah, chan); 1565 ath9k_hw_rfbus_done(ah); 1566 1567 if (band_switch || ini_reloaded) { 1568 ah->ah_flags |= AH_FASTCC; 1569 ath9k_hw_init_cal(ah, chan); 1570 ah->ah_flags &= ~AH_FASTCC; 1571 } 1572 1573 return true; 1574 } 1575 1576 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1577 { 1578 u32 gpio_mask = ah->gpio_mask; 1579 int i; 1580 1581 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1582 if (!(gpio_mask & 1)) 1583 continue; 1584 1585 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1586 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1587 } 1588 } 1589 1590 void ath9k_hw_check_nav(struct ath_hw *ah) 1591 { 1592 struct ath_common *common = ath9k_hw_common(ah); 1593 u32 val; 1594 1595 val = REG_READ(ah, AR_NAV); 1596 if (val != 0xdeadbeef && val > 0x7fff) { 1597 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1598 REG_WRITE(ah, AR_NAV, 0); 1599 } 1600 } 1601 EXPORT_SYMBOL(ath9k_hw_check_nav); 1602 1603 bool ath9k_hw_check_alive(struct ath_hw *ah) 1604 { 1605 int count = 50; 1606 u32 reg, last_val; 1607 1608 if (AR_SREV_9300(ah)) 1609 return !ath9k_hw_detect_mac_hang(ah); 1610 1611 if (AR_SREV_9285_12_OR_LATER(ah)) 1612 return true; 1613 1614 last_val = REG_READ(ah, AR_OBS_BUS_1); 1615 do { 1616 reg = REG_READ(ah, AR_OBS_BUS_1); 1617 if (reg != last_val) 1618 return true; 1619 1620 udelay(1); 1621 last_val = reg; 1622 if ((reg & 0x7E7FFFEF) == 0x00702400) 1623 continue; 1624 1625 switch (reg & 0x7E000B00) { 1626 case 0x1E000000: 1627 case 0x52000B00: 1628 case 0x18000B00: 1629 continue; 1630 default: 1631 return true; 1632 } 1633 } while (count-- > 0); 1634 1635 return false; 1636 } 1637 EXPORT_SYMBOL(ath9k_hw_check_alive); 1638 1639 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1640 { 1641 /* Setup MFP options for CCMP */ 1642 if (AR_SREV_9280_20_OR_LATER(ah)) { 1643 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1644 * frames when constructing CCMP AAD. */ 1645 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1646 0xc7ff); 1647 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1648 ah->sw_mgmt_crypto_tx = true; 1649 else 1650 ah->sw_mgmt_crypto_tx = false; 1651 ah->sw_mgmt_crypto_rx = false; 1652 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1653 /* Disable hardware crypto for management frames */ 1654 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1655 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1656 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1657 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1658 ah->sw_mgmt_crypto_tx = true; 1659 ah->sw_mgmt_crypto_rx = true; 1660 } else { 1661 ah->sw_mgmt_crypto_tx = true; 1662 ah->sw_mgmt_crypto_rx = true; 1663 } 1664 } 1665 1666 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1667 u32 macStaId1, u32 saveDefAntenna) 1668 { 1669 struct ath_common *common = ath9k_hw_common(ah); 1670 1671 ENABLE_REGWRITE_BUFFER(ah); 1672 1673 REG_RMW(ah, AR_STA_ID1, macStaId1 1674 | AR_STA_ID1_RTS_USE_DEF 1675 | ah->sta_id1_defaults, 1676 ~AR_STA_ID1_SADH_MASK); 1677 ath_hw_setbssidmask(common); 1678 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1679 ath9k_hw_write_associd(ah); 1680 REG_WRITE(ah, AR_ISR, ~0); 1681 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1682 1683 REGWRITE_BUFFER_FLUSH(ah); 1684 1685 ath9k_hw_set_operating_mode(ah, ah->opmode); 1686 } 1687 1688 static void ath9k_hw_init_queues(struct ath_hw *ah) 1689 { 1690 int i; 1691 1692 ENABLE_REGWRITE_BUFFER(ah); 1693 1694 for (i = 0; i < AR_NUM_DCU; i++) 1695 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1696 1697 REGWRITE_BUFFER_FLUSH(ah); 1698 1699 ah->intr_txqs = 0; 1700 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1701 ath9k_hw_resettxqueue(ah, i); 1702 } 1703 1704 /* 1705 * For big endian systems turn on swapping for descriptors 1706 */ 1707 static void ath9k_hw_init_desc(struct ath_hw *ah) 1708 { 1709 struct ath_common *common = ath9k_hw_common(ah); 1710 1711 if (AR_SREV_9100(ah)) { 1712 u32 mask; 1713 mask = REG_READ(ah, AR_CFG); 1714 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1715 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1716 mask); 1717 } else { 1718 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1719 REG_WRITE(ah, AR_CFG, mask); 1720 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1721 REG_READ(ah, AR_CFG)); 1722 } 1723 } else { 1724 if (common->bus_ops->ath_bus_type == ATH_USB) { 1725 /* Configure AR9271 target WLAN */ 1726 if (AR_SREV_9271(ah)) 1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1728 else 1729 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1730 } 1731 #ifdef __BIG_ENDIAN 1732 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1733 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1734 AR_SREV_9561(ah)) 1735 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1736 else 1737 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1738 #endif 1739 } 1740 } 1741 1742 /* 1743 * Fast channel change: 1744 * (Change synthesizer based on channel freq without resetting chip) 1745 */ 1746 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1747 { 1748 struct ath_common *common = ath9k_hw_common(ah); 1749 struct ath9k_hw_capabilities *pCap = &ah->caps; 1750 int ret; 1751 1752 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1753 goto fail; 1754 1755 if (ah->chip_fullsleep) 1756 goto fail; 1757 1758 if (!ah->curchan) 1759 goto fail; 1760 1761 if (chan->channel == ah->curchan->channel) 1762 goto fail; 1763 1764 if ((ah->curchan->channelFlags | chan->channelFlags) & 1765 (CHANNEL_HALF | CHANNEL_QUARTER)) 1766 goto fail; 1767 1768 /* 1769 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1770 */ 1771 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1772 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1773 goto fail; 1774 1775 if (!ath9k_hw_check_alive(ah)) 1776 goto fail; 1777 1778 /* 1779 * For AR9462, make sure that calibration data for 1780 * re-using are present. 1781 */ 1782 if (AR_SREV_9462(ah) && (ah->caldata && 1783 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1784 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1785 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1786 goto fail; 1787 1788 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1789 ah->curchan->channel, chan->channel); 1790 1791 ret = ath9k_hw_channel_change(ah, chan); 1792 if (!ret) 1793 goto fail; 1794 1795 if (ath9k_hw_mci_is_enabled(ah)) 1796 ar9003_mci_2g5g_switch(ah, false); 1797 1798 ath9k_hw_loadnf(ah, ah->curchan); 1799 ath9k_hw_start_nfcal(ah, true); 1800 1801 if (AR_SREV_9271(ah)) 1802 ar9002_hw_load_ani_reg(ah, chan); 1803 1804 return 0; 1805 fail: 1806 return -EINVAL; 1807 } 1808 1809 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1810 { 1811 struct timespec ts; 1812 s64 usec; 1813 1814 if (!cur) { 1815 getrawmonotonic(&ts); 1816 cur = &ts; 1817 } 1818 1819 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1820 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1821 1822 return (u32) usec; 1823 } 1824 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1825 1826 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1827 struct ath9k_hw_cal_data *caldata, bool fastcc) 1828 { 1829 struct ath_common *common = ath9k_hw_common(ah); 1830 u32 saveLedState; 1831 u32 saveDefAntenna; 1832 u32 macStaId1; 1833 u64 tsf = 0; 1834 s64 usec = 0; 1835 int r; 1836 bool start_mci_reset = false; 1837 bool save_fullsleep = ah->chip_fullsleep; 1838 1839 if (ath9k_hw_mci_is_enabled(ah)) { 1840 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1841 if (start_mci_reset) 1842 return 0; 1843 } 1844 1845 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1846 return -EIO; 1847 1848 if (ah->curchan && !ah->chip_fullsleep) 1849 ath9k_hw_getnf(ah, ah->curchan); 1850 1851 ah->caldata = caldata; 1852 if (caldata && (chan->channel != caldata->channel || 1853 chan->channelFlags != caldata->channelFlags)) { 1854 /* Operating channel changed, reset channel calibration data */ 1855 memset(caldata, 0, sizeof(*caldata)); 1856 ath9k_init_nfcal_hist_buffer(ah, chan); 1857 } else if (caldata) { 1858 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1859 } 1860 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1861 1862 if (fastcc) { 1863 r = ath9k_hw_do_fastcc(ah, chan); 1864 if (!r) 1865 return r; 1866 } 1867 1868 if (ath9k_hw_mci_is_enabled(ah)) 1869 ar9003_mci_stop_bt(ah, save_fullsleep); 1870 1871 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1872 if (saveDefAntenna == 0) 1873 saveDefAntenna = 1; 1874 1875 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1876 1877 /* Save TSF before chip reset, a cold reset clears it */ 1878 tsf = ath9k_hw_gettsf64(ah); 1879 usec = ktime_to_us(ktime_get_raw()); 1880 1881 saveLedState = REG_READ(ah, AR_CFG_LED) & 1882 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1883 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1884 1885 ath9k_hw_mark_phy_inactive(ah); 1886 1887 ah->paprd_table_write_done = false; 1888 1889 /* Only required on the first reset */ 1890 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1891 REG_WRITE(ah, 1892 AR9271_RESET_POWER_DOWN_CONTROL, 1893 AR9271_RADIO_RF_RST); 1894 udelay(50); 1895 } 1896 1897 if (!ath9k_hw_chip_reset(ah, chan)) { 1898 ath_err(common, "Chip reset failed\n"); 1899 return -EINVAL; 1900 } 1901 1902 /* Only required on the first reset */ 1903 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1904 ah->htc_reset_init = false; 1905 REG_WRITE(ah, 1906 AR9271_RESET_POWER_DOWN_CONTROL, 1907 AR9271_GATE_MAC_CTL); 1908 udelay(50); 1909 } 1910 1911 /* Restore TSF */ 1912 usec = ktime_to_us(ktime_get_raw()) - usec; 1913 ath9k_hw_settsf64(ah, tsf + usec); 1914 1915 if (AR_SREV_9280_20_OR_LATER(ah)) 1916 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1917 1918 if (!AR_SREV_9300_20_OR_LATER(ah)) 1919 ar9002_hw_enable_async_fifo(ah); 1920 1921 r = ath9k_hw_process_ini(ah, chan); 1922 if (r) 1923 return r; 1924 1925 ath9k_hw_set_rfmode(ah, chan); 1926 1927 if (ath9k_hw_mci_is_enabled(ah)) 1928 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1929 1930 /* 1931 * Some AR91xx SoC devices frequently fail to accept TSF writes 1932 * right after the chip reset. When that happens, write a new 1933 * value after the initvals have been applied, with an offset 1934 * based on measured time difference 1935 */ 1936 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1937 tsf += 1500; 1938 ath9k_hw_settsf64(ah, tsf); 1939 } 1940 1941 ath9k_hw_init_mfp(ah); 1942 1943 ath9k_hw_set_delta_slope(ah, chan); 1944 ath9k_hw_spur_mitigate_freq(ah, chan); 1945 ah->eep_ops->set_board_values(ah, chan); 1946 1947 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1948 1949 r = ath9k_hw_rf_set_freq(ah, chan); 1950 if (r) 1951 return r; 1952 1953 ath9k_hw_set_clockrate(ah); 1954 1955 ath9k_hw_init_queues(ah); 1956 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1957 ath9k_hw_ani_cache_ini_regs(ah); 1958 ath9k_hw_init_qos(ah); 1959 1960 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1961 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1962 1963 ath9k_hw_init_global_settings(ah); 1964 1965 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1966 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1967 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1968 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1969 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1970 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1971 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1972 } 1973 1974 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1975 1976 ath9k_hw_set_dma(ah); 1977 1978 if (!ath9k_hw_mci_is_enabled(ah)) 1979 REG_WRITE(ah, AR_OBS, 8); 1980 1981 ENABLE_REG_RMW_BUFFER(ah); 1982 if (ah->config.rx_intr_mitigation) { 1983 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1984 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1985 } 1986 1987 if (ah->config.tx_intr_mitigation) { 1988 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1989 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1990 } 1991 REG_RMW_BUFFER_FLUSH(ah); 1992 1993 ath9k_hw_init_bb(ah, chan); 1994 1995 if (caldata) { 1996 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1997 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1998 } 1999 if (!ath9k_hw_init_cal(ah, chan)) 2000 return -EIO; 2001 2002 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2003 return -EIO; 2004 2005 ENABLE_REGWRITE_BUFFER(ah); 2006 2007 ath9k_hw_restore_chainmask(ah); 2008 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2009 2010 REGWRITE_BUFFER_FLUSH(ah); 2011 2012 ath9k_hw_gen_timer_start_tsf2(ah); 2013 2014 ath9k_hw_init_desc(ah); 2015 2016 if (ath9k_hw_btcoex_is_enabled(ah)) 2017 ath9k_hw_btcoex_enable(ah); 2018 2019 if (ath9k_hw_mci_is_enabled(ah)) 2020 ar9003_mci_check_bt(ah); 2021 2022 if (AR_SREV_9300_20_OR_LATER(ah)) { 2023 ath9k_hw_loadnf(ah, chan); 2024 ath9k_hw_start_nfcal(ah, true); 2025 } 2026 2027 if (AR_SREV_9300_20_OR_LATER(ah)) 2028 ar9003_hw_bb_watchdog_config(ah); 2029 2030 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 2031 ar9003_hw_disable_phy_restart(ah); 2032 2033 ath9k_hw_apply_gpio_override(ah); 2034 2035 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2036 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2037 2038 if (ah->hw->conf.radar_enabled) { 2039 /* set HW specific DFS configuration */ 2040 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 2041 ath9k_hw_set_radar_params(ah); 2042 } 2043 2044 return 0; 2045 } 2046 EXPORT_SYMBOL(ath9k_hw_reset); 2047 2048 /******************************/ 2049 /* Power Management (Chipset) */ 2050 /******************************/ 2051 2052 /* 2053 * Notify Power Mgt is disabled in self-generated frames. 2054 * If requested, force chip to sleep. 2055 */ 2056 static void ath9k_set_power_sleep(struct ath_hw *ah) 2057 { 2058 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2059 2060 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2061 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2062 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2063 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2064 /* xxx Required for WLAN only case ? */ 2065 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2066 udelay(100); 2067 } 2068 2069 /* 2070 * Clear the RTC force wake bit to allow the 2071 * mac to go to sleep. 2072 */ 2073 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2074 2075 if (ath9k_hw_mci_is_enabled(ah)) 2076 udelay(100); 2077 2078 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2079 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2080 2081 /* Shutdown chip. Active low */ 2082 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2083 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2084 udelay(2); 2085 } 2086 2087 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2088 if (AR_SREV_9300_20_OR_LATER(ah)) 2089 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2090 } 2091 2092 /* 2093 * Notify Power Management is enabled in self-generating 2094 * frames. If request, set power mode of chip to 2095 * auto/normal. Duration in units of 128us (1/8 TU). 2096 */ 2097 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2098 { 2099 struct ath9k_hw_capabilities *pCap = &ah->caps; 2100 2101 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2102 2103 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2104 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2105 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2106 AR_RTC_FORCE_WAKE_ON_INT); 2107 } else { 2108 2109 /* When chip goes into network sleep, it could be waken 2110 * up by MCI_INT interrupt caused by BT's HW messages 2111 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2112 * rate (~100us). This will cause chip to leave and 2113 * re-enter network sleep mode frequently, which in 2114 * consequence will have WLAN MCI HW to generate lots of 2115 * SYS_WAKING and SYS_SLEEPING messages which will make 2116 * BT CPU to busy to process. 2117 */ 2118 if (ath9k_hw_mci_is_enabled(ah)) 2119 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2120 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2121 /* 2122 * Clear the RTC force wake bit to allow the 2123 * mac to go to sleep. 2124 */ 2125 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2126 2127 if (ath9k_hw_mci_is_enabled(ah)) 2128 udelay(30); 2129 } 2130 2131 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2132 if (AR_SREV_9300_20_OR_LATER(ah)) 2133 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2134 } 2135 2136 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2137 { 2138 u32 val; 2139 int i; 2140 2141 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2142 if (AR_SREV_9300_20_OR_LATER(ah)) { 2143 REG_WRITE(ah, AR_WA, ah->WARegVal); 2144 udelay(10); 2145 } 2146 2147 if ((REG_READ(ah, AR_RTC_STATUS) & 2148 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2149 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2150 return false; 2151 } 2152 if (!AR_SREV_9300_20_OR_LATER(ah)) 2153 ath9k_hw_init_pll(ah, NULL); 2154 } 2155 if (AR_SREV_9100(ah)) 2156 REG_SET_BIT(ah, AR_RTC_RESET, 2157 AR_RTC_RESET_EN); 2158 2159 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2160 AR_RTC_FORCE_WAKE_EN); 2161 if (AR_SREV_9100(ah)) 2162 mdelay(10); 2163 else 2164 udelay(50); 2165 2166 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2167 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2168 if (val == AR_RTC_STATUS_ON) 2169 break; 2170 udelay(50); 2171 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2172 AR_RTC_FORCE_WAKE_EN); 2173 } 2174 if (i == 0) { 2175 ath_err(ath9k_hw_common(ah), 2176 "Failed to wakeup in %uus\n", 2177 POWER_UP_TIME / 20); 2178 return false; 2179 } 2180 2181 if (ath9k_hw_mci_is_enabled(ah)) 2182 ar9003_mci_set_power_awake(ah); 2183 2184 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2185 2186 return true; 2187 } 2188 2189 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2190 { 2191 struct ath_common *common = ath9k_hw_common(ah); 2192 int status = true; 2193 static const char *modes[] = { 2194 "AWAKE", 2195 "FULL-SLEEP", 2196 "NETWORK SLEEP", 2197 "UNDEFINED" 2198 }; 2199 2200 if (ah->power_mode == mode) 2201 return status; 2202 2203 ath_dbg(common, RESET, "%s -> %s\n", 2204 modes[ah->power_mode], modes[mode]); 2205 2206 switch (mode) { 2207 case ATH9K_PM_AWAKE: 2208 status = ath9k_hw_set_power_awake(ah); 2209 break; 2210 case ATH9K_PM_FULL_SLEEP: 2211 if (ath9k_hw_mci_is_enabled(ah)) 2212 ar9003_mci_set_full_sleep(ah); 2213 2214 ath9k_set_power_sleep(ah); 2215 ah->chip_fullsleep = true; 2216 break; 2217 case ATH9K_PM_NETWORK_SLEEP: 2218 ath9k_set_power_network_sleep(ah); 2219 break; 2220 default: 2221 ath_err(common, "Unknown power mode %u\n", mode); 2222 return false; 2223 } 2224 ah->power_mode = mode; 2225 2226 /* 2227 * XXX: If this warning never comes up after a while then 2228 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2229 * ath9k_hw_setpower() return type void. 2230 */ 2231 2232 if (!(ah->ah_flags & AH_UNPLUGGED)) 2233 ATH_DBG_WARN_ON_ONCE(!status); 2234 2235 return status; 2236 } 2237 EXPORT_SYMBOL(ath9k_hw_setpower); 2238 2239 /*******************/ 2240 /* Beacon Handling */ 2241 /*******************/ 2242 2243 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2244 { 2245 int flags = 0; 2246 2247 ENABLE_REGWRITE_BUFFER(ah); 2248 2249 switch (ah->opmode) { 2250 case NL80211_IFTYPE_ADHOC: 2251 REG_SET_BIT(ah, AR_TXCFG, 2252 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2253 case NL80211_IFTYPE_MESH_POINT: 2254 case NL80211_IFTYPE_AP: 2255 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2256 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2257 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2258 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2259 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2260 flags |= 2261 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2262 break; 2263 default: 2264 ath_dbg(ath9k_hw_common(ah), BEACON, 2265 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2266 return; 2267 break; 2268 } 2269 2270 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2271 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2272 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2273 2274 REGWRITE_BUFFER_FLUSH(ah); 2275 2276 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2277 } 2278 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2279 2280 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2281 const struct ath9k_beacon_state *bs) 2282 { 2283 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2284 struct ath9k_hw_capabilities *pCap = &ah->caps; 2285 struct ath_common *common = ath9k_hw_common(ah); 2286 2287 ENABLE_REGWRITE_BUFFER(ah); 2288 2289 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2290 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2291 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2292 2293 REGWRITE_BUFFER_FLUSH(ah); 2294 2295 REG_RMW_FIELD(ah, AR_RSSI_THR, 2296 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2297 2298 beaconintval = bs->bs_intval; 2299 2300 if (bs->bs_sleepduration > beaconintval) 2301 beaconintval = bs->bs_sleepduration; 2302 2303 dtimperiod = bs->bs_dtimperiod; 2304 if (bs->bs_sleepduration > dtimperiod) 2305 dtimperiod = bs->bs_sleepduration; 2306 2307 if (beaconintval == dtimperiod) 2308 nextTbtt = bs->bs_nextdtim; 2309 else 2310 nextTbtt = bs->bs_nexttbtt; 2311 2312 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); 2313 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt); 2314 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval); 2315 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod); 2316 2317 ENABLE_REGWRITE_BUFFER(ah); 2318 2319 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2320 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2321 2322 REG_WRITE(ah, AR_SLEEP1, 2323 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2324 | AR_SLEEP1_ASSUME_DTIM); 2325 2326 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2327 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2328 else 2329 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2330 2331 REG_WRITE(ah, AR_SLEEP2, 2332 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2333 2334 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2335 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2336 2337 REGWRITE_BUFFER_FLUSH(ah); 2338 2339 REG_SET_BIT(ah, AR_TIMER_MODE, 2340 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2341 AR_DTIM_TIMER_EN); 2342 2343 /* TSF Out of Range Threshold */ 2344 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2345 } 2346 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2347 2348 /*******************/ 2349 /* HW Capabilities */ 2350 /*******************/ 2351 2352 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2353 { 2354 eeprom_chainmask &= chip_chainmask; 2355 if (eeprom_chainmask) 2356 return eeprom_chainmask; 2357 else 2358 return chip_chainmask; 2359 } 2360 2361 /** 2362 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2363 * @ah: the atheros hardware data structure 2364 * 2365 * We enable DFS support upstream on chipsets which have passed a series 2366 * of tests. The testing requirements are going to be documented. Desired 2367 * test requirements are documented at: 2368 * 2369 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2370 * 2371 * Once a new chipset gets properly tested an individual commit can be used 2372 * to document the testing for DFS for that chipset. 2373 */ 2374 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2375 { 2376 2377 switch (ah->hw_version.macVersion) { 2378 /* for temporary testing DFS with 9280 */ 2379 case AR_SREV_VERSION_9280: 2380 /* AR9580 will likely be our first target to get testing on */ 2381 case AR_SREV_VERSION_9580: 2382 return true; 2383 default: 2384 return false; 2385 } 2386 } 2387 2388 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2389 { 2390 struct ath9k_hw_capabilities *pCap = &ah->caps; 2391 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2392 struct ath_common *common = ath9k_hw_common(ah); 2393 2394 u16 eeval; 2395 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2396 2397 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2398 regulatory->current_rd = eeval; 2399 2400 if (ah->opmode != NL80211_IFTYPE_AP && 2401 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2402 if (regulatory->current_rd == 0x64 || 2403 regulatory->current_rd == 0x65) 2404 regulatory->current_rd += 5; 2405 else if (regulatory->current_rd == 0x41) 2406 regulatory->current_rd = 0x43; 2407 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2408 regulatory->current_rd); 2409 } 2410 2411 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2412 2413 if (eeval & AR5416_OPFLAGS_11A) { 2414 if (ah->disable_5ghz) 2415 ath_warn(common, "disabling 5GHz band\n"); 2416 else 2417 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2418 } 2419 2420 if (eeval & AR5416_OPFLAGS_11G) { 2421 if (ah->disable_2ghz) 2422 ath_warn(common, "disabling 2GHz band\n"); 2423 else 2424 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2425 } 2426 2427 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2428 ath_err(common, "both bands are disabled\n"); 2429 return -EINVAL; 2430 } 2431 2432 if (AR_SREV_9485(ah) || 2433 AR_SREV_9285(ah) || 2434 AR_SREV_9330(ah) || 2435 AR_SREV_9565(ah)) 2436 pCap->chip_chainmask = 1; 2437 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2438 pCap->chip_chainmask = 7; 2439 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2440 AR_SREV_9340(ah) || 2441 AR_SREV_9462(ah) || 2442 AR_SREV_9531(ah)) 2443 pCap->chip_chainmask = 3; 2444 else 2445 pCap->chip_chainmask = 7; 2446 2447 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2448 /* 2449 * For AR9271 we will temporarilly uses the rx chainmax as read from 2450 * the EEPROM. 2451 */ 2452 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2453 !(eeval & AR5416_OPFLAGS_11A) && 2454 !(AR_SREV_9271(ah))) 2455 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2456 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2457 else if (AR_SREV_9100(ah)) 2458 pCap->rx_chainmask = 0x7; 2459 else 2460 /* Use rx_chainmask from EEPROM. */ 2461 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2462 2463 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2464 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2465 ah->txchainmask = pCap->tx_chainmask; 2466 ah->rxchainmask = pCap->rx_chainmask; 2467 2468 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2469 2470 /* enable key search for every frame in an aggregate */ 2471 if (AR_SREV_9300_20_OR_LATER(ah)) 2472 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2473 2474 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2475 2476 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2477 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2478 else 2479 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2480 2481 if (AR_SREV_9271(ah)) 2482 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2483 else if (AR_DEVID_7010(ah)) 2484 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2485 else if (AR_SREV_9300_20_OR_LATER(ah)) 2486 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2487 else if (AR_SREV_9287_11_OR_LATER(ah)) 2488 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2489 else if (AR_SREV_9285_12_OR_LATER(ah)) 2490 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2491 else if (AR_SREV_9280_20_OR_LATER(ah)) 2492 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2493 else 2494 pCap->num_gpio_pins = AR_NUM_GPIO; 2495 2496 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2497 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2498 else 2499 pCap->rts_aggr_limit = (8 * 1024); 2500 2501 #ifdef CONFIG_ATH9K_RFKILL 2502 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2503 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2504 ah->rfkill_gpio = 2505 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2506 ah->rfkill_polarity = 2507 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2508 2509 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2510 } 2511 #endif 2512 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2513 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2514 else 2515 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2516 2517 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2518 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2519 else 2520 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2521 2522 if (AR_SREV_9300_20_OR_LATER(ah)) { 2523 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2524 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2525 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2526 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2527 2528 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2529 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2530 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2531 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2532 pCap->txs_len = sizeof(struct ar9003_txs); 2533 } else { 2534 pCap->tx_desc_len = sizeof(struct ath_desc); 2535 if (AR_SREV_9280_20(ah)) 2536 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2537 } 2538 2539 if (AR_SREV_9300_20_OR_LATER(ah)) 2540 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2541 2542 if (AR_SREV_9561(ah)) 2543 ah->ent_mode = 0x3BDA000; 2544 else if (AR_SREV_9300_20_OR_LATER(ah)) 2545 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2546 2547 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2548 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2549 2550 if (AR_SREV_9285(ah)) { 2551 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2552 ant_div_ctl1 = 2553 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2554 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2555 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2556 ath_info(common, "Enable LNA combining\n"); 2557 } 2558 } 2559 } 2560 2561 if (AR_SREV_9300_20_OR_LATER(ah)) { 2562 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2563 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2564 } 2565 2566 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2567 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2568 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2569 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2570 ath_info(common, "Enable LNA combining\n"); 2571 } 2572 } 2573 2574 if (ath9k_hw_dfs_tested(ah)) 2575 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2576 2577 tx_chainmask = pCap->tx_chainmask; 2578 rx_chainmask = pCap->rx_chainmask; 2579 while (tx_chainmask || rx_chainmask) { 2580 if (tx_chainmask & BIT(0)) 2581 pCap->max_txchains++; 2582 if (rx_chainmask & BIT(0)) 2583 pCap->max_rxchains++; 2584 2585 tx_chainmask >>= 1; 2586 rx_chainmask >>= 1; 2587 } 2588 2589 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2590 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2591 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2592 2593 if (AR_SREV_9462_20_OR_LATER(ah)) 2594 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2595 } 2596 2597 if (AR_SREV_9300_20_OR_LATER(ah) && 2598 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2599 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2600 2601 #ifdef CONFIG_ATH9K_WOW 2602 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2603 ah->wow.max_patterns = MAX_NUM_PATTERN; 2604 else 2605 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2606 #endif 2607 2608 return 0; 2609 } 2610 2611 /****************************/ 2612 /* GPIO / RFKILL / Antennae */ 2613 /****************************/ 2614 2615 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2616 u32 gpio, u32 type) 2617 { 2618 int addr; 2619 u32 gpio_shift, tmp; 2620 2621 if (gpio > 11) 2622 addr = AR_GPIO_OUTPUT_MUX3; 2623 else if (gpio > 5) 2624 addr = AR_GPIO_OUTPUT_MUX2; 2625 else 2626 addr = AR_GPIO_OUTPUT_MUX1; 2627 2628 gpio_shift = (gpio % 6) * 5; 2629 2630 if (AR_SREV_9280_20_OR_LATER(ah) 2631 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2632 REG_RMW(ah, addr, (type << gpio_shift), 2633 (0x1f << gpio_shift)); 2634 } else { 2635 tmp = REG_READ(ah, addr); 2636 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2637 tmp &= ~(0x1f << gpio_shift); 2638 tmp |= (type << gpio_shift); 2639 REG_WRITE(ah, addr, tmp); 2640 } 2641 } 2642 2643 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2644 { 2645 u32 gpio_shift; 2646 2647 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2648 2649 if (AR_DEVID_7010(ah)) { 2650 gpio_shift = gpio; 2651 REG_RMW(ah, AR7010_GPIO_OE, 2652 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2653 (AR7010_GPIO_OE_MASK << gpio_shift)); 2654 return; 2655 } 2656 2657 gpio_shift = gpio << 1; 2658 REG_RMW(ah, 2659 AR_GPIO_OE_OUT, 2660 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2661 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2662 } 2663 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2664 2665 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2666 { 2667 #define MS_REG_READ(x, y) \ 2668 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2669 2670 if (gpio >= ah->caps.num_gpio_pins) 2671 return 0xffffffff; 2672 2673 if (AR_DEVID_7010(ah)) { 2674 u32 val; 2675 val = REG_READ(ah, AR7010_GPIO_IN); 2676 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2677 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2678 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2679 AR_GPIO_BIT(gpio)) != 0; 2680 else if (AR_SREV_9271(ah)) 2681 return MS_REG_READ(AR9271, gpio) != 0; 2682 else if (AR_SREV_9287_11_OR_LATER(ah)) 2683 return MS_REG_READ(AR9287, gpio) != 0; 2684 else if (AR_SREV_9285_12_OR_LATER(ah)) 2685 return MS_REG_READ(AR9285, gpio) != 0; 2686 else if (AR_SREV_9280_20_OR_LATER(ah)) 2687 return MS_REG_READ(AR928X, gpio) != 0; 2688 else 2689 return MS_REG_READ(AR, gpio) != 0; 2690 } 2691 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2692 2693 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2694 u32 ah_signal_type) 2695 { 2696 u32 gpio_shift; 2697 2698 if (AR_DEVID_7010(ah)) { 2699 gpio_shift = gpio; 2700 REG_RMW(ah, AR7010_GPIO_OE, 2701 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2702 (AR7010_GPIO_OE_MASK << gpio_shift)); 2703 return; 2704 } 2705 2706 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2707 gpio_shift = 2 * gpio; 2708 REG_RMW(ah, 2709 AR_GPIO_OE_OUT, 2710 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2711 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2712 } 2713 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2714 2715 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2716 { 2717 if (AR_DEVID_7010(ah)) { 2718 val = val ? 0 : 1; 2719 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2720 AR_GPIO_BIT(gpio)); 2721 return; 2722 } 2723 2724 if (AR_SREV_9271(ah)) 2725 val = ~val; 2726 2727 if ((1 << gpio) & AR_GPIO_OE_OUT_MASK) 2728 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2729 AR_GPIO_BIT(gpio)); 2730 else 2731 gpio_set_value(gpio, val & 1); 2732 } 2733 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2734 2735 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label) 2736 { 2737 if (gpio >= ah->caps.num_gpio_pins) 2738 return; 2739 2740 gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label); 2741 } 2742 EXPORT_SYMBOL(ath9k_hw_request_gpio); 2743 2744 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2745 { 2746 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2747 } 2748 EXPORT_SYMBOL(ath9k_hw_setantenna); 2749 2750 /*********************/ 2751 /* General Operation */ 2752 /*********************/ 2753 2754 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2755 { 2756 u32 bits = REG_READ(ah, AR_RX_FILTER); 2757 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2758 2759 if (phybits & AR_PHY_ERR_RADAR) 2760 bits |= ATH9K_RX_FILTER_PHYRADAR; 2761 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2762 bits |= ATH9K_RX_FILTER_PHYERR; 2763 2764 return bits; 2765 } 2766 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2767 2768 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2769 { 2770 u32 phybits; 2771 2772 ENABLE_REGWRITE_BUFFER(ah); 2773 2774 REG_WRITE(ah, AR_RX_FILTER, bits); 2775 2776 phybits = 0; 2777 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2778 phybits |= AR_PHY_ERR_RADAR; 2779 if (bits & ATH9K_RX_FILTER_PHYERR) 2780 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2781 REG_WRITE(ah, AR_PHY_ERR, phybits); 2782 2783 if (phybits) 2784 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2785 else 2786 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2787 2788 REGWRITE_BUFFER_FLUSH(ah); 2789 } 2790 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2791 2792 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2793 { 2794 if (ath9k_hw_mci_is_enabled(ah)) 2795 ar9003_mci_bt_gain_ctrl(ah); 2796 2797 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2798 return false; 2799 2800 ath9k_hw_init_pll(ah, NULL); 2801 ah->htc_reset_init = true; 2802 return true; 2803 } 2804 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2805 2806 bool ath9k_hw_disable(struct ath_hw *ah) 2807 { 2808 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2809 return false; 2810 2811 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2812 return false; 2813 2814 ath9k_hw_init_pll(ah, NULL); 2815 return true; 2816 } 2817 EXPORT_SYMBOL(ath9k_hw_disable); 2818 2819 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2820 { 2821 enum eeprom_param gain_param; 2822 2823 if (IS_CHAN_2GHZ(chan)) 2824 gain_param = EEP_ANTENNA_GAIN_2G; 2825 else 2826 gain_param = EEP_ANTENNA_GAIN_5G; 2827 2828 return ah->eep_ops->get_eeprom(ah, gain_param); 2829 } 2830 2831 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2832 bool test) 2833 { 2834 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2835 struct ieee80211_channel *channel; 2836 int chan_pwr, new_pwr, max_gain; 2837 int ant_gain, ant_reduction = 0; 2838 2839 if (!chan) 2840 return; 2841 2842 channel = chan->chan; 2843 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2844 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2845 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2846 2847 ant_gain = get_antenna_gain(ah, chan); 2848 if (ant_gain > max_gain) 2849 ant_reduction = ant_gain - max_gain; 2850 2851 ah->eep_ops->set_txpower(ah, chan, 2852 ath9k_regd_get_ctl(reg, chan), 2853 ant_reduction, new_pwr, test); 2854 } 2855 2856 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2857 { 2858 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2859 struct ath9k_channel *chan = ah->curchan; 2860 struct ieee80211_channel *channel = chan->chan; 2861 2862 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2863 if (test) 2864 channel->max_power = MAX_RATE_POWER / 2; 2865 2866 ath9k_hw_apply_txpower(ah, chan, test); 2867 2868 if (test) 2869 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2870 } 2871 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2872 2873 void ath9k_hw_setopmode(struct ath_hw *ah) 2874 { 2875 ath9k_hw_set_operating_mode(ah, ah->opmode); 2876 } 2877 EXPORT_SYMBOL(ath9k_hw_setopmode); 2878 2879 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2880 { 2881 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2882 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2883 } 2884 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2885 2886 void ath9k_hw_write_associd(struct ath_hw *ah) 2887 { 2888 struct ath_common *common = ath9k_hw_common(ah); 2889 2890 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2891 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2892 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2893 } 2894 EXPORT_SYMBOL(ath9k_hw_write_associd); 2895 2896 #define ATH9K_MAX_TSF_READ 10 2897 2898 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2899 { 2900 u32 tsf_lower, tsf_upper1, tsf_upper2; 2901 int i; 2902 2903 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2904 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2905 tsf_lower = REG_READ(ah, AR_TSF_L32); 2906 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2907 if (tsf_upper2 == tsf_upper1) 2908 break; 2909 tsf_upper1 = tsf_upper2; 2910 } 2911 2912 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2913 2914 return (((u64)tsf_upper1 << 32) | tsf_lower); 2915 } 2916 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2917 2918 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2919 { 2920 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2921 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2922 } 2923 EXPORT_SYMBOL(ath9k_hw_settsf64); 2924 2925 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2926 { 2927 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2928 AH_TSF_WRITE_TIMEOUT)) 2929 ath_dbg(ath9k_hw_common(ah), RESET, 2930 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2931 2932 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2933 } 2934 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2935 2936 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2937 { 2938 if (set) 2939 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2940 else 2941 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2942 } 2943 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2944 2945 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2946 { 2947 u32 macmode; 2948 2949 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2950 macmode = AR_2040_JOINED_RX_CLEAR; 2951 else 2952 macmode = 0; 2953 2954 REG_WRITE(ah, AR_2040_MODE, macmode); 2955 } 2956 2957 /* HW Generic timers configuration */ 2958 2959 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2960 { 2961 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2962 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2963 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2964 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2965 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2969 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2970 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2971 AR_NDP2_TIMER_MODE, 0x0002}, 2972 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2973 AR_NDP2_TIMER_MODE, 0x0004}, 2974 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2975 AR_NDP2_TIMER_MODE, 0x0008}, 2976 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2977 AR_NDP2_TIMER_MODE, 0x0010}, 2978 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2979 AR_NDP2_TIMER_MODE, 0x0020}, 2980 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2981 AR_NDP2_TIMER_MODE, 0x0040}, 2982 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2983 AR_NDP2_TIMER_MODE, 0x0080} 2984 }; 2985 2986 /* HW generic timer primitives */ 2987 2988 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2989 { 2990 return REG_READ(ah, AR_TSF_L32); 2991 } 2992 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2993 2994 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 2995 { 2996 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2997 2998 if (timer_table->tsf2_enabled) { 2999 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 3000 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 3001 } 3002 } 3003 3004 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3005 void (*trigger)(void *), 3006 void (*overflow)(void *), 3007 void *arg, 3008 u8 timer_index) 3009 { 3010 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3011 struct ath_gen_timer *timer; 3012 3013 if ((timer_index < AR_FIRST_NDP_TIMER) || 3014 (timer_index >= ATH_MAX_GEN_TIMER)) 3015 return NULL; 3016 3017 if ((timer_index > AR_FIRST_NDP_TIMER) && 3018 !AR_SREV_9300_20_OR_LATER(ah)) 3019 return NULL; 3020 3021 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3022 if (timer == NULL) 3023 return NULL; 3024 3025 /* allocate a hardware generic timer slot */ 3026 timer_table->timers[timer_index] = timer; 3027 timer->index = timer_index; 3028 timer->trigger = trigger; 3029 timer->overflow = overflow; 3030 timer->arg = arg; 3031 3032 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 3033 timer_table->tsf2_enabled = true; 3034 ath9k_hw_gen_timer_start_tsf2(ah); 3035 } 3036 3037 return timer; 3038 } 3039 EXPORT_SYMBOL(ath_gen_timer_alloc); 3040 3041 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3042 struct ath_gen_timer *timer, 3043 u32 timer_next, 3044 u32 timer_period) 3045 { 3046 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3047 u32 mask = 0; 3048 3049 timer_table->timer_mask |= BIT(timer->index); 3050 3051 /* 3052 * Program generic timer registers 3053 */ 3054 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3055 timer_next); 3056 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3057 timer_period); 3058 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3059 gen_tmr_configuration[timer->index].mode_mask); 3060 3061 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3062 /* 3063 * Starting from AR9462, each generic timer can select which tsf 3064 * to use. But we still follow the old rule, 0 - 7 use tsf and 3065 * 8 - 15 use tsf2. 3066 */ 3067 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3068 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3069 (1 << timer->index)); 3070 else 3071 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3072 (1 << timer->index)); 3073 } 3074 3075 if (timer->trigger) 3076 mask |= SM(AR_GENTMR_BIT(timer->index), 3077 AR_IMR_S5_GENTIMER_TRIG); 3078 if (timer->overflow) 3079 mask |= SM(AR_GENTMR_BIT(timer->index), 3080 AR_IMR_S5_GENTIMER_THRESH); 3081 3082 REG_SET_BIT(ah, AR_IMR_S5, mask); 3083 3084 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3085 ah->imask |= ATH9K_INT_GENTIMER; 3086 ath9k_hw_set_interrupts(ah); 3087 } 3088 } 3089 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3090 3091 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3092 { 3093 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3094 3095 /* Clear generic timer enable bits. */ 3096 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3097 gen_tmr_configuration[timer->index].mode_mask); 3098 3099 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3100 /* 3101 * Need to switch back to TSF if it was using TSF2. 3102 */ 3103 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3104 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3105 (1 << timer->index)); 3106 } 3107 } 3108 3109 /* Disable both trigger and thresh interrupt masks */ 3110 REG_CLR_BIT(ah, AR_IMR_S5, 3111 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3112 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3113 3114 timer_table->timer_mask &= ~BIT(timer->index); 3115 3116 if (timer_table->timer_mask == 0) { 3117 ah->imask &= ~ATH9K_INT_GENTIMER; 3118 ath9k_hw_set_interrupts(ah); 3119 } 3120 } 3121 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3122 3123 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3124 { 3125 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3126 3127 /* free the hardware generic timer slot */ 3128 timer_table->timers[timer->index] = NULL; 3129 kfree(timer); 3130 } 3131 EXPORT_SYMBOL(ath_gen_timer_free); 3132 3133 /* 3134 * Generic Timer Interrupts handling 3135 */ 3136 void ath_gen_timer_isr(struct ath_hw *ah) 3137 { 3138 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3139 struct ath_gen_timer *timer; 3140 unsigned long trigger_mask, thresh_mask; 3141 unsigned int index; 3142 3143 /* get hardware generic timer interrupt status */ 3144 trigger_mask = ah->intr_gen_timer_trigger; 3145 thresh_mask = ah->intr_gen_timer_thresh; 3146 trigger_mask &= timer_table->timer_mask; 3147 thresh_mask &= timer_table->timer_mask; 3148 3149 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3150 timer = timer_table->timers[index]; 3151 if (!timer) 3152 continue; 3153 if (!timer->overflow) 3154 continue; 3155 3156 trigger_mask &= ~BIT(index); 3157 timer->overflow(timer->arg); 3158 } 3159 3160 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3161 timer = timer_table->timers[index]; 3162 if (!timer) 3163 continue; 3164 if (!timer->trigger) 3165 continue; 3166 timer->trigger(timer->arg); 3167 } 3168 } 3169 EXPORT_SYMBOL(ath_gen_timer_isr); 3170 3171 /********/ 3172 /* HTC */ 3173 /********/ 3174 3175 static struct { 3176 u32 version; 3177 const char * name; 3178 } ath_mac_bb_names[] = { 3179 /* Devices with external radios */ 3180 { AR_SREV_VERSION_5416_PCI, "5416" }, 3181 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3182 { AR_SREV_VERSION_9100, "9100" }, 3183 { AR_SREV_VERSION_9160, "9160" }, 3184 /* Single-chip solutions */ 3185 { AR_SREV_VERSION_9280, "9280" }, 3186 { AR_SREV_VERSION_9285, "9285" }, 3187 { AR_SREV_VERSION_9287, "9287" }, 3188 { AR_SREV_VERSION_9271, "9271" }, 3189 { AR_SREV_VERSION_9300, "9300" }, 3190 { AR_SREV_VERSION_9330, "9330" }, 3191 { AR_SREV_VERSION_9340, "9340" }, 3192 { AR_SREV_VERSION_9485, "9485" }, 3193 { AR_SREV_VERSION_9462, "9462" }, 3194 { AR_SREV_VERSION_9550, "9550" }, 3195 { AR_SREV_VERSION_9565, "9565" }, 3196 { AR_SREV_VERSION_9531, "9531" }, 3197 { AR_SREV_VERSION_9561, "9561" }, 3198 }; 3199 3200 /* For devices with external radios */ 3201 static struct { 3202 u16 version; 3203 const char * name; 3204 } ath_rf_names[] = { 3205 { 0, "5133" }, 3206 { AR_RAD5133_SREV_MAJOR, "5133" }, 3207 { AR_RAD5122_SREV_MAJOR, "5122" }, 3208 { AR_RAD2133_SREV_MAJOR, "2133" }, 3209 { AR_RAD2122_SREV_MAJOR, "2122" } 3210 }; 3211 3212 /* 3213 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3214 */ 3215 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3216 { 3217 int i; 3218 3219 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3220 if (ath_mac_bb_names[i].version == mac_bb_version) { 3221 return ath_mac_bb_names[i].name; 3222 } 3223 } 3224 3225 return "????"; 3226 } 3227 3228 /* 3229 * Return the RF name. "????" is returned if the RF is unknown. 3230 * Used for devices with external radios. 3231 */ 3232 static const char *ath9k_hw_rf_name(u16 rf_version) 3233 { 3234 int i; 3235 3236 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3237 if (ath_rf_names[i].version == rf_version) { 3238 return ath_rf_names[i].name; 3239 } 3240 } 3241 3242 return "????"; 3243 } 3244 3245 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3246 { 3247 int used; 3248 3249 /* chipsets >= AR9280 are single-chip */ 3250 if (AR_SREV_9280_20_OR_LATER(ah)) { 3251 used = scnprintf(hw_name, len, 3252 "Atheros AR%s Rev:%x", 3253 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3254 ah->hw_version.macRev); 3255 } 3256 else { 3257 used = scnprintf(hw_name, len, 3258 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3259 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3260 ah->hw_version.macRev, 3261 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3262 & AR_RADIO_SREV_MAJOR)), 3263 ah->hw_version.phyRev); 3264 } 3265 3266 hw_name[used] = '\0'; 3267 } 3268 EXPORT_SYMBOL(ath9k_hw_name); 3269