1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <linux/gpio.h> 24 #include <asm/unaligned.h> 25 26 #include "hw.h" 27 #include "hw-ops.h" 28 #include "ar9003_mac.h" 29 #include "ar9003_mci.h" 30 #include "ar9003_phy.h" 31 #include "ath9k.h" 32 33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 41 { 42 struct ath_common *common = ath9k_hw_common(ah); 43 struct ath9k_channel *chan = ah->curchan; 44 unsigned int clockrate; 45 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 48 clockrate = 117; 49 else if (!chan) /* should really check for CCK instead */ 50 clockrate = ATH9K_CLOCK_RATE_CCK; 51 else if (IS_CHAN_2GHZ(chan)) 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 55 else 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 57 58 if (chan) { 59 if (IS_CHAN_HT40(chan)) 60 clockrate *= 2; 61 if (IS_CHAN_HALF_RATE(chan)) 62 clockrate /= 2; 63 if (IS_CHAN_QUARTER_RATE(chan)) 64 clockrate /= 4; 65 } 66 67 common->clockrate = clockrate; 68 } 69 70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 71 { 72 struct ath_common *common = ath9k_hw_common(ah); 73 74 return usecs * common->clockrate; 75 } 76 77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 78 { 79 int i; 80 81 BUG_ON(timeout < AH_TIME_QUANTUM); 82 83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 84 if ((REG_READ(ah, reg) & mask) == val) 85 return true; 86 87 udelay(AH_TIME_QUANTUM); 88 } 89 90 ath_dbg(ath9k_hw_common(ah), ANY, 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 92 timeout, reg, REG_READ(ah, reg), mask, val); 93 94 return false; 95 } 96 EXPORT_SYMBOL(ath9k_hw_wait); 97 98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 99 int hw_delay) 100 { 101 hw_delay /= 10; 102 103 if (IS_CHAN_HALF_RATE(chan)) 104 hw_delay *= 2; 105 else if (IS_CHAN_QUARTER_RATE(chan)) 106 hw_delay *= 4; 107 108 udelay(hw_delay + BASE_ACTIVATE_DELAY); 109 } 110 111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 112 int column, unsigned int *writecnt) 113 { 114 int r; 115 116 ENABLE_REGWRITE_BUFFER(ah); 117 for (r = 0; r < array->ia_rows; r++) { 118 REG_WRITE(ah, INI_RA(array, r, 0), 119 INI_RA(array, r, column)); 120 DO_DELAY(*writecnt); 121 } 122 REGWRITE_BUFFER_FLUSH(ah); 123 } 124 125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) 126 { 127 u32 *tmp_reg_list, *tmp_data; 128 int i; 129 130 tmp_reg_list = kmalloc_array(size, sizeof(u32), GFP_KERNEL); 131 if (!tmp_reg_list) { 132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); 133 return; 134 } 135 136 tmp_data = kmalloc_array(size, sizeof(u32), GFP_KERNEL); 137 if (!tmp_data) { 138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); 139 goto error_tmp_data; 140 } 141 142 for (i = 0; i < size; i++) 143 tmp_reg_list[i] = array[i][0]; 144 145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); 146 147 for (i = 0; i < size; i++) 148 array[i][1] = tmp_data[i]; 149 150 kfree(tmp_data); 151 error_tmp_data: 152 kfree(tmp_reg_list); 153 } 154 155 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 156 { 157 u32 retval; 158 int i; 159 160 for (i = 0, retval = 0; i < n; i++) { 161 retval = (retval << 1) | (val & 1); 162 val >>= 1; 163 } 164 return retval; 165 } 166 167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 168 u8 phy, int kbps, 169 u32 frameLen, u16 rateix, 170 bool shortPreamble) 171 { 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 173 174 if (kbps == 0) 175 return 0; 176 177 switch (phy) { 178 case WLAN_RC_PHY_CCK: 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 180 if (shortPreamble) 181 phyTime >>= 1; 182 numBits = frameLen << 3; 183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 184 break; 185 case WLAN_RC_PHY_OFDM: 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 187 bitsPerSymbol = 188 ((kbps >> 2) * OFDM_SYMBOL_TIME_QUARTER) / 1000; 189 numBits = OFDM_PLCP_BITS + (frameLen << 3); 190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 191 txTime = OFDM_SIFS_TIME_QUARTER 192 + OFDM_PREAMBLE_TIME_QUARTER 193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 194 } else if (ah->curchan && 195 IS_CHAN_HALF_RATE(ah->curchan)) { 196 bitsPerSymbol = 197 ((kbps >> 1) * OFDM_SYMBOL_TIME_HALF) / 1000; 198 numBits = OFDM_PLCP_BITS + (frameLen << 3); 199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 200 txTime = OFDM_SIFS_TIME_HALF + 201 OFDM_PREAMBLE_TIME_HALF 202 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 203 } else { 204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 205 numBits = OFDM_PLCP_BITS + (frameLen << 3); 206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 208 + (numSymbols * OFDM_SYMBOL_TIME); 209 } 210 break; 211 default: 212 ath_err(ath9k_hw_common(ah), 213 "Unknown phy %u (rate ix %u)\n", phy, rateix); 214 txTime = 0; 215 break; 216 } 217 218 return txTime; 219 } 220 EXPORT_SYMBOL(ath9k_hw_computetxtime); 221 222 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 223 struct ath9k_channel *chan, 224 struct chan_centers *centers) 225 { 226 int8_t extoff; 227 228 if (!IS_CHAN_HT40(chan)) { 229 centers->ctl_center = centers->ext_center = 230 centers->synth_center = chan->channel; 231 return; 232 } 233 234 if (IS_CHAN_HT40PLUS(chan)) { 235 centers->synth_center = 236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 237 extoff = 1; 238 } else { 239 centers->synth_center = 240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 241 extoff = -1; 242 } 243 244 centers->ctl_center = 245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 246 /* 25 MHz spacing is supported by hw but not on upper layers */ 247 centers->ext_center = 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 249 } 250 251 /******************/ 252 /* Chip Revisions */ 253 /******************/ 254 255 static bool ath9k_hw_read_revisions(struct ath_hw *ah) 256 { 257 u32 srev; 258 u32 val; 259 260 if (ah->get_mac_revision) 261 ah->hw_version.macRev = ah->get_mac_revision(); 262 263 switch (ah->hw_version.devid) { 264 case AR5416_AR9100_DEVID: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 266 break; 267 case AR9300_DEVID_AR9330: 268 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 269 if (!ah->get_mac_revision) { 270 val = REG_READ(ah, AR_SREV); 271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 272 } 273 return true; 274 case AR9300_DEVID_AR9340: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 276 return true; 277 case AR9300_DEVID_QCA955X: 278 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 279 return true; 280 case AR9300_DEVID_AR953X: 281 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 282 return true; 283 case AR9300_DEVID_QCA956X: 284 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 285 return true; 286 } 287 288 srev = REG_READ(ah, AR_SREV); 289 290 if (srev == -EIO) { 291 ath_err(ath9k_hw_common(ah), 292 "Failed to read SREV register"); 293 return false; 294 } 295 296 val = srev & AR_SREV_ID; 297 298 if (val == 0xFF) { 299 val = srev; 300 ah->hw_version.macVersion = 301 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 302 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 303 304 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 305 ah->is_pciexpress = true; 306 else 307 ah->is_pciexpress = (val & 308 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 309 } else { 310 if (!AR_SREV_9100(ah)) 311 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 312 313 ah->hw_version.macRev = val & AR_SREV_REVISION; 314 315 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 316 ah->is_pciexpress = true; 317 } 318 319 return true; 320 } 321 322 /************************************/ 323 /* HW Attach, Detach, Init Routines */ 324 /************************************/ 325 326 static void ath9k_hw_disablepcie(struct ath_hw *ah) 327 { 328 if (!AR_SREV_5416(ah)) 329 return; 330 331 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 332 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 333 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 334 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 335 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 336 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 337 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 338 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 339 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 340 341 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 342 } 343 344 /* This should work for all families including legacy */ 345 static bool ath9k_hw_chip_test(struct ath_hw *ah) 346 { 347 struct ath_common *common = ath9k_hw_common(ah); 348 u32 regAddr[2] = { AR_STA_ID0 }; 349 u32 regHold[2]; 350 static const u32 patternData[4] = { 351 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 352 }; 353 int i, j, loop_max; 354 355 if (!AR_SREV_9300_20_OR_LATER(ah)) { 356 loop_max = 2; 357 regAddr[1] = AR_PHY_BASE + (8 << 2); 358 } else 359 loop_max = 1; 360 361 for (i = 0; i < loop_max; i++) { 362 u32 addr = regAddr[i]; 363 u32 wrData, rdData; 364 365 regHold[i] = REG_READ(ah, addr); 366 for (j = 0; j < 0x100; j++) { 367 wrData = (j << 16) | j; 368 REG_WRITE(ah, addr, wrData); 369 rdData = REG_READ(ah, addr); 370 if (rdData != wrData) { 371 ath_err(common, 372 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 373 addr, wrData, rdData); 374 return false; 375 } 376 } 377 for (j = 0; j < 4; j++) { 378 wrData = patternData[j]; 379 REG_WRITE(ah, addr, wrData); 380 rdData = REG_READ(ah, addr); 381 if (wrData != rdData) { 382 ath_err(common, 383 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 384 addr, wrData, rdData); 385 return false; 386 } 387 } 388 REG_WRITE(ah, regAddr[i], regHold[i]); 389 } 390 udelay(100); 391 392 return true; 393 } 394 395 static void ath9k_hw_init_config(struct ath_hw *ah) 396 { 397 struct ath_common *common = ath9k_hw_common(ah); 398 399 ah->config.dma_beacon_response_time = 1; 400 ah->config.sw_beacon_response_time = 6; 401 ah->config.cwm_ignore_extcca = false; 402 ah->config.analog_shiftreg = 1; 403 404 ah->config.rx_intr_mitigation = true; 405 406 if (AR_SREV_9300_20_OR_LATER(ah)) { 407 ah->config.rimt_last = 500; 408 ah->config.rimt_first = 2000; 409 } else { 410 ah->config.rimt_last = 250; 411 ah->config.rimt_first = 700; 412 } 413 414 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 415 ah->config.pll_pwrsave = 7; 416 417 /* 418 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 420 * This means we use it for all AR5416 devices, and the few 421 * minor PCI AR9280 devices out there. 422 * 423 * Serialization is required because these devices do not handle 424 * well the case of two concurrent reads/writes due to the latency 425 * involved. During one read/write another read/write can be issued 426 * on another CPU while the previous read/write may still be working 427 * on our hardware, if we hit this case the hardware poops in a loop. 428 * We prevent this by serializing reads and writes. 429 * 430 * This issue is not present on PCI-Express devices or pre-AR5416 431 * devices (legacy, 802.11abg). 432 */ 433 if (num_possible_cpus() > 1) 434 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 435 436 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 437 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 438 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 439 !ah->is_pciexpress)) { 440 ah->config.serialize_regmode = SER_REG_MODE_ON; 441 } else { 442 ah->config.serialize_regmode = SER_REG_MODE_OFF; 443 } 444 } 445 446 ath_dbg(common, RESET, "serialize_regmode is %d\n", 447 ah->config.serialize_regmode); 448 449 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 450 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 451 else 452 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 453 } 454 455 static void ath9k_hw_init_defaults(struct ath_hw *ah) 456 { 457 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 458 459 regulatory->country_code = CTRY_DEFAULT; 460 regulatory->power_limit = MAX_COMBINED_POWER; 461 462 ah->hw_version.magic = AR5416_MAGIC; 463 ah->hw_version.subvendorid = 0; 464 465 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 466 AR_STA_ID1_MCAST_KSRCH; 467 if (AR_SREV_9100(ah)) 468 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 469 470 ah->slottime = 9; 471 ah->globaltxtimeout = (u32) -1; 472 ah->power_mode = ATH9K_PM_UNDEFINED; 473 ah->htc_reset_init = true; 474 475 ah->tpc_enabled = false; 476 477 ah->ani_function = ATH9K_ANI_ALL; 478 if (!AR_SREV_9300_20_OR_LATER(ah)) 479 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 480 481 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 482 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 483 else 484 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 485 } 486 487 static void ath9k_hw_init_macaddr(struct ath_hw *ah) 488 { 489 struct ath_common *common = ath9k_hw_common(ah); 490 int i; 491 u16 eeval; 492 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 493 494 /* MAC address may already be loaded via ath9k_platform_data */ 495 if (is_valid_ether_addr(common->macaddr)) 496 return; 497 498 for (i = 0; i < 3; i++) { 499 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 500 common->macaddr[2 * i] = eeval >> 8; 501 common->macaddr[2 * i + 1] = eeval & 0xff; 502 } 503 504 if (is_valid_ether_addr(common->macaddr)) 505 return; 506 507 ath_err(common, "eeprom contains invalid mac address: %pM\n", 508 common->macaddr); 509 510 eth_random_addr(common->macaddr); 511 ath_err(common, "random mac address will be used: %pM\n", 512 common->macaddr); 513 514 return; 515 } 516 517 static int ath9k_hw_post_init(struct ath_hw *ah) 518 { 519 struct ath_common *common = ath9k_hw_common(ah); 520 int ecode; 521 522 if (common->bus_ops->ath_bus_type != ATH_USB) { 523 if (!ath9k_hw_chip_test(ah)) 524 return -ENODEV; 525 } 526 527 if (!AR_SREV_9300_20_OR_LATER(ah)) { 528 ecode = ar9002_hw_rf_claim(ah); 529 if (ecode != 0) 530 return ecode; 531 } 532 533 ecode = ath9k_hw_eeprom_init(ah); 534 if (ecode != 0) 535 return ecode; 536 537 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 538 ah->eep_ops->get_eeprom_ver(ah), 539 ah->eep_ops->get_eeprom_rev(ah)); 540 541 ath9k_hw_ani_init(ah); 542 543 /* 544 * EEPROM needs to be initialized before we do this. 545 * This is required for regulatory compliance. 546 */ 547 if (AR_SREV_9300_20_OR_LATER(ah)) { 548 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 549 if ((regdmn & 0xF0) == CTL_FCC) { 550 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 551 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 552 } 553 } 554 555 return 0; 556 } 557 558 static int ath9k_hw_attach_ops(struct ath_hw *ah) 559 { 560 if (!AR_SREV_9300_20_OR_LATER(ah)) 561 return ar9002_hw_attach_ops(ah); 562 563 ar9003_hw_attach_ops(ah); 564 return 0; 565 } 566 567 /* Called for all hardware families */ 568 static int __ath9k_hw_init(struct ath_hw *ah) 569 { 570 struct ath_common *common = ath9k_hw_common(ah); 571 int r = 0; 572 573 if (!ath9k_hw_read_revisions(ah)) { 574 ath_err(common, "Could not read hardware revisions"); 575 return -EOPNOTSUPP; 576 } 577 578 switch (ah->hw_version.macVersion) { 579 case AR_SREV_VERSION_5416_PCI: 580 case AR_SREV_VERSION_5416_PCIE: 581 case AR_SREV_VERSION_9160: 582 case AR_SREV_VERSION_9100: 583 case AR_SREV_VERSION_9280: 584 case AR_SREV_VERSION_9285: 585 case AR_SREV_VERSION_9287: 586 case AR_SREV_VERSION_9271: 587 case AR_SREV_VERSION_9300: 588 case AR_SREV_VERSION_9330: 589 case AR_SREV_VERSION_9485: 590 case AR_SREV_VERSION_9340: 591 case AR_SREV_VERSION_9462: 592 case AR_SREV_VERSION_9550: 593 case AR_SREV_VERSION_9565: 594 case AR_SREV_VERSION_9531: 595 case AR_SREV_VERSION_9561: 596 break; 597 default: 598 ath_err(common, 599 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 600 ah->hw_version.macVersion, ah->hw_version.macRev); 601 return -EOPNOTSUPP; 602 } 603 604 /* 605 * Read back AR_WA into a permanent copy and set bits 14 and 17. 606 * We need to do this to avoid RMW of this register. We cannot 607 * read the reg when chip is asleep. 608 */ 609 if (AR_SREV_9300_20_OR_LATER(ah)) { 610 ah->WARegVal = REG_READ(ah, AR_WA); 611 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 612 AR_WA_ASPM_TIMER_BASED_DISABLE); 613 } 614 615 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 616 ath_err(common, "Couldn't reset chip\n"); 617 return -EIO; 618 } 619 620 if (AR_SREV_9565(ah)) { 621 ah->WARegVal |= AR_WA_BIT22; 622 REG_WRITE(ah, AR_WA, ah->WARegVal); 623 } 624 625 ath9k_hw_init_defaults(ah); 626 ath9k_hw_init_config(ah); 627 628 r = ath9k_hw_attach_ops(ah); 629 if (r) 630 return r; 631 632 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 633 ath_err(common, "Couldn't wakeup chip\n"); 634 return -EIO; 635 } 636 637 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 638 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 639 ah->is_pciexpress = false; 640 641 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 642 ath9k_hw_init_cal_settings(ah); 643 644 if (!ah->is_pciexpress) 645 ath9k_hw_disablepcie(ah); 646 647 r = ath9k_hw_post_init(ah); 648 if (r) 649 return r; 650 651 ath9k_hw_init_mode_gain_regs(ah); 652 r = ath9k_hw_fill_cap_info(ah); 653 if (r) 654 return r; 655 656 ath9k_hw_init_macaddr(ah); 657 ath9k_hw_init_hang_checks(ah); 658 659 common->state = ATH_HW_INITIALIZED; 660 661 return 0; 662 } 663 664 int ath9k_hw_init(struct ath_hw *ah) 665 { 666 int ret; 667 struct ath_common *common = ath9k_hw_common(ah); 668 669 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 670 switch (ah->hw_version.devid) { 671 case AR5416_DEVID_PCI: 672 case AR5416_DEVID_PCIE: 673 case AR5416_AR9100_DEVID: 674 case AR9160_DEVID_PCI: 675 case AR9280_DEVID_PCI: 676 case AR9280_DEVID_PCIE: 677 case AR9285_DEVID_PCIE: 678 case AR9287_DEVID_PCI: 679 case AR9287_DEVID_PCIE: 680 case AR2427_DEVID_PCIE: 681 case AR9300_DEVID_PCIE: 682 case AR9300_DEVID_AR9485_PCIE: 683 case AR9300_DEVID_AR9330: 684 case AR9300_DEVID_AR9340: 685 case AR9300_DEVID_QCA955X: 686 case AR9300_DEVID_AR9580: 687 case AR9300_DEVID_AR9462: 688 case AR9485_DEVID_AR1111: 689 case AR9300_DEVID_AR9565: 690 case AR9300_DEVID_AR953X: 691 case AR9300_DEVID_QCA956X: 692 break; 693 default: 694 if (common->bus_ops->ath_bus_type == ATH_USB) 695 break; 696 ath_err(common, "Hardware device ID 0x%04x not supported\n", 697 ah->hw_version.devid); 698 return -EOPNOTSUPP; 699 } 700 701 ret = __ath9k_hw_init(ah); 702 if (ret) { 703 ath_err(common, 704 "Unable to initialize hardware; initialization status: %d\n", 705 ret); 706 return ret; 707 } 708 709 ath_dynack_init(ah); 710 711 return 0; 712 } 713 EXPORT_SYMBOL(ath9k_hw_init); 714 715 static void ath9k_hw_init_qos(struct ath_hw *ah) 716 { 717 ENABLE_REGWRITE_BUFFER(ah); 718 719 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 720 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 721 722 REG_WRITE(ah, AR_QOS_NO_ACK, 723 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 724 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 725 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 726 727 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 728 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 729 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 730 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 731 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 732 733 REGWRITE_BUFFER_FLUSH(ah); 734 } 735 736 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 737 { 738 struct ath_common *common = ath9k_hw_common(ah); 739 int i = 0; 740 741 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 742 udelay(100); 743 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 744 745 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 746 747 udelay(100); 748 749 if (WARN_ON_ONCE(i >= 100)) { 750 ath_err(common, "PLL4 measurement not done\n"); 751 break; 752 } 753 754 i++; 755 } 756 757 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 758 } 759 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 760 761 static void ath9k_hw_init_pll(struct ath_hw *ah, 762 struct ath9k_channel *chan) 763 { 764 u32 pll; 765 766 pll = ath9k_hw_compute_pll_control(ah, chan); 767 768 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 769 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 771 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 773 AR_CH0_DPLL2_KD, 0x40); 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 775 AR_CH0_DPLL2_KI, 0x4); 776 777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 778 AR_CH0_BB_DPLL1_REFDIV, 0x5); 779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 780 AR_CH0_BB_DPLL1_NINI, 0x58); 781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 782 AR_CH0_BB_DPLL1_NFRAC, 0x0); 783 784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 785 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 787 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 789 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 790 791 /* program BB PLL phase_shift to 0x6 */ 792 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 793 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 794 795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 796 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 797 udelay(1000); 798 } else if (AR_SREV_9330(ah)) { 799 u32 ddr_dpll2, pll_control2, kd; 800 801 if (ah->is_clk_25mhz) { 802 ddr_dpll2 = 0x18e82f01; 803 pll_control2 = 0xe04a3d; 804 kd = 0x1d; 805 } else { 806 ddr_dpll2 = 0x19e82f01; 807 pll_control2 = 0x886666; 808 kd = 0x3d; 809 } 810 811 /* program DDR PLL ki and kd value */ 812 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 813 814 /* program DDR PLL phase_shift */ 815 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 816 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 817 818 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 819 pll | AR_RTC_9300_PLL_BYPASS); 820 udelay(1000); 821 822 /* program refdiv, nint, frac to RTC register */ 823 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 824 825 /* program BB PLL kd and ki value */ 826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 828 829 /* program BB PLL phase_shift */ 830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 831 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 832 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 833 AR_SREV_9561(ah)) { 834 u32 regval, pll2_divint, pll2_divfrac, refdiv; 835 836 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 837 pll | AR_RTC_9300_SOC_PLL_BYPASS); 838 udelay(1000); 839 840 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 841 udelay(100); 842 843 if (ah->is_clk_25mhz) { 844 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 845 pll2_divint = 0x1c; 846 pll2_divfrac = 0xa3d2; 847 refdiv = 1; 848 } else { 849 pll2_divint = 0x54; 850 pll2_divfrac = 0x1eb85; 851 refdiv = 3; 852 } 853 } else { 854 if (AR_SREV_9340(ah)) { 855 pll2_divint = 88; 856 pll2_divfrac = 0; 857 refdiv = 5; 858 } else { 859 pll2_divint = 0x11; 860 pll2_divfrac = (AR_SREV_9531(ah) || 861 AR_SREV_9561(ah)) ? 862 0x26665 : 0x26666; 863 refdiv = 1; 864 } 865 } 866 867 regval = REG_READ(ah, AR_PHY_PLL_MODE); 868 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 869 regval |= (0x1 << 22); 870 else 871 regval |= (0x1 << 16); 872 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 873 udelay(100); 874 875 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 876 (pll2_divint << 18) | pll2_divfrac); 877 udelay(100); 878 879 regval = REG_READ(ah, AR_PHY_PLL_MODE); 880 if (AR_SREV_9340(ah)) 881 regval = (regval & 0x80071fff) | 882 (0x1 << 30) | 883 (0x1 << 13) | 884 (0x4 << 26) | 885 (0x18 << 19); 886 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 887 regval = (regval & 0x01c00fff) | 888 (0x1 << 31) | 889 (0x2 << 29) | 890 (0xa << 25) | 891 (0x1 << 19); 892 893 if (AR_SREV_9531(ah)) 894 regval |= (0x6 << 12); 895 } else 896 regval = (regval & 0x80071fff) | 897 (0x3 << 30) | 898 (0x1 << 13) | 899 (0x4 << 26) | 900 (0x60 << 19); 901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 902 903 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 904 REG_WRITE(ah, AR_PHY_PLL_MODE, 905 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 906 else 907 REG_WRITE(ah, AR_PHY_PLL_MODE, 908 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 909 910 udelay(1000); 911 } 912 913 if (AR_SREV_9565(ah)) 914 pll |= 0x40000; 915 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 916 917 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 918 AR_SREV_9550(ah)) 919 udelay(1000); 920 921 /* Switch the core clock for ar9271 to 117Mhz */ 922 if (AR_SREV_9271(ah)) { 923 udelay(500); 924 REG_WRITE(ah, 0x50040, 0x304); 925 } 926 927 udelay(RTC_PLL_SETTLE_DELAY); 928 929 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 930 } 931 932 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 933 enum nl80211_iftype opmode) 934 { 935 u32 sync_default = AR_INTR_SYNC_DEFAULT; 936 u32 imr_reg = AR_IMR_TXERR | 937 AR_IMR_TXURN | 938 AR_IMR_RXERR | 939 AR_IMR_RXORN | 940 AR_IMR_BCNMISC; 941 u32 msi_cfg = 0; 942 943 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 944 AR_SREV_9561(ah)) 945 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 946 947 if (AR_SREV_9300_20_OR_LATER(ah)) { 948 imr_reg |= AR_IMR_RXOK_HP; 949 if (ah->config.rx_intr_mitigation) { 950 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 951 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 952 } else { 953 imr_reg |= AR_IMR_RXOK_LP; 954 msi_cfg |= AR_INTCFG_MSI_RXOK; 955 } 956 } else { 957 if (ah->config.rx_intr_mitigation) { 958 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 959 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 960 } else { 961 imr_reg |= AR_IMR_RXOK; 962 msi_cfg |= AR_INTCFG_MSI_RXOK; 963 } 964 } 965 966 if (ah->config.tx_intr_mitigation) { 967 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 968 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR; 969 } else { 970 imr_reg |= AR_IMR_TXOK; 971 msi_cfg |= AR_INTCFG_MSI_TXOK; 972 } 973 974 ENABLE_REGWRITE_BUFFER(ah); 975 976 REG_WRITE(ah, AR_IMR, imr_reg); 977 ah->imrs2_reg |= AR_IMR_S2_GTT; 978 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 979 980 if (ah->msi_enabled) { 981 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); 982 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; 983 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; 984 REG_WRITE(ah, AR_INTCFG, msi_cfg); 985 ath_dbg(ath9k_hw_common(ah), ANY, 986 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n", 987 REG_READ(ah, AR_INTCFG), msi_cfg); 988 } 989 990 if (!AR_SREV_9100(ah)) { 991 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 992 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 993 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 994 } 995 996 REGWRITE_BUFFER_FLUSH(ah); 997 998 if (AR_SREV_9300_20_OR_LATER(ah)) { 999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 1000 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 1002 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 1003 } 1004 } 1005 1006 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 1007 { 1008 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 1009 val = min(val, (u32) 0xFFFF); 1010 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 1011 } 1012 1013 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1014 { 1015 u32 val = ath9k_hw_mac_to_clks(ah, us); 1016 val = min(val, (u32) 0xFFFF); 1017 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1018 } 1019 1020 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1021 { 1022 u32 val = ath9k_hw_mac_to_clks(ah, us); 1023 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1024 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1025 } 1026 1027 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1028 { 1029 u32 val = ath9k_hw_mac_to_clks(ah, us); 1030 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1031 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1032 } 1033 1034 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1035 { 1036 if (tu > 0xFFFF) { 1037 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1038 tu); 1039 ah->globaltxtimeout = (u32) -1; 1040 return false; 1041 } else { 1042 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1043 ah->globaltxtimeout = tu; 1044 return true; 1045 } 1046 } 1047 1048 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1049 { 1050 struct ath_common *common = ath9k_hw_common(ah); 1051 const struct ath9k_channel *chan = ah->curchan; 1052 int acktimeout, ctstimeout, ack_offset = 0; 1053 int slottime; 1054 int sifstime; 1055 int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0; 1056 u32 reg; 1057 1058 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1059 ah->misc_mode); 1060 1061 if (!chan) 1062 return; 1063 1064 if (ah->misc_mode != 0) 1065 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1066 1067 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1068 rx_lat = 41; 1069 else 1070 rx_lat = 37; 1071 tx_lat = 54; 1072 1073 if (IS_CHAN_5GHZ(chan)) 1074 sifstime = 16; 1075 else 1076 sifstime = 10; 1077 1078 if (IS_CHAN_HALF_RATE(chan)) { 1079 eifs = 175; 1080 rx_lat *= 2; 1081 tx_lat *= 2; 1082 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1083 tx_lat += 11; 1084 1085 sifstime = 32; 1086 ack_offset = 16; 1087 ack_shift = 3; 1088 slottime = 13; 1089 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1090 eifs = 340; 1091 rx_lat = (rx_lat * 4) - 1; 1092 tx_lat *= 4; 1093 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1094 tx_lat += 22; 1095 1096 sifstime = 64; 1097 ack_offset = 32; 1098 ack_shift = 1; 1099 slottime = 21; 1100 } else { 1101 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1102 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1103 reg = AR_USEC_ASYNC_FIFO; 1104 } else { 1105 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1106 common->clockrate; 1107 reg = REG_READ(ah, AR_USEC); 1108 } 1109 rx_lat = MS(reg, AR_USEC_RX_LAT); 1110 tx_lat = MS(reg, AR_USEC_TX_LAT); 1111 1112 slottime = ah->slottime; 1113 } 1114 1115 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1116 slottime += 3 * ah->coverage_class; 1117 acktimeout = slottime + sifstime + ack_offset; 1118 ctstimeout = acktimeout; 1119 1120 /* 1121 * Workaround for early ACK timeouts, add an offset to match the 1122 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1123 * This was initially only meant to work around an issue with delayed 1124 * BA frames in some implementations, but it has been found to fix ACK 1125 * timeout issues in other cases as well. 1126 */ 1127 if (IS_CHAN_2GHZ(chan) && 1128 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1129 acktimeout += 64 - sifstime - ah->slottime; 1130 ctstimeout += 48 - sifstime - ah->slottime; 1131 } 1132 1133 if (ah->dynack.enabled) { 1134 acktimeout = ah->dynack.ackto; 1135 ctstimeout = acktimeout; 1136 slottime = (acktimeout - 3) / 2; 1137 } else { 1138 ah->dynack.ackto = acktimeout; 1139 } 1140 1141 ath9k_hw_set_sifs_time(ah, sifstime); 1142 ath9k_hw_setslottime(ah, slottime); 1143 ath9k_hw_set_ack_timeout(ah, acktimeout); 1144 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1145 if (ah->globaltxtimeout != (u32) -1) 1146 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1147 1148 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1149 REG_RMW(ah, AR_USEC, 1150 (common->clockrate - 1) | 1151 SM(rx_lat, AR_USEC_RX_LAT) | 1152 SM(tx_lat, AR_USEC_TX_LAT), 1153 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1154 1155 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) 1156 REG_RMW(ah, AR_TXSIFS, 1157 sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT), 1158 (AR_TXSIFS_TIME | AR_TXSIFS_ACK_SHIFT)); 1159 } 1160 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1161 1162 void ath9k_hw_deinit(struct ath_hw *ah) 1163 { 1164 struct ath_common *common = ath9k_hw_common(ah); 1165 1166 if (common->state < ATH_HW_INITIALIZED) 1167 return; 1168 1169 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1170 } 1171 EXPORT_SYMBOL(ath9k_hw_deinit); 1172 1173 /*******/ 1174 /* INI */ 1175 /*******/ 1176 1177 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1178 { 1179 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1180 1181 if (IS_CHAN_2GHZ(chan)) 1182 ctl |= CTL_11G; 1183 else 1184 ctl |= CTL_11A; 1185 1186 return ctl; 1187 } 1188 1189 /****************************************/ 1190 /* Reset and Channel Switching Routines */ 1191 /****************************************/ 1192 1193 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1194 { 1195 struct ath_common *common = ath9k_hw_common(ah); 1196 int txbuf_size; 1197 1198 ENABLE_REGWRITE_BUFFER(ah); 1199 1200 /* 1201 * set AHB_MODE not to do cacheline prefetches 1202 */ 1203 if (!AR_SREV_9300_20_OR_LATER(ah)) 1204 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1205 1206 /* 1207 * let mac dma reads be in 128 byte chunks 1208 */ 1209 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1210 1211 REGWRITE_BUFFER_FLUSH(ah); 1212 1213 /* 1214 * Restore TX Trigger Level to its pre-reset value. 1215 * The initial value depends on whether aggregation is enabled, and is 1216 * adjusted whenever underruns are detected. 1217 */ 1218 if (!AR_SREV_9300_20_OR_LATER(ah)) 1219 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1220 1221 ENABLE_REGWRITE_BUFFER(ah); 1222 1223 /* 1224 * let mac dma writes be in 128 byte chunks 1225 */ 1226 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1227 1228 /* 1229 * Setup receive FIFO threshold to hold off TX activities 1230 */ 1231 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1232 1233 if (AR_SREV_9300_20_OR_LATER(ah)) { 1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1235 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1236 1237 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1238 ah->caps.rx_status_len); 1239 } 1240 1241 /* 1242 * reduce the number of usable entries in PCU TXBUF to avoid 1243 * wrap around issues. 1244 */ 1245 if (AR_SREV_9285(ah)) { 1246 /* For AR9285 the number of Fifos are reduced to half. 1247 * So set the usable tx buf size also to half to 1248 * avoid data/delimiter underruns 1249 */ 1250 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1251 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1252 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1253 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1254 } else { 1255 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1256 } 1257 1258 if (!AR_SREV_9271(ah)) 1259 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1260 1261 REGWRITE_BUFFER_FLUSH(ah); 1262 1263 if (AR_SREV_9300_20_OR_LATER(ah)) 1264 ath9k_hw_reset_txstatus_ring(ah); 1265 } 1266 1267 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1268 { 1269 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1270 u32 set = AR_STA_ID1_KSRCH_MODE; 1271 1272 ENABLE_REG_RMW_BUFFER(ah); 1273 switch (opmode) { 1274 case NL80211_IFTYPE_ADHOC: 1275 if (!AR_SREV_9340_13(ah)) { 1276 set |= AR_STA_ID1_ADHOC; 1277 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1278 break; 1279 } 1280 fallthrough; 1281 case NL80211_IFTYPE_OCB: 1282 case NL80211_IFTYPE_MESH_POINT: 1283 case NL80211_IFTYPE_AP: 1284 set |= AR_STA_ID1_STA_AP; 1285 fallthrough; 1286 case NL80211_IFTYPE_STATION: 1287 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1288 break; 1289 default: 1290 if (!ah->is_monitoring) 1291 set = 0; 1292 break; 1293 } 1294 REG_RMW(ah, AR_STA_ID1, set, mask); 1295 REG_RMW_BUFFER_FLUSH(ah); 1296 } 1297 1298 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1299 u32 *coef_mantissa, u32 *coef_exponent) 1300 { 1301 u32 coef_exp, coef_man; 1302 1303 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1304 if ((coef_scaled >> coef_exp) & 0x1) 1305 break; 1306 1307 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1308 1309 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1310 1311 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1312 *coef_exponent = coef_exp - 16; 1313 } 1314 1315 /* AR9330 WAR: 1316 * call external reset function to reset WMAC if: 1317 * - doing a cold reset 1318 * - we have pending frames in the TX queues. 1319 */ 1320 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1321 { 1322 int i, npend = 0; 1323 1324 for (i = 0; i < AR_NUM_QCU; i++) { 1325 npend = ath9k_hw_numtxpending(ah, i); 1326 if (npend) 1327 break; 1328 } 1329 1330 if (ah->external_reset && 1331 (npend || type == ATH9K_RESET_COLD)) { 1332 int reset_err = 0; 1333 1334 ath_dbg(ath9k_hw_common(ah), RESET, 1335 "reset MAC via external reset\n"); 1336 1337 reset_err = ah->external_reset(); 1338 if (reset_err) { 1339 ath_err(ath9k_hw_common(ah), 1340 "External reset failed, err=%d\n", 1341 reset_err); 1342 return false; 1343 } 1344 1345 REG_WRITE(ah, AR_RTC_RESET, 1); 1346 } 1347 1348 return true; 1349 } 1350 1351 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1352 { 1353 u32 rst_flags; 1354 u32 tmpReg; 1355 1356 if (AR_SREV_9100(ah)) { 1357 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1358 AR_RTC_DERIVED_CLK_PERIOD, 1); 1359 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1360 } 1361 1362 ENABLE_REGWRITE_BUFFER(ah); 1363 1364 if (AR_SREV_9300_20_OR_LATER(ah)) { 1365 REG_WRITE(ah, AR_WA, ah->WARegVal); 1366 udelay(10); 1367 } 1368 1369 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1370 AR_RTC_FORCE_WAKE_ON_INT); 1371 1372 if (AR_SREV_9100(ah)) { 1373 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1374 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1375 } else { 1376 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1377 if (AR_SREV_9340(ah)) 1378 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1379 else 1380 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1381 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1382 1383 if (tmpReg) { 1384 u32 val; 1385 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1386 1387 val = AR_RC_HOSTIF; 1388 if (!AR_SREV_9300_20_OR_LATER(ah)) 1389 val |= AR_RC_AHB; 1390 REG_WRITE(ah, AR_RC, val); 1391 1392 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1393 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1394 1395 rst_flags = AR_RTC_RC_MAC_WARM; 1396 if (type == ATH9K_RESET_COLD) 1397 rst_flags |= AR_RTC_RC_MAC_COLD; 1398 } 1399 1400 if (AR_SREV_9330(ah)) { 1401 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1402 return false; 1403 } 1404 1405 if (ath9k_hw_mci_is_enabled(ah)) 1406 ar9003_mci_check_gpm_offset(ah); 1407 1408 /* DMA HALT added to resolve ar9300 and ar9580 bus error during 1409 * RTC_RC reg read 1410 */ 1411 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { 1412 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1413 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, 1414 20 * AH_WAIT_TIMEOUT); 1415 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1416 } 1417 1418 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1419 1420 REGWRITE_BUFFER_FLUSH(ah); 1421 1422 if (AR_SREV_9300_20_OR_LATER(ah)) 1423 udelay(50); 1424 else if (AR_SREV_9100(ah)) 1425 mdelay(10); 1426 else 1427 udelay(100); 1428 1429 REG_WRITE(ah, AR_RTC_RC, 0); 1430 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1431 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1432 return false; 1433 } 1434 1435 if (!AR_SREV_9100(ah)) 1436 REG_WRITE(ah, AR_RC, 0); 1437 1438 if (AR_SREV_9100(ah)) 1439 udelay(50); 1440 1441 return true; 1442 } 1443 1444 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1445 { 1446 ENABLE_REGWRITE_BUFFER(ah); 1447 1448 if (AR_SREV_9300_20_OR_LATER(ah)) { 1449 REG_WRITE(ah, AR_WA, ah->WARegVal); 1450 udelay(10); 1451 } 1452 1453 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1454 AR_RTC_FORCE_WAKE_ON_INT); 1455 1456 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1457 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1458 1459 REG_WRITE(ah, AR_RTC_RESET, 0); 1460 1461 REGWRITE_BUFFER_FLUSH(ah); 1462 1463 udelay(2); 1464 1465 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1466 REG_WRITE(ah, AR_RC, 0); 1467 1468 REG_WRITE(ah, AR_RTC_RESET, 1); 1469 1470 if (!ath9k_hw_wait(ah, 1471 AR_RTC_STATUS, 1472 AR_RTC_STATUS_M, 1473 AR_RTC_STATUS_ON, 1474 AH_WAIT_TIMEOUT)) { 1475 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1476 return false; 1477 } 1478 1479 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1480 } 1481 1482 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1483 { 1484 bool ret = false; 1485 1486 if (AR_SREV_9300_20_OR_LATER(ah)) { 1487 REG_WRITE(ah, AR_WA, ah->WARegVal); 1488 udelay(10); 1489 } 1490 1491 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1492 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1493 1494 if (!ah->reset_power_on) 1495 type = ATH9K_RESET_POWER_ON; 1496 1497 switch (type) { 1498 case ATH9K_RESET_POWER_ON: 1499 ret = ath9k_hw_set_reset_power_on(ah); 1500 if (ret) 1501 ah->reset_power_on = true; 1502 break; 1503 case ATH9K_RESET_WARM: 1504 case ATH9K_RESET_COLD: 1505 ret = ath9k_hw_set_reset(ah, type); 1506 break; 1507 default: 1508 break; 1509 } 1510 1511 return ret; 1512 } 1513 1514 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1515 struct ath9k_channel *chan) 1516 { 1517 int reset_type = ATH9K_RESET_WARM; 1518 1519 if (AR_SREV_9280(ah)) { 1520 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1521 reset_type = ATH9K_RESET_POWER_ON; 1522 else 1523 reset_type = ATH9K_RESET_COLD; 1524 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1525 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1526 reset_type = ATH9K_RESET_COLD; 1527 1528 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1529 return false; 1530 1531 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1532 return false; 1533 1534 ah->chip_fullsleep = false; 1535 1536 if (AR_SREV_9330(ah)) 1537 ar9003_hw_internal_regulator_apply(ah); 1538 ath9k_hw_init_pll(ah, chan); 1539 1540 return true; 1541 } 1542 1543 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1544 struct ath9k_channel *chan) 1545 { 1546 struct ath_common *common = ath9k_hw_common(ah); 1547 struct ath9k_hw_capabilities *pCap = &ah->caps; 1548 bool band_switch = false, mode_diff = false; 1549 u8 ini_reloaded = 0; 1550 u32 qnum; 1551 int r; 1552 1553 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1554 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1555 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1556 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1557 } 1558 1559 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1560 if (ath9k_hw_numtxpending(ah, qnum)) { 1561 ath_dbg(common, QUEUE, 1562 "Transmit frames pending on queue %d\n", qnum); 1563 return false; 1564 } 1565 } 1566 1567 if (!ath9k_hw_rfbus_req(ah)) { 1568 ath_err(common, "Could not kill baseband RX\n"); 1569 return false; 1570 } 1571 1572 if (band_switch || mode_diff) { 1573 ath9k_hw_mark_phy_inactive(ah); 1574 udelay(5); 1575 1576 if (band_switch) 1577 ath9k_hw_init_pll(ah, chan); 1578 1579 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1580 ath_err(common, "Failed to do fast channel change\n"); 1581 return false; 1582 } 1583 } 1584 1585 ath9k_hw_set_channel_regs(ah, chan); 1586 1587 r = ath9k_hw_rf_set_freq(ah, chan); 1588 if (r) { 1589 ath_err(common, "Failed to set channel\n"); 1590 return false; 1591 } 1592 ath9k_hw_set_clockrate(ah); 1593 ath9k_hw_apply_txpower(ah, chan, false); 1594 1595 ath9k_hw_set_delta_slope(ah, chan); 1596 ath9k_hw_spur_mitigate_freq(ah, chan); 1597 1598 if (band_switch || ini_reloaded) 1599 ah->eep_ops->set_board_values(ah, chan); 1600 1601 ath9k_hw_init_bb(ah, chan); 1602 ath9k_hw_rfbus_done(ah); 1603 1604 if (band_switch || ini_reloaded) { 1605 ah->ah_flags |= AH_FASTCC; 1606 ath9k_hw_init_cal(ah, chan); 1607 ah->ah_flags &= ~AH_FASTCC; 1608 } 1609 1610 return true; 1611 } 1612 1613 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1614 { 1615 u32 gpio_mask = ah->gpio_mask; 1616 int i; 1617 1618 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1619 if (!(gpio_mask & 1)) 1620 continue; 1621 1622 ath9k_hw_gpio_request_out(ah, i, NULL, 1623 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1624 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1625 ath9k_hw_gpio_free(ah, i); 1626 } 1627 } 1628 1629 void ath9k_hw_check_nav(struct ath_hw *ah) 1630 { 1631 struct ath_common *common = ath9k_hw_common(ah); 1632 u32 val; 1633 1634 val = REG_READ(ah, AR_NAV); 1635 if (val != 0xdeadbeef && val > 0x7fff) { 1636 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1637 REG_WRITE(ah, AR_NAV, 0); 1638 } 1639 } 1640 EXPORT_SYMBOL(ath9k_hw_check_nav); 1641 1642 bool ath9k_hw_check_alive(struct ath_hw *ah) 1643 { 1644 int count = 50; 1645 u32 reg, last_val; 1646 1647 /* Check if chip failed to wake up */ 1648 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) 1649 return false; 1650 1651 if (AR_SREV_9300(ah)) 1652 return !ath9k_hw_detect_mac_hang(ah); 1653 1654 if (AR_SREV_9285_12_OR_LATER(ah)) 1655 return true; 1656 1657 last_val = REG_READ(ah, AR_OBS_BUS_1); 1658 do { 1659 reg = REG_READ(ah, AR_OBS_BUS_1); 1660 if (reg != last_val) 1661 return true; 1662 1663 udelay(1); 1664 last_val = reg; 1665 if ((reg & 0x7E7FFFEF) == 0x00702400) 1666 continue; 1667 1668 switch (reg & 0x7E000B00) { 1669 case 0x1E000000: 1670 case 0x52000B00: 1671 case 0x18000B00: 1672 continue; 1673 default: 1674 return true; 1675 } 1676 } while (count-- > 0); 1677 1678 return false; 1679 } 1680 EXPORT_SYMBOL(ath9k_hw_check_alive); 1681 1682 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1683 { 1684 /* Setup MFP options for CCMP */ 1685 if (AR_SREV_9280_20_OR_LATER(ah)) { 1686 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1687 * frames when constructing CCMP AAD. */ 1688 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1689 0xc7ff); 1690 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1691 ah->sw_mgmt_crypto_tx = true; 1692 else 1693 ah->sw_mgmt_crypto_tx = false; 1694 ah->sw_mgmt_crypto_rx = false; 1695 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1696 /* Disable hardware crypto for management frames */ 1697 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1698 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1699 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1700 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1701 ah->sw_mgmt_crypto_tx = true; 1702 ah->sw_mgmt_crypto_rx = true; 1703 } else { 1704 ah->sw_mgmt_crypto_tx = true; 1705 ah->sw_mgmt_crypto_rx = true; 1706 } 1707 } 1708 1709 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1710 u32 macStaId1, u32 saveDefAntenna) 1711 { 1712 struct ath_common *common = ath9k_hw_common(ah); 1713 1714 ENABLE_REGWRITE_BUFFER(ah); 1715 1716 REG_RMW(ah, AR_STA_ID1, macStaId1 1717 | AR_STA_ID1_RTS_USE_DEF 1718 | ah->sta_id1_defaults, 1719 ~AR_STA_ID1_SADH_MASK); 1720 ath_hw_setbssidmask(common); 1721 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1722 ath9k_hw_write_associd(ah); 1723 REG_WRITE(ah, AR_ISR, ~0); 1724 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1725 1726 REGWRITE_BUFFER_FLUSH(ah); 1727 1728 ath9k_hw_set_operating_mode(ah, ah->opmode); 1729 } 1730 1731 static void ath9k_hw_init_queues(struct ath_hw *ah) 1732 { 1733 int i; 1734 1735 ENABLE_REGWRITE_BUFFER(ah); 1736 1737 for (i = 0; i < AR_NUM_DCU; i++) 1738 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1739 1740 REGWRITE_BUFFER_FLUSH(ah); 1741 1742 ah->intr_txqs = 0; 1743 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1744 ath9k_hw_resettxqueue(ah, i); 1745 } 1746 1747 /* 1748 * For big endian systems turn on swapping for descriptors 1749 */ 1750 static void ath9k_hw_init_desc(struct ath_hw *ah) 1751 { 1752 struct ath_common *common = ath9k_hw_common(ah); 1753 1754 if (AR_SREV_9100(ah)) { 1755 u32 mask; 1756 mask = REG_READ(ah, AR_CFG); 1757 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1758 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1759 mask); 1760 } else { 1761 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1762 REG_WRITE(ah, AR_CFG, mask); 1763 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1764 REG_READ(ah, AR_CFG)); 1765 } 1766 } else { 1767 if (common->bus_ops->ath_bus_type == ATH_USB) { 1768 /* Configure AR9271 target WLAN */ 1769 if (AR_SREV_9271(ah)) 1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1771 else 1772 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1773 } 1774 #ifdef __BIG_ENDIAN 1775 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1776 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1777 AR_SREV_9561(ah)) 1778 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1779 else 1780 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1781 #endif 1782 } 1783 } 1784 1785 /* 1786 * Fast channel change: 1787 * (Change synthesizer based on channel freq without resetting chip) 1788 */ 1789 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1790 { 1791 struct ath_common *common = ath9k_hw_common(ah); 1792 struct ath9k_hw_capabilities *pCap = &ah->caps; 1793 int ret; 1794 1795 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1796 goto fail; 1797 1798 if (ah->chip_fullsleep) 1799 goto fail; 1800 1801 if (!ah->curchan) 1802 goto fail; 1803 1804 if (chan->channel == ah->curchan->channel) 1805 goto fail; 1806 1807 if ((ah->curchan->channelFlags | chan->channelFlags) & 1808 (CHANNEL_HALF | CHANNEL_QUARTER)) 1809 goto fail; 1810 1811 /* 1812 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1813 */ 1814 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1815 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1816 goto fail; 1817 1818 if (!ath9k_hw_check_alive(ah)) 1819 goto fail; 1820 1821 /* 1822 * For AR9462, make sure that calibration data for 1823 * re-using are present. 1824 */ 1825 if (AR_SREV_9462(ah) && (ah->caldata && 1826 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1827 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1828 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1829 goto fail; 1830 1831 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1832 ah->curchan->channel, chan->channel); 1833 1834 ret = ath9k_hw_channel_change(ah, chan); 1835 if (!ret) 1836 goto fail; 1837 1838 if (ath9k_hw_mci_is_enabled(ah)) 1839 ar9003_mci_2g5g_switch(ah, false); 1840 1841 ath9k_hw_loadnf(ah, ah->curchan); 1842 ath9k_hw_start_nfcal(ah, true); 1843 1844 if (AR_SREV_9271(ah)) 1845 ar9002_hw_load_ani_reg(ah, chan); 1846 1847 return 0; 1848 fail: 1849 return -EINVAL; 1850 } 1851 1852 u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur) 1853 { 1854 struct timespec64 ts; 1855 s64 usec; 1856 1857 if (!cur) { 1858 ktime_get_raw_ts64(&ts); 1859 cur = &ts; 1860 } 1861 1862 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1863 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1864 1865 return (u32) usec; 1866 } 1867 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1868 1869 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1870 struct ath9k_hw_cal_data *caldata, bool fastcc) 1871 { 1872 struct ath_common *common = ath9k_hw_common(ah); 1873 u32 saveLedState; 1874 u32 saveDefAntenna; 1875 u32 macStaId1; 1876 struct timespec64 tsf_ts; 1877 u32 tsf_offset; 1878 u64 tsf = 0; 1879 int r; 1880 bool start_mci_reset = false; 1881 bool save_fullsleep = ah->chip_fullsleep; 1882 1883 if (ath9k_hw_mci_is_enabled(ah)) { 1884 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1885 if (start_mci_reset) 1886 return 0; 1887 } 1888 1889 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1890 return -EIO; 1891 1892 if (ah->curchan && !ah->chip_fullsleep) 1893 ath9k_hw_getnf(ah, ah->curchan); 1894 1895 ah->caldata = caldata; 1896 if (caldata && (chan->channel != caldata->channel || 1897 chan->channelFlags != caldata->channelFlags)) { 1898 /* Operating channel changed, reset channel calibration data */ 1899 memset(caldata, 0, sizeof(*caldata)); 1900 ath9k_init_nfcal_hist_buffer(ah, chan); 1901 } else if (caldata) { 1902 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1903 } 1904 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1905 1906 if (fastcc) { 1907 r = ath9k_hw_do_fastcc(ah, chan); 1908 if (!r) 1909 return r; 1910 } 1911 1912 if (ath9k_hw_mci_is_enabled(ah)) 1913 ar9003_mci_stop_bt(ah, save_fullsleep); 1914 1915 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1916 if (saveDefAntenna == 0) 1917 saveDefAntenna = 1; 1918 1919 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1920 1921 /* Save TSF before chip reset, a cold reset clears it */ 1922 ktime_get_raw_ts64(&tsf_ts); 1923 tsf = ath9k_hw_gettsf64(ah); 1924 1925 saveLedState = REG_READ(ah, AR_CFG_LED) & 1926 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1927 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1928 1929 ath9k_hw_mark_phy_inactive(ah); 1930 1931 ah->paprd_table_write_done = false; 1932 1933 /* Only required on the first reset */ 1934 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1935 REG_WRITE(ah, 1936 AR9271_RESET_POWER_DOWN_CONTROL, 1937 AR9271_RADIO_RF_RST); 1938 udelay(50); 1939 } 1940 1941 if (!ath9k_hw_chip_reset(ah, chan)) { 1942 ath_err(common, "Chip reset failed\n"); 1943 return -EINVAL; 1944 } 1945 1946 /* Only required on the first reset */ 1947 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1948 ah->htc_reset_init = false; 1949 REG_WRITE(ah, 1950 AR9271_RESET_POWER_DOWN_CONTROL, 1951 AR9271_GATE_MAC_CTL); 1952 udelay(50); 1953 } 1954 1955 /* Restore TSF */ 1956 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1957 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1958 1959 if (AR_SREV_9280_20_OR_LATER(ah)) 1960 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1961 1962 if (!AR_SREV_9300_20_OR_LATER(ah)) 1963 ar9002_hw_enable_async_fifo(ah); 1964 1965 r = ath9k_hw_process_ini(ah, chan); 1966 if (r) 1967 return r; 1968 1969 ath9k_hw_set_rfmode(ah, chan); 1970 1971 if (ath9k_hw_mci_is_enabled(ah)) 1972 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1973 1974 /* 1975 * Some AR91xx SoC devices frequently fail to accept TSF writes 1976 * right after the chip reset. When that happens, write a new 1977 * value after the initvals have been applied. 1978 */ 1979 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1980 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1981 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1982 } 1983 1984 ath9k_hw_init_mfp(ah); 1985 1986 ath9k_hw_set_delta_slope(ah, chan); 1987 ath9k_hw_spur_mitigate_freq(ah, chan); 1988 ah->eep_ops->set_board_values(ah, chan); 1989 1990 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1991 1992 r = ath9k_hw_rf_set_freq(ah, chan); 1993 if (r) 1994 return r; 1995 1996 ath9k_hw_set_clockrate(ah); 1997 1998 ath9k_hw_init_queues(ah); 1999 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 2000 ath9k_hw_ani_cache_ini_regs(ah); 2001 ath9k_hw_init_qos(ah); 2002 2003 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2004 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); 2005 2006 ath9k_hw_init_global_settings(ah); 2007 2008 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 2009 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 2010 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 2011 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 2012 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 2013 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2014 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2015 } 2016 2017 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2018 2019 ath9k_hw_set_dma(ah); 2020 2021 if (!ath9k_hw_mci_is_enabled(ah)) 2022 REG_WRITE(ah, AR_OBS, 8); 2023 2024 ENABLE_REG_RMW_BUFFER(ah); 2025 if (ah->config.rx_intr_mitigation) { 2026 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 2027 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 2028 } 2029 2030 if (ah->config.tx_intr_mitigation) { 2031 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2032 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2033 } 2034 REG_RMW_BUFFER_FLUSH(ah); 2035 2036 ath9k_hw_init_bb(ah, chan); 2037 2038 if (caldata) { 2039 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 2040 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 2041 } 2042 if (!ath9k_hw_init_cal(ah, chan)) 2043 return -EIO; 2044 2045 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2046 return -EIO; 2047 2048 ENABLE_REGWRITE_BUFFER(ah); 2049 2050 ath9k_hw_restore_chainmask(ah); 2051 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2052 2053 REGWRITE_BUFFER_FLUSH(ah); 2054 2055 ath9k_hw_gen_timer_start_tsf2(ah); 2056 2057 ath9k_hw_init_desc(ah); 2058 2059 if (ath9k_hw_btcoex_is_enabled(ah)) 2060 ath9k_hw_btcoex_enable(ah); 2061 2062 if (ath9k_hw_mci_is_enabled(ah)) 2063 ar9003_mci_check_bt(ah); 2064 2065 if (AR_SREV_9300_20_OR_LATER(ah)) { 2066 ath9k_hw_loadnf(ah, chan); 2067 ath9k_hw_start_nfcal(ah, true); 2068 } 2069 2070 if (AR_SREV_9300_20_OR_LATER(ah)) 2071 ar9003_hw_bb_watchdog_config(ah); 2072 2073 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 2074 ar9003_hw_disable_phy_restart(ah); 2075 2076 ath9k_hw_apply_gpio_override(ah); 2077 2078 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2079 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2080 2081 if (ah->hw->conf.radar_enabled) { 2082 /* set HW specific DFS configuration */ 2083 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 2084 ath9k_hw_set_radar_params(ah); 2085 } 2086 2087 return 0; 2088 } 2089 EXPORT_SYMBOL(ath9k_hw_reset); 2090 2091 /******************************/ 2092 /* Power Management (Chipset) */ 2093 /******************************/ 2094 2095 /* 2096 * Notify Power Mgt is disabled in self-generated frames. 2097 * If requested, force chip to sleep. 2098 */ 2099 static void ath9k_set_power_sleep(struct ath_hw *ah) 2100 { 2101 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2102 2103 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2104 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2105 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2106 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2107 /* xxx Required for WLAN only case ? */ 2108 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2109 udelay(100); 2110 } 2111 2112 /* 2113 * Clear the RTC force wake bit to allow the 2114 * mac to go to sleep. 2115 */ 2116 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2117 2118 if (ath9k_hw_mci_is_enabled(ah)) 2119 udelay(100); 2120 2121 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2122 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2123 2124 /* Shutdown chip. Active low */ 2125 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2126 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2127 udelay(2); 2128 } 2129 2130 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2131 if (AR_SREV_9300_20_OR_LATER(ah)) 2132 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2133 } 2134 2135 /* 2136 * Notify Power Management is enabled in self-generating 2137 * frames. If request, set power mode of chip to 2138 * auto/normal. Duration in units of 128us (1/8 TU). 2139 */ 2140 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2141 { 2142 struct ath9k_hw_capabilities *pCap = &ah->caps; 2143 2144 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2145 2146 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2147 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2148 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2149 AR_RTC_FORCE_WAKE_ON_INT); 2150 } else { 2151 2152 /* When chip goes into network sleep, it could be waken 2153 * up by MCI_INT interrupt caused by BT's HW messages 2154 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2155 * rate (~100us). This will cause chip to leave and 2156 * re-enter network sleep mode frequently, which in 2157 * consequence will have WLAN MCI HW to generate lots of 2158 * SYS_WAKING and SYS_SLEEPING messages which will make 2159 * BT CPU to busy to process. 2160 */ 2161 if (ath9k_hw_mci_is_enabled(ah)) 2162 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2163 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2164 /* 2165 * Clear the RTC force wake bit to allow the 2166 * mac to go to sleep. 2167 */ 2168 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2169 2170 if (ath9k_hw_mci_is_enabled(ah)) 2171 udelay(30); 2172 } 2173 2174 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2175 if (AR_SREV_9300_20_OR_LATER(ah)) 2176 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2177 } 2178 2179 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2180 { 2181 u32 val; 2182 int i; 2183 2184 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2185 if (AR_SREV_9300_20_OR_LATER(ah)) { 2186 REG_WRITE(ah, AR_WA, ah->WARegVal); 2187 udelay(10); 2188 } 2189 2190 if ((REG_READ(ah, AR_RTC_STATUS) & 2191 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2192 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2193 return false; 2194 } 2195 if (!AR_SREV_9300_20_OR_LATER(ah)) 2196 ath9k_hw_init_pll(ah, NULL); 2197 } 2198 if (AR_SREV_9100(ah)) 2199 REG_SET_BIT(ah, AR_RTC_RESET, 2200 AR_RTC_RESET_EN); 2201 2202 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2203 AR_RTC_FORCE_WAKE_EN); 2204 if (AR_SREV_9100(ah)) 2205 mdelay(10); 2206 else 2207 udelay(50); 2208 2209 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2210 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2211 if (val == AR_RTC_STATUS_ON) 2212 break; 2213 udelay(50); 2214 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2215 AR_RTC_FORCE_WAKE_EN); 2216 } 2217 if (i == 0) { 2218 ath_err(ath9k_hw_common(ah), 2219 "Failed to wakeup in %uus\n", 2220 POWER_UP_TIME / 20); 2221 return false; 2222 } 2223 2224 if (ath9k_hw_mci_is_enabled(ah)) 2225 ar9003_mci_set_power_awake(ah); 2226 2227 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2228 2229 return true; 2230 } 2231 2232 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2233 { 2234 struct ath_common *common = ath9k_hw_common(ah); 2235 int status = true; 2236 static const char *modes[] = { 2237 "AWAKE", 2238 "FULL-SLEEP", 2239 "NETWORK SLEEP", 2240 "UNDEFINED" 2241 }; 2242 2243 if (ah->power_mode == mode) 2244 return status; 2245 2246 ath_dbg(common, RESET, "%s -> %s\n", 2247 modes[ah->power_mode], modes[mode]); 2248 2249 switch (mode) { 2250 case ATH9K_PM_AWAKE: 2251 status = ath9k_hw_set_power_awake(ah); 2252 break; 2253 case ATH9K_PM_FULL_SLEEP: 2254 if (ath9k_hw_mci_is_enabled(ah)) 2255 ar9003_mci_set_full_sleep(ah); 2256 2257 ath9k_set_power_sleep(ah); 2258 ah->chip_fullsleep = true; 2259 break; 2260 case ATH9K_PM_NETWORK_SLEEP: 2261 ath9k_set_power_network_sleep(ah); 2262 break; 2263 default: 2264 ath_err(common, "Unknown power mode %u\n", mode); 2265 return false; 2266 } 2267 ah->power_mode = mode; 2268 2269 /* 2270 * XXX: If this warning never comes up after a while then 2271 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2272 * ath9k_hw_setpower() return type void. 2273 */ 2274 2275 if (!(ah->ah_flags & AH_UNPLUGGED)) 2276 ATH_DBG_WARN_ON_ONCE(!status); 2277 2278 return status; 2279 } 2280 EXPORT_SYMBOL(ath9k_hw_setpower); 2281 2282 /*******************/ 2283 /* Beacon Handling */ 2284 /*******************/ 2285 2286 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2287 { 2288 int flags = 0; 2289 2290 ENABLE_REGWRITE_BUFFER(ah); 2291 2292 switch (ah->opmode) { 2293 case NL80211_IFTYPE_ADHOC: 2294 REG_SET_BIT(ah, AR_TXCFG, 2295 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2296 fallthrough; 2297 case NL80211_IFTYPE_MESH_POINT: 2298 case NL80211_IFTYPE_AP: 2299 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2300 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2301 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2302 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2303 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2304 flags |= 2305 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2306 break; 2307 default: 2308 ath_dbg(ath9k_hw_common(ah), BEACON, 2309 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2310 return; 2311 } 2312 2313 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2314 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2315 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2316 2317 REGWRITE_BUFFER_FLUSH(ah); 2318 2319 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2320 } 2321 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2322 2323 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2324 const struct ath9k_beacon_state *bs) 2325 { 2326 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2327 struct ath9k_hw_capabilities *pCap = &ah->caps; 2328 struct ath_common *common = ath9k_hw_common(ah); 2329 2330 ENABLE_REGWRITE_BUFFER(ah); 2331 2332 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2333 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2334 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2335 2336 REGWRITE_BUFFER_FLUSH(ah); 2337 2338 REG_RMW_FIELD(ah, AR_RSSI_THR, 2339 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2340 2341 beaconintval = bs->bs_intval; 2342 2343 if (bs->bs_sleepduration > beaconintval) 2344 beaconintval = bs->bs_sleepduration; 2345 2346 dtimperiod = bs->bs_dtimperiod; 2347 if (bs->bs_sleepduration > dtimperiod) 2348 dtimperiod = bs->bs_sleepduration; 2349 2350 if (beaconintval == dtimperiod) 2351 nextTbtt = bs->bs_nextdtim; 2352 else 2353 nextTbtt = bs->bs_nexttbtt; 2354 2355 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); 2356 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt); 2357 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval); 2358 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod); 2359 2360 ENABLE_REGWRITE_BUFFER(ah); 2361 2362 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2363 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2364 2365 REG_WRITE(ah, AR_SLEEP1, 2366 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2367 | AR_SLEEP1_ASSUME_DTIM); 2368 2369 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2370 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2371 else 2372 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2373 2374 REG_WRITE(ah, AR_SLEEP2, 2375 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2376 2377 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2378 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2379 2380 REGWRITE_BUFFER_FLUSH(ah); 2381 2382 REG_SET_BIT(ah, AR_TIMER_MODE, 2383 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2384 AR_DTIM_TIMER_EN); 2385 2386 /* TSF Out of Range Threshold */ 2387 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2388 } 2389 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2390 2391 /*******************/ 2392 /* HW Capabilities */ 2393 /*******************/ 2394 2395 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2396 { 2397 eeprom_chainmask &= chip_chainmask; 2398 if (eeprom_chainmask) 2399 return eeprom_chainmask; 2400 else 2401 return chip_chainmask; 2402 } 2403 2404 /** 2405 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2406 * @ah: the atheros hardware data structure 2407 * 2408 * We enable DFS support upstream on chipsets which have passed a series 2409 * of tests. The testing requirements are going to be documented. Desired 2410 * test requirements are documented at: 2411 * 2412 * https://wireless.wiki.kernel.org/en/users/Drivers/ath9k/dfs 2413 * 2414 * Once a new chipset gets properly tested an individual commit can be used 2415 * to document the testing for DFS for that chipset. 2416 */ 2417 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2418 { 2419 2420 switch (ah->hw_version.macVersion) { 2421 /* for temporary testing DFS with 9280 */ 2422 case AR_SREV_VERSION_9280: 2423 /* AR9580 will likely be our first target to get testing on */ 2424 case AR_SREV_VERSION_9580: 2425 return true; 2426 default: 2427 return false; 2428 } 2429 } 2430 2431 static void ath9k_gpio_cap_init(struct ath_hw *ah) 2432 { 2433 struct ath9k_hw_capabilities *pCap = &ah->caps; 2434 2435 if (AR_SREV_9271(ah)) { 2436 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2437 pCap->gpio_mask = AR9271_GPIO_MASK; 2438 } else if (AR_DEVID_7010(ah)) { 2439 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2440 pCap->gpio_mask = AR7010_GPIO_MASK; 2441 } else if (AR_SREV_9287(ah)) { 2442 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2443 pCap->gpio_mask = AR9287_GPIO_MASK; 2444 } else if (AR_SREV_9285(ah)) { 2445 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2446 pCap->gpio_mask = AR9285_GPIO_MASK; 2447 } else if (AR_SREV_9280(ah)) { 2448 pCap->num_gpio_pins = AR9280_NUM_GPIO; 2449 pCap->gpio_mask = AR9280_GPIO_MASK; 2450 } else if (AR_SREV_9300(ah)) { 2451 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2452 pCap->gpio_mask = AR9300_GPIO_MASK; 2453 } else if (AR_SREV_9330(ah)) { 2454 pCap->num_gpio_pins = AR9330_NUM_GPIO; 2455 pCap->gpio_mask = AR9330_GPIO_MASK; 2456 } else if (AR_SREV_9340(ah)) { 2457 pCap->num_gpio_pins = AR9340_NUM_GPIO; 2458 pCap->gpio_mask = AR9340_GPIO_MASK; 2459 } else if (AR_SREV_9462(ah)) { 2460 pCap->num_gpio_pins = AR9462_NUM_GPIO; 2461 pCap->gpio_mask = AR9462_GPIO_MASK; 2462 } else if (AR_SREV_9485(ah)) { 2463 pCap->num_gpio_pins = AR9485_NUM_GPIO; 2464 pCap->gpio_mask = AR9485_GPIO_MASK; 2465 } else if (AR_SREV_9531(ah)) { 2466 pCap->num_gpio_pins = AR9531_NUM_GPIO; 2467 pCap->gpio_mask = AR9531_GPIO_MASK; 2468 } else if (AR_SREV_9550(ah)) { 2469 pCap->num_gpio_pins = AR9550_NUM_GPIO; 2470 pCap->gpio_mask = AR9550_GPIO_MASK; 2471 } else if (AR_SREV_9561(ah)) { 2472 pCap->num_gpio_pins = AR9561_NUM_GPIO; 2473 pCap->gpio_mask = AR9561_GPIO_MASK; 2474 } else if (AR_SREV_9565(ah)) { 2475 pCap->num_gpio_pins = AR9565_NUM_GPIO; 2476 pCap->gpio_mask = AR9565_GPIO_MASK; 2477 } else if (AR_SREV_9580(ah)) { 2478 pCap->num_gpio_pins = AR9580_NUM_GPIO; 2479 pCap->gpio_mask = AR9580_GPIO_MASK; 2480 } else { 2481 pCap->num_gpio_pins = AR_NUM_GPIO; 2482 pCap->gpio_mask = AR_GPIO_MASK; 2483 } 2484 } 2485 2486 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2487 { 2488 struct ath9k_hw_capabilities *pCap = &ah->caps; 2489 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2490 struct ath_common *common = ath9k_hw_common(ah); 2491 2492 u16 eeval; 2493 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2494 2495 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2496 regulatory->current_rd = eeval; 2497 2498 if (ah->opmode != NL80211_IFTYPE_AP && 2499 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2500 if (regulatory->current_rd == 0x64 || 2501 regulatory->current_rd == 0x65) 2502 regulatory->current_rd += 5; 2503 else if (regulatory->current_rd == 0x41) 2504 regulatory->current_rd = 0x43; 2505 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2506 regulatory->current_rd); 2507 } 2508 2509 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2510 2511 if (eeval & AR5416_OPFLAGS_11A) { 2512 if (ah->disable_5ghz) 2513 ath_warn(common, "disabling 5GHz band\n"); 2514 else 2515 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2516 } 2517 2518 if (eeval & AR5416_OPFLAGS_11G) { 2519 if (ah->disable_2ghz) 2520 ath_warn(common, "disabling 2GHz band\n"); 2521 else 2522 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2523 } 2524 2525 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2526 ath_err(common, "both bands are disabled\n"); 2527 return -EINVAL; 2528 } 2529 2530 ath9k_gpio_cap_init(ah); 2531 2532 if (AR_SREV_9485(ah) || 2533 AR_SREV_9285(ah) || 2534 AR_SREV_9330(ah) || 2535 AR_SREV_9565(ah)) 2536 pCap->chip_chainmask = 1; 2537 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2538 pCap->chip_chainmask = 7; 2539 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2540 AR_SREV_9340(ah) || 2541 AR_SREV_9462(ah) || 2542 AR_SREV_9531(ah)) 2543 pCap->chip_chainmask = 3; 2544 else 2545 pCap->chip_chainmask = 7; 2546 2547 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2548 /* 2549 * For AR9271 we will temporarilly uses the rx chainmax as read from 2550 * the EEPROM. 2551 */ 2552 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2553 !(eeval & AR5416_OPFLAGS_11A) && 2554 !(AR_SREV_9271(ah))) 2555 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2556 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2557 else if (AR_SREV_9100(ah)) 2558 pCap->rx_chainmask = 0x7; 2559 else 2560 /* Use rx_chainmask from EEPROM. */ 2561 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2562 2563 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2564 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2565 ah->txchainmask = pCap->tx_chainmask; 2566 ah->rxchainmask = pCap->rx_chainmask; 2567 2568 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2569 2570 /* enable key search for every frame in an aggregate */ 2571 if (AR_SREV_9300_20_OR_LATER(ah)) 2572 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2573 2574 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2575 2576 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2577 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2578 else 2579 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2580 2581 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2582 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2583 else 2584 pCap->rts_aggr_limit = (8 * 1024); 2585 2586 #ifdef CONFIG_ATH9K_RFKILL 2587 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2588 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2589 ah->rfkill_gpio = 2590 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2591 ah->rfkill_polarity = 2592 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2593 2594 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2595 } 2596 #endif 2597 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2598 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2599 else 2600 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2601 2602 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2603 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2604 else 2605 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2606 2607 if (AR_SREV_9300_20_OR_LATER(ah)) { 2608 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2609 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2610 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2611 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2612 2613 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2614 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2615 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2616 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2617 pCap->txs_len = sizeof(struct ar9003_txs); 2618 } else { 2619 pCap->tx_desc_len = sizeof(struct ath_desc); 2620 if (AR_SREV_9280_20(ah)) 2621 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2622 } 2623 2624 if (AR_SREV_9300_20_OR_LATER(ah)) 2625 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2626 2627 if (AR_SREV_9561(ah)) 2628 ah->ent_mode = 0x3BDA000; 2629 else if (AR_SREV_9300_20_OR_LATER(ah)) 2630 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2631 2632 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2633 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2634 2635 if (AR_SREV_9285(ah)) { 2636 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2637 ant_div_ctl1 = 2638 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2639 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2640 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2641 ath_info(common, "Enable LNA combining\n"); 2642 } 2643 } 2644 } 2645 2646 if (AR_SREV_9300_20_OR_LATER(ah)) { 2647 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2648 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2649 } 2650 2651 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2652 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2653 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2654 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2655 ath_info(common, "Enable LNA combining\n"); 2656 } 2657 } 2658 2659 if (ath9k_hw_dfs_tested(ah)) 2660 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2661 2662 tx_chainmask = pCap->tx_chainmask; 2663 rx_chainmask = pCap->rx_chainmask; 2664 while (tx_chainmask || rx_chainmask) { 2665 if (tx_chainmask & BIT(0)) 2666 pCap->max_txchains++; 2667 if (rx_chainmask & BIT(0)) 2668 pCap->max_rxchains++; 2669 2670 tx_chainmask >>= 1; 2671 rx_chainmask >>= 1; 2672 } 2673 2674 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2675 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2676 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2677 2678 if (AR_SREV_9462_20_OR_LATER(ah)) 2679 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2680 } 2681 2682 if (AR_SREV_9300_20_OR_LATER(ah) && 2683 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2684 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2685 2686 #ifdef CONFIG_ATH9K_WOW 2687 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2688 ah->wow.max_patterns = MAX_NUM_PATTERN; 2689 else 2690 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2691 #endif 2692 2693 return 0; 2694 } 2695 2696 /****************************/ 2697 /* GPIO / RFKILL / Antennae */ 2698 /****************************/ 2699 2700 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) 2701 { 2702 int addr; 2703 u32 gpio_shift, tmp; 2704 2705 if (gpio > 11) 2706 addr = AR_GPIO_OUTPUT_MUX3; 2707 else if (gpio > 5) 2708 addr = AR_GPIO_OUTPUT_MUX2; 2709 else 2710 addr = AR_GPIO_OUTPUT_MUX1; 2711 2712 gpio_shift = (gpio % 6) * 5; 2713 2714 if (AR_SREV_9280_20_OR_LATER(ah) || 2715 (addr != AR_GPIO_OUTPUT_MUX1)) { 2716 REG_RMW(ah, addr, (type << gpio_shift), 2717 (0x1f << gpio_shift)); 2718 } else { 2719 tmp = REG_READ(ah, addr); 2720 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2721 tmp &= ~(0x1f << gpio_shift); 2722 tmp |= (type << gpio_shift); 2723 REG_WRITE(ah, addr, tmp); 2724 } 2725 } 2726 2727 /* BSP should set the corresponding MUX register correctly. 2728 */ 2729 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, 2730 const char *label) 2731 { 2732 if (ah->caps.gpio_requested & BIT(gpio)) 2733 return; 2734 2735 /* may be requested by BSP, free anyway */ 2736 gpio_free(gpio); 2737 2738 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label)) 2739 return; 2740 2741 ah->caps.gpio_requested |= BIT(gpio); 2742 } 2743 2744 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, 2745 u32 ah_signal_type) 2746 { 2747 u32 gpio_set, gpio_shift = gpio; 2748 2749 if (AR_DEVID_7010(ah)) { 2750 gpio_set = out ? 2751 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT; 2752 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, 2753 AR7010_GPIO_OE_MASK << gpio_shift); 2754 } else if (AR_SREV_SOC(ah)) { 2755 gpio_set = out ? 1 : 0; 2756 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2757 gpio_set << gpio_shift); 2758 } else { 2759 gpio_shift = gpio << 1; 2760 gpio_set = out ? 2761 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO; 2762 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2763 AR_GPIO_OE_OUT_DRV << gpio_shift); 2764 2765 if (out) 2766 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2767 } 2768 } 2769 2770 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, 2771 const char *label, u32 ah_signal_type) 2772 { 2773 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2774 2775 if (BIT(gpio) & ah->caps.gpio_mask) 2776 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); 2777 else if (AR_SREV_SOC(ah)) 2778 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); 2779 else 2780 WARN_ON(1); 2781 } 2782 2783 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) 2784 { 2785 ath9k_hw_gpio_request(ah, gpio, false, label, 0); 2786 } 2787 EXPORT_SYMBOL(ath9k_hw_gpio_request_in); 2788 2789 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, 2790 u32 ah_signal_type) 2791 { 2792 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); 2793 } 2794 EXPORT_SYMBOL(ath9k_hw_gpio_request_out); 2795 2796 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) 2797 { 2798 if (!AR_SREV_SOC(ah)) 2799 return; 2800 2801 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2802 2803 if (ah->caps.gpio_requested & BIT(gpio)) { 2804 gpio_free(gpio); 2805 ah->caps.gpio_requested &= ~BIT(gpio); 2806 } 2807 } 2808 EXPORT_SYMBOL(ath9k_hw_gpio_free); 2809 2810 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2811 { 2812 u32 val = 0xffffffff; 2813 2814 #define MS_REG_READ(x, y) \ 2815 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) 2816 2817 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2818 2819 if (BIT(gpio) & ah->caps.gpio_mask) { 2820 if (AR_SREV_9271(ah)) 2821 val = MS_REG_READ(AR9271, gpio); 2822 else if (AR_SREV_9287(ah)) 2823 val = MS_REG_READ(AR9287, gpio); 2824 else if (AR_SREV_9285(ah)) 2825 val = MS_REG_READ(AR9285, gpio); 2826 else if (AR_SREV_9280(ah)) 2827 val = MS_REG_READ(AR928X, gpio); 2828 else if (AR_DEVID_7010(ah)) 2829 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); 2830 else if (AR_SREV_9300_20_OR_LATER(ah)) 2831 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); 2832 else 2833 val = MS_REG_READ(AR, gpio); 2834 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2835 val = gpio_get_value(gpio) & BIT(gpio); 2836 } else { 2837 WARN_ON(1); 2838 } 2839 2840 return !!val; 2841 } 2842 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2843 2844 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2845 { 2846 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2847 2848 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) 2849 val = !val; 2850 else 2851 val = !!val; 2852 2853 if (BIT(gpio) & ah->caps.gpio_mask) { 2854 u32 out_addr = AR_DEVID_7010(ah) ? 2855 AR7010_GPIO_OUT : AR_GPIO_IN_OUT; 2856 2857 REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); 2858 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2859 gpio_set_value(gpio, val); 2860 } else { 2861 WARN_ON(1); 2862 } 2863 } 2864 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2865 2866 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2867 { 2868 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2869 } 2870 EXPORT_SYMBOL(ath9k_hw_setantenna); 2871 2872 /*********************/ 2873 /* General Operation */ 2874 /*********************/ 2875 2876 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2877 { 2878 u32 bits = REG_READ(ah, AR_RX_FILTER); 2879 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2880 2881 if (phybits & AR_PHY_ERR_RADAR) 2882 bits |= ATH9K_RX_FILTER_PHYRADAR; 2883 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2884 bits |= ATH9K_RX_FILTER_PHYERR; 2885 2886 return bits; 2887 } 2888 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2889 2890 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2891 { 2892 u32 phybits; 2893 2894 ENABLE_REGWRITE_BUFFER(ah); 2895 2896 REG_WRITE(ah, AR_RX_FILTER, bits); 2897 2898 phybits = 0; 2899 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2900 phybits |= AR_PHY_ERR_RADAR; 2901 if (bits & ATH9K_RX_FILTER_PHYERR) 2902 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2903 REG_WRITE(ah, AR_PHY_ERR, phybits); 2904 2905 if (phybits) 2906 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2907 else 2908 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2909 2910 REGWRITE_BUFFER_FLUSH(ah); 2911 } 2912 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2913 2914 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2915 { 2916 if (ath9k_hw_mci_is_enabled(ah)) 2917 ar9003_mci_bt_gain_ctrl(ah); 2918 2919 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2920 return false; 2921 2922 ath9k_hw_init_pll(ah, NULL); 2923 ah->htc_reset_init = true; 2924 return true; 2925 } 2926 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2927 2928 bool ath9k_hw_disable(struct ath_hw *ah) 2929 { 2930 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2931 return false; 2932 2933 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2934 return false; 2935 2936 ath9k_hw_init_pll(ah, NULL); 2937 return true; 2938 } 2939 EXPORT_SYMBOL(ath9k_hw_disable); 2940 2941 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2942 { 2943 enum eeprom_param gain_param; 2944 2945 if (IS_CHAN_2GHZ(chan)) 2946 gain_param = EEP_ANTENNA_GAIN_2G; 2947 else 2948 gain_param = EEP_ANTENNA_GAIN_5G; 2949 2950 return ah->eep_ops->get_eeprom(ah, gain_param); 2951 } 2952 2953 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2954 bool test) 2955 { 2956 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2957 struct ieee80211_channel *channel; 2958 int chan_pwr, new_pwr; 2959 u16 ctl = NO_CTL; 2960 2961 if (!chan) 2962 return; 2963 2964 if (!test) 2965 ctl = ath9k_regd_get_ctl(reg, chan); 2966 2967 channel = chan->chan; 2968 chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER); 2969 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2970 2971 ah->eep_ops->set_txpower(ah, chan, ctl, 2972 get_antenna_gain(ah, chan), new_pwr, test); 2973 } 2974 2975 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2976 { 2977 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2978 struct ath9k_channel *chan = ah->curchan; 2979 struct ieee80211_channel *channel = chan->chan; 2980 2981 reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER); 2982 if (test) 2983 channel->max_power = MAX_COMBINED_POWER / 2; 2984 2985 ath9k_hw_apply_txpower(ah, chan, test); 2986 2987 if (test) 2988 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2989 } 2990 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2991 2992 void ath9k_hw_setopmode(struct ath_hw *ah) 2993 { 2994 ath9k_hw_set_operating_mode(ah, ah->opmode); 2995 } 2996 EXPORT_SYMBOL(ath9k_hw_setopmode); 2997 2998 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2999 { 3000 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3001 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3002 } 3003 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 3004 3005 void ath9k_hw_write_associd(struct ath_hw *ah) 3006 { 3007 struct ath_common *common = ath9k_hw_common(ah); 3008 3009 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 3010 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 3011 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3012 } 3013 EXPORT_SYMBOL(ath9k_hw_write_associd); 3014 3015 #define ATH9K_MAX_TSF_READ 10 3016 3017 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3018 { 3019 u32 tsf_lower, tsf_upper1, tsf_upper2; 3020 int i; 3021 3022 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 3023 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 3024 tsf_lower = REG_READ(ah, AR_TSF_L32); 3025 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 3026 if (tsf_upper2 == tsf_upper1) 3027 break; 3028 tsf_upper1 = tsf_upper2; 3029 } 3030 3031 WARN_ON( i == ATH9K_MAX_TSF_READ ); 3032 3033 return (((u64)tsf_upper1 << 32) | tsf_lower); 3034 } 3035 EXPORT_SYMBOL(ath9k_hw_gettsf64); 3036 3037 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3038 { 3039 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3040 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3041 } 3042 EXPORT_SYMBOL(ath9k_hw_settsf64); 3043 3044 void ath9k_hw_reset_tsf(struct ath_hw *ah) 3045 { 3046 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3047 AH_TSF_WRITE_TIMEOUT)) 3048 ath_dbg(ath9k_hw_common(ah), RESET, 3049 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3050 3051 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3052 } 3053 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 3054 3055 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 3056 { 3057 if (set) 3058 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3059 else 3060 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3061 } 3062 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 3063 3064 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 3065 { 3066 u32 macmode; 3067 3068 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 3069 macmode = AR_2040_JOINED_RX_CLEAR; 3070 else 3071 macmode = 0; 3072 3073 REG_WRITE(ah, AR_2040_MODE, macmode); 3074 } 3075 3076 /* HW Generic timers configuration */ 3077 3078 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 3079 { 3080 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3081 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3082 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3083 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3084 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3085 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3086 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3087 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3088 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 3089 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 3090 AR_NDP2_TIMER_MODE, 0x0002}, 3091 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3092 AR_NDP2_TIMER_MODE, 0x0004}, 3093 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3094 AR_NDP2_TIMER_MODE, 0x0008}, 3095 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3096 AR_NDP2_TIMER_MODE, 0x0010}, 3097 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3098 AR_NDP2_TIMER_MODE, 0x0020}, 3099 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3100 AR_NDP2_TIMER_MODE, 0x0040}, 3101 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3102 AR_NDP2_TIMER_MODE, 0x0080} 3103 }; 3104 3105 /* HW generic timer primitives */ 3106 3107 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3108 { 3109 return REG_READ(ah, AR_TSF_L32); 3110 } 3111 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3112 3113 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 3114 { 3115 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3116 3117 if (timer_table->tsf2_enabled) { 3118 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 3119 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 3120 } 3121 } 3122 3123 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3124 void (*trigger)(void *), 3125 void (*overflow)(void *), 3126 void *arg, 3127 u8 timer_index) 3128 { 3129 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3130 struct ath_gen_timer *timer; 3131 3132 if ((timer_index < AR_FIRST_NDP_TIMER) || 3133 (timer_index >= ATH_MAX_GEN_TIMER)) 3134 return NULL; 3135 3136 if ((timer_index > AR_FIRST_NDP_TIMER) && 3137 !AR_SREV_9300_20_OR_LATER(ah)) 3138 return NULL; 3139 3140 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3141 if (timer == NULL) 3142 return NULL; 3143 3144 /* allocate a hardware generic timer slot */ 3145 timer_table->timers[timer_index] = timer; 3146 timer->index = timer_index; 3147 timer->trigger = trigger; 3148 timer->overflow = overflow; 3149 timer->arg = arg; 3150 3151 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 3152 timer_table->tsf2_enabled = true; 3153 ath9k_hw_gen_timer_start_tsf2(ah); 3154 } 3155 3156 return timer; 3157 } 3158 EXPORT_SYMBOL(ath_gen_timer_alloc); 3159 3160 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3161 struct ath_gen_timer *timer, 3162 u32 timer_next, 3163 u32 timer_period) 3164 { 3165 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3166 u32 mask = 0; 3167 3168 timer_table->timer_mask |= BIT(timer->index); 3169 3170 /* 3171 * Program generic timer registers 3172 */ 3173 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3174 timer_next); 3175 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3176 timer_period); 3177 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3178 gen_tmr_configuration[timer->index].mode_mask); 3179 3180 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3181 /* 3182 * Starting from AR9462, each generic timer can select which tsf 3183 * to use. But we still follow the old rule, 0 - 7 use tsf and 3184 * 8 - 15 use tsf2. 3185 */ 3186 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3187 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3188 (1 << timer->index)); 3189 else 3190 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3191 (1 << timer->index)); 3192 } 3193 3194 if (timer->trigger) 3195 mask |= SM(AR_GENTMR_BIT(timer->index), 3196 AR_IMR_S5_GENTIMER_TRIG); 3197 if (timer->overflow) 3198 mask |= SM(AR_GENTMR_BIT(timer->index), 3199 AR_IMR_S5_GENTIMER_THRESH); 3200 3201 REG_SET_BIT(ah, AR_IMR_S5, mask); 3202 3203 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3204 ah->imask |= ATH9K_INT_GENTIMER; 3205 ath9k_hw_set_interrupts(ah); 3206 } 3207 } 3208 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3209 3210 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3211 { 3212 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3213 3214 /* Clear generic timer enable bits. */ 3215 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3216 gen_tmr_configuration[timer->index].mode_mask); 3217 3218 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3219 /* 3220 * Need to switch back to TSF if it was using TSF2. 3221 */ 3222 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3223 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3224 (1 << timer->index)); 3225 } 3226 } 3227 3228 /* Disable both trigger and thresh interrupt masks */ 3229 REG_CLR_BIT(ah, AR_IMR_S5, 3230 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3231 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3232 3233 timer_table->timer_mask &= ~BIT(timer->index); 3234 3235 if (timer_table->timer_mask == 0) { 3236 ah->imask &= ~ATH9K_INT_GENTIMER; 3237 ath9k_hw_set_interrupts(ah); 3238 } 3239 } 3240 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3241 3242 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3243 { 3244 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3245 3246 /* free the hardware generic timer slot */ 3247 timer_table->timers[timer->index] = NULL; 3248 kfree(timer); 3249 } 3250 EXPORT_SYMBOL(ath_gen_timer_free); 3251 3252 /* 3253 * Generic Timer Interrupts handling 3254 */ 3255 void ath_gen_timer_isr(struct ath_hw *ah) 3256 { 3257 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3258 struct ath_gen_timer *timer; 3259 unsigned long trigger_mask, thresh_mask; 3260 unsigned int index; 3261 3262 /* get hardware generic timer interrupt status */ 3263 trigger_mask = ah->intr_gen_timer_trigger; 3264 thresh_mask = ah->intr_gen_timer_thresh; 3265 trigger_mask &= timer_table->timer_mask; 3266 thresh_mask &= timer_table->timer_mask; 3267 3268 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3269 timer = timer_table->timers[index]; 3270 if (!timer) 3271 continue; 3272 if (!timer->overflow) 3273 continue; 3274 3275 trigger_mask &= ~BIT(index); 3276 timer->overflow(timer->arg); 3277 } 3278 3279 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3280 timer = timer_table->timers[index]; 3281 if (!timer) 3282 continue; 3283 if (!timer->trigger) 3284 continue; 3285 timer->trigger(timer->arg); 3286 } 3287 } 3288 EXPORT_SYMBOL(ath_gen_timer_isr); 3289 3290 /********/ 3291 /* HTC */ 3292 /********/ 3293 3294 static struct { 3295 u32 version; 3296 const char * name; 3297 } ath_mac_bb_names[] = { 3298 /* Devices with external radios */ 3299 { AR_SREV_VERSION_5416_PCI, "5416" }, 3300 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3301 { AR_SREV_VERSION_9100, "9100" }, 3302 { AR_SREV_VERSION_9160, "9160" }, 3303 /* Single-chip solutions */ 3304 { AR_SREV_VERSION_9280, "9280" }, 3305 { AR_SREV_VERSION_9285, "9285" }, 3306 { AR_SREV_VERSION_9287, "9287" }, 3307 { AR_SREV_VERSION_9271, "9271" }, 3308 { AR_SREV_VERSION_9300, "9300" }, 3309 { AR_SREV_VERSION_9330, "9330" }, 3310 { AR_SREV_VERSION_9340, "9340" }, 3311 { AR_SREV_VERSION_9485, "9485" }, 3312 { AR_SREV_VERSION_9462, "9462" }, 3313 { AR_SREV_VERSION_9550, "9550" }, 3314 { AR_SREV_VERSION_9565, "9565" }, 3315 { AR_SREV_VERSION_9531, "9531" }, 3316 { AR_SREV_VERSION_9561, "9561" }, 3317 }; 3318 3319 /* For devices with external radios */ 3320 static struct { 3321 u16 version; 3322 const char * name; 3323 } ath_rf_names[] = { 3324 { 0, "5133" }, 3325 { AR_RAD5133_SREV_MAJOR, "5133" }, 3326 { AR_RAD5122_SREV_MAJOR, "5122" }, 3327 { AR_RAD2133_SREV_MAJOR, "2133" }, 3328 { AR_RAD2122_SREV_MAJOR, "2122" } 3329 }; 3330 3331 /* 3332 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3333 */ 3334 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3335 { 3336 int i; 3337 3338 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3339 if (ath_mac_bb_names[i].version == mac_bb_version) { 3340 return ath_mac_bb_names[i].name; 3341 } 3342 } 3343 3344 return "????"; 3345 } 3346 3347 /* 3348 * Return the RF name. "????" is returned if the RF is unknown. 3349 * Used for devices with external radios. 3350 */ 3351 static const char *ath9k_hw_rf_name(u16 rf_version) 3352 { 3353 int i; 3354 3355 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3356 if (ath_rf_names[i].version == rf_version) { 3357 return ath_rf_names[i].name; 3358 } 3359 } 3360 3361 return "????"; 3362 } 3363 3364 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3365 { 3366 int used; 3367 3368 /* chipsets >= AR9280 are single-chip */ 3369 if (AR_SREV_9280_20_OR_LATER(ah)) { 3370 used = scnprintf(hw_name, len, 3371 "Atheros AR%s Rev:%x", 3372 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3373 ah->hw_version.macRev); 3374 } 3375 else { 3376 used = scnprintf(hw_name, len, 3377 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3378 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3379 ah->hw_version.macRev, 3380 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3381 & AR_RADIO_SREV_MAJOR)), 3382 ah->hw_version.phyRev); 3383 } 3384 3385 hw_name[used] = '\0'; 3386 } 3387 EXPORT_SYMBOL(ath9k_hw_name); 3388