1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <linux/gpio.h> 24 #include <asm/unaligned.h> 25 26 #include "hw.h" 27 #include "hw-ops.h" 28 #include "ar9003_mac.h" 29 #include "ar9003_mci.h" 30 #include "ar9003_phy.h" 31 #include "ath9k.h" 32 33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 41 { 42 struct ath_common *common = ath9k_hw_common(ah); 43 struct ath9k_channel *chan = ah->curchan; 44 unsigned int clockrate; 45 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 48 clockrate = 117; 49 else if (!chan) /* should really check for CCK instead */ 50 clockrate = ATH9K_CLOCK_RATE_CCK; 51 else if (IS_CHAN_2GHZ(chan)) 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 55 else 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 57 58 if (chan) { 59 if (IS_CHAN_HT40(chan)) 60 clockrate *= 2; 61 if (IS_CHAN_HALF_RATE(chan)) 62 clockrate /= 2; 63 if (IS_CHAN_QUARTER_RATE(chan)) 64 clockrate /= 4; 65 } 66 67 common->clockrate = clockrate; 68 } 69 70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 71 { 72 struct ath_common *common = ath9k_hw_common(ah); 73 74 return usecs * common->clockrate; 75 } 76 77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 78 { 79 int i; 80 81 BUG_ON(timeout < AH_TIME_QUANTUM); 82 83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 84 if ((REG_READ(ah, reg) & mask) == val) 85 return true; 86 87 udelay(AH_TIME_QUANTUM); 88 } 89 90 ath_dbg(ath9k_hw_common(ah), ANY, 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 92 timeout, reg, REG_READ(ah, reg), mask, val); 93 94 return false; 95 } 96 EXPORT_SYMBOL(ath9k_hw_wait); 97 98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 99 int hw_delay) 100 { 101 hw_delay /= 10; 102 103 if (IS_CHAN_HALF_RATE(chan)) 104 hw_delay *= 2; 105 else if (IS_CHAN_QUARTER_RATE(chan)) 106 hw_delay *= 4; 107 108 udelay(hw_delay + BASE_ACTIVATE_DELAY); 109 } 110 111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 112 int column, unsigned int *writecnt) 113 { 114 int r; 115 116 ENABLE_REGWRITE_BUFFER(ah); 117 for (r = 0; r < array->ia_rows; r++) { 118 REG_WRITE(ah, INI_RA(array, r, 0), 119 INI_RA(array, r, column)); 120 DO_DELAY(*writecnt); 121 } 122 REGWRITE_BUFFER_FLUSH(ah); 123 } 124 125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) 126 { 127 u32 *tmp_reg_list, *tmp_data; 128 int i; 129 130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL); 131 if (!tmp_reg_list) { 132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); 133 return; 134 } 135 136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL); 137 if (!tmp_data) { 138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); 139 goto error_tmp_data; 140 } 141 142 for (i = 0; i < size; i++) 143 tmp_reg_list[i] = array[i][0]; 144 145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); 146 147 for (i = 0; i < size; i++) 148 array[i][1] = tmp_data[i]; 149 150 kfree(tmp_data); 151 error_tmp_data: 152 kfree(tmp_reg_list); 153 } 154 155 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 156 { 157 u32 retval; 158 int i; 159 160 for (i = 0, retval = 0; i < n; i++) { 161 retval = (retval << 1) | (val & 1); 162 val >>= 1; 163 } 164 return retval; 165 } 166 167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 168 u8 phy, int kbps, 169 u32 frameLen, u16 rateix, 170 bool shortPreamble) 171 { 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 173 174 if (kbps == 0) 175 return 0; 176 177 switch (phy) { 178 case WLAN_RC_PHY_CCK: 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 180 if (shortPreamble) 181 phyTime >>= 1; 182 numBits = frameLen << 3; 183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 184 break; 185 case WLAN_RC_PHY_OFDM: 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 188 numBits = OFDM_PLCP_BITS + (frameLen << 3); 189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 190 txTime = OFDM_SIFS_TIME_QUARTER 191 + OFDM_PREAMBLE_TIME_QUARTER 192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 193 } else if (ah->curchan && 194 IS_CHAN_HALF_RATE(ah->curchan)) { 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 196 numBits = OFDM_PLCP_BITS + (frameLen << 3); 197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 198 txTime = OFDM_SIFS_TIME_HALF + 199 OFDM_PREAMBLE_TIME_HALF 200 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 201 } else { 202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 203 numBits = OFDM_PLCP_BITS + (frameLen << 3); 204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 206 + (numSymbols * OFDM_SYMBOL_TIME); 207 } 208 break; 209 default: 210 ath_err(ath9k_hw_common(ah), 211 "Unknown phy %u (rate ix %u)\n", phy, rateix); 212 txTime = 0; 213 break; 214 } 215 216 return txTime; 217 } 218 EXPORT_SYMBOL(ath9k_hw_computetxtime); 219 220 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 221 struct ath9k_channel *chan, 222 struct chan_centers *centers) 223 { 224 int8_t extoff; 225 226 if (!IS_CHAN_HT40(chan)) { 227 centers->ctl_center = centers->ext_center = 228 centers->synth_center = chan->channel; 229 return; 230 } 231 232 if (IS_CHAN_HT40PLUS(chan)) { 233 centers->synth_center = 234 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 235 extoff = 1; 236 } else { 237 centers->synth_center = 238 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 239 extoff = -1; 240 } 241 242 centers->ctl_center = 243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 244 /* 25 MHz spacing is supported by hw but not on upper layers */ 245 centers->ext_center = 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 247 } 248 249 /******************/ 250 /* Chip Revisions */ 251 /******************/ 252 253 static void ath9k_hw_read_revisions(struct ath_hw *ah) 254 { 255 u32 val; 256 257 if (ah->get_mac_revision) 258 ah->hw_version.macRev = ah->get_mac_revision(); 259 260 switch (ah->hw_version.devid) { 261 case AR5416_AR9100_DEVID: 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 263 break; 264 case AR9300_DEVID_AR9330: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 266 if (!ah->get_mac_revision) { 267 val = REG_READ(ah, AR_SREV); 268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 269 } 270 return; 271 case AR9300_DEVID_AR9340: 272 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 273 return; 274 case AR9300_DEVID_QCA955X: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 276 return; 277 case AR9300_DEVID_AR953X: 278 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 279 return; 280 case AR9300_DEVID_QCA956X: 281 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 282 } 283 284 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 285 286 if (val == 0xFF) { 287 val = REG_READ(ah, AR_SREV); 288 ah->hw_version.macVersion = 289 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 290 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 291 292 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 293 ah->is_pciexpress = true; 294 else 295 ah->is_pciexpress = (val & 296 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 297 } else { 298 if (!AR_SREV_9100(ah)) 299 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 300 301 ah->hw_version.macRev = val & AR_SREV_REVISION; 302 303 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 304 ah->is_pciexpress = true; 305 } 306 } 307 308 /************************************/ 309 /* HW Attach, Detach, Init Routines */ 310 /************************************/ 311 312 static void ath9k_hw_disablepcie(struct ath_hw *ah) 313 { 314 if (!AR_SREV_5416(ah)) 315 return; 316 317 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 324 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 325 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 326 327 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 328 } 329 330 /* This should work for all families including legacy */ 331 static bool ath9k_hw_chip_test(struct ath_hw *ah) 332 { 333 struct ath_common *common = ath9k_hw_common(ah); 334 u32 regAddr[2] = { AR_STA_ID0 }; 335 u32 regHold[2]; 336 static const u32 patternData[4] = { 337 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 338 }; 339 int i, j, loop_max; 340 341 if (!AR_SREV_9300_20_OR_LATER(ah)) { 342 loop_max = 2; 343 regAddr[1] = AR_PHY_BASE + (8 << 2); 344 } else 345 loop_max = 1; 346 347 for (i = 0; i < loop_max; i++) { 348 u32 addr = regAddr[i]; 349 u32 wrData, rdData; 350 351 regHold[i] = REG_READ(ah, addr); 352 for (j = 0; j < 0x100; j++) { 353 wrData = (j << 16) | j; 354 REG_WRITE(ah, addr, wrData); 355 rdData = REG_READ(ah, addr); 356 if (rdData != wrData) { 357 ath_err(common, 358 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 359 addr, wrData, rdData); 360 return false; 361 } 362 } 363 for (j = 0; j < 4; j++) { 364 wrData = patternData[j]; 365 REG_WRITE(ah, addr, wrData); 366 rdData = REG_READ(ah, addr); 367 if (wrData != rdData) { 368 ath_err(common, 369 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 370 addr, wrData, rdData); 371 return false; 372 } 373 } 374 REG_WRITE(ah, regAddr[i], regHold[i]); 375 } 376 udelay(100); 377 378 return true; 379 } 380 381 static void ath9k_hw_init_config(struct ath_hw *ah) 382 { 383 struct ath_common *common = ath9k_hw_common(ah); 384 385 ah->config.dma_beacon_response_time = 1; 386 ah->config.sw_beacon_response_time = 6; 387 ah->config.cwm_ignore_extcca = 0; 388 ah->config.analog_shiftreg = 1; 389 390 ah->config.rx_intr_mitigation = true; 391 392 if (AR_SREV_9300_20_OR_LATER(ah)) { 393 ah->config.rimt_last = 500; 394 ah->config.rimt_first = 2000; 395 } else { 396 ah->config.rimt_last = 250; 397 ah->config.rimt_first = 700; 398 } 399 400 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 401 ah->config.pll_pwrsave = 7; 402 403 /* 404 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 405 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 406 * This means we use it for all AR5416 devices, and the few 407 * minor PCI AR9280 devices out there. 408 * 409 * Serialization is required because these devices do not handle 410 * well the case of two concurrent reads/writes due to the latency 411 * involved. During one read/write another read/write can be issued 412 * on another CPU while the previous read/write may still be working 413 * on our hardware, if we hit this case the hardware poops in a loop. 414 * We prevent this by serializing reads and writes. 415 * 416 * This issue is not present on PCI-Express devices or pre-AR5416 417 * devices (legacy, 802.11abg). 418 */ 419 if (num_possible_cpus() > 1) 420 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 421 422 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 423 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 424 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 425 !ah->is_pciexpress)) { 426 ah->config.serialize_regmode = SER_REG_MODE_ON; 427 } else { 428 ah->config.serialize_regmode = SER_REG_MODE_OFF; 429 } 430 } 431 432 ath_dbg(common, RESET, "serialize_regmode is %d\n", 433 ah->config.serialize_regmode); 434 435 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 436 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 437 else 438 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 439 } 440 441 static void ath9k_hw_init_defaults(struct ath_hw *ah) 442 { 443 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 444 445 regulatory->country_code = CTRY_DEFAULT; 446 regulatory->power_limit = MAX_RATE_POWER; 447 448 ah->hw_version.magic = AR5416_MAGIC; 449 ah->hw_version.subvendorid = 0; 450 451 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 452 AR_STA_ID1_MCAST_KSRCH; 453 if (AR_SREV_9100(ah)) 454 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 455 456 ah->slottime = ATH9K_SLOT_TIME_9; 457 ah->globaltxtimeout = (u32) -1; 458 ah->power_mode = ATH9K_PM_UNDEFINED; 459 ah->htc_reset_init = true; 460 461 ah->tpc_enabled = false; 462 463 ah->ani_function = ATH9K_ANI_ALL; 464 if (!AR_SREV_9300_20_OR_LATER(ah)) 465 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 466 467 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 468 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 469 else 470 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 471 } 472 473 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 474 { 475 struct ath_common *common = ath9k_hw_common(ah); 476 u32 sum; 477 int i; 478 u16 eeval; 479 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 480 481 sum = 0; 482 for (i = 0; i < 3; i++) { 483 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 484 sum += eeval; 485 common->macaddr[2 * i] = eeval >> 8; 486 common->macaddr[2 * i + 1] = eeval & 0xff; 487 } 488 if (!is_valid_ether_addr(common->macaddr)) { 489 ath_err(common, 490 "eeprom contains invalid mac address: %pM\n", 491 common->macaddr); 492 493 random_ether_addr(common->macaddr); 494 ath_err(common, 495 "random mac address will be used: %pM\n", 496 common->macaddr); 497 } 498 499 return 0; 500 } 501 502 static int ath9k_hw_post_init(struct ath_hw *ah) 503 { 504 struct ath_common *common = ath9k_hw_common(ah); 505 int ecode; 506 507 if (common->bus_ops->ath_bus_type != ATH_USB) { 508 if (!ath9k_hw_chip_test(ah)) 509 return -ENODEV; 510 } 511 512 if (!AR_SREV_9300_20_OR_LATER(ah)) { 513 ecode = ar9002_hw_rf_claim(ah); 514 if (ecode != 0) 515 return ecode; 516 } 517 518 ecode = ath9k_hw_eeprom_init(ah); 519 if (ecode != 0) 520 return ecode; 521 522 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 523 ah->eep_ops->get_eeprom_ver(ah), 524 ah->eep_ops->get_eeprom_rev(ah)); 525 526 ath9k_hw_ani_init(ah); 527 528 /* 529 * EEPROM needs to be initialized before we do this. 530 * This is required for regulatory compliance. 531 */ 532 if (AR_SREV_9300_20_OR_LATER(ah)) { 533 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 534 if ((regdmn & 0xF0) == CTL_FCC) { 535 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 536 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 537 } 538 } 539 540 return 0; 541 } 542 543 static int ath9k_hw_attach_ops(struct ath_hw *ah) 544 { 545 if (!AR_SREV_9300_20_OR_LATER(ah)) 546 return ar9002_hw_attach_ops(ah); 547 548 ar9003_hw_attach_ops(ah); 549 return 0; 550 } 551 552 /* Called for all hardware families */ 553 static int __ath9k_hw_init(struct ath_hw *ah) 554 { 555 struct ath_common *common = ath9k_hw_common(ah); 556 int r = 0; 557 558 ath9k_hw_read_revisions(ah); 559 560 switch (ah->hw_version.macVersion) { 561 case AR_SREV_VERSION_5416_PCI: 562 case AR_SREV_VERSION_5416_PCIE: 563 case AR_SREV_VERSION_9160: 564 case AR_SREV_VERSION_9100: 565 case AR_SREV_VERSION_9280: 566 case AR_SREV_VERSION_9285: 567 case AR_SREV_VERSION_9287: 568 case AR_SREV_VERSION_9271: 569 case AR_SREV_VERSION_9300: 570 case AR_SREV_VERSION_9330: 571 case AR_SREV_VERSION_9485: 572 case AR_SREV_VERSION_9340: 573 case AR_SREV_VERSION_9462: 574 case AR_SREV_VERSION_9550: 575 case AR_SREV_VERSION_9565: 576 case AR_SREV_VERSION_9531: 577 case AR_SREV_VERSION_9561: 578 break; 579 default: 580 ath_err(common, 581 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 582 ah->hw_version.macVersion, ah->hw_version.macRev); 583 return -EOPNOTSUPP; 584 } 585 586 /* 587 * Read back AR_WA into a permanent copy and set bits 14 and 17. 588 * We need to do this to avoid RMW of this register. We cannot 589 * read the reg when chip is asleep. 590 */ 591 if (AR_SREV_9300_20_OR_LATER(ah)) { 592 ah->WARegVal = REG_READ(ah, AR_WA); 593 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 594 AR_WA_ASPM_TIMER_BASED_DISABLE); 595 } 596 597 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 ath_err(common, "Couldn't reset chip\n"); 599 return -EIO; 600 } 601 602 if (AR_SREV_9565(ah)) { 603 ah->WARegVal |= AR_WA_BIT22; 604 REG_WRITE(ah, AR_WA, ah->WARegVal); 605 } 606 607 ath9k_hw_init_defaults(ah); 608 ath9k_hw_init_config(ah); 609 610 r = ath9k_hw_attach_ops(ah); 611 if (r) 612 return r; 613 614 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 615 ath_err(common, "Couldn't wakeup chip\n"); 616 return -EIO; 617 } 618 619 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 620 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 621 ah->is_pciexpress = false; 622 623 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 624 ath9k_hw_init_cal_settings(ah); 625 626 if (!ah->is_pciexpress) 627 ath9k_hw_disablepcie(ah); 628 629 r = ath9k_hw_post_init(ah); 630 if (r) 631 return r; 632 633 ath9k_hw_init_mode_gain_regs(ah); 634 r = ath9k_hw_fill_cap_info(ah); 635 if (r) 636 return r; 637 638 r = ath9k_hw_init_macaddr(ah); 639 if (r) { 640 ath_err(common, "Failed to initialize MAC address\n"); 641 return r; 642 } 643 644 ath9k_hw_init_hang_checks(ah); 645 646 common->state = ATH_HW_INITIALIZED; 647 648 return 0; 649 } 650 651 int ath9k_hw_init(struct ath_hw *ah) 652 { 653 int ret; 654 struct ath_common *common = ath9k_hw_common(ah); 655 656 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 657 switch (ah->hw_version.devid) { 658 case AR5416_DEVID_PCI: 659 case AR5416_DEVID_PCIE: 660 case AR5416_AR9100_DEVID: 661 case AR9160_DEVID_PCI: 662 case AR9280_DEVID_PCI: 663 case AR9280_DEVID_PCIE: 664 case AR9285_DEVID_PCIE: 665 case AR9287_DEVID_PCI: 666 case AR9287_DEVID_PCIE: 667 case AR2427_DEVID_PCIE: 668 case AR9300_DEVID_PCIE: 669 case AR9300_DEVID_AR9485_PCIE: 670 case AR9300_DEVID_AR9330: 671 case AR9300_DEVID_AR9340: 672 case AR9300_DEVID_QCA955X: 673 case AR9300_DEVID_AR9580: 674 case AR9300_DEVID_AR9462: 675 case AR9485_DEVID_AR1111: 676 case AR9300_DEVID_AR9565: 677 case AR9300_DEVID_AR953X: 678 case AR9300_DEVID_QCA956X: 679 break; 680 default: 681 if (common->bus_ops->ath_bus_type == ATH_USB) 682 break; 683 ath_err(common, "Hardware device ID 0x%04x not supported\n", 684 ah->hw_version.devid); 685 return -EOPNOTSUPP; 686 } 687 688 ret = __ath9k_hw_init(ah); 689 if (ret) { 690 ath_err(common, 691 "Unable to initialize hardware; initialization status: %d\n", 692 ret); 693 return ret; 694 } 695 696 ath_dynack_init(ah); 697 698 return 0; 699 } 700 EXPORT_SYMBOL(ath9k_hw_init); 701 702 static void ath9k_hw_init_qos(struct ath_hw *ah) 703 { 704 ENABLE_REGWRITE_BUFFER(ah); 705 706 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 707 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 708 709 REG_WRITE(ah, AR_QOS_NO_ACK, 710 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 711 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 712 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 713 714 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 715 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 716 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 717 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 718 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 719 720 REGWRITE_BUFFER_FLUSH(ah); 721 } 722 723 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 724 { 725 struct ath_common *common = ath9k_hw_common(ah); 726 int i = 0; 727 728 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 729 udelay(100); 730 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 731 732 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 733 734 udelay(100); 735 736 if (WARN_ON_ONCE(i >= 100)) { 737 ath_err(common, "PLL4 meaurement not done\n"); 738 break; 739 } 740 741 i++; 742 } 743 744 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 745 } 746 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 747 748 static void ath9k_hw_init_pll(struct ath_hw *ah, 749 struct ath9k_channel *chan) 750 { 751 u32 pll; 752 753 pll = ath9k_hw_compute_pll_control(ah, chan); 754 755 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 756 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 758 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 760 AR_CH0_DPLL2_KD, 0x40); 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 762 AR_CH0_DPLL2_KI, 0x4); 763 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 765 AR_CH0_BB_DPLL1_REFDIV, 0x5); 766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 767 AR_CH0_BB_DPLL1_NINI, 0x58); 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 769 AR_CH0_BB_DPLL1_NFRAC, 0x0); 770 771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 772 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 774 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 775 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 776 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 777 778 /* program BB PLL phase_shift to 0x6 */ 779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 780 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 781 782 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 783 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 784 udelay(1000); 785 } else if (AR_SREV_9330(ah)) { 786 u32 ddr_dpll2, pll_control2, kd; 787 788 if (ah->is_clk_25mhz) { 789 ddr_dpll2 = 0x18e82f01; 790 pll_control2 = 0xe04a3d; 791 kd = 0x1d; 792 } else { 793 ddr_dpll2 = 0x19e82f01; 794 pll_control2 = 0x886666; 795 kd = 0x3d; 796 } 797 798 /* program DDR PLL ki and kd value */ 799 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 800 801 /* program DDR PLL phase_shift */ 802 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 803 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 804 805 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 806 pll | AR_RTC_9300_PLL_BYPASS); 807 udelay(1000); 808 809 /* program refdiv, nint, frac to RTC register */ 810 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 811 812 /* program BB PLL kd and ki value */ 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 815 816 /* program BB PLL phase_shift */ 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 818 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 819 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 820 AR_SREV_9561(ah)) { 821 u32 regval, pll2_divint, pll2_divfrac, refdiv; 822 823 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 824 pll | AR_RTC_9300_SOC_PLL_BYPASS); 825 udelay(1000); 826 827 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 828 udelay(100); 829 830 if (ah->is_clk_25mhz) { 831 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 832 pll2_divint = 0x1c; 833 pll2_divfrac = 0xa3d2; 834 refdiv = 1; 835 } else { 836 pll2_divint = 0x54; 837 pll2_divfrac = 0x1eb85; 838 refdiv = 3; 839 } 840 } else { 841 if (AR_SREV_9340(ah)) { 842 pll2_divint = 88; 843 pll2_divfrac = 0; 844 refdiv = 5; 845 } else { 846 pll2_divint = 0x11; 847 pll2_divfrac = (AR_SREV_9531(ah) || 848 AR_SREV_9561(ah)) ? 849 0x26665 : 0x26666; 850 refdiv = 1; 851 } 852 } 853 854 regval = REG_READ(ah, AR_PHY_PLL_MODE); 855 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 856 regval |= (0x1 << 22); 857 else 858 regval |= (0x1 << 16); 859 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 860 udelay(100); 861 862 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 863 (pll2_divint << 18) | pll2_divfrac); 864 udelay(100); 865 866 regval = REG_READ(ah, AR_PHY_PLL_MODE); 867 if (AR_SREV_9340(ah)) 868 regval = (regval & 0x80071fff) | 869 (0x1 << 30) | 870 (0x1 << 13) | 871 (0x4 << 26) | 872 (0x18 << 19); 873 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 874 regval = (regval & 0x01c00fff) | 875 (0x1 << 31) | 876 (0x2 << 29) | 877 (0xa << 25) | 878 (0x1 << 19); 879 880 if (AR_SREV_9531(ah)) 881 regval |= (0x6 << 12); 882 } else 883 regval = (regval & 0x80071fff) | 884 (0x3 << 30) | 885 (0x1 << 13) | 886 (0x4 << 26) | 887 (0x60 << 19); 888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 889 890 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 891 REG_WRITE(ah, AR_PHY_PLL_MODE, 892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 893 else 894 REG_WRITE(ah, AR_PHY_PLL_MODE, 895 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 896 897 udelay(1000); 898 } 899 900 if (AR_SREV_9565(ah)) 901 pll |= 0x40000; 902 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 903 904 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 905 AR_SREV_9550(ah)) 906 udelay(1000); 907 908 /* Switch the core clock for ar9271 to 117Mhz */ 909 if (AR_SREV_9271(ah)) { 910 udelay(500); 911 REG_WRITE(ah, 0x50040, 0x304); 912 } 913 914 udelay(RTC_PLL_SETTLE_DELAY); 915 916 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 917 } 918 919 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 920 enum nl80211_iftype opmode) 921 { 922 u32 sync_default = AR_INTR_SYNC_DEFAULT; 923 u32 imr_reg = AR_IMR_TXERR | 924 AR_IMR_TXURN | 925 AR_IMR_RXERR | 926 AR_IMR_RXORN | 927 AR_IMR_BCNMISC; 928 929 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 930 AR_SREV_9561(ah)) 931 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 932 933 if (AR_SREV_9300_20_OR_LATER(ah)) { 934 imr_reg |= AR_IMR_RXOK_HP; 935 if (ah->config.rx_intr_mitigation) 936 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 937 else 938 imr_reg |= AR_IMR_RXOK_LP; 939 940 } else { 941 if (ah->config.rx_intr_mitigation) 942 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 943 else 944 imr_reg |= AR_IMR_RXOK; 945 } 946 947 if (ah->config.tx_intr_mitigation) 948 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 949 else 950 imr_reg |= AR_IMR_TXOK; 951 952 ENABLE_REGWRITE_BUFFER(ah); 953 954 REG_WRITE(ah, AR_IMR, imr_reg); 955 ah->imrs2_reg |= AR_IMR_S2_GTT; 956 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 957 958 if (!AR_SREV_9100(ah)) { 959 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 960 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 961 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 962 } 963 964 REGWRITE_BUFFER_FLUSH(ah); 965 966 if (AR_SREV_9300_20_OR_LATER(ah)) { 967 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 969 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 971 } 972 } 973 974 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 975 { 976 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 977 val = min(val, (u32) 0xFFFF); 978 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 979 } 980 981 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 982 { 983 u32 val = ath9k_hw_mac_to_clks(ah, us); 984 val = min(val, (u32) 0xFFFF); 985 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 986 } 987 988 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 989 { 990 u32 val = ath9k_hw_mac_to_clks(ah, us); 991 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 992 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 993 } 994 995 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 996 { 997 u32 val = ath9k_hw_mac_to_clks(ah, us); 998 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 999 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1000 } 1001 1002 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1003 { 1004 if (tu > 0xFFFF) { 1005 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1006 tu); 1007 ah->globaltxtimeout = (u32) -1; 1008 return false; 1009 } else { 1010 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1011 ah->globaltxtimeout = tu; 1012 return true; 1013 } 1014 } 1015 1016 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1017 { 1018 struct ath_common *common = ath9k_hw_common(ah); 1019 const struct ath9k_channel *chan = ah->curchan; 1020 int acktimeout, ctstimeout, ack_offset = 0; 1021 int slottime; 1022 int sifstime; 1023 int rx_lat = 0, tx_lat = 0, eifs = 0; 1024 u32 reg; 1025 1026 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1027 ah->misc_mode); 1028 1029 if (!chan) 1030 return; 1031 1032 if (ah->misc_mode != 0) 1033 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1034 1035 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1036 rx_lat = 41; 1037 else 1038 rx_lat = 37; 1039 tx_lat = 54; 1040 1041 if (IS_CHAN_5GHZ(chan)) 1042 sifstime = 16; 1043 else 1044 sifstime = 10; 1045 1046 if (IS_CHAN_HALF_RATE(chan)) { 1047 eifs = 175; 1048 rx_lat *= 2; 1049 tx_lat *= 2; 1050 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1051 tx_lat += 11; 1052 1053 sifstime = 32; 1054 ack_offset = 16; 1055 slottime = 13; 1056 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1057 eifs = 340; 1058 rx_lat = (rx_lat * 4) - 1; 1059 tx_lat *= 4; 1060 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1061 tx_lat += 22; 1062 1063 sifstime = 64; 1064 ack_offset = 32; 1065 slottime = 21; 1066 } else { 1067 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1068 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1069 reg = AR_USEC_ASYNC_FIFO; 1070 } else { 1071 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1072 common->clockrate; 1073 reg = REG_READ(ah, AR_USEC); 1074 } 1075 rx_lat = MS(reg, AR_USEC_RX_LAT); 1076 tx_lat = MS(reg, AR_USEC_TX_LAT); 1077 1078 slottime = ah->slottime; 1079 } 1080 1081 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1082 slottime += 3 * ah->coverage_class; 1083 acktimeout = slottime + sifstime + ack_offset; 1084 ctstimeout = acktimeout; 1085 1086 /* 1087 * Workaround for early ACK timeouts, add an offset to match the 1088 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1089 * This was initially only meant to work around an issue with delayed 1090 * BA frames in some implementations, but it has been found to fix ACK 1091 * timeout issues in other cases as well. 1092 */ 1093 if (IS_CHAN_2GHZ(chan) && 1094 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1095 acktimeout += 64 - sifstime - ah->slottime; 1096 ctstimeout += 48 - sifstime - ah->slottime; 1097 } 1098 1099 if (ah->dynack.enabled) { 1100 acktimeout = ah->dynack.ackto; 1101 ctstimeout = acktimeout; 1102 slottime = (acktimeout - 3) / 2; 1103 } else { 1104 ah->dynack.ackto = acktimeout; 1105 } 1106 1107 ath9k_hw_set_sifs_time(ah, sifstime); 1108 ath9k_hw_setslottime(ah, slottime); 1109 ath9k_hw_set_ack_timeout(ah, acktimeout); 1110 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1111 if (ah->globaltxtimeout != (u32) -1) 1112 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1113 1114 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1115 REG_RMW(ah, AR_USEC, 1116 (common->clockrate - 1) | 1117 SM(rx_lat, AR_USEC_RX_LAT) | 1118 SM(tx_lat, AR_USEC_TX_LAT), 1119 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1120 1121 } 1122 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1123 1124 void ath9k_hw_deinit(struct ath_hw *ah) 1125 { 1126 struct ath_common *common = ath9k_hw_common(ah); 1127 1128 if (common->state < ATH_HW_INITIALIZED) 1129 return; 1130 1131 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1132 } 1133 EXPORT_SYMBOL(ath9k_hw_deinit); 1134 1135 /*******/ 1136 /* INI */ 1137 /*******/ 1138 1139 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1140 { 1141 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1142 1143 if (IS_CHAN_2GHZ(chan)) 1144 ctl |= CTL_11G; 1145 else 1146 ctl |= CTL_11A; 1147 1148 return ctl; 1149 } 1150 1151 /****************************************/ 1152 /* Reset and Channel Switching Routines */ 1153 /****************************************/ 1154 1155 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1156 { 1157 struct ath_common *common = ath9k_hw_common(ah); 1158 int txbuf_size; 1159 1160 ENABLE_REGWRITE_BUFFER(ah); 1161 1162 /* 1163 * set AHB_MODE not to do cacheline prefetches 1164 */ 1165 if (!AR_SREV_9300_20_OR_LATER(ah)) 1166 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1167 1168 /* 1169 * let mac dma reads be in 128 byte chunks 1170 */ 1171 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1172 1173 REGWRITE_BUFFER_FLUSH(ah); 1174 1175 /* 1176 * Restore TX Trigger Level to its pre-reset value. 1177 * The initial value depends on whether aggregation is enabled, and is 1178 * adjusted whenever underruns are detected. 1179 */ 1180 if (!AR_SREV_9300_20_OR_LATER(ah)) 1181 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1182 1183 ENABLE_REGWRITE_BUFFER(ah); 1184 1185 /* 1186 * let mac dma writes be in 128 byte chunks 1187 */ 1188 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1189 1190 /* 1191 * Setup receive FIFO threshold to hold off TX activities 1192 */ 1193 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1194 1195 if (AR_SREV_9300_20_OR_LATER(ah)) { 1196 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1198 1199 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1200 ah->caps.rx_status_len); 1201 } 1202 1203 /* 1204 * reduce the number of usable entries in PCU TXBUF to avoid 1205 * wrap around issues. 1206 */ 1207 if (AR_SREV_9285(ah)) { 1208 /* For AR9285 the number of Fifos are reduced to half. 1209 * So set the usable tx buf size also to half to 1210 * avoid data/delimiter underruns 1211 */ 1212 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1213 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1214 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1215 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1216 } else { 1217 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1218 } 1219 1220 if (!AR_SREV_9271(ah)) 1221 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1222 1223 REGWRITE_BUFFER_FLUSH(ah); 1224 1225 if (AR_SREV_9300_20_OR_LATER(ah)) 1226 ath9k_hw_reset_txstatus_ring(ah); 1227 } 1228 1229 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1230 { 1231 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1232 u32 set = AR_STA_ID1_KSRCH_MODE; 1233 1234 ENABLE_REG_RMW_BUFFER(ah); 1235 switch (opmode) { 1236 case NL80211_IFTYPE_ADHOC: 1237 if (!AR_SREV_9340_13(ah)) { 1238 set |= AR_STA_ID1_ADHOC; 1239 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1240 break; 1241 } 1242 /* fall through */ 1243 case NL80211_IFTYPE_MESH_POINT: 1244 case NL80211_IFTYPE_AP: 1245 set |= AR_STA_ID1_STA_AP; 1246 /* fall through */ 1247 case NL80211_IFTYPE_STATION: 1248 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1249 break; 1250 default: 1251 if (!ah->is_monitoring) 1252 set = 0; 1253 break; 1254 } 1255 REG_RMW(ah, AR_STA_ID1, set, mask); 1256 REG_RMW_BUFFER_FLUSH(ah); 1257 } 1258 1259 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1260 u32 *coef_mantissa, u32 *coef_exponent) 1261 { 1262 u32 coef_exp, coef_man; 1263 1264 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1265 if ((coef_scaled >> coef_exp) & 0x1) 1266 break; 1267 1268 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1269 1270 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1271 1272 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1273 *coef_exponent = coef_exp - 16; 1274 } 1275 1276 /* AR9330 WAR: 1277 * call external reset function to reset WMAC if: 1278 * - doing a cold reset 1279 * - we have pending frames in the TX queues. 1280 */ 1281 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1282 { 1283 int i, npend = 0; 1284 1285 for (i = 0; i < AR_NUM_QCU; i++) { 1286 npend = ath9k_hw_numtxpending(ah, i); 1287 if (npend) 1288 break; 1289 } 1290 1291 if (ah->external_reset && 1292 (npend || type == ATH9K_RESET_COLD)) { 1293 int reset_err = 0; 1294 1295 ath_dbg(ath9k_hw_common(ah), RESET, 1296 "reset MAC via external reset\n"); 1297 1298 reset_err = ah->external_reset(); 1299 if (reset_err) { 1300 ath_err(ath9k_hw_common(ah), 1301 "External reset failed, err=%d\n", 1302 reset_err); 1303 return false; 1304 } 1305 1306 REG_WRITE(ah, AR_RTC_RESET, 1); 1307 } 1308 1309 return true; 1310 } 1311 1312 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1313 { 1314 u32 rst_flags; 1315 u32 tmpReg; 1316 1317 if (AR_SREV_9100(ah)) { 1318 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1319 AR_RTC_DERIVED_CLK_PERIOD, 1); 1320 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1321 } 1322 1323 ENABLE_REGWRITE_BUFFER(ah); 1324 1325 if (AR_SREV_9300_20_OR_LATER(ah)) { 1326 REG_WRITE(ah, AR_WA, ah->WARegVal); 1327 udelay(10); 1328 } 1329 1330 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1331 AR_RTC_FORCE_WAKE_ON_INT); 1332 1333 if (AR_SREV_9100(ah)) { 1334 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1335 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1336 } else { 1337 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1338 if (AR_SREV_9340(ah)) 1339 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1340 else 1341 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1342 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1343 1344 if (tmpReg) { 1345 u32 val; 1346 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1347 1348 val = AR_RC_HOSTIF; 1349 if (!AR_SREV_9300_20_OR_LATER(ah)) 1350 val |= AR_RC_AHB; 1351 REG_WRITE(ah, AR_RC, val); 1352 1353 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1354 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1355 1356 rst_flags = AR_RTC_RC_MAC_WARM; 1357 if (type == ATH9K_RESET_COLD) 1358 rst_flags |= AR_RTC_RC_MAC_COLD; 1359 } 1360 1361 if (AR_SREV_9330(ah)) { 1362 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1363 return false; 1364 } 1365 1366 if (ath9k_hw_mci_is_enabled(ah)) 1367 ar9003_mci_check_gpm_offset(ah); 1368 1369 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1370 1371 REGWRITE_BUFFER_FLUSH(ah); 1372 1373 if (AR_SREV_9300_20_OR_LATER(ah)) 1374 udelay(50); 1375 else if (AR_SREV_9100(ah)) 1376 mdelay(10); 1377 else 1378 udelay(100); 1379 1380 REG_WRITE(ah, AR_RTC_RC, 0); 1381 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1382 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1383 return false; 1384 } 1385 1386 if (!AR_SREV_9100(ah)) 1387 REG_WRITE(ah, AR_RC, 0); 1388 1389 if (AR_SREV_9100(ah)) 1390 udelay(50); 1391 1392 return true; 1393 } 1394 1395 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1396 { 1397 ENABLE_REGWRITE_BUFFER(ah); 1398 1399 if (AR_SREV_9300_20_OR_LATER(ah)) { 1400 REG_WRITE(ah, AR_WA, ah->WARegVal); 1401 udelay(10); 1402 } 1403 1404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1405 AR_RTC_FORCE_WAKE_ON_INT); 1406 1407 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1408 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1409 1410 REG_WRITE(ah, AR_RTC_RESET, 0); 1411 1412 REGWRITE_BUFFER_FLUSH(ah); 1413 1414 udelay(2); 1415 1416 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1417 REG_WRITE(ah, AR_RC, 0); 1418 1419 REG_WRITE(ah, AR_RTC_RESET, 1); 1420 1421 if (!ath9k_hw_wait(ah, 1422 AR_RTC_STATUS, 1423 AR_RTC_STATUS_M, 1424 AR_RTC_STATUS_ON, 1425 AH_WAIT_TIMEOUT)) { 1426 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1427 return false; 1428 } 1429 1430 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1431 } 1432 1433 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1434 { 1435 bool ret = false; 1436 1437 if (AR_SREV_9300_20_OR_LATER(ah)) { 1438 REG_WRITE(ah, AR_WA, ah->WARegVal); 1439 udelay(10); 1440 } 1441 1442 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1443 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1444 1445 if (!ah->reset_power_on) 1446 type = ATH9K_RESET_POWER_ON; 1447 1448 switch (type) { 1449 case ATH9K_RESET_POWER_ON: 1450 ret = ath9k_hw_set_reset_power_on(ah); 1451 if (ret) 1452 ah->reset_power_on = true; 1453 break; 1454 case ATH9K_RESET_WARM: 1455 case ATH9K_RESET_COLD: 1456 ret = ath9k_hw_set_reset(ah, type); 1457 break; 1458 default: 1459 break; 1460 } 1461 1462 return ret; 1463 } 1464 1465 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1466 struct ath9k_channel *chan) 1467 { 1468 int reset_type = ATH9K_RESET_WARM; 1469 1470 if (AR_SREV_9280(ah)) { 1471 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1472 reset_type = ATH9K_RESET_POWER_ON; 1473 else 1474 reset_type = ATH9K_RESET_COLD; 1475 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1476 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1477 reset_type = ATH9K_RESET_COLD; 1478 1479 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1480 return false; 1481 1482 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1483 return false; 1484 1485 ah->chip_fullsleep = false; 1486 1487 if (AR_SREV_9330(ah)) 1488 ar9003_hw_internal_regulator_apply(ah); 1489 ath9k_hw_init_pll(ah, chan); 1490 1491 return true; 1492 } 1493 1494 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1495 struct ath9k_channel *chan) 1496 { 1497 struct ath_common *common = ath9k_hw_common(ah); 1498 struct ath9k_hw_capabilities *pCap = &ah->caps; 1499 bool band_switch = false, mode_diff = false; 1500 u8 ini_reloaded = 0; 1501 u32 qnum; 1502 int r; 1503 1504 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1505 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1506 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1507 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1508 } 1509 1510 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1511 if (ath9k_hw_numtxpending(ah, qnum)) { 1512 ath_dbg(common, QUEUE, 1513 "Transmit frames pending on queue %d\n", qnum); 1514 return false; 1515 } 1516 } 1517 1518 if (!ath9k_hw_rfbus_req(ah)) { 1519 ath_err(common, "Could not kill baseband RX\n"); 1520 return false; 1521 } 1522 1523 if (band_switch || mode_diff) { 1524 ath9k_hw_mark_phy_inactive(ah); 1525 udelay(5); 1526 1527 if (band_switch) 1528 ath9k_hw_init_pll(ah, chan); 1529 1530 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1531 ath_err(common, "Failed to do fast channel change\n"); 1532 return false; 1533 } 1534 } 1535 1536 ath9k_hw_set_channel_regs(ah, chan); 1537 1538 r = ath9k_hw_rf_set_freq(ah, chan); 1539 if (r) { 1540 ath_err(common, "Failed to set channel\n"); 1541 return false; 1542 } 1543 ath9k_hw_set_clockrate(ah); 1544 ath9k_hw_apply_txpower(ah, chan, false); 1545 1546 ath9k_hw_set_delta_slope(ah, chan); 1547 ath9k_hw_spur_mitigate_freq(ah, chan); 1548 1549 if (band_switch || ini_reloaded) 1550 ah->eep_ops->set_board_values(ah, chan); 1551 1552 ath9k_hw_init_bb(ah, chan); 1553 ath9k_hw_rfbus_done(ah); 1554 1555 if (band_switch || ini_reloaded) { 1556 ah->ah_flags |= AH_FASTCC; 1557 ath9k_hw_init_cal(ah, chan); 1558 ah->ah_flags &= ~AH_FASTCC; 1559 } 1560 1561 return true; 1562 } 1563 1564 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1565 { 1566 u32 gpio_mask = ah->gpio_mask; 1567 int i; 1568 1569 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1570 if (!(gpio_mask & 1)) 1571 continue; 1572 1573 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1574 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1575 } 1576 } 1577 1578 void ath9k_hw_check_nav(struct ath_hw *ah) 1579 { 1580 struct ath_common *common = ath9k_hw_common(ah); 1581 u32 val; 1582 1583 val = REG_READ(ah, AR_NAV); 1584 if (val != 0xdeadbeef && val > 0x7fff) { 1585 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1586 REG_WRITE(ah, AR_NAV, 0); 1587 } 1588 } 1589 EXPORT_SYMBOL(ath9k_hw_check_nav); 1590 1591 bool ath9k_hw_check_alive(struct ath_hw *ah) 1592 { 1593 int count = 50; 1594 u32 reg, last_val; 1595 1596 if (AR_SREV_9300(ah)) 1597 return !ath9k_hw_detect_mac_hang(ah); 1598 1599 if (AR_SREV_9285_12_OR_LATER(ah)) 1600 return true; 1601 1602 last_val = REG_READ(ah, AR_OBS_BUS_1); 1603 do { 1604 reg = REG_READ(ah, AR_OBS_BUS_1); 1605 if (reg != last_val) 1606 return true; 1607 1608 udelay(1); 1609 last_val = reg; 1610 if ((reg & 0x7E7FFFEF) == 0x00702400) 1611 continue; 1612 1613 switch (reg & 0x7E000B00) { 1614 case 0x1E000000: 1615 case 0x52000B00: 1616 case 0x18000B00: 1617 continue; 1618 default: 1619 return true; 1620 } 1621 } while (count-- > 0); 1622 1623 return false; 1624 } 1625 EXPORT_SYMBOL(ath9k_hw_check_alive); 1626 1627 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1628 { 1629 /* Setup MFP options for CCMP */ 1630 if (AR_SREV_9280_20_OR_LATER(ah)) { 1631 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1632 * frames when constructing CCMP AAD. */ 1633 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1634 0xc7ff); 1635 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1636 ah->sw_mgmt_crypto_tx = true; 1637 else 1638 ah->sw_mgmt_crypto_tx = false; 1639 ah->sw_mgmt_crypto_rx = false; 1640 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1641 /* Disable hardware crypto for management frames */ 1642 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1643 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1644 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1645 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1646 ah->sw_mgmt_crypto_tx = true; 1647 ah->sw_mgmt_crypto_rx = true; 1648 } else { 1649 ah->sw_mgmt_crypto_tx = true; 1650 ah->sw_mgmt_crypto_rx = true; 1651 } 1652 } 1653 1654 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1655 u32 macStaId1, u32 saveDefAntenna) 1656 { 1657 struct ath_common *common = ath9k_hw_common(ah); 1658 1659 ENABLE_REGWRITE_BUFFER(ah); 1660 1661 REG_RMW(ah, AR_STA_ID1, macStaId1 1662 | AR_STA_ID1_RTS_USE_DEF 1663 | ah->sta_id1_defaults, 1664 ~AR_STA_ID1_SADH_MASK); 1665 ath_hw_setbssidmask(common); 1666 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1667 ath9k_hw_write_associd(ah); 1668 REG_WRITE(ah, AR_ISR, ~0); 1669 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1670 1671 REGWRITE_BUFFER_FLUSH(ah); 1672 1673 ath9k_hw_set_operating_mode(ah, ah->opmode); 1674 } 1675 1676 static void ath9k_hw_init_queues(struct ath_hw *ah) 1677 { 1678 int i; 1679 1680 ENABLE_REGWRITE_BUFFER(ah); 1681 1682 for (i = 0; i < AR_NUM_DCU; i++) 1683 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1684 1685 REGWRITE_BUFFER_FLUSH(ah); 1686 1687 ah->intr_txqs = 0; 1688 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1689 ath9k_hw_resettxqueue(ah, i); 1690 } 1691 1692 /* 1693 * For big endian systems turn on swapping for descriptors 1694 */ 1695 static void ath9k_hw_init_desc(struct ath_hw *ah) 1696 { 1697 struct ath_common *common = ath9k_hw_common(ah); 1698 1699 if (AR_SREV_9100(ah)) { 1700 u32 mask; 1701 mask = REG_READ(ah, AR_CFG); 1702 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1703 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1704 mask); 1705 } else { 1706 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1707 REG_WRITE(ah, AR_CFG, mask); 1708 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1709 REG_READ(ah, AR_CFG)); 1710 } 1711 } else { 1712 if (common->bus_ops->ath_bus_type == ATH_USB) { 1713 /* Configure AR9271 target WLAN */ 1714 if (AR_SREV_9271(ah)) 1715 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1716 else 1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1718 } 1719 #ifdef __BIG_ENDIAN 1720 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1721 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1722 AR_SREV_9561(ah)) 1723 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1724 else 1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1726 #endif 1727 } 1728 } 1729 1730 /* 1731 * Fast channel change: 1732 * (Change synthesizer based on channel freq without resetting chip) 1733 */ 1734 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1735 { 1736 struct ath_common *common = ath9k_hw_common(ah); 1737 struct ath9k_hw_capabilities *pCap = &ah->caps; 1738 int ret; 1739 1740 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1741 goto fail; 1742 1743 if (ah->chip_fullsleep) 1744 goto fail; 1745 1746 if (!ah->curchan) 1747 goto fail; 1748 1749 if (chan->channel == ah->curchan->channel) 1750 goto fail; 1751 1752 if ((ah->curchan->channelFlags | chan->channelFlags) & 1753 (CHANNEL_HALF | CHANNEL_QUARTER)) 1754 goto fail; 1755 1756 /* 1757 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1758 */ 1759 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1760 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1761 goto fail; 1762 1763 if (!ath9k_hw_check_alive(ah)) 1764 goto fail; 1765 1766 /* 1767 * For AR9462, make sure that calibration data for 1768 * re-using are present. 1769 */ 1770 if (AR_SREV_9462(ah) && (ah->caldata && 1771 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1772 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1773 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1774 goto fail; 1775 1776 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1777 ah->curchan->channel, chan->channel); 1778 1779 ret = ath9k_hw_channel_change(ah, chan); 1780 if (!ret) 1781 goto fail; 1782 1783 if (ath9k_hw_mci_is_enabled(ah)) 1784 ar9003_mci_2g5g_switch(ah, false); 1785 1786 ath9k_hw_loadnf(ah, ah->curchan); 1787 ath9k_hw_start_nfcal(ah, true); 1788 1789 if (AR_SREV_9271(ah)) 1790 ar9002_hw_load_ani_reg(ah, chan); 1791 1792 return 0; 1793 fail: 1794 return -EINVAL; 1795 } 1796 1797 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1798 { 1799 struct timespec ts; 1800 s64 usec; 1801 1802 if (!cur) { 1803 getrawmonotonic(&ts); 1804 cur = &ts; 1805 } 1806 1807 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1808 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1809 1810 return (u32) usec; 1811 } 1812 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1813 1814 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1815 struct ath9k_hw_cal_data *caldata, bool fastcc) 1816 { 1817 struct ath_common *common = ath9k_hw_common(ah); 1818 u32 saveLedState; 1819 u32 saveDefAntenna; 1820 u32 macStaId1; 1821 u64 tsf = 0; 1822 s64 usec = 0; 1823 int r; 1824 bool start_mci_reset = false; 1825 bool save_fullsleep = ah->chip_fullsleep; 1826 1827 if (ath9k_hw_mci_is_enabled(ah)) { 1828 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1829 if (start_mci_reset) 1830 return 0; 1831 } 1832 1833 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1834 return -EIO; 1835 1836 if (ah->curchan && !ah->chip_fullsleep) 1837 ath9k_hw_getnf(ah, ah->curchan); 1838 1839 ah->caldata = caldata; 1840 if (caldata && (chan->channel != caldata->channel || 1841 chan->channelFlags != caldata->channelFlags)) { 1842 /* Operating channel changed, reset channel calibration data */ 1843 memset(caldata, 0, sizeof(*caldata)); 1844 ath9k_init_nfcal_hist_buffer(ah, chan); 1845 } else if (caldata) { 1846 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1847 } 1848 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1849 1850 if (fastcc) { 1851 r = ath9k_hw_do_fastcc(ah, chan); 1852 if (!r) 1853 return r; 1854 } 1855 1856 if (ath9k_hw_mci_is_enabled(ah)) 1857 ar9003_mci_stop_bt(ah, save_fullsleep); 1858 1859 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1860 if (saveDefAntenna == 0) 1861 saveDefAntenna = 1; 1862 1863 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1864 1865 /* Save TSF before chip reset, a cold reset clears it */ 1866 tsf = ath9k_hw_gettsf64(ah); 1867 usec = ktime_to_us(ktime_get_raw()); 1868 1869 saveLedState = REG_READ(ah, AR_CFG_LED) & 1870 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1871 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1872 1873 ath9k_hw_mark_phy_inactive(ah); 1874 1875 ah->paprd_table_write_done = false; 1876 1877 /* Only required on the first reset */ 1878 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1879 REG_WRITE(ah, 1880 AR9271_RESET_POWER_DOWN_CONTROL, 1881 AR9271_RADIO_RF_RST); 1882 udelay(50); 1883 } 1884 1885 if (!ath9k_hw_chip_reset(ah, chan)) { 1886 ath_err(common, "Chip reset failed\n"); 1887 return -EINVAL; 1888 } 1889 1890 /* Only required on the first reset */ 1891 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1892 ah->htc_reset_init = false; 1893 REG_WRITE(ah, 1894 AR9271_RESET_POWER_DOWN_CONTROL, 1895 AR9271_GATE_MAC_CTL); 1896 udelay(50); 1897 } 1898 1899 /* Restore TSF */ 1900 usec = ktime_to_us(ktime_get_raw()) - usec; 1901 ath9k_hw_settsf64(ah, tsf + usec); 1902 1903 if (AR_SREV_9280_20_OR_LATER(ah)) 1904 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1905 1906 if (!AR_SREV_9300_20_OR_LATER(ah)) 1907 ar9002_hw_enable_async_fifo(ah); 1908 1909 r = ath9k_hw_process_ini(ah, chan); 1910 if (r) 1911 return r; 1912 1913 ath9k_hw_set_rfmode(ah, chan); 1914 1915 if (ath9k_hw_mci_is_enabled(ah)) 1916 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1917 1918 /* 1919 * Some AR91xx SoC devices frequently fail to accept TSF writes 1920 * right after the chip reset. When that happens, write a new 1921 * value after the initvals have been applied, with an offset 1922 * based on measured time difference 1923 */ 1924 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1925 tsf += 1500; 1926 ath9k_hw_settsf64(ah, tsf); 1927 } 1928 1929 ath9k_hw_init_mfp(ah); 1930 1931 ath9k_hw_set_delta_slope(ah, chan); 1932 ath9k_hw_spur_mitigate_freq(ah, chan); 1933 ah->eep_ops->set_board_values(ah, chan); 1934 1935 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1936 1937 r = ath9k_hw_rf_set_freq(ah, chan); 1938 if (r) 1939 return r; 1940 1941 ath9k_hw_set_clockrate(ah); 1942 1943 ath9k_hw_init_queues(ah); 1944 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1945 ath9k_hw_ani_cache_ini_regs(ah); 1946 ath9k_hw_init_qos(ah); 1947 1948 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1949 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1950 1951 ath9k_hw_init_global_settings(ah); 1952 1953 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1954 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1955 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1956 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1957 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1958 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1959 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1960 } 1961 1962 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1963 1964 ath9k_hw_set_dma(ah); 1965 1966 if (!ath9k_hw_mci_is_enabled(ah)) 1967 REG_WRITE(ah, AR_OBS, 8); 1968 1969 ENABLE_REG_RMW_BUFFER(ah); 1970 if (ah->config.rx_intr_mitigation) { 1971 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1972 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1973 } 1974 1975 if (ah->config.tx_intr_mitigation) { 1976 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1977 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1978 } 1979 REG_RMW_BUFFER_FLUSH(ah); 1980 1981 ath9k_hw_init_bb(ah, chan); 1982 1983 if (caldata) { 1984 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1985 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1986 } 1987 if (!ath9k_hw_init_cal(ah, chan)) 1988 return -EIO; 1989 1990 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1991 return -EIO; 1992 1993 ENABLE_REGWRITE_BUFFER(ah); 1994 1995 ath9k_hw_restore_chainmask(ah); 1996 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1997 1998 REGWRITE_BUFFER_FLUSH(ah); 1999 2000 ath9k_hw_gen_timer_start_tsf2(ah); 2001 2002 ath9k_hw_init_desc(ah); 2003 2004 if (ath9k_hw_btcoex_is_enabled(ah)) 2005 ath9k_hw_btcoex_enable(ah); 2006 2007 if (ath9k_hw_mci_is_enabled(ah)) 2008 ar9003_mci_check_bt(ah); 2009 2010 if (AR_SREV_9300_20_OR_LATER(ah)) { 2011 ath9k_hw_loadnf(ah, chan); 2012 ath9k_hw_start_nfcal(ah, true); 2013 } 2014 2015 if (AR_SREV_9300_20_OR_LATER(ah)) 2016 ar9003_hw_bb_watchdog_config(ah); 2017 2018 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 2019 ar9003_hw_disable_phy_restart(ah); 2020 2021 ath9k_hw_apply_gpio_override(ah); 2022 2023 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2024 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2025 2026 if (ah->hw->conf.radar_enabled) { 2027 /* set HW specific DFS configuration */ 2028 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 2029 ath9k_hw_set_radar_params(ah); 2030 } 2031 2032 return 0; 2033 } 2034 EXPORT_SYMBOL(ath9k_hw_reset); 2035 2036 /******************************/ 2037 /* Power Management (Chipset) */ 2038 /******************************/ 2039 2040 /* 2041 * Notify Power Mgt is disabled in self-generated frames. 2042 * If requested, force chip to sleep. 2043 */ 2044 static void ath9k_set_power_sleep(struct ath_hw *ah) 2045 { 2046 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2047 2048 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2049 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2050 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2051 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2052 /* xxx Required for WLAN only case ? */ 2053 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2054 udelay(100); 2055 } 2056 2057 /* 2058 * Clear the RTC force wake bit to allow the 2059 * mac to go to sleep. 2060 */ 2061 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2062 2063 if (ath9k_hw_mci_is_enabled(ah)) 2064 udelay(100); 2065 2066 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2067 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2068 2069 /* Shutdown chip. Active low */ 2070 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2071 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2072 udelay(2); 2073 } 2074 2075 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2076 if (AR_SREV_9300_20_OR_LATER(ah)) 2077 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2078 } 2079 2080 /* 2081 * Notify Power Management is enabled in self-generating 2082 * frames. If request, set power mode of chip to 2083 * auto/normal. Duration in units of 128us (1/8 TU). 2084 */ 2085 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2086 { 2087 struct ath9k_hw_capabilities *pCap = &ah->caps; 2088 2089 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2090 2091 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2092 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2093 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2094 AR_RTC_FORCE_WAKE_ON_INT); 2095 } else { 2096 2097 /* When chip goes into network sleep, it could be waken 2098 * up by MCI_INT interrupt caused by BT's HW messages 2099 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2100 * rate (~100us). This will cause chip to leave and 2101 * re-enter network sleep mode frequently, which in 2102 * consequence will have WLAN MCI HW to generate lots of 2103 * SYS_WAKING and SYS_SLEEPING messages which will make 2104 * BT CPU to busy to process. 2105 */ 2106 if (ath9k_hw_mci_is_enabled(ah)) 2107 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2108 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2109 /* 2110 * Clear the RTC force wake bit to allow the 2111 * mac to go to sleep. 2112 */ 2113 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2114 2115 if (ath9k_hw_mci_is_enabled(ah)) 2116 udelay(30); 2117 } 2118 2119 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2120 if (AR_SREV_9300_20_OR_LATER(ah)) 2121 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2122 } 2123 2124 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2125 { 2126 u32 val; 2127 int i; 2128 2129 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2130 if (AR_SREV_9300_20_OR_LATER(ah)) { 2131 REG_WRITE(ah, AR_WA, ah->WARegVal); 2132 udelay(10); 2133 } 2134 2135 if ((REG_READ(ah, AR_RTC_STATUS) & 2136 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2137 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2138 return false; 2139 } 2140 if (!AR_SREV_9300_20_OR_LATER(ah)) 2141 ath9k_hw_init_pll(ah, NULL); 2142 } 2143 if (AR_SREV_9100(ah)) 2144 REG_SET_BIT(ah, AR_RTC_RESET, 2145 AR_RTC_RESET_EN); 2146 2147 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2148 AR_RTC_FORCE_WAKE_EN); 2149 if (AR_SREV_9100(ah)) 2150 mdelay(10); 2151 else 2152 udelay(50); 2153 2154 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2155 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2156 if (val == AR_RTC_STATUS_ON) 2157 break; 2158 udelay(50); 2159 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2160 AR_RTC_FORCE_WAKE_EN); 2161 } 2162 if (i == 0) { 2163 ath_err(ath9k_hw_common(ah), 2164 "Failed to wakeup in %uus\n", 2165 POWER_UP_TIME / 20); 2166 return false; 2167 } 2168 2169 if (ath9k_hw_mci_is_enabled(ah)) 2170 ar9003_mci_set_power_awake(ah); 2171 2172 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2173 2174 return true; 2175 } 2176 2177 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2178 { 2179 struct ath_common *common = ath9k_hw_common(ah); 2180 int status = true; 2181 static const char *modes[] = { 2182 "AWAKE", 2183 "FULL-SLEEP", 2184 "NETWORK SLEEP", 2185 "UNDEFINED" 2186 }; 2187 2188 if (ah->power_mode == mode) 2189 return status; 2190 2191 ath_dbg(common, RESET, "%s -> %s\n", 2192 modes[ah->power_mode], modes[mode]); 2193 2194 switch (mode) { 2195 case ATH9K_PM_AWAKE: 2196 status = ath9k_hw_set_power_awake(ah); 2197 break; 2198 case ATH9K_PM_FULL_SLEEP: 2199 if (ath9k_hw_mci_is_enabled(ah)) 2200 ar9003_mci_set_full_sleep(ah); 2201 2202 ath9k_set_power_sleep(ah); 2203 ah->chip_fullsleep = true; 2204 break; 2205 case ATH9K_PM_NETWORK_SLEEP: 2206 ath9k_set_power_network_sleep(ah); 2207 break; 2208 default: 2209 ath_err(common, "Unknown power mode %u\n", mode); 2210 return false; 2211 } 2212 ah->power_mode = mode; 2213 2214 /* 2215 * XXX: If this warning never comes up after a while then 2216 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2217 * ath9k_hw_setpower() return type void. 2218 */ 2219 2220 if (!(ah->ah_flags & AH_UNPLUGGED)) 2221 ATH_DBG_WARN_ON_ONCE(!status); 2222 2223 return status; 2224 } 2225 EXPORT_SYMBOL(ath9k_hw_setpower); 2226 2227 /*******************/ 2228 /* Beacon Handling */ 2229 /*******************/ 2230 2231 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2232 { 2233 int flags = 0; 2234 2235 ENABLE_REGWRITE_BUFFER(ah); 2236 2237 switch (ah->opmode) { 2238 case NL80211_IFTYPE_ADHOC: 2239 REG_SET_BIT(ah, AR_TXCFG, 2240 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2241 case NL80211_IFTYPE_MESH_POINT: 2242 case NL80211_IFTYPE_AP: 2243 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2244 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2245 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2246 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2247 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2248 flags |= 2249 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2250 break; 2251 default: 2252 ath_dbg(ath9k_hw_common(ah), BEACON, 2253 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2254 return; 2255 break; 2256 } 2257 2258 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2259 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2260 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2261 2262 REGWRITE_BUFFER_FLUSH(ah); 2263 2264 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2265 } 2266 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2267 2268 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2269 const struct ath9k_beacon_state *bs) 2270 { 2271 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2272 struct ath9k_hw_capabilities *pCap = &ah->caps; 2273 struct ath_common *common = ath9k_hw_common(ah); 2274 2275 ENABLE_REGWRITE_BUFFER(ah); 2276 2277 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2278 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2279 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2280 2281 REGWRITE_BUFFER_FLUSH(ah); 2282 2283 REG_RMW_FIELD(ah, AR_RSSI_THR, 2284 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2285 2286 beaconintval = bs->bs_intval; 2287 2288 if (bs->bs_sleepduration > beaconintval) 2289 beaconintval = bs->bs_sleepduration; 2290 2291 dtimperiod = bs->bs_dtimperiod; 2292 if (bs->bs_sleepduration > dtimperiod) 2293 dtimperiod = bs->bs_sleepduration; 2294 2295 if (beaconintval == dtimperiod) 2296 nextTbtt = bs->bs_nextdtim; 2297 else 2298 nextTbtt = bs->bs_nexttbtt; 2299 2300 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2301 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2302 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2303 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2304 2305 ENABLE_REGWRITE_BUFFER(ah); 2306 2307 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2308 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2309 2310 REG_WRITE(ah, AR_SLEEP1, 2311 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2312 | AR_SLEEP1_ASSUME_DTIM); 2313 2314 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2315 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2316 else 2317 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2318 2319 REG_WRITE(ah, AR_SLEEP2, 2320 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2321 2322 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2323 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2324 2325 REGWRITE_BUFFER_FLUSH(ah); 2326 2327 REG_SET_BIT(ah, AR_TIMER_MODE, 2328 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2329 AR_DTIM_TIMER_EN); 2330 2331 /* TSF Out of Range Threshold */ 2332 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2333 } 2334 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2335 2336 /*******************/ 2337 /* HW Capabilities */ 2338 /*******************/ 2339 2340 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2341 { 2342 eeprom_chainmask &= chip_chainmask; 2343 if (eeprom_chainmask) 2344 return eeprom_chainmask; 2345 else 2346 return chip_chainmask; 2347 } 2348 2349 /** 2350 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2351 * @ah: the atheros hardware data structure 2352 * 2353 * We enable DFS support upstream on chipsets which have passed a series 2354 * of tests. The testing requirements are going to be documented. Desired 2355 * test requirements are documented at: 2356 * 2357 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2358 * 2359 * Once a new chipset gets properly tested an individual commit can be used 2360 * to document the testing for DFS for that chipset. 2361 */ 2362 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2363 { 2364 2365 switch (ah->hw_version.macVersion) { 2366 /* for temporary testing DFS with 9280 */ 2367 case AR_SREV_VERSION_9280: 2368 /* AR9580 will likely be our first target to get testing on */ 2369 case AR_SREV_VERSION_9580: 2370 return true; 2371 default: 2372 return false; 2373 } 2374 } 2375 2376 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2377 { 2378 struct ath9k_hw_capabilities *pCap = &ah->caps; 2379 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2380 struct ath_common *common = ath9k_hw_common(ah); 2381 2382 u16 eeval; 2383 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2384 2385 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2386 regulatory->current_rd = eeval; 2387 2388 if (ah->opmode != NL80211_IFTYPE_AP && 2389 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2390 if (regulatory->current_rd == 0x64 || 2391 regulatory->current_rd == 0x65) 2392 regulatory->current_rd += 5; 2393 else if (regulatory->current_rd == 0x41) 2394 regulatory->current_rd = 0x43; 2395 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2396 regulatory->current_rd); 2397 } 2398 2399 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2400 2401 if (eeval & AR5416_OPFLAGS_11A) { 2402 if (ah->disable_5ghz) 2403 ath_warn(common, "disabling 5GHz band\n"); 2404 else 2405 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2406 } 2407 2408 if (eeval & AR5416_OPFLAGS_11G) { 2409 if (ah->disable_2ghz) 2410 ath_warn(common, "disabling 2GHz band\n"); 2411 else 2412 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2413 } 2414 2415 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2416 ath_err(common, "both bands are disabled\n"); 2417 return -EINVAL; 2418 } 2419 2420 if (AR_SREV_9485(ah) || 2421 AR_SREV_9285(ah) || 2422 AR_SREV_9330(ah) || 2423 AR_SREV_9565(ah)) 2424 pCap->chip_chainmask = 1; 2425 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2426 pCap->chip_chainmask = 7; 2427 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2428 AR_SREV_9340(ah) || 2429 AR_SREV_9462(ah) || 2430 AR_SREV_9531(ah)) 2431 pCap->chip_chainmask = 3; 2432 else 2433 pCap->chip_chainmask = 7; 2434 2435 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2436 /* 2437 * For AR9271 we will temporarilly uses the rx chainmax as read from 2438 * the EEPROM. 2439 */ 2440 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2441 !(eeval & AR5416_OPFLAGS_11A) && 2442 !(AR_SREV_9271(ah))) 2443 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2444 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2445 else if (AR_SREV_9100(ah)) 2446 pCap->rx_chainmask = 0x7; 2447 else 2448 /* Use rx_chainmask from EEPROM. */ 2449 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2450 2451 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2452 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2453 ah->txchainmask = pCap->tx_chainmask; 2454 ah->rxchainmask = pCap->rx_chainmask; 2455 2456 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2457 2458 /* enable key search for every frame in an aggregate */ 2459 if (AR_SREV_9300_20_OR_LATER(ah)) 2460 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2461 2462 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2463 2464 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2465 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2466 else 2467 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2468 2469 if (AR_SREV_9271(ah)) 2470 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2471 else if (AR_DEVID_7010(ah)) 2472 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2473 else if (AR_SREV_9300_20_OR_LATER(ah)) 2474 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2475 else if (AR_SREV_9287_11_OR_LATER(ah)) 2476 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2477 else if (AR_SREV_9285_12_OR_LATER(ah)) 2478 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2479 else if (AR_SREV_9280_20_OR_LATER(ah)) 2480 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2481 else 2482 pCap->num_gpio_pins = AR_NUM_GPIO; 2483 2484 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2485 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2486 else 2487 pCap->rts_aggr_limit = (8 * 1024); 2488 2489 #ifdef CONFIG_ATH9K_RFKILL 2490 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2491 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2492 ah->rfkill_gpio = 2493 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2494 ah->rfkill_polarity = 2495 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2496 2497 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2498 } 2499 #endif 2500 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2501 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2502 else 2503 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2504 2505 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2506 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2507 else 2508 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2509 2510 if (AR_SREV_9300_20_OR_LATER(ah)) { 2511 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2512 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2513 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2514 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2515 2516 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2517 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2518 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2519 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2520 pCap->txs_len = sizeof(struct ar9003_txs); 2521 } else { 2522 pCap->tx_desc_len = sizeof(struct ath_desc); 2523 if (AR_SREV_9280_20(ah)) 2524 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2525 } 2526 2527 if (AR_SREV_9300_20_OR_LATER(ah)) 2528 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2529 2530 if (AR_SREV_9561(ah)) 2531 ah->ent_mode = 0x3BDA000; 2532 else if (AR_SREV_9300_20_OR_LATER(ah)) 2533 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2534 2535 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2536 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2537 2538 if (AR_SREV_9285(ah)) { 2539 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2540 ant_div_ctl1 = 2541 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2542 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2543 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2544 ath_info(common, "Enable LNA combining\n"); 2545 } 2546 } 2547 } 2548 2549 if (AR_SREV_9300_20_OR_LATER(ah)) { 2550 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2551 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2552 } 2553 2554 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2555 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2556 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2557 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2558 ath_info(common, "Enable LNA combining\n"); 2559 } 2560 } 2561 2562 if (ath9k_hw_dfs_tested(ah)) 2563 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2564 2565 tx_chainmask = pCap->tx_chainmask; 2566 rx_chainmask = pCap->rx_chainmask; 2567 while (tx_chainmask || rx_chainmask) { 2568 if (tx_chainmask & BIT(0)) 2569 pCap->max_txchains++; 2570 if (rx_chainmask & BIT(0)) 2571 pCap->max_rxchains++; 2572 2573 tx_chainmask >>= 1; 2574 rx_chainmask >>= 1; 2575 } 2576 2577 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2578 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2579 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2580 2581 if (AR_SREV_9462_20_OR_LATER(ah)) 2582 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2583 } 2584 2585 if (AR_SREV_9300_20_OR_LATER(ah) && 2586 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2587 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2588 2589 #ifdef CONFIG_ATH9K_WOW 2590 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2591 ah->wow.max_patterns = MAX_NUM_PATTERN; 2592 else 2593 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2594 #endif 2595 2596 return 0; 2597 } 2598 2599 /****************************/ 2600 /* GPIO / RFKILL / Antennae */ 2601 /****************************/ 2602 2603 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2604 u32 gpio, u32 type) 2605 { 2606 int addr; 2607 u32 gpio_shift, tmp; 2608 2609 if (gpio > 11) 2610 addr = AR_GPIO_OUTPUT_MUX3; 2611 else if (gpio > 5) 2612 addr = AR_GPIO_OUTPUT_MUX2; 2613 else 2614 addr = AR_GPIO_OUTPUT_MUX1; 2615 2616 gpio_shift = (gpio % 6) * 5; 2617 2618 if (AR_SREV_9280_20_OR_LATER(ah) 2619 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2620 REG_RMW(ah, addr, (type << gpio_shift), 2621 (0x1f << gpio_shift)); 2622 } else { 2623 tmp = REG_READ(ah, addr); 2624 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2625 tmp &= ~(0x1f << gpio_shift); 2626 tmp |= (type << gpio_shift); 2627 REG_WRITE(ah, addr, tmp); 2628 } 2629 } 2630 2631 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2632 { 2633 u32 gpio_shift; 2634 2635 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2636 2637 if (AR_DEVID_7010(ah)) { 2638 gpio_shift = gpio; 2639 REG_RMW(ah, AR7010_GPIO_OE, 2640 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2641 (AR7010_GPIO_OE_MASK << gpio_shift)); 2642 return; 2643 } 2644 2645 gpio_shift = gpio << 1; 2646 REG_RMW(ah, 2647 AR_GPIO_OE_OUT, 2648 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2649 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2650 } 2651 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2652 2653 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2654 { 2655 #define MS_REG_READ(x, y) \ 2656 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2657 2658 if (gpio >= ah->caps.num_gpio_pins) 2659 return 0xffffffff; 2660 2661 if (AR_DEVID_7010(ah)) { 2662 u32 val; 2663 val = REG_READ(ah, AR7010_GPIO_IN); 2664 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2665 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2666 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2667 AR_GPIO_BIT(gpio)) != 0; 2668 else if (AR_SREV_9271(ah)) 2669 return MS_REG_READ(AR9271, gpio) != 0; 2670 else if (AR_SREV_9287_11_OR_LATER(ah)) 2671 return MS_REG_READ(AR9287, gpio) != 0; 2672 else if (AR_SREV_9285_12_OR_LATER(ah)) 2673 return MS_REG_READ(AR9285, gpio) != 0; 2674 else if (AR_SREV_9280_20_OR_LATER(ah)) 2675 return MS_REG_READ(AR928X, gpio) != 0; 2676 else 2677 return MS_REG_READ(AR, gpio) != 0; 2678 } 2679 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2680 2681 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2682 u32 ah_signal_type) 2683 { 2684 u32 gpio_shift; 2685 2686 if (AR_DEVID_7010(ah)) { 2687 gpio_shift = gpio; 2688 REG_RMW(ah, AR7010_GPIO_OE, 2689 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2690 (AR7010_GPIO_OE_MASK << gpio_shift)); 2691 return; 2692 } 2693 2694 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2695 gpio_shift = 2 * gpio; 2696 REG_RMW(ah, 2697 AR_GPIO_OE_OUT, 2698 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2699 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2700 } 2701 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2702 2703 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2704 { 2705 if (AR_DEVID_7010(ah)) { 2706 val = val ? 0 : 1; 2707 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2708 AR_GPIO_BIT(gpio)); 2709 return; 2710 } 2711 2712 if (AR_SREV_9271(ah)) 2713 val = ~val; 2714 2715 if ((1 << gpio) & AR_GPIO_OE_OUT_MASK) 2716 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2717 AR_GPIO_BIT(gpio)); 2718 else 2719 gpio_set_value(gpio, val & 1); 2720 } 2721 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2722 2723 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label) 2724 { 2725 if (gpio >= ah->caps.num_gpio_pins) 2726 return; 2727 2728 gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label); 2729 } 2730 EXPORT_SYMBOL(ath9k_hw_request_gpio); 2731 2732 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2733 { 2734 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2735 } 2736 EXPORT_SYMBOL(ath9k_hw_setantenna); 2737 2738 /*********************/ 2739 /* General Operation */ 2740 /*********************/ 2741 2742 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2743 { 2744 u32 bits = REG_READ(ah, AR_RX_FILTER); 2745 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2746 2747 if (phybits & AR_PHY_ERR_RADAR) 2748 bits |= ATH9K_RX_FILTER_PHYRADAR; 2749 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2750 bits |= ATH9K_RX_FILTER_PHYERR; 2751 2752 return bits; 2753 } 2754 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2755 2756 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2757 { 2758 u32 phybits; 2759 2760 ENABLE_REGWRITE_BUFFER(ah); 2761 2762 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2763 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2764 2765 REG_WRITE(ah, AR_RX_FILTER, bits); 2766 2767 phybits = 0; 2768 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2769 phybits |= AR_PHY_ERR_RADAR; 2770 if (bits & ATH9K_RX_FILTER_PHYERR) 2771 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2772 REG_WRITE(ah, AR_PHY_ERR, phybits); 2773 2774 if (phybits) 2775 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2776 else 2777 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2778 2779 REGWRITE_BUFFER_FLUSH(ah); 2780 } 2781 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2782 2783 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2784 { 2785 if (ath9k_hw_mci_is_enabled(ah)) 2786 ar9003_mci_bt_gain_ctrl(ah); 2787 2788 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2789 return false; 2790 2791 ath9k_hw_init_pll(ah, NULL); 2792 ah->htc_reset_init = true; 2793 return true; 2794 } 2795 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2796 2797 bool ath9k_hw_disable(struct ath_hw *ah) 2798 { 2799 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2800 return false; 2801 2802 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2803 return false; 2804 2805 ath9k_hw_init_pll(ah, NULL); 2806 return true; 2807 } 2808 EXPORT_SYMBOL(ath9k_hw_disable); 2809 2810 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2811 { 2812 enum eeprom_param gain_param; 2813 2814 if (IS_CHAN_2GHZ(chan)) 2815 gain_param = EEP_ANTENNA_GAIN_2G; 2816 else 2817 gain_param = EEP_ANTENNA_GAIN_5G; 2818 2819 return ah->eep_ops->get_eeprom(ah, gain_param); 2820 } 2821 2822 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2823 bool test) 2824 { 2825 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2826 struct ieee80211_channel *channel; 2827 int chan_pwr, new_pwr, max_gain; 2828 int ant_gain, ant_reduction = 0; 2829 2830 if (!chan) 2831 return; 2832 2833 channel = chan->chan; 2834 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2835 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2836 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2837 2838 ant_gain = get_antenna_gain(ah, chan); 2839 if (ant_gain > max_gain) 2840 ant_reduction = ant_gain - max_gain; 2841 2842 ah->eep_ops->set_txpower(ah, chan, 2843 ath9k_regd_get_ctl(reg, chan), 2844 ant_reduction, new_pwr, test); 2845 } 2846 2847 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2848 { 2849 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2850 struct ath9k_channel *chan = ah->curchan; 2851 struct ieee80211_channel *channel = chan->chan; 2852 2853 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2854 if (test) 2855 channel->max_power = MAX_RATE_POWER / 2; 2856 2857 ath9k_hw_apply_txpower(ah, chan, test); 2858 2859 if (test) 2860 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2861 } 2862 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2863 2864 void ath9k_hw_setopmode(struct ath_hw *ah) 2865 { 2866 ath9k_hw_set_operating_mode(ah, ah->opmode); 2867 } 2868 EXPORT_SYMBOL(ath9k_hw_setopmode); 2869 2870 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2871 { 2872 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2873 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2874 } 2875 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2876 2877 void ath9k_hw_write_associd(struct ath_hw *ah) 2878 { 2879 struct ath_common *common = ath9k_hw_common(ah); 2880 2881 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2882 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2883 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2884 } 2885 EXPORT_SYMBOL(ath9k_hw_write_associd); 2886 2887 #define ATH9K_MAX_TSF_READ 10 2888 2889 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2890 { 2891 u32 tsf_lower, tsf_upper1, tsf_upper2; 2892 int i; 2893 2894 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2895 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2896 tsf_lower = REG_READ(ah, AR_TSF_L32); 2897 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2898 if (tsf_upper2 == tsf_upper1) 2899 break; 2900 tsf_upper1 = tsf_upper2; 2901 } 2902 2903 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2904 2905 return (((u64)tsf_upper1 << 32) | tsf_lower); 2906 } 2907 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2908 2909 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2910 { 2911 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2912 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2913 } 2914 EXPORT_SYMBOL(ath9k_hw_settsf64); 2915 2916 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2917 { 2918 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2919 AH_TSF_WRITE_TIMEOUT)) 2920 ath_dbg(ath9k_hw_common(ah), RESET, 2921 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2922 2923 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2924 } 2925 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2926 2927 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2928 { 2929 if (set) 2930 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2931 else 2932 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2933 } 2934 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2935 2936 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2937 { 2938 u32 macmode; 2939 2940 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2941 macmode = AR_2040_JOINED_RX_CLEAR; 2942 else 2943 macmode = 0; 2944 2945 REG_WRITE(ah, AR_2040_MODE, macmode); 2946 } 2947 2948 /* HW Generic timers configuration */ 2949 2950 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2951 { 2952 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2953 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2959 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2960 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2961 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2962 AR_NDP2_TIMER_MODE, 0x0002}, 2963 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2964 AR_NDP2_TIMER_MODE, 0x0004}, 2965 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2966 AR_NDP2_TIMER_MODE, 0x0008}, 2967 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2968 AR_NDP2_TIMER_MODE, 0x0010}, 2969 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2970 AR_NDP2_TIMER_MODE, 0x0020}, 2971 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2972 AR_NDP2_TIMER_MODE, 0x0040}, 2973 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2974 AR_NDP2_TIMER_MODE, 0x0080} 2975 }; 2976 2977 /* HW generic timer primitives */ 2978 2979 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2980 { 2981 return REG_READ(ah, AR_TSF_L32); 2982 } 2983 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2984 2985 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 2986 { 2987 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2988 2989 if (timer_table->tsf2_enabled) { 2990 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 2991 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 2992 } 2993 } 2994 2995 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2996 void (*trigger)(void *), 2997 void (*overflow)(void *), 2998 void *arg, 2999 u8 timer_index) 3000 { 3001 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3002 struct ath_gen_timer *timer; 3003 3004 if ((timer_index < AR_FIRST_NDP_TIMER) || 3005 (timer_index >= ATH_MAX_GEN_TIMER)) 3006 return NULL; 3007 3008 if ((timer_index > AR_FIRST_NDP_TIMER) && 3009 !AR_SREV_9300_20_OR_LATER(ah)) 3010 return NULL; 3011 3012 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3013 if (timer == NULL) 3014 return NULL; 3015 3016 /* allocate a hardware generic timer slot */ 3017 timer_table->timers[timer_index] = timer; 3018 timer->index = timer_index; 3019 timer->trigger = trigger; 3020 timer->overflow = overflow; 3021 timer->arg = arg; 3022 3023 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 3024 timer_table->tsf2_enabled = true; 3025 ath9k_hw_gen_timer_start_tsf2(ah); 3026 } 3027 3028 return timer; 3029 } 3030 EXPORT_SYMBOL(ath_gen_timer_alloc); 3031 3032 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3033 struct ath_gen_timer *timer, 3034 u32 timer_next, 3035 u32 timer_period) 3036 { 3037 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3038 u32 mask = 0; 3039 3040 timer_table->timer_mask |= BIT(timer->index); 3041 3042 /* 3043 * Program generic timer registers 3044 */ 3045 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3046 timer_next); 3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3048 timer_period); 3049 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3050 gen_tmr_configuration[timer->index].mode_mask); 3051 3052 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3053 /* 3054 * Starting from AR9462, each generic timer can select which tsf 3055 * to use. But we still follow the old rule, 0 - 7 use tsf and 3056 * 8 - 15 use tsf2. 3057 */ 3058 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3059 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3060 (1 << timer->index)); 3061 else 3062 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3063 (1 << timer->index)); 3064 } 3065 3066 if (timer->trigger) 3067 mask |= SM(AR_GENTMR_BIT(timer->index), 3068 AR_IMR_S5_GENTIMER_TRIG); 3069 if (timer->overflow) 3070 mask |= SM(AR_GENTMR_BIT(timer->index), 3071 AR_IMR_S5_GENTIMER_THRESH); 3072 3073 REG_SET_BIT(ah, AR_IMR_S5, mask); 3074 3075 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3076 ah->imask |= ATH9K_INT_GENTIMER; 3077 ath9k_hw_set_interrupts(ah); 3078 } 3079 } 3080 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3081 3082 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3083 { 3084 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3085 3086 /* Clear generic timer enable bits. */ 3087 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3088 gen_tmr_configuration[timer->index].mode_mask); 3089 3090 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3091 /* 3092 * Need to switch back to TSF if it was using TSF2. 3093 */ 3094 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3095 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3096 (1 << timer->index)); 3097 } 3098 } 3099 3100 /* Disable both trigger and thresh interrupt masks */ 3101 REG_CLR_BIT(ah, AR_IMR_S5, 3102 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3103 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3104 3105 timer_table->timer_mask &= ~BIT(timer->index); 3106 3107 if (timer_table->timer_mask == 0) { 3108 ah->imask &= ~ATH9K_INT_GENTIMER; 3109 ath9k_hw_set_interrupts(ah); 3110 } 3111 } 3112 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3113 3114 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3115 { 3116 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3117 3118 /* free the hardware generic timer slot */ 3119 timer_table->timers[timer->index] = NULL; 3120 kfree(timer); 3121 } 3122 EXPORT_SYMBOL(ath_gen_timer_free); 3123 3124 /* 3125 * Generic Timer Interrupts handling 3126 */ 3127 void ath_gen_timer_isr(struct ath_hw *ah) 3128 { 3129 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3130 struct ath_gen_timer *timer; 3131 unsigned long trigger_mask, thresh_mask; 3132 unsigned int index; 3133 3134 /* get hardware generic timer interrupt status */ 3135 trigger_mask = ah->intr_gen_timer_trigger; 3136 thresh_mask = ah->intr_gen_timer_thresh; 3137 trigger_mask &= timer_table->timer_mask; 3138 thresh_mask &= timer_table->timer_mask; 3139 3140 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3141 timer = timer_table->timers[index]; 3142 if (!timer) 3143 continue; 3144 if (!timer->overflow) 3145 continue; 3146 3147 trigger_mask &= ~BIT(index); 3148 timer->overflow(timer->arg); 3149 } 3150 3151 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3152 timer = timer_table->timers[index]; 3153 if (!timer) 3154 continue; 3155 if (!timer->trigger) 3156 continue; 3157 timer->trigger(timer->arg); 3158 } 3159 } 3160 EXPORT_SYMBOL(ath_gen_timer_isr); 3161 3162 /********/ 3163 /* HTC */ 3164 /********/ 3165 3166 static struct { 3167 u32 version; 3168 const char * name; 3169 } ath_mac_bb_names[] = { 3170 /* Devices with external radios */ 3171 { AR_SREV_VERSION_5416_PCI, "5416" }, 3172 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3173 { AR_SREV_VERSION_9100, "9100" }, 3174 { AR_SREV_VERSION_9160, "9160" }, 3175 /* Single-chip solutions */ 3176 { AR_SREV_VERSION_9280, "9280" }, 3177 { AR_SREV_VERSION_9285, "9285" }, 3178 { AR_SREV_VERSION_9287, "9287" }, 3179 { AR_SREV_VERSION_9271, "9271" }, 3180 { AR_SREV_VERSION_9300, "9300" }, 3181 { AR_SREV_VERSION_9330, "9330" }, 3182 { AR_SREV_VERSION_9340, "9340" }, 3183 { AR_SREV_VERSION_9485, "9485" }, 3184 { AR_SREV_VERSION_9462, "9462" }, 3185 { AR_SREV_VERSION_9550, "9550" }, 3186 { AR_SREV_VERSION_9565, "9565" }, 3187 { AR_SREV_VERSION_9531, "9531" }, 3188 }; 3189 3190 /* For devices with external radios */ 3191 static struct { 3192 u16 version; 3193 const char * name; 3194 } ath_rf_names[] = { 3195 { 0, "5133" }, 3196 { AR_RAD5133_SREV_MAJOR, "5133" }, 3197 { AR_RAD5122_SREV_MAJOR, "5122" }, 3198 { AR_RAD2133_SREV_MAJOR, "2133" }, 3199 { AR_RAD2122_SREV_MAJOR, "2122" } 3200 }; 3201 3202 /* 3203 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3204 */ 3205 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3206 { 3207 int i; 3208 3209 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3210 if (ath_mac_bb_names[i].version == mac_bb_version) { 3211 return ath_mac_bb_names[i].name; 3212 } 3213 } 3214 3215 return "????"; 3216 } 3217 3218 /* 3219 * Return the RF name. "????" is returned if the RF is unknown. 3220 * Used for devices with external radios. 3221 */ 3222 static const char *ath9k_hw_rf_name(u16 rf_version) 3223 { 3224 int i; 3225 3226 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3227 if (ath_rf_names[i].version == rf_version) { 3228 return ath_rf_names[i].name; 3229 } 3230 } 3231 3232 return "????"; 3233 } 3234 3235 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3236 { 3237 int used; 3238 3239 /* chipsets >= AR9280 are single-chip */ 3240 if (AR_SREV_9280_20_OR_LATER(ah)) { 3241 used = scnprintf(hw_name, len, 3242 "Atheros AR%s Rev:%x", 3243 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3244 ah->hw_version.macRev); 3245 } 3246 else { 3247 used = scnprintf(hw_name, len, 3248 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3249 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3250 ah->hw_version.macRev, 3251 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3252 & AR_RADIO_SREV_MAJOR)), 3253 ah->hw_version.phyRev); 3254 } 3255 3256 hw_name[used] = '\0'; 3257 } 3258 EXPORT_SYMBOL(ath9k_hw_name); 3259