1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "ar9003_phy.h" 28 #include "debug.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static int __init ath9k_init(void) 39 { 40 return 0; 41 } 42 module_init(ath9k_init); 43 44 static void __exit ath9k_exit(void) 45 { 46 return; 47 } 48 module_exit(ath9k_exit); 49 50 /* Private hardware callbacks */ 51 52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 55 } 56 57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59 { 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61 } 62 63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64 { 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69 } 70 71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72 { 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78 } 79 80 /********************/ 81 /* Helper Functions */ 82 /********************/ 83 84 #ifdef CONFIG_ATH9K_DEBUGFS 85 86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 87 { 88 struct ath_softc *sc = common->priv; 89 if (sync_cause) 90 sc->debug.stats.istats.sync_cause_all++; 91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 92 sc->debug.stats.istats.sync_rtc_irq++; 93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 94 sc->debug.stats.istats.sync_mac_irq++; 95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 96 sc->debug.stats.istats.eeprom_illegal_access++; 97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 98 sc->debug.stats.istats.apb_timeout++; 99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 100 sc->debug.stats.istats.pci_mode_conflict++; 101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 102 sc->debug.stats.istats.host1_fatal++; 103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 104 sc->debug.stats.istats.host1_perr++; 105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 106 sc->debug.stats.istats.trcv_fifo_perr++; 107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 108 sc->debug.stats.istats.radm_cpl_ep++; 109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 110 sc->debug.stats.istats.radm_cpl_dllp_abort++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 112 sc->debug.stats.istats.radm_cpl_tlp_abort++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 114 sc->debug.stats.istats.radm_cpl_ecrc_err++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 116 sc->debug.stats.istats.radm_cpl_timeout++; 117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 118 sc->debug.stats.istats.local_timeout++; 119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 120 sc->debug.stats.istats.pm_access++; 121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 122 sc->debug.stats.istats.mac_awake++; 123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 124 sc->debug.stats.istats.mac_asleep++; 125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 126 sc->debug.stats.istats.mac_sleep_access++; 127 } 128 #endif 129 130 131 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 132 { 133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 134 struct ath_common *common = ath9k_hw_common(ah); 135 unsigned int clockrate; 136 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 139 clockrate = 117; 140 else if (!ah->curchan) /* should really check for CCK instead */ 141 clockrate = ATH9K_CLOCK_RATE_CCK; 142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 146 else 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 148 149 if (conf_is_ht40(conf)) 150 clockrate *= 2; 151 152 if (ah->curchan) { 153 if (IS_CHAN_HALF_RATE(ah->curchan)) 154 clockrate /= 2; 155 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 156 clockrate /= 4; 157 } 158 159 common->clockrate = clockrate; 160 } 161 162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 163 { 164 struct ath_common *common = ath9k_hw_common(ah); 165 166 return usecs * common->clockrate; 167 } 168 169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 170 { 171 int i; 172 173 BUG_ON(timeout < AH_TIME_QUANTUM); 174 175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 176 if ((REG_READ(ah, reg) & mask) == val) 177 return true; 178 179 udelay(AH_TIME_QUANTUM); 180 } 181 182 ath_dbg(ath9k_hw_common(ah), ANY, 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 184 timeout, reg, REG_READ(ah, reg), mask, val); 185 186 return false; 187 } 188 EXPORT_SYMBOL(ath9k_hw_wait); 189 190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 191 int hw_delay) 192 { 193 if (IS_CHAN_B(chan)) 194 hw_delay = (4 * hw_delay) / 22; 195 else 196 hw_delay /= 10; 197 198 if (IS_CHAN_HALF_RATE(chan)) 199 hw_delay *= 2; 200 else if (IS_CHAN_QUARTER_RATE(chan)) 201 hw_delay *= 4; 202 203 udelay(hw_delay + BASE_ACTIVATE_DELAY); 204 } 205 206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 207 int column, unsigned int *writecnt) 208 { 209 int r; 210 211 ENABLE_REGWRITE_BUFFER(ah); 212 for (r = 0; r < array->ia_rows; r++) { 213 REG_WRITE(ah, INI_RA(array, r, 0), 214 INI_RA(array, r, column)); 215 DO_DELAY(*writecnt); 216 } 217 REGWRITE_BUFFER_FLUSH(ah); 218 } 219 220 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 221 { 222 u32 retval; 223 int i; 224 225 for (i = 0, retval = 0; i < n; i++) { 226 retval = (retval << 1) | (val & 1); 227 val >>= 1; 228 } 229 return retval; 230 } 231 232 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 233 u8 phy, int kbps, 234 u32 frameLen, u16 rateix, 235 bool shortPreamble) 236 { 237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 238 239 if (kbps == 0) 240 return 0; 241 242 switch (phy) { 243 case WLAN_RC_PHY_CCK: 244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 245 if (shortPreamble) 246 phyTime >>= 1; 247 numBits = frameLen << 3; 248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 249 break; 250 case WLAN_RC_PHY_OFDM: 251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 253 numBits = OFDM_PLCP_BITS + (frameLen << 3); 254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 255 txTime = OFDM_SIFS_TIME_QUARTER 256 + OFDM_PREAMBLE_TIME_QUARTER 257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 258 } else if (ah->curchan && 259 IS_CHAN_HALF_RATE(ah->curchan)) { 260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 261 numBits = OFDM_PLCP_BITS + (frameLen << 3); 262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 263 txTime = OFDM_SIFS_TIME_HALF + 264 OFDM_PREAMBLE_TIME_HALF 265 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 266 } else { 267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 268 numBits = OFDM_PLCP_BITS + (frameLen << 3); 269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 271 + (numSymbols * OFDM_SYMBOL_TIME); 272 } 273 break; 274 default: 275 ath_err(ath9k_hw_common(ah), 276 "Unknown phy %u (rate ix %u)\n", phy, rateix); 277 txTime = 0; 278 break; 279 } 280 281 return txTime; 282 } 283 EXPORT_SYMBOL(ath9k_hw_computetxtime); 284 285 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 286 struct ath9k_channel *chan, 287 struct chan_centers *centers) 288 { 289 int8_t extoff; 290 291 if (!IS_CHAN_HT40(chan)) { 292 centers->ctl_center = centers->ext_center = 293 centers->synth_center = chan->channel; 294 return; 295 } 296 297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 298 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 299 centers->synth_center = 300 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 301 extoff = 1; 302 } else { 303 centers->synth_center = 304 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 305 extoff = -1; 306 } 307 308 centers->ctl_center = 309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 310 /* 25 MHz spacing is supported by hw but not on upper layers */ 311 centers->ext_center = 312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 313 } 314 315 /******************/ 316 /* Chip Revisions */ 317 /******************/ 318 319 static void ath9k_hw_read_revisions(struct ath_hw *ah) 320 { 321 u32 val; 322 323 switch (ah->hw_version.devid) { 324 case AR5416_AR9100_DEVID: 325 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 326 break; 327 case AR9300_DEVID_AR9330: 328 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 329 if (ah->get_mac_revision) { 330 ah->hw_version.macRev = ah->get_mac_revision(); 331 } else { 332 val = REG_READ(ah, AR_SREV); 333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 334 } 335 return; 336 case AR9300_DEVID_AR9340: 337 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 338 val = REG_READ(ah, AR_SREV); 339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 340 return; 341 case AR9300_DEVID_QCA955X: 342 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 343 return; 344 } 345 346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 347 348 if (val == 0xFF) { 349 val = REG_READ(ah, AR_SREV); 350 ah->hw_version.macVersion = 351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 353 354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 355 ah->is_pciexpress = true; 356 else 357 ah->is_pciexpress = (val & 358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 359 } else { 360 if (!AR_SREV_9100(ah)) 361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 362 363 ah->hw_version.macRev = val & AR_SREV_REVISION; 364 365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 366 ah->is_pciexpress = true; 367 } 368 } 369 370 /************************************/ 371 /* HW Attach, Detach, Init Routines */ 372 /************************************/ 373 374 static void ath9k_hw_disablepcie(struct ath_hw *ah) 375 { 376 if (!AR_SREV_5416(ah)) 377 return; 378 379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 388 389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 390 } 391 392 /* This should work for all families including legacy */ 393 static bool ath9k_hw_chip_test(struct ath_hw *ah) 394 { 395 struct ath_common *common = ath9k_hw_common(ah); 396 u32 regAddr[2] = { AR_STA_ID0 }; 397 u32 regHold[2]; 398 static const u32 patternData[4] = { 399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 400 }; 401 int i, j, loop_max; 402 403 if (!AR_SREV_9300_20_OR_LATER(ah)) { 404 loop_max = 2; 405 regAddr[1] = AR_PHY_BASE + (8 << 2); 406 } else 407 loop_max = 1; 408 409 for (i = 0; i < loop_max; i++) { 410 u32 addr = regAddr[i]; 411 u32 wrData, rdData; 412 413 regHold[i] = REG_READ(ah, addr); 414 for (j = 0; j < 0x100; j++) { 415 wrData = (j << 16) | j; 416 REG_WRITE(ah, addr, wrData); 417 rdData = REG_READ(ah, addr); 418 if (rdData != wrData) { 419 ath_err(common, 420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 421 addr, wrData, rdData); 422 return false; 423 } 424 } 425 for (j = 0; j < 4; j++) { 426 wrData = patternData[j]; 427 REG_WRITE(ah, addr, wrData); 428 rdData = REG_READ(ah, addr); 429 if (wrData != rdData) { 430 ath_err(common, 431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 432 addr, wrData, rdData); 433 return false; 434 } 435 } 436 REG_WRITE(ah, regAddr[i], regHold[i]); 437 } 438 udelay(100); 439 440 return true; 441 } 442 443 static void ath9k_hw_init_config(struct ath_hw *ah) 444 { 445 int i; 446 447 ah->config.dma_beacon_response_time = 1; 448 ah->config.sw_beacon_response_time = 6; 449 ah->config.additional_swba_backoff = 0; 450 ah->config.ack_6mb = 0x0; 451 ah->config.cwm_ignore_extcca = 0; 452 ah->config.pcie_clock_req = 0; 453 ah->config.analog_shiftreg = 1; 454 455 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 456 ah->config.spurchans[i][0] = AR_NO_SPUR; 457 ah->config.spurchans[i][1] = AR_NO_SPUR; 458 } 459 460 ah->config.rx_intr_mitigation = true; 461 ah->config.pcieSerDesWrite = true; 462 463 /* 464 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 465 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 466 * This means we use it for all AR5416 devices, and the few 467 * minor PCI AR9280 devices out there. 468 * 469 * Serialization is required because these devices do not handle 470 * well the case of two concurrent reads/writes due to the latency 471 * involved. During one read/write another read/write can be issued 472 * on another CPU while the previous read/write may still be working 473 * on our hardware, if we hit this case the hardware poops in a loop. 474 * We prevent this by serializing reads and writes. 475 * 476 * This issue is not present on PCI-Express devices or pre-AR5416 477 * devices (legacy, 802.11abg). 478 */ 479 if (num_possible_cpus() > 1) 480 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 481 } 482 483 static void ath9k_hw_init_defaults(struct ath_hw *ah) 484 { 485 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 486 487 regulatory->country_code = CTRY_DEFAULT; 488 regulatory->power_limit = MAX_RATE_POWER; 489 490 ah->hw_version.magic = AR5416_MAGIC; 491 ah->hw_version.subvendorid = 0; 492 493 ah->atim_window = 0; 494 ah->sta_id1_defaults = 495 AR_STA_ID1_CRPT_MIC_ENABLE | 496 AR_STA_ID1_MCAST_KSRCH; 497 if (AR_SREV_9100(ah)) 498 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 499 ah->slottime = ATH9K_SLOT_TIME_9; 500 ah->globaltxtimeout = (u32) -1; 501 ah->power_mode = ATH9K_PM_UNDEFINED; 502 ah->htc_reset_init = true; 503 } 504 505 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 506 { 507 struct ath_common *common = ath9k_hw_common(ah); 508 u32 sum; 509 int i; 510 u16 eeval; 511 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 512 513 sum = 0; 514 for (i = 0; i < 3; i++) { 515 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 516 sum += eeval; 517 common->macaddr[2 * i] = eeval >> 8; 518 common->macaddr[2 * i + 1] = eeval & 0xff; 519 } 520 if (sum == 0 || sum == 0xffff * 3) 521 return -EADDRNOTAVAIL; 522 523 return 0; 524 } 525 526 static int ath9k_hw_post_init(struct ath_hw *ah) 527 { 528 struct ath_common *common = ath9k_hw_common(ah); 529 int ecode; 530 531 if (common->bus_ops->ath_bus_type != ATH_USB) { 532 if (!ath9k_hw_chip_test(ah)) 533 return -ENODEV; 534 } 535 536 if (!AR_SREV_9300_20_OR_LATER(ah)) { 537 ecode = ar9002_hw_rf_claim(ah); 538 if (ecode != 0) 539 return ecode; 540 } 541 542 ecode = ath9k_hw_eeprom_init(ah); 543 if (ecode != 0) 544 return ecode; 545 546 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 547 ah->eep_ops->get_eeprom_ver(ah), 548 ah->eep_ops->get_eeprom_rev(ah)); 549 550 ath9k_hw_ani_init(ah); 551 552 return 0; 553 } 554 555 static int ath9k_hw_attach_ops(struct ath_hw *ah) 556 { 557 if (!AR_SREV_9300_20_OR_LATER(ah)) 558 return ar9002_hw_attach_ops(ah); 559 560 ar9003_hw_attach_ops(ah); 561 return 0; 562 } 563 564 /* Called for all hardware families */ 565 static int __ath9k_hw_init(struct ath_hw *ah) 566 { 567 struct ath_common *common = ath9k_hw_common(ah); 568 int r = 0; 569 570 ath9k_hw_read_revisions(ah); 571 572 /* 573 * Read back AR_WA into a permanent copy and set bits 14 and 17. 574 * We need to do this to avoid RMW of this register. We cannot 575 * read the reg when chip is asleep. 576 */ 577 if (AR_SREV_9300_20_OR_LATER(ah)) { 578 ah->WARegVal = REG_READ(ah, AR_WA); 579 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 580 AR_WA_ASPM_TIMER_BASED_DISABLE); 581 } 582 583 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 584 ath_err(common, "Couldn't reset chip\n"); 585 return -EIO; 586 } 587 588 if (AR_SREV_9565(ah)) { 589 ah->WARegVal |= AR_WA_BIT22; 590 REG_WRITE(ah, AR_WA, ah->WARegVal); 591 } 592 593 ath9k_hw_init_defaults(ah); 594 ath9k_hw_init_config(ah); 595 596 r = ath9k_hw_attach_ops(ah); 597 if (r) 598 return r; 599 600 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 601 ath_err(common, "Couldn't wakeup chip\n"); 602 return -EIO; 603 } 604 605 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 606 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 607 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 608 !ah->is_pciexpress)) { 609 ah->config.serialize_regmode = 610 SER_REG_MODE_ON; 611 } else { 612 ah->config.serialize_regmode = 613 SER_REG_MODE_OFF; 614 } 615 } 616 617 ath_dbg(common, RESET, "serialize_regmode is %d\n", 618 ah->config.serialize_regmode); 619 620 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 621 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 622 else 623 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 624 625 switch (ah->hw_version.macVersion) { 626 case AR_SREV_VERSION_5416_PCI: 627 case AR_SREV_VERSION_5416_PCIE: 628 case AR_SREV_VERSION_9160: 629 case AR_SREV_VERSION_9100: 630 case AR_SREV_VERSION_9280: 631 case AR_SREV_VERSION_9285: 632 case AR_SREV_VERSION_9287: 633 case AR_SREV_VERSION_9271: 634 case AR_SREV_VERSION_9300: 635 case AR_SREV_VERSION_9330: 636 case AR_SREV_VERSION_9485: 637 case AR_SREV_VERSION_9340: 638 case AR_SREV_VERSION_9462: 639 case AR_SREV_VERSION_9550: 640 case AR_SREV_VERSION_9565: 641 break; 642 default: 643 ath_err(common, 644 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 645 ah->hw_version.macVersion, ah->hw_version.macRev); 646 return -EOPNOTSUPP; 647 } 648 649 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 650 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 651 ah->is_pciexpress = false; 652 653 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 654 ath9k_hw_init_cal_settings(ah); 655 656 ah->ani_function = ATH9K_ANI_ALL; 657 if (!AR_SREV_9300_20_OR_LATER(ah)) 658 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 659 660 if (!ah->is_pciexpress) 661 ath9k_hw_disablepcie(ah); 662 663 r = ath9k_hw_post_init(ah); 664 if (r) 665 return r; 666 667 ath9k_hw_init_mode_gain_regs(ah); 668 r = ath9k_hw_fill_cap_info(ah); 669 if (r) 670 return r; 671 672 r = ath9k_hw_init_macaddr(ah); 673 if (r) { 674 ath_err(common, "Failed to initialize MAC address\n"); 675 return r; 676 } 677 678 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 679 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 680 else 681 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 682 683 if (AR_SREV_9330(ah)) 684 ah->bb_watchdog_timeout_ms = 85; 685 else 686 ah->bb_watchdog_timeout_ms = 25; 687 688 common->state = ATH_HW_INITIALIZED; 689 690 return 0; 691 } 692 693 int ath9k_hw_init(struct ath_hw *ah) 694 { 695 int ret; 696 struct ath_common *common = ath9k_hw_common(ah); 697 698 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 699 switch (ah->hw_version.devid) { 700 case AR5416_DEVID_PCI: 701 case AR5416_DEVID_PCIE: 702 case AR5416_AR9100_DEVID: 703 case AR9160_DEVID_PCI: 704 case AR9280_DEVID_PCI: 705 case AR9280_DEVID_PCIE: 706 case AR9285_DEVID_PCIE: 707 case AR9287_DEVID_PCI: 708 case AR9287_DEVID_PCIE: 709 case AR2427_DEVID_PCIE: 710 case AR9300_DEVID_PCIE: 711 case AR9300_DEVID_AR9485_PCIE: 712 case AR9300_DEVID_AR9330: 713 case AR9300_DEVID_AR9340: 714 case AR9300_DEVID_QCA955X: 715 case AR9300_DEVID_AR9580: 716 case AR9300_DEVID_AR9462: 717 case AR9485_DEVID_AR1111: 718 case AR9300_DEVID_AR9565: 719 break; 720 default: 721 if (common->bus_ops->ath_bus_type == ATH_USB) 722 break; 723 ath_err(common, "Hardware device ID 0x%04x not supported\n", 724 ah->hw_version.devid); 725 return -EOPNOTSUPP; 726 } 727 728 ret = __ath9k_hw_init(ah); 729 if (ret) { 730 ath_err(common, 731 "Unable to initialize hardware; initialization status: %d\n", 732 ret); 733 return ret; 734 } 735 736 return 0; 737 } 738 EXPORT_SYMBOL(ath9k_hw_init); 739 740 static void ath9k_hw_init_qos(struct ath_hw *ah) 741 { 742 ENABLE_REGWRITE_BUFFER(ah); 743 744 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 745 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 746 747 REG_WRITE(ah, AR_QOS_NO_ACK, 748 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 749 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 750 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 751 752 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 753 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 754 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 755 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 756 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 757 758 REGWRITE_BUFFER_FLUSH(ah); 759 } 760 761 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 762 { 763 struct ath_common *common = ath9k_hw_common(ah); 764 int i = 0; 765 766 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 767 udelay(100); 768 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 769 770 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 771 772 udelay(100); 773 774 if (WARN_ON_ONCE(i >= 100)) { 775 ath_err(common, "PLL4 meaurement not done\n"); 776 break; 777 } 778 779 i++; 780 } 781 782 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 783 } 784 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 785 786 static void ath9k_hw_init_pll(struct ath_hw *ah, 787 struct ath9k_channel *chan) 788 { 789 u32 pll; 790 791 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 792 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 793 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 794 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 796 AR_CH0_DPLL2_KD, 0x40); 797 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 798 AR_CH0_DPLL2_KI, 0x4); 799 800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 801 AR_CH0_BB_DPLL1_REFDIV, 0x5); 802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 803 AR_CH0_BB_DPLL1_NINI, 0x58); 804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 805 AR_CH0_BB_DPLL1_NFRAC, 0x0); 806 807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 808 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 810 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 812 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 813 814 /* program BB PLL phase_shift to 0x6 */ 815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 816 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 817 818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 819 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 820 udelay(1000); 821 } else if (AR_SREV_9330(ah)) { 822 u32 ddr_dpll2, pll_control2, kd; 823 824 if (ah->is_clk_25mhz) { 825 ddr_dpll2 = 0x18e82f01; 826 pll_control2 = 0xe04a3d; 827 kd = 0x1d; 828 } else { 829 ddr_dpll2 = 0x19e82f01; 830 pll_control2 = 0x886666; 831 kd = 0x3d; 832 } 833 834 /* program DDR PLL ki and kd value */ 835 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 836 837 /* program DDR PLL phase_shift */ 838 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 839 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 840 841 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 842 udelay(1000); 843 844 /* program refdiv, nint, frac to RTC register */ 845 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 846 847 /* program BB PLL kd and ki value */ 848 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 849 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 850 851 /* program BB PLL phase_shift */ 852 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 853 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 854 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 855 u32 regval, pll2_divint, pll2_divfrac, refdiv; 856 857 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 858 udelay(1000); 859 860 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 861 udelay(100); 862 863 if (ah->is_clk_25mhz) { 864 pll2_divint = 0x54; 865 pll2_divfrac = 0x1eb85; 866 refdiv = 3; 867 } else { 868 if (AR_SREV_9340(ah)) { 869 pll2_divint = 88; 870 pll2_divfrac = 0; 871 refdiv = 5; 872 } else { 873 pll2_divint = 0x11; 874 pll2_divfrac = 0x26666; 875 refdiv = 1; 876 } 877 } 878 879 regval = REG_READ(ah, AR_PHY_PLL_MODE); 880 regval |= (0x1 << 16); 881 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 882 udelay(100); 883 884 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 885 (pll2_divint << 18) | pll2_divfrac); 886 udelay(100); 887 888 regval = REG_READ(ah, AR_PHY_PLL_MODE); 889 if (AR_SREV_9340(ah)) 890 regval = (regval & 0x80071fff) | (0x1 << 30) | 891 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 892 else 893 regval = (regval & 0x80071fff) | (0x3 << 30) | 894 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 895 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 896 REG_WRITE(ah, AR_PHY_PLL_MODE, 897 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 898 udelay(1000); 899 } 900 901 pll = ath9k_hw_compute_pll_control(ah, chan); 902 if (AR_SREV_9565(ah)) 903 pll |= 0x40000; 904 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 905 906 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 907 AR_SREV_9550(ah)) 908 udelay(1000); 909 910 /* Switch the core clock for ar9271 to 117Mhz */ 911 if (AR_SREV_9271(ah)) { 912 udelay(500); 913 REG_WRITE(ah, 0x50040, 0x304); 914 } 915 916 udelay(RTC_PLL_SETTLE_DELAY); 917 918 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 919 920 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 921 if (ah->is_clk_25mhz) { 922 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 923 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 924 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 925 } else { 926 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 927 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 928 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 929 } 930 udelay(100); 931 } 932 } 933 934 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 935 enum nl80211_iftype opmode) 936 { 937 u32 sync_default = AR_INTR_SYNC_DEFAULT; 938 u32 imr_reg = AR_IMR_TXERR | 939 AR_IMR_TXURN | 940 AR_IMR_RXERR | 941 AR_IMR_RXORN | 942 AR_IMR_BCNMISC; 943 944 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 945 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 946 947 if (AR_SREV_9300_20_OR_LATER(ah)) { 948 imr_reg |= AR_IMR_RXOK_HP; 949 if (ah->config.rx_intr_mitigation) 950 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 951 else 952 imr_reg |= AR_IMR_RXOK_LP; 953 954 } else { 955 if (ah->config.rx_intr_mitigation) 956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 957 else 958 imr_reg |= AR_IMR_RXOK; 959 } 960 961 if (ah->config.tx_intr_mitigation) 962 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 963 else 964 imr_reg |= AR_IMR_TXOK; 965 966 ENABLE_REGWRITE_BUFFER(ah); 967 968 REG_WRITE(ah, AR_IMR, imr_reg); 969 ah->imrs2_reg |= AR_IMR_S2_GTT; 970 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 971 972 if (!AR_SREV_9100(ah)) { 973 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 974 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 975 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 976 } 977 978 REGWRITE_BUFFER_FLUSH(ah); 979 980 if (AR_SREV_9300_20_OR_LATER(ah)) { 981 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 982 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 983 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 984 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 985 } 986 } 987 988 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 989 { 990 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 991 val = min(val, (u32) 0xFFFF); 992 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 993 } 994 995 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 996 { 997 u32 val = ath9k_hw_mac_to_clks(ah, us); 998 val = min(val, (u32) 0xFFFF); 999 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1000 } 1001 1002 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1003 { 1004 u32 val = ath9k_hw_mac_to_clks(ah, us); 1005 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1006 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1007 } 1008 1009 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1010 { 1011 u32 val = ath9k_hw_mac_to_clks(ah, us); 1012 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1013 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1014 } 1015 1016 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1017 { 1018 if (tu > 0xFFFF) { 1019 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1020 tu); 1021 ah->globaltxtimeout = (u32) -1; 1022 return false; 1023 } else { 1024 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1025 ah->globaltxtimeout = tu; 1026 return true; 1027 } 1028 } 1029 1030 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1031 { 1032 struct ath_common *common = ath9k_hw_common(ah); 1033 struct ieee80211_conf *conf = &common->hw->conf; 1034 const struct ath9k_channel *chan = ah->curchan; 1035 int acktimeout, ctstimeout, ack_offset = 0; 1036 int slottime; 1037 int sifstime; 1038 int rx_lat = 0, tx_lat = 0, eifs = 0; 1039 u32 reg; 1040 1041 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1042 ah->misc_mode); 1043 1044 if (!chan) 1045 return; 1046 1047 if (ah->misc_mode != 0) 1048 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1049 1050 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1051 rx_lat = 41; 1052 else 1053 rx_lat = 37; 1054 tx_lat = 54; 1055 1056 if (IS_CHAN_5GHZ(chan)) 1057 sifstime = 16; 1058 else 1059 sifstime = 10; 1060 1061 if (IS_CHAN_HALF_RATE(chan)) { 1062 eifs = 175; 1063 rx_lat *= 2; 1064 tx_lat *= 2; 1065 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1066 tx_lat += 11; 1067 1068 sifstime = 32; 1069 ack_offset = 16; 1070 slottime = 13; 1071 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1072 eifs = 340; 1073 rx_lat = (rx_lat * 4) - 1; 1074 tx_lat *= 4; 1075 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1076 tx_lat += 22; 1077 1078 sifstime = 64; 1079 ack_offset = 32; 1080 slottime = 21; 1081 } else { 1082 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1083 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1084 reg = AR_USEC_ASYNC_FIFO; 1085 } else { 1086 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1087 common->clockrate; 1088 reg = REG_READ(ah, AR_USEC); 1089 } 1090 rx_lat = MS(reg, AR_USEC_RX_LAT); 1091 tx_lat = MS(reg, AR_USEC_TX_LAT); 1092 1093 slottime = ah->slottime; 1094 } 1095 1096 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1097 slottime += 3 * ah->coverage_class; 1098 acktimeout = slottime + sifstime + ack_offset; 1099 ctstimeout = acktimeout; 1100 1101 /* 1102 * Workaround for early ACK timeouts, add an offset to match the 1103 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1104 * This was initially only meant to work around an issue with delayed 1105 * BA frames in some implementations, but it has been found to fix ACK 1106 * timeout issues in other cases as well. 1107 */ 1108 if (conf->chandef.chan && 1109 conf->chandef.chan->band == IEEE80211_BAND_2GHZ && 1110 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1111 acktimeout += 64 - sifstime - ah->slottime; 1112 ctstimeout += 48 - sifstime - ah->slottime; 1113 } 1114 1115 ath9k_hw_set_sifs_time(ah, sifstime); 1116 ath9k_hw_setslottime(ah, slottime); 1117 ath9k_hw_set_ack_timeout(ah, acktimeout); 1118 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1119 if (ah->globaltxtimeout != (u32) -1) 1120 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1121 1122 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1123 REG_RMW(ah, AR_USEC, 1124 (common->clockrate - 1) | 1125 SM(rx_lat, AR_USEC_RX_LAT) | 1126 SM(tx_lat, AR_USEC_TX_LAT), 1127 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1128 1129 } 1130 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1131 1132 void ath9k_hw_deinit(struct ath_hw *ah) 1133 { 1134 struct ath_common *common = ath9k_hw_common(ah); 1135 1136 if (common->state < ATH_HW_INITIALIZED) 1137 return; 1138 1139 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1140 } 1141 EXPORT_SYMBOL(ath9k_hw_deinit); 1142 1143 /*******/ 1144 /* INI */ 1145 /*******/ 1146 1147 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1148 { 1149 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1150 1151 if (IS_CHAN_B(chan)) 1152 ctl |= CTL_11B; 1153 else if (IS_CHAN_G(chan)) 1154 ctl |= CTL_11G; 1155 else 1156 ctl |= CTL_11A; 1157 1158 return ctl; 1159 } 1160 1161 /****************************************/ 1162 /* Reset and Channel Switching Routines */ 1163 /****************************************/ 1164 1165 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1166 { 1167 struct ath_common *common = ath9k_hw_common(ah); 1168 int txbuf_size; 1169 1170 ENABLE_REGWRITE_BUFFER(ah); 1171 1172 /* 1173 * set AHB_MODE not to do cacheline prefetches 1174 */ 1175 if (!AR_SREV_9300_20_OR_LATER(ah)) 1176 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1177 1178 /* 1179 * let mac dma reads be in 128 byte chunks 1180 */ 1181 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1182 1183 REGWRITE_BUFFER_FLUSH(ah); 1184 1185 /* 1186 * Restore TX Trigger Level to its pre-reset value. 1187 * The initial value depends on whether aggregation is enabled, and is 1188 * adjusted whenever underruns are detected. 1189 */ 1190 if (!AR_SREV_9300_20_OR_LATER(ah)) 1191 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1192 1193 ENABLE_REGWRITE_BUFFER(ah); 1194 1195 /* 1196 * let mac dma writes be in 128 byte chunks 1197 */ 1198 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1199 1200 /* 1201 * Setup receive FIFO threshold to hold off TX activities 1202 */ 1203 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1204 1205 if (AR_SREV_9300_20_OR_LATER(ah)) { 1206 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1207 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1208 1209 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1210 ah->caps.rx_status_len); 1211 } 1212 1213 /* 1214 * reduce the number of usable entries in PCU TXBUF to avoid 1215 * wrap around issues. 1216 */ 1217 if (AR_SREV_9285(ah)) { 1218 /* For AR9285 the number of Fifos are reduced to half. 1219 * So set the usable tx buf size also to half to 1220 * avoid data/delimiter underruns 1221 */ 1222 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1223 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1224 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1225 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1226 } else { 1227 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1228 } 1229 1230 if (!AR_SREV_9271(ah)) 1231 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1232 1233 REGWRITE_BUFFER_FLUSH(ah); 1234 1235 if (AR_SREV_9300_20_OR_LATER(ah)) 1236 ath9k_hw_reset_txstatus_ring(ah); 1237 } 1238 1239 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1240 { 1241 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1242 u32 set = AR_STA_ID1_KSRCH_MODE; 1243 1244 switch (opmode) { 1245 case NL80211_IFTYPE_ADHOC: 1246 set |= AR_STA_ID1_ADHOC; 1247 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1248 break; 1249 case NL80211_IFTYPE_MESH_POINT: 1250 case NL80211_IFTYPE_AP: 1251 set |= AR_STA_ID1_STA_AP; 1252 /* fall through */ 1253 case NL80211_IFTYPE_STATION: 1254 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1255 break; 1256 default: 1257 if (!ah->is_monitoring) 1258 set = 0; 1259 break; 1260 } 1261 REG_RMW(ah, AR_STA_ID1, set, mask); 1262 } 1263 1264 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1265 u32 *coef_mantissa, u32 *coef_exponent) 1266 { 1267 u32 coef_exp, coef_man; 1268 1269 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1270 if ((coef_scaled >> coef_exp) & 0x1) 1271 break; 1272 1273 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1274 1275 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1276 1277 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1278 *coef_exponent = coef_exp - 16; 1279 } 1280 1281 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1282 { 1283 u32 rst_flags; 1284 u32 tmpReg; 1285 1286 if (AR_SREV_9100(ah)) { 1287 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1288 AR_RTC_DERIVED_CLK_PERIOD, 1); 1289 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1290 } 1291 1292 ENABLE_REGWRITE_BUFFER(ah); 1293 1294 if (AR_SREV_9300_20_OR_LATER(ah)) { 1295 REG_WRITE(ah, AR_WA, ah->WARegVal); 1296 udelay(10); 1297 } 1298 1299 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1300 AR_RTC_FORCE_WAKE_ON_INT); 1301 1302 if (AR_SREV_9100(ah)) { 1303 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1304 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1305 } else { 1306 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1307 if (AR_SREV_9340(ah)) 1308 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1309 else 1310 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1311 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1312 1313 if (tmpReg) { 1314 u32 val; 1315 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1316 1317 val = AR_RC_HOSTIF; 1318 if (!AR_SREV_9300_20_OR_LATER(ah)) 1319 val |= AR_RC_AHB; 1320 REG_WRITE(ah, AR_RC, val); 1321 1322 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1323 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1324 1325 rst_flags = AR_RTC_RC_MAC_WARM; 1326 if (type == ATH9K_RESET_COLD) 1327 rst_flags |= AR_RTC_RC_MAC_COLD; 1328 } 1329 1330 if (AR_SREV_9330(ah)) { 1331 int npend = 0; 1332 int i; 1333 1334 /* AR9330 WAR: 1335 * call external reset function to reset WMAC if: 1336 * - doing a cold reset 1337 * - we have pending frames in the TX queues 1338 */ 1339 1340 for (i = 0; i < AR_NUM_QCU; i++) { 1341 npend = ath9k_hw_numtxpending(ah, i); 1342 if (npend) 1343 break; 1344 } 1345 1346 if (ah->external_reset && 1347 (npend || type == ATH9K_RESET_COLD)) { 1348 int reset_err = 0; 1349 1350 ath_dbg(ath9k_hw_common(ah), RESET, 1351 "reset MAC via external reset\n"); 1352 1353 reset_err = ah->external_reset(); 1354 if (reset_err) { 1355 ath_err(ath9k_hw_common(ah), 1356 "External reset failed, err=%d\n", 1357 reset_err); 1358 return false; 1359 } 1360 1361 REG_WRITE(ah, AR_RTC_RESET, 1); 1362 } 1363 } 1364 1365 if (ath9k_hw_mci_is_enabled(ah)) 1366 ar9003_mci_check_gpm_offset(ah); 1367 1368 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1369 1370 REGWRITE_BUFFER_FLUSH(ah); 1371 1372 udelay(50); 1373 1374 REG_WRITE(ah, AR_RTC_RC, 0); 1375 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1376 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1377 return false; 1378 } 1379 1380 if (!AR_SREV_9100(ah)) 1381 REG_WRITE(ah, AR_RC, 0); 1382 1383 if (AR_SREV_9100(ah)) 1384 udelay(50); 1385 1386 return true; 1387 } 1388 1389 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1390 { 1391 ENABLE_REGWRITE_BUFFER(ah); 1392 1393 if (AR_SREV_9300_20_OR_LATER(ah)) { 1394 REG_WRITE(ah, AR_WA, ah->WARegVal); 1395 udelay(10); 1396 } 1397 1398 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1399 AR_RTC_FORCE_WAKE_ON_INT); 1400 1401 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1402 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1403 1404 REG_WRITE(ah, AR_RTC_RESET, 0); 1405 1406 REGWRITE_BUFFER_FLUSH(ah); 1407 1408 if (!AR_SREV_9300_20_OR_LATER(ah)) 1409 udelay(2); 1410 1411 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1412 REG_WRITE(ah, AR_RC, 0); 1413 1414 REG_WRITE(ah, AR_RTC_RESET, 1); 1415 1416 if (!ath9k_hw_wait(ah, 1417 AR_RTC_STATUS, 1418 AR_RTC_STATUS_M, 1419 AR_RTC_STATUS_ON, 1420 AH_WAIT_TIMEOUT)) { 1421 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1422 return false; 1423 } 1424 1425 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1426 } 1427 1428 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1429 { 1430 bool ret = false; 1431 1432 if (AR_SREV_9300_20_OR_LATER(ah)) { 1433 REG_WRITE(ah, AR_WA, ah->WARegVal); 1434 udelay(10); 1435 } 1436 1437 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1438 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1439 1440 if (!ah->reset_power_on) 1441 type = ATH9K_RESET_POWER_ON; 1442 1443 switch (type) { 1444 case ATH9K_RESET_POWER_ON: 1445 ret = ath9k_hw_set_reset_power_on(ah); 1446 if (ret) 1447 ah->reset_power_on = true; 1448 break; 1449 case ATH9K_RESET_WARM: 1450 case ATH9K_RESET_COLD: 1451 ret = ath9k_hw_set_reset(ah, type); 1452 break; 1453 default: 1454 break; 1455 } 1456 1457 return ret; 1458 } 1459 1460 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1461 struct ath9k_channel *chan) 1462 { 1463 int reset_type = ATH9K_RESET_WARM; 1464 1465 if (AR_SREV_9280(ah)) { 1466 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1467 reset_type = ATH9K_RESET_POWER_ON; 1468 else 1469 reset_type = ATH9K_RESET_COLD; 1470 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1471 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1472 reset_type = ATH9K_RESET_COLD; 1473 1474 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1475 return false; 1476 1477 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1478 return false; 1479 1480 ah->chip_fullsleep = false; 1481 1482 if (AR_SREV_9330(ah)) 1483 ar9003_hw_internal_regulator_apply(ah); 1484 ath9k_hw_init_pll(ah, chan); 1485 ath9k_hw_set_rfmode(ah, chan); 1486 1487 return true; 1488 } 1489 1490 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1491 struct ath9k_channel *chan) 1492 { 1493 struct ath_common *common = ath9k_hw_common(ah); 1494 struct ath9k_hw_capabilities *pCap = &ah->caps; 1495 bool band_switch = false, mode_diff = false; 1496 u8 ini_reloaded = 0; 1497 u32 qnum; 1498 int r; 1499 1500 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1501 u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1502 u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1503 band_switch = (cur != new); 1504 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1505 } 1506 1507 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1508 if (ath9k_hw_numtxpending(ah, qnum)) { 1509 ath_dbg(common, QUEUE, 1510 "Transmit frames pending on queue %d\n", qnum); 1511 return false; 1512 } 1513 } 1514 1515 if (!ath9k_hw_rfbus_req(ah)) { 1516 ath_err(common, "Could not kill baseband RX\n"); 1517 return false; 1518 } 1519 1520 if (band_switch || mode_diff) { 1521 ath9k_hw_mark_phy_inactive(ah); 1522 udelay(5); 1523 1524 if (band_switch) 1525 ath9k_hw_init_pll(ah, chan); 1526 1527 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1528 ath_err(common, "Failed to do fast channel change\n"); 1529 return false; 1530 } 1531 } 1532 1533 ath9k_hw_set_channel_regs(ah, chan); 1534 1535 r = ath9k_hw_rf_set_freq(ah, chan); 1536 if (r) { 1537 ath_err(common, "Failed to set channel\n"); 1538 return false; 1539 } 1540 ath9k_hw_set_clockrate(ah); 1541 ath9k_hw_apply_txpower(ah, chan, false); 1542 1543 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1544 ath9k_hw_set_delta_slope(ah, chan); 1545 1546 ath9k_hw_spur_mitigate_freq(ah, chan); 1547 1548 if (band_switch || ini_reloaded) 1549 ah->eep_ops->set_board_values(ah, chan); 1550 1551 ath9k_hw_init_bb(ah, chan); 1552 ath9k_hw_rfbus_done(ah); 1553 1554 if (band_switch || ini_reloaded) { 1555 ah->ah_flags |= AH_FASTCC; 1556 ath9k_hw_init_cal(ah, chan); 1557 ah->ah_flags &= ~AH_FASTCC; 1558 } 1559 1560 return true; 1561 } 1562 1563 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1564 { 1565 u32 gpio_mask = ah->gpio_mask; 1566 int i; 1567 1568 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1569 if (!(gpio_mask & 1)) 1570 continue; 1571 1572 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1573 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1574 } 1575 } 1576 1577 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1578 int *hang_state, int *hang_pos) 1579 { 1580 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1581 u32 chain_state, dcs_pos, i; 1582 1583 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1584 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1585 for (i = 0; i < 3; i++) { 1586 if (chain_state == dcu_chain_state[i]) { 1587 *hang_state = chain_state; 1588 *hang_pos = dcs_pos; 1589 return true; 1590 } 1591 } 1592 } 1593 return false; 1594 } 1595 1596 #define DCU_COMPLETE_STATE 1 1597 #define DCU_COMPLETE_STATE_MASK 0x3 1598 #define NUM_STATUS_READS 50 1599 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1600 { 1601 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1602 u32 i, hang_pos, hang_state, num_state = 6; 1603 1604 comp_state = REG_READ(ah, AR_DMADBG_6); 1605 1606 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1607 ath_dbg(ath9k_hw_common(ah), RESET, 1608 "MAC Hang signature not found at DCU complete\n"); 1609 return false; 1610 } 1611 1612 chain_state = REG_READ(ah, dcs_reg); 1613 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1614 goto hang_check_iter; 1615 1616 dcs_reg = AR_DMADBG_5; 1617 num_state = 4; 1618 chain_state = REG_READ(ah, dcs_reg); 1619 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1620 goto hang_check_iter; 1621 1622 ath_dbg(ath9k_hw_common(ah), RESET, 1623 "MAC Hang signature 1 not found\n"); 1624 return false; 1625 1626 hang_check_iter: 1627 ath_dbg(ath9k_hw_common(ah), RESET, 1628 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1629 chain_state, comp_state, hang_state, hang_pos); 1630 1631 for (i = 0; i < NUM_STATUS_READS; i++) { 1632 chain_state = REG_READ(ah, dcs_reg); 1633 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1634 comp_state = REG_READ(ah, AR_DMADBG_6); 1635 1636 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1637 DCU_COMPLETE_STATE) || 1638 (chain_state != hang_state)) 1639 return false; 1640 } 1641 1642 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1643 1644 return true; 1645 } 1646 1647 bool ath9k_hw_check_alive(struct ath_hw *ah) 1648 { 1649 int count = 50; 1650 u32 reg; 1651 1652 if (AR_SREV_9300(ah)) 1653 return !ath9k_hw_detect_mac_hang(ah); 1654 1655 if (AR_SREV_9285_12_OR_LATER(ah)) 1656 return true; 1657 1658 do { 1659 reg = REG_READ(ah, AR_OBS_BUS_1); 1660 1661 if ((reg & 0x7E7FFFEF) == 0x00702400) 1662 continue; 1663 1664 switch (reg & 0x7E000B00) { 1665 case 0x1E000000: 1666 case 0x52000B00: 1667 case 0x18000B00: 1668 continue; 1669 default: 1670 return true; 1671 } 1672 } while (count-- > 0); 1673 1674 return false; 1675 } 1676 EXPORT_SYMBOL(ath9k_hw_check_alive); 1677 1678 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1679 { 1680 /* Setup MFP options for CCMP */ 1681 if (AR_SREV_9280_20_OR_LATER(ah)) { 1682 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1683 * frames when constructing CCMP AAD. */ 1684 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1685 0xc7ff); 1686 ah->sw_mgmt_crypto = false; 1687 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1688 /* Disable hardware crypto for management frames */ 1689 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1690 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1691 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1692 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1693 ah->sw_mgmt_crypto = true; 1694 } else { 1695 ah->sw_mgmt_crypto = true; 1696 } 1697 } 1698 1699 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1700 u32 macStaId1, u32 saveDefAntenna) 1701 { 1702 struct ath_common *common = ath9k_hw_common(ah); 1703 1704 ENABLE_REGWRITE_BUFFER(ah); 1705 1706 REG_RMW(ah, AR_STA_ID1, macStaId1 1707 | AR_STA_ID1_RTS_USE_DEF 1708 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1709 | ah->sta_id1_defaults, 1710 ~AR_STA_ID1_SADH_MASK); 1711 ath_hw_setbssidmask(common); 1712 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1713 ath9k_hw_write_associd(ah); 1714 REG_WRITE(ah, AR_ISR, ~0); 1715 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1716 1717 REGWRITE_BUFFER_FLUSH(ah); 1718 1719 ath9k_hw_set_operating_mode(ah, ah->opmode); 1720 } 1721 1722 static void ath9k_hw_init_queues(struct ath_hw *ah) 1723 { 1724 int i; 1725 1726 ENABLE_REGWRITE_BUFFER(ah); 1727 1728 for (i = 0; i < AR_NUM_DCU; i++) 1729 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1730 1731 REGWRITE_BUFFER_FLUSH(ah); 1732 1733 ah->intr_txqs = 0; 1734 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1735 ath9k_hw_resettxqueue(ah, i); 1736 } 1737 1738 /* 1739 * For big endian systems turn on swapping for descriptors 1740 */ 1741 static void ath9k_hw_init_desc(struct ath_hw *ah) 1742 { 1743 struct ath_common *common = ath9k_hw_common(ah); 1744 1745 if (AR_SREV_9100(ah)) { 1746 u32 mask; 1747 mask = REG_READ(ah, AR_CFG); 1748 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1749 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1750 mask); 1751 } else { 1752 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1753 REG_WRITE(ah, AR_CFG, mask); 1754 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1755 REG_READ(ah, AR_CFG)); 1756 } 1757 } else { 1758 if (common->bus_ops->ath_bus_type == ATH_USB) { 1759 /* Configure AR9271 target WLAN */ 1760 if (AR_SREV_9271(ah)) 1761 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1762 else 1763 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1764 } 1765 #ifdef __BIG_ENDIAN 1766 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1767 AR_SREV_9550(ah)) 1768 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1769 else 1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1771 #endif 1772 } 1773 } 1774 1775 /* 1776 * Fast channel change: 1777 * (Change synthesizer based on channel freq without resetting chip) 1778 */ 1779 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1780 { 1781 struct ath_common *common = ath9k_hw_common(ah); 1782 struct ath9k_hw_capabilities *pCap = &ah->caps; 1783 int ret; 1784 1785 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1786 goto fail; 1787 1788 if (ah->chip_fullsleep) 1789 goto fail; 1790 1791 if (!ah->curchan) 1792 goto fail; 1793 1794 if (chan->channel == ah->curchan->channel) 1795 goto fail; 1796 1797 if ((ah->curchan->channelFlags | chan->channelFlags) & 1798 (CHANNEL_HALF | CHANNEL_QUARTER)) 1799 goto fail; 1800 1801 /* 1802 * If cross-band fcc is not supoprted, bail out if 1803 * either channelFlags or chanmode differ. 1804 * 1805 * chanmode will be different if the HT operating mode 1806 * changes because of CSA. 1807 */ 1808 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH)) { 1809 if ((chan->channelFlags & CHANNEL_ALL) != 1810 (ah->curchan->channelFlags & CHANNEL_ALL)) 1811 goto fail; 1812 1813 if (chan->chanmode != ah->curchan->chanmode) 1814 goto fail; 1815 } 1816 1817 if (!ath9k_hw_check_alive(ah)) 1818 goto fail; 1819 1820 /* 1821 * For AR9462, make sure that calibration data for 1822 * re-using are present. 1823 */ 1824 if (AR_SREV_9462(ah) && (ah->caldata && 1825 (!ah->caldata->done_txiqcal_once || 1826 !ah->caldata->done_txclcal_once || 1827 !ah->caldata->rtt_done))) 1828 goto fail; 1829 1830 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1831 ah->curchan->channel, chan->channel); 1832 1833 ret = ath9k_hw_channel_change(ah, chan); 1834 if (!ret) 1835 goto fail; 1836 1837 if (ath9k_hw_mci_is_enabled(ah)) 1838 ar9003_mci_2g5g_switch(ah, false); 1839 1840 ath9k_hw_loadnf(ah, ah->curchan); 1841 ath9k_hw_start_nfcal(ah, true); 1842 1843 if (AR_SREV_9271(ah)) 1844 ar9002_hw_load_ani_reg(ah, chan); 1845 1846 return 0; 1847 fail: 1848 return -EINVAL; 1849 } 1850 1851 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1852 struct ath9k_hw_cal_data *caldata, bool fastcc) 1853 { 1854 struct ath_common *common = ath9k_hw_common(ah); 1855 u32 saveLedState; 1856 u32 saveDefAntenna; 1857 u32 macStaId1; 1858 u64 tsf = 0; 1859 int r; 1860 bool start_mci_reset = false; 1861 bool save_fullsleep = ah->chip_fullsleep; 1862 1863 if (ath9k_hw_mci_is_enabled(ah)) { 1864 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1865 if (start_mci_reset) 1866 return 0; 1867 } 1868 1869 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1870 return -EIO; 1871 1872 if (ah->curchan && !ah->chip_fullsleep) 1873 ath9k_hw_getnf(ah, ah->curchan); 1874 1875 ah->caldata = caldata; 1876 if (caldata && (chan->channel != caldata->channel || 1877 chan->channelFlags != caldata->channelFlags || 1878 chan->chanmode != caldata->chanmode)) { 1879 /* Operating channel changed, reset channel calibration data */ 1880 memset(caldata, 0, sizeof(*caldata)); 1881 ath9k_init_nfcal_hist_buffer(ah, chan); 1882 } else if (caldata) { 1883 caldata->paprd_packet_sent = false; 1884 } 1885 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1886 1887 if (fastcc) { 1888 r = ath9k_hw_do_fastcc(ah, chan); 1889 if (!r) 1890 return r; 1891 } 1892 1893 if (ath9k_hw_mci_is_enabled(ah)) 1894 ar9003_mci_stop_bt(ah, save_fullsleep); 1895 1896 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1897 if (saveDefAntenna == 0) 1898 saveDefAntenna = 1; 1899 1900 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1901 1902 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1903 if (AR_SREV_9100(ah) || 1904 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1905 tsf = ath9k_hw_gettsf64(ah); 1906 1907 saveLedState = REG_READ(ah, AR_CFG_LED) & 1908 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1909 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1910 1911 ath9k_hw_mark_phy_inactive(ah); 1912 1913 ah->paprd_table_write_done = false; 1914 1915 /* Only required on the first reset */ 1916 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1917 REG_WRITE(ah, 1918 AR9271_RESET_POWER_DOWN_CONTROL, 1919 AR9271_RADIO_RF_RST); 1920 udelay(50); 1921 } 1922 1923 if (!ath9k_hw_chip_reset(ah, chan)) { 1924 ath_err(common, "Chip reset failed\n"); 1925 return -EINVAL; 1926 } 1927 1928 /* Only required on the first reset */ 1929 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1930 ah->htc_reset_init = false; 1931 REG_WRITE(ah, 1932 AR9271_RESET_POWER_DOWN_CONTROL, 1933 AR9271_GATE_MAC_CTL); 1934 udelay(50); 1935 } 1936 1937 /* Restore TSF */ 1938 if (tsf) 1939 ath9k_hw_settsf64(ah, tsf); 1940 1941 if (AR_SREV_9280_20_OR_LATER(ah)) 1942 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1943 1944 if (!AR_SREV_9300_20_OR_LATER(ah)) 1945 ar9002_hw_enable_async_fifo(ah); 1946 1947 r = ath9k_hw_process_ini(ah, chan); 1948 if (r) 1949 return r; 1950 1951 if (ath9k_hw_mci_is_enabled(ah)) 1952 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1953 1954 /* 1955 * Some AR91xx SoC devices frequently fail to accept TSF writes 1956 * right after the chip reset. When that happens, write a new 1957 * value after the initvals have been applied, with an offset 1958 * based on measured time difference 1959 */ 1960 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1961 tsf += 1500; 1962 ath9k_hw_settsf64(ah, tsf); 1963 } 1964 1965 ath9k_hw_init_mfp(ah); 1966 1967 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1968 ath9k_hw_set_delta_slope(ah, chan); 1969 1970 ath9k_hw_spur_mitigate_freq(ah, chan); 1971 ah->eep_ops->set_board_values(ah, chan); 1972 1973 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1974 1975 r = ath9k_hw_rf_set_freq(ah, chan); 1976 if (r) 1977 return r; 1978 1979 ath9k_hw_set_clockrate(ah); 1980 1981 ath9k_hw_init_queues(ah); 1982 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1983 ath9k_hw_ani_cache_ini_regs(ah); 1984 ath9k_hw_init_qos(ah); 1985 1986 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1987 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1988 1989 ath9k_hw_init_global_settings(ah); 1990 1991 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1992 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1993 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1994 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1995 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1996 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1997 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1998 } 1999 2000 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2001 2002 ath9k_hw_set_dma(ah); 2003 2004 if (!ath9k_hw_mci_is_enabled(ah)) 2005 REG_WRITE(ah, AR_OBS, 8); 2006 2007 if (ah->config.rx_intr_mitigation) { 2008 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2009 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2010 } 2011 2012 if (ah->config.tx_intr_mitigation) { 2013 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2014 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2015 } 2016 2017 ath9k_hw_init_bb(ah, chan); 2018 2019 if (caldata) { 2020 caldata->done_txiqcal_once = false; 2021 caldata->done_txclcal_once = false; 2022 } 2023 if (!ath9k_hw_init_cal(ah, chan)) 2024 return -EIO; 2025 2026 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2027 return -EIO; 2028 2029 ENABLE_REGWRITE_BUFFER(ah); 2030 2031 ath9k_hw_restore_chainmask(ah); 2032 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2033 2034 REGWRITE_BUFFER_FLUSH(ah); 2035 2036 ath9k_hw_init_desc(ah); 2037 2038 if (ath9k_hw_btcoex_is_enabled(ah)) 2039 ath9k_hw_btcoex_enable(ah); 2040 2041 if (ath9k_hw_mci_is_enabled(ah)) 2042 ar9003_mci_check_bt(ah); 2043 2044 ath9k_hw_loadnf(ah, chan); 2045 ath9k_hw_start_nfcal(ah, true); 2046 2047 if (AR_SREV_9300_20_OR_LATER(ah)) { 2048 ar9003_hw_bb_watchdog_config(ah); 2049 ar9003_hw_disable_phy_restart(ah); 2050 } 2051 2052 ath9k_hw_apply_gpio_override(ah); 2053 2054 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2055 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2056 2057 return 0; 2058 } 2059 EXPORT_SYMBOL(ath9k_hw_reset); 2060 2061 /******************************/ 2062 /* Power Management (Chipset) */ 2063 /******************************/ 2064 2065 /* 2066 * Notify Power Mgt is disabled in self-generated frames. 2067 * If requested, force chip to sleep. 2068 */ 2069 static void ath9k_set_power_sleep(struct ath_hw *ah) 2070 { 2071 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2072 2073 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2074 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2075 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2076 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2077 /* xxx Required for WLAN only case ? */ 2078 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2079 udelay(100); 2080 } 2081 2082 /* 2083 * Clear the RTC force wake bit to allow the 2084 * mac to go to sleep. 2085 */ 2086 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2087 2088 if (ath9k_hw_mci_is_enabled(ah)) 2089 udelay(100); 2090 2091 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2092 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2093 2094 /* Shutdown chip. Active low */ 2095 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2096 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2097 udelay(2); 2098 } 2099 2100 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2101 if (AR_SREV_9300_20_OR_LATER(ah)) 2102 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2103 } 2104 2105 /* 2106 * Notify Power Management is enabled in self-generating 2107 * frames. If request, set power mode of chip to 2108 * auto/normal. Duration in units of 128us (1/8 TU). 2109 */ 2110 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2111 { 2112 struct ath9k_hw_capabilities *pCap = &ah->caps; 2113 2114 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2115 2116 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2117 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2118 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2119 AR_RTC_FORCE_WAKE_ON_INT); 2120 } else { 2121 2122 /* When chip goes into network sleep, it could be waken 2123 * up by MCI_INT interrupt caused by BT's HW messages 2124 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2125 * rate (~100us). This will cause chip to leave and 2126 * re-enter network sleep mode frequently, which in 2127 * consequence will have WLAN MCI HW to generate lots of 2128 * SYS_WAKING and SYS_SLEEPING messages which will make 2129 * BT CPU to busy to process. 2130 */ 2131 if (ath9k_hw_mci_is_enabled(ah)) 2132 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2133 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2134 /* 2135 * Clear the RTC force wake bit to allow the 2136 * mac to go to sleep. 2137 */ 2138 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2139 2140 if (ath9k_hw_mci_is_enabled(ah)) 2141 udelay(30); 2142 } 2143 2144 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2145 if (AR_SREV_9300_20_OR_LATER(ah)) 2146 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2147 } 2148 2149 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2150 { 2151 u32 val; 2152 int i; 2153 2154 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2155 if (AR_SREV_9300_20_OR_LATER(ah)) { 2156 REG_WRITE(ah, AR_WA, ah->WARegVal); 2157 udelay(10); 2158 } 2159 2160 if ((REG_READ(ah, AR_RTC_STATUS) & 2161 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2162 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2163 return false; 2164 } 2165 if (!AR_SREV_9300_20_OR_LATER(ah)) 2166 ath9k_hw_init_pll(ah, NULL); 2167 } 2168 if (AR_SREV_9100(ah)) 2169 REG_SET_BIT(ah, AR_RTC_RESET, 2170 AR_RTC_RESET_EN); 2171 2172 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2173 AR_RTC_FORCE_WAKE_EN); 2174 udelay(50); 2175 2176 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2177 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2178 if (val == AR_RTC_STATUS_ON) 2179 break; 2180 udelay(50); 2181 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2182 AR_RTC_FORCE_WAKE_EN); 2183 } 2184 if (i == 0) { 2185 ath_err(ath9k_hw_common(ah), 2186 "Failed to wakeup in %uus\n", 2187 POWER_UP_TIME / 20); 2188 return false; 2189 } 2190 2191 if (ath9k_hw_mci_is_enabled(ah)) 2192 ar9003_mci_set_power_awake(ah); 2193 2194 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2195 2196 return true; 2197 } 2198 2199 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2200 { 2201 struct ath_common *common = ath9k_hw_common(ah); 2202 int status = true; 2203 static const char *modes[] = { 2204 "AWAKE", 2205 "FULL-SLEEP", 2206 "NETWORK SLEEP", 2207 "UNDEFINED" 2208 }; 2209 2210 if (ah->power_mode == mode) 2211 return status; 2212 2213 ath_dbg(common, RESET, "%s -> %s\n", 2214 modes[ah->power_mode], modes[mode]); 2215 2216 switch (mode) { 2217 case ATH9K_PM_AWAKE: 2218 status = ath9k_hw_set_power_awake(ah); 2219 break; 2220 case ATH9K_PM_FULL_SLEEP: 2221 if (ath9k_hw_mci_is_enabled(ah)) 2222 ar9003_mci_set_full_sleep(ah); 2223 2224 ath9k_set_power_sleep(ah); 2225 ah->chip_fullsleep = true; 2226 break; 2227 case ATH9K_PM_NETWORK_SLEEP: 2228 ath9k_set_power_network_sleep(ah); 2229 break; 2230 default: 2231 ath_err(common, "Unknown power mode %u\n", mode); 2232 return false; 2233 } 2234 ah->power_mode = mode; 2235 2236 /* 2237 * XXX: If this warning never comes up after a while then 2238 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2239 * ath9k_hw_setpower() return type void. 2240 */ 2241 2242 if (!(ah->ah_flags & AH_UNPLUGGED)) 2243 ATH_DBG_WARN_ON_ONCE(!status); 2244 2245 return status; 2246 } 2247 EXPORT_SYMBOL(ath9k_hw_setpower); 2248 2249 /*******************/ 2250 /* Beacon Handling */ 2251 /*******************/ 2252 2253 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2254 { 2255 int flags = 0; 2256 2257 ENABLE_REGWRITE_BUFFER(ah); 2258 2259 switch (ah->opmode) { 2260 case NL80211_IFTYPE_ADHOC: 2261 REG_SET_BIT(ah, AR_TXCFG, 2262 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2263 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2264 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2265 flags |= AR_NDP_TIMER_EN; 2266 case NL80211_IFTYPE_MESH_POINT: 2267 case NL80211_IFTYPE_AP: 2268 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2269 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2270 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2271 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2272 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2273 flags |= 2274 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2275 break; 2276 default: 2277 ath_dbg(ath9k_hw_common(ah), BEACON, 2278 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2279 return; 2280 break; 2281 } 2282 2283 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2284 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2285 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2286 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2287 2288 REGWRITE_BUFFER_FLUSH(ah); 2289 2290 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2291 } 2292 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2293 2294 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2295 const struct ath9k_beacon_state *bs) 2296 { 2297 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2298 struct ath9k_hw_capabilities *pCap = &ah->caps; 2299 struct ath_common *common = ath9k_hw_common(ah); 2300 2301 ENABLE_REGWRITE_BUFFER(ah); 2302 2303 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2304 2305 REG_WRITE(ah, AR_BEACON_PERIOD, 2306 TU_TO_USEC(bs->bs_intval)); 2307 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2308 TU_TO_USEC(bs->bs_intval)); 2309 2310 REGWRITE_BUFFER_FLUSH(ah); 2311 2312 REG_RMW_FIELD(ah, AR_RSSI_THR, 2313 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2314 2315 beaconintval = bs->bs_intval; 2316 2317 if (bs->bs_sleepduration > beaconintval) 2318 beaconintval = bs->bs_sleepduration; 2319 2320 dtimperiod = bs->bs_dtimperiod; 2321 if (bs->bs_sleepduration > dtimperiod) 2322 dtimperiod = bs->bs_sleepduration; 2323 2324 if (beaconintval == dtimperiod) 2325 nextTbtt = bs->bs_nextdtim; 2326 else 2327 nextTbtt = bs->bs_nexttbtt; 2328 2329 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2330 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2331 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2332 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2333 2334 ENABLE_REGWRITE_BUFFER(ah); 2335 2336 REG_WRITE(ah, AR_NEXT_DTIM, 2337 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2338 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2339 2340 REG_WRITE(ah, AR_SLEEP1, 2341 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2342 | AR_SLEEP1_ASSUME_DTIM); 2343 2344 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2345 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2346 else 2347 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2348 2349 REG_WRITE(ah, AR_SLEEP2, 2350 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2351 2352 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2353 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2354 2355 REGWRITE_BUFFER_FLUSH(ah); 2356 2357 REG_SET_BIT(ah, AR_TIMER_MODE, 2358 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2359 AR_DTIM_TIMER_EN); 2360 2361 /* TSF Out of Range Threshold */ 2362 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2363 } 2364 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2365 2366 /*******************/ 2367 /* HW Capabilities */ 2368 /*******************/ 2369 2370 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2371 { 2372 eeprom_chainmask &= chip_chainmask; 2373 if (eeprom_chainmask) 2374 return eeprom_chainmask; 2375 else 2376 return chip_chainmask; 2377 } 2378 2379 /** 2380 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2381 * @ah: the atheros hardware data structure 2382 * 2383 * We enable DFS support upstream on chipsets which have passed a series 2384 * of tests. The testing requirements are going to be documented. Desired 2385 * test requirements are documented at: 2386 * 2387 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2388 * 2389 * Once a new chipset gets properly tested an individual commit can be used 2390 * to document the testing for DFS for that chipset. 2391 */ 2392 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2393 { 2394 2395 switch (ah->hw_version.macVersion) { 2396 /* for temporary testing DFS with 9280 */ 2397 case AR_SREV_VERSION_9280: 2398 /* AR9580 will likely be our first target to get testing on */ 2399 case AR_SREV_VERSION_9580: 2400 return true; 2401 default: 2402 return false; 2403 } 2404 } 2405 2406 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2407 { 2408 struct ath9k_hw_capabilities *pCap = &ah->caps; 2409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2410 struct ath_common *common = ath9k_hw_common(ah); 2411 unsigned int chip_chainmask; 2412 2413 u16 eeval; 2414 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2415 2416 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2417 regulatory->current_rd = eeval; 2418 2419 if (ah->opmode != NL80211_IFTYPE_AP && 2420 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2421 if (regulatory->current_rd == 0x64 || 2422 regulatory->current_rd == 0x65) 2423 regulatory->current_rd += 5; 2424 else if (regulatory->current_rd == 0x41) 2425 regulatory->current_rd = 0x43; 2426 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2427 regulatory->current_rd); 2428 } 2429 2430 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2431 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2432 ath_err(common, 2433 "no band has been marked as supported in EEPROM\n"); 2434 return -EINVAL; 2435 } 2436 2437 if (eeval & AR5416_OPFLAGS_11A) 2438 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2439 2440 if (eeval & AR5416_OPFLAGS_11G) 2441 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2442 2443 if (AR_SREV_9485(ah) || 2444 AR_SREV_9285(ah) || 2445 AR_SREV_9330(ah) || 2446 AR_SREV_9565(ah)) 2447 chip_chainmask = 1; 2448 else if (AR_SREV_9462(ah)) 2449 chip_chainmask = 3; 2450 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2451 chip_chainmask = 7; 2452 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2453 chip_chainmask = 3; 2454 else 2455 chip_chainmask = 7; 2456 2457 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2458 /* 2459 * For AR9271 we will temporarilly uses the rx chainmax as read from 2460 * the EEPROM. 2461 */ 2462 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2463 !(eeval & AR5416_OPFLAGS_11A) && 2464 !(AR_SREV_9271(ah))) 2465 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2466 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2467 else if (AR_SREV_9100(ah)) 2468 pCap->rx_chainmask = 0x7; 2469 else 2470 /* Use rx_chainmask from EEPROM. */ 2471 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2472 2473 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2474 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2475 ah->txchainmask = pCap->tx_chainmask; 2476 ah->rxchainmask = pCap->rx_chainmask; 2477 2478 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2479 2480 /* enable key search for every frame in an aggregate */ 2481 if (AR_SREV_9300_20_OR_LATER(ah)) 2482 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2483 2484 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2485 2486 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2487 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2488 else 2489 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2490 2491 if (AR_SREV_9271(ah)) 2492 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2493 else if (AR_DEVID_7010(ah)) 2494 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2495 else if (AR_SREV_9300_20_OR_LATER(ah)) 2496 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2497 else if (AR_SREV_9287_11_OR_LATER(ah)) 2498 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2499 else if (AR_SREV_9285_12_OR_LATER(ah)) 2500 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2501 else if (AR_SREV_9280_20_OR_LATER(ah)) 2502 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2503 else 2504 pCap->num_gpio_pins = AR_NUM_GPIO; 2505 2506 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2507 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2508 else 2509 pCap->rts_aggr_limit = (8 * 1024); 2510 2511 #ifdef CONFIG_ATH9K_RFKILL 2512 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2513 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2514 ah->rfkill_gpio = 2515 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2516 ah->rfkill_polarity = 2517 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2518 2519 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2520 } 2521 #endif 2522 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2523 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2524 else 2525 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2526 2527 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2528 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2529 else 2530 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2531 2532 if (AR_SREV_9300_20_OR_LATER(ah)) { 2533 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2534 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2535 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2536 2537 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2538 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2539 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2540 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2541 pCap->txs_len = sizeof(struct ar9003_txs); 2542 } else { 2543 pCap->tx_desc_len = sizeof(struct ath_desc); 2544 if (AR_SREV_9280_20(ah)) 2545 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2546 } 2547 2548 if (AR_SREV_9300_20_OR_LATER(ah)) 2549 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2550 2551 if (AR_SREV_9300_20_OR_LATER(ah)) 2552 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2553 2554 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2555 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2556 2557 if (AR_SREV_9285(ah)) { 2558 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2559 ant_div_ctl1 = 2560 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2561 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2562 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2563 ath_info(common, "Enable LNA combining\n"); 2564 } 2565 } 2566 } 2567 2568 if (AR_SREV_9300_20_OR_LATER(ah)) { 2569 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2570 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2571 } 2572 2573 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2575 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2576 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2577 ath_info(common, "Enable LNA combining\n"); 2578 } 2579 } 2580 2581 if (ath9k_hw_dfs_tested(ah)) 2582 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2583 2584 tx_chainmask = pCap->tx_chainmask; 2585 rx_chainmask = pCap->rx_chainmask; 2586 while (tx_chainmask || rx_chainmask) { 2587 if (tx_chainmask & BIT(0)) 2588 pCap->max_txchains++; 2589 if (rx_chainmask & BIT(0)) 2590 pCap->max_rxchains++; 2591 2592 tx_chainmask >>= 1; 2593 rx_chainmask >>= 1; 2594 } 2595 2596 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2597 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2598 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2599 2600 if (AR_SREV_9462_20_OR_LATER(ah)) 2601 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2602 } 2603 2604 if (AR_SREV_9462(ah)) 2605 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2606 2607 if (AR_SREV_9300_20_OR_LATER(ah) && 2608 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2609 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2610 2611 /* 2612 * Fast channel change across bands is available 2613 * only for AR9462 and AR9565. 2614 */ 2615 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2616 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH; 2617 2618 return 0; 2619 } 2620 2621 /****************************/ 2622 /* GPIO / RFKILL / Antennae */ 2623 /****************************/ 2624 2625 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2626 u32 gpio, u32 type) 2627 { 2628 int addr; 2629 u32 gpio_shift, tmp; 2630 2631 if (gpio > 11) 2632 addr = AR_GPIO_OUTPUT_MUX3; 2633 else if (gpio > 5) 2634 addr = AR_GPIO_OUTPUT_MUX2; 2635 else 2636 addr = AR_GPIO_OUTPUT_MUX1; 2637 2638 gpio_shift = (gpio % 6) * 5; 2639 2640 if (AR_SREV_9280_20_OR_LATER(ah) 2641 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2642 REG_RMW(ah, addr, (type << gpio_shift), 2643 (0x1f << gpio_shift)); 2644 } else { 2645 tmp = REG_READ(ah, addr); 2646 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2647 tmp &= ~(0x1f << gpio_shift); 2648 tmp |= (type << gpio_shift); 2649 REG_WRITE(ah, addr, tmp); 2650 } 2651 } 2652 2653 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2654 { 2655 u32 gpio_shift; 2656 2657 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2658 2659 if (AR_DEVID_7010(ah)) { 2660 gpio_shift = gpio; 2661 REG_RMW(ah, AR7010_GPIO_OE, 2662 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2663 (AR7010_GPIO_OE_MASK << gpio_shift)); 2664 return; 2665 } 2666 2667 gpio_shift = gpio << 1; 2668 REG_RMW(ah, 2669 AR_GPIO_OE_OUT, 2670 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2671 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2672 } 2673 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2674 2675 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2676 { 2677 #define MS_REG_READ(x, y) \ 2678 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2679 2680 if (gpio >= ah->caps.num_gpio_pins) 2681 return 0xffffffff; 2682 2683 if (AR_DEVID_7010(ah)) { 2684 u32 val; 2685 val = REG_READ(ah, AR7010_GPIO_IN); 2686 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2687 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2688 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2689 AR_GPIO_BIT(gpio)) != 0; 2690 else if (AR_SREV_9271(ah)) 2691 return MS_REG_READ(AR9271, gpio) != 0; 2692 else if (AR_SREV_9287_11_OR_LATER(ah)) 2693 return MS_REG_READ(AR9287, gpio) != 0; 2694 else if (AR_SREV_9285_12_OR_LATER(ah)) 2695 return MS_REG_READ(AR9285, gpio) != 0; 2696 else if (AR_SREV_9280_20_OR_LATER(ah)) 2697 return MS_REG_READ(AR928X, gpio) != 0; 2698 else 2699 return MS_REG_READ(AR, gpio) != 0; 2700 } 2701 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2702 2703 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2704 u32 ah_signal_type) 2705 { 2706 u32 gpio_shift; 2707 2708 if (AR_DEVID_7010(ah)) { 2709 gpio_shift = gpio; 2710 REG_RMW(ah, AR7010_GPIO_OE, 2711 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2712 (AR7010_GPIO_OE_MASK << gpio_shift)); 2713 return; 2714 } 2715 2716 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2717 gpio_shift = 2 * gpio; 2718 REG_RMW(ah, 2719 AR_GPIO_OE_OUT, 2720 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2721 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2722 } 2723 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2724 2725 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2726 { 2727 if (AR_DEVID_7010(ah)) { 2728 val = val ? 0 : 1; 2729 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2730 AR_GPIO_BIT(gpio)); 2731 return; 2732 } 2733 2734 if (AR_SREV_9271(ah)) 2735 val = ~val; 2736 2737 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2738 AR_GPIO_BIT(gpio)); 2739 } 2740 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2741 2742 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2743 { 2744 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2745 } 2746 EXPORT_SYMBOL(ath9k_hw_setantenna); 2747 2748 /*********************/ 2749 /* General Operation */ 2750 /*********************/ 2751 2752 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2753 { 2754 u32 bits = REG_READ(ah, AR_RX_FILTER); 2755 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2756 2757 if (phybits & AR_PHY_ERR_RADAR) 2758 bits |= ATH9K_RX_FILTER_PHYRADAR; 2759 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2760 bits |= ATH9K_RX_FILTER_PHYERR; 2761 2762 return bits; 2763 } 2764 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2765 2766 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2767 { 2768 u32 phybits; 2769 2770 ENABLE_REGWRITE_BUFFER(ah); 2771 2772 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2773 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2774 2775 REG_WRITE(ah, AR_RX_FILTER, bits); 2776 2777 phybits = 0; 2778 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2779 phybits |= AR_PHY_ERR_RADAR; 2780 if (bits & ATH9K_RX_FILTER_PHYERR) 2781 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2782 REG_WRITE(ah, AR_PHY_ERR, phybits); 2783 2784 if (phybits) 2785 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2786 else 2787 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2788 2789 REGWRITE_BUFFER_FLUSH(ah); 2790 } 2791 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2792 2793 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2794 { 2795 if (ath9k_hw_mci_is_enabled(ah)) 2796 ar9003_mci_bt_gain_ctrl(ah); 2797 2798 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2799 return false; 2800 2801 ath9k_hw_init_pll(ah, NULL); 2802 ah->htc_reset_init = true; 2803 return true; 2804 } 2805 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2806 2807 bool ath9k_hw_disable(struct ath_hw *ah) 2808 { 2809 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2810 return false; 2811 2812 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2813 return false; 2814 2815 ath9k_hw_init_pll(ah, NULL); 2816 return true; 2817 } 2818 EXPORT_SYMBOL(ath9k_hw_disable); 2819 2820 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2821 { 2822 enum eeprom_param gain_param; 2823 2824 if (IS_CHAN_2GHZ(chan)) 2825 gain_param = EEP_ANTENNA_GAIN_2G; 2826 else 2827 gain_param = EEP_ANTENNA_GAIN_5G; 2828 2829 return ah->eep_ops->get_eeprom(ah, gain_param); 2830 } 2831 2832 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2833 bool test) 2834 { 2835 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2836 struct ieee80211_channel *channel; 2837 int chan_pwr, new_pwr, max_gain; 2838 int ant_gain, ant_reduction = 0; 2839 2840 if (!chan) 2841 return; 2842 2843 channel = chan->chan; 2844 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2845 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2846 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2847 2848 ant_gain = get_antenna_gain(ah, chan); 2849 if (ant_gain > max_gain) 2850 ant_reduction = ant_gain - max_gain; 2851 2852 ah->eep_ops->set_txpower(ah, chan, 2853 ath9k_regd_get_ctl(reg, chan), 2854 ant_reduction, new_pwr, test); 2855 } 2856 2857 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2858 { 2859 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2860 struct ath9k_channel *chan = ah->curchan; 2861 struct ieee80211_channel *channel = chan->chan; 2862 2863 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2864 if (test) 2865 channel->max_power = MAX_RATE_POWER / 2; 2866 2867 ath9k_hw_apply_txpower(ah, chan, test); 2868 2869 if (test) 2870 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2871 } 2872 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2873 2874 void ath9k_hw_setopmode(struct ath_hw *ah) 2875 { 2876 ath9k_hw_set_operating_mode(ah, ah->opmode); 2877 } 2878 EXPORT_SYMBOL(ath9k_hw_setopmode); 2879 2880 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2881 { 2882 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2883 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2884 } 2885 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2886 2887 void ath9k_hw_write_associd(struct ath_hw *ah) 2888 { 2889 struct ath_common *common = ath9k_hw_common(ah); 2890 2891 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2892 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2893 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2894 } 2895 EXPORT_SYMBOL(ath9k_hw_write_associd); 2896 2897 #define ATH9K_MAX_TSF_READ 10 2898 2899 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2900 { 2901 u32 tsf_lower, tsf_upper1, tsf_upper2; 2902 int i; 2903 2904 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2905 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2906 tsf_lower = REG_READ(ah, AR_TSF_L32); 2907 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2908 if (tsf_upper2 == tsf_upper1) 2909 break; 2910 tsf_upper1 = tsf_upper2; 2911 } 2912 2913 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2914 2915 return (((u64)tsf_upper1 << 32) | tsf_lower); 2916 } 2917 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2918 2919 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2920 { 2921 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2922 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2923 } 2924 EXPORT_SYMBOL(ath9k_hw_settsf64); 2925 2926 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2927 { 2928 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2929 AH_TSF_WRITE_TIMEOUT)) 2930 ath_dbg(ath9k_hw_common(ah), RESET, 2931 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2932 2933 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2934 } 2935 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2936 2937 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2938 { 2939 if (set) 2940 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2941 else 2942 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2943 } 2944 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2945 2946 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2947 { 2948 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2949 u32 macmode; 2950 2951 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2952 macmode = AR_2040_JOINED_RX_CLEAR; 2953 else 2954 macmode = 0; 2955 2956 REG_WRITE(ah, AR_2040_MODE, macmode); 2957 } 2958 2959 /* HW Generic timers configuration */ 2960 2961 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2962 { 2963 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2964 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2965 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2970 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2971 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2972 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2973 AR_NDP2_TIMER_MODE, 0x0002}, 2974 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2975 AR_NDP2_TIMER_MODE, 0x0004}, 2976 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2977 AR_NDP2_TIMER_MODE, 0x0008}, 2978 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2979 AR_NDP2_TIMER_MODE, 0x0010}, 2980 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2981 AR_NDP2_TIMER_MODE, 0x0020}, 2982 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2983 AR_NDP2_TIMER_MODE, 0x0040}, 2984 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2985 AR_NDP2_TIMER_MODE, 0x0080} 2986 }; 2987 2988 /* HW generic timer primitives */ 2989 2990 /* compute and clear index of rightmost 1 */ 2991 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2992 { 2993 u32 b; 2994 2995 b = *mask; 2996 b &= (0-b); 2997 *mask &= ~b; 2998 b *= debruijn32; 2999 b >>= 27; 3000 3001 return timer_table->gen_timer_index[b]; 3002 } 3003 3004 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3005 { 3006 return REG_READ(ah, AR_TSF_L32); 3007 } 3008 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3009 3010 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3011 void (*trigger)(void *), 3012 void (*overflow)(void *), 3013 void *arg, 3014 u8 timer_index) 3015 { 3016 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3017 struct ath_gen_timer *timer; 3018 3019 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3020 if (timer == NULL) 3021 return NULL; 3022 3023 /* allocate a hardware generic timer slot */ 3024 timer_table->timers[timer_index] = timer; 3025 timer->index = timer_index; 3026 timer->trigger = trigger; 3027 timer->overflow = overflow; 3028 timer->arg = arg; 3029 3030 return timer; 3031 } 3032 EXPORT_SYMBOL(ath_gen_timer_alloc); 3033 3034 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3035 struct ath_gen_timer *timer, 3036 u32 trig_timeout, 3037 u32 timer_period) 3038 { 3039 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3040 u32 tsf, timer_next; 3041 3042 BUG_ON(!timer_period); 3043 3044 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3045 3046 tsf = ath9k_hw_gettsf32(ah); 3047 3048 timer_next = tsf + trig_timeout; 3049 3050 ath_dbg(ath9k_hw_common(ah), BTCOEX, 3051 "current tsf %x period %x timer_next %x\n", 3052 tsf, timer_period, timer_next); 3053 3054 /* 3055 * Program generic timer registers 3056 */ 3057 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3058 timer_next); 3059 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3060 timer_period); 3061 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3062 gen_tmr_configuration[timer->index].mode_mask); 3063 3064 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3065 /* 3066 * Starting from AR9462, each generic timer can select which tsf 3067 * to use. But we still follow the old rule, 0 - 7 use tsf and 3068 * 8 - 15 use tsf2. 3069 */ 3070 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3071 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3072 (1 << timer->index)); 3073 else 3074 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3075 (1 << timer->index)); 3076 } 3077 3078 /* Enable both trigger and thresh interrupt masks */ 3079 REG_SET_BIT(ah, AR_IMR_S5, 3080 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3081 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3082 } 3083 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3084 3085 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3086 { 3087 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3088 3089 if ((timer->index < AR_FIRST_NDP_TIMER) || 3090 (timer->index >= ATH_MAX_GEN_TIMER)) { 3091 return; 3092 } 3093 3094 /* Clear generic timer enable bits. */ 3095 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3096 gen_tmr_configuration[timer->index].mode_mask); 3097 3098 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3099 /* 3100 * Need to switch back to TSF if it was using TSF2. 3101 */ 3102 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3103 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3104 (1 << timer->index)); 3105 } 3106 } 3107 3108 /* Disable both trigger and thresh interrupt masks */ 3109 REG_CLR_BIT(ah, AR_IMR_S5, 3110 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3111 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3112 3113 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3114 } 3115 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3116 3117 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3118 { 3119 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3120 3121 /* free the hardware generic timer slot */ 3122 timer_table->timers[timer->index] = NULL; 3123 kfree(timer); 3124 } 3125 EXPORT_SYMBOL(ath_gen_timer_free); 3126 3127 /* 3128 * Generic Timer Interrupts handling 3129 */ 3130 void ath_gen_timer_isr(struct ath_hw *ah) 3131 { 3132 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3133 struct ath_gen_timer *timer; 3134 struct ath_common *common = ath9k_hw_common(ah); 3135 u32 trigger_mask, thresh_mask, index; 3136 3137 /* get hardware generic timer interrupt status */ 3138 trigger_mask = ah->intr_gen_timer_trigger; 3139 thresh_mask = ah->intr_gen_timer_thresh; 3140 trigger_mask &= timer_table->timer_mask.val; 3141 thresh_mask &= timer_table->timer_mask.val; 3142 3143 trigger_mask &= ~thresh_mask; 3144 3145 while (thresh_mask) { 3146 index = rightmost_index(timer_table, &thresh_mask); 3147 timer = timer_table->timers[index]; 3148 BUG_ON(!timer); 3149 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n", 3150 index); 3151 timer->overflow(timer->arg); 3152 } 3153 3154 while (trigger_mask) { 3155 index = rightmost_index(timer_table, &trigger_mask); 3156 timer = timer_table->timers[index]; 3157 BUG_ON(!timer); 3158 ath_dbg(common, BTCOEX, 3159 "Gen timer[%d] trigger\n", index); 3160 timer->trigger(timer->arg); 3161 } 3162 } 3163 EXPORT_SYMBOL(ath_gen_timer_isr); 3164 3165 /********/ 3166 /* HTC */ 3167 /********/ 3168 3169 static struct { 3170 u32 version; 3171 const char * name; 3172 } ath_mac_bb_names[] = { 3173 /* Devices with external radios */ 3174 { AR_SREV_VERSION_5416_PCI, "5416" }, 3175 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3176 { AR_SREV_VERSION_9100, "9100" }, 3177 { AR_SREV_VERSION_9160, "9160" }, 3178 /* Single-chip solutions */ 3179 { AR_SREV_VERSION_9280, "9280" }, 3180 { AR_SREV_VERSION_9285, "9285" }, 3181 { AR_SREV_VERSION_9287, "9287" }, 3182 { AR_SREV_VERSION_9271, "9271" }, 3183 { AR_SREV_VERSION_9300, "9300" }, 3184 { AR_SREV_VERSION_9330, "9330" }, 3185 { AR_SREV_VERSION_9340, "9340" }, 3186 { AR_SREV_VERSION_9485, "9485" }, 3187 { AR_SREV_VERSION_9462, "9462" }, 3188 { AR_SREV_VERSION_9550, "9550" }, 3189 { AR_SREV_VERSION_9565, "9565" }, 3190 }; 3191 3192 /* For devices with external radios */ 3193 static struct { 3194 u16 version; 3195 const char * name; 3196 } ath_rf_names[] = { 3197 { 0, "5133" }, 3198 { AR_RAD5133_SREV_MAJOR, "5133" }, 3199 { AR_RAD5122_SREV_MAJOR, "5122" }, 3200 { AR_RAD2133_SREV_MAJOR, "2133" }, 3201 { AR_RAD2122_SREV_MAJOR, "2122" } 3202 }; 3203 3204 /* 3205 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3206 */ 3207 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3208 { 3209 int i; 3210 3211 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3212 if (ath_mac_bb_names[i].version == mac_bb_version) { 3213 return ath_mac_bb_names[i].name; 3214 } 3215 } 3216 3217 return "????"; 3218 } 3219 3220 /* 3221 * Return the RF name. "????" is returned if the RF is unknown. 3222 * Used for devices with external radios. 3223 */ 3224 static const char *ath9k_hw_rf_name(u16 rf_version) 3225 { 3226 int i; 3227 3228 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3229 if (ath_rf_names[i].version == rf_version) { 3230 return ath_rf_names[i].name; 3231 } 3232 } 3233 3234 return "????"; 3235 } 3236 3237 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3238 { 3239 int used; 3240 3241 /* chipsets >= AR9280 are single-chip */ 3242 if (AR_SREV_9280_20_OR_LATER(ah)) { 3243 used = snprintf(hw_name, len, 3244 "Atheros AR%s Rev:%x", 3245 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3246 ah->hw_version.macRev); 3247 } 3248 else { 3249 used = snprintf(hw_name, len, 3250 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3251 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3252 ah->hw_version.macRev, 3253 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3254 AR_RADIO_SREV_MAJOR)), 3255 ah->hw_version.phyRev); 3256 } 3257 3258 hw_name[used] = '\0'; 3259 } 3260 EXPORT_SYMBOL(ath9k_hw_name); 3261