1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_HW_OPS_H 18 #define ATH9K_HW_OPS_H 19 20 #include "hw.h" 21 22 /* Hardware core and driver accessible callbacks */ 23 24 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah, 25 int restore, 26 int power_off) 27 { 28 ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off); 29 } 30 31 static inline void ath9k_hw_rxena(struct ath_hw *ah) 32 { 33 ath9k_hw_ops(ah)->rx_enable(ah); 34 } 35 36 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds, 37 u32 link) 38 { 39 ath9k_hw_ops(ah)->set_desc_link(ds, link); 40 } 41 42 static inline bool ath9k_hw_calibrate(struct ath_hw *ah, 43 struct ath9k_channel *chan, 44 u8 rxchainmask, 45 bool longcal) 46 { 47 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal); 48 } 49 50 static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 51 { 52 return ath9k_hw_ops(ah)->get_isr(ah, masked); 53 } 54 55 static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen, 56 bool is_firstseg, bool is_lastseg, 57 const void *ds0, dma_addr_t buf_addr, 58 unsigned int qcu) 59 { 60 ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg, 61 ds0, buf_addr, qcu); 62 } 63 64 static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds, 65 struct ath_tx_status *ts) 66 { 67 return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts); 68 } 69 70 static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds, 71 u32 pktLen, enum ath9k_pkt_type type, 72 u32 txPower, u32 keyIx, 73 enum ath9k_key_type keyType, 74 u32 flags) 75 { 76 ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx, 77 keyType, flags); 78 } 79 80 static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, 81 void *lastds, 82 u32 durUpdateEn, u32 rtsctsRate, 83 u32 rtsctsDuration, 84 struct ath9k_11n_rate_series series[], 85 u32 nseries, u32 flags) 86 { 87 ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn, 88 rtsctsRate, rtsctsDuration, series, 89 nseries, flags); 90 } 91 92 static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 93 u32 aggrLen) 94 { 95 ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen); 96 } 97 98 static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 99 u32 numDelims) 100 { 101 ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims); 102 } 103 104 static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) 105 { 106 ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds); 107 } 108 109 static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds) 110 { 111 ath9k_hw_ops(ah)->clr11n_aggr(ah, ds); 112 } 113 114 static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) 115 { 116 ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val); 117 } 118 119 static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah, 120 struct ath_hw_antcomb_conf *antconf) 121 { 122 ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf); 123 } 124 125 static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah, 126 struct ath_hw_antcomb_conf *antconf) 127 { 128 ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf); 129 } 130 131 /* Private hardware call ops */ 132 133 /* PHY ops */ 134 135 static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah, 136 struct ath9k_channel *chan) 137 { 138 return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan); 139 } 140 141 static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah, 142 struct ath9k_channel *chan) 143 { 144 ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan); 145 } 146 147 static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah) 148 { 149 if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks) 150 return 0; 151 152 return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah); 153 } 154 155 static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah) 156 { 157 if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks) 158 return; 159 160 ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah); 161 } 162 163 static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 164 struct ath9k_channel *chan, 165 u16 modesIndex) 166 { 167 if (!ath9k_hw_private_ops(ah)->set_rf_regs) 168 return true; 169 170 return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex); 171 } 172 173 static inline void ath9k_hw_init_bb(struct ath_hw *ah, 174 struct ath9k_channel *chan) 175 { 176 return ath9k_hw_private_ops(ah)->init_bb(ah, chan); 177 } 178 179 static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah, 180 struct ath9k_channel *chan) 181 { 182 return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan); 183 } 184 185 static inline int ath9k_hw_process_ini(struct ath_hw *ah, 186 struct ath9k_channel *chan) 187 { 188 return ath9k_hw_private_ops(ah)->process_ini(ah, chan); 189 } 190 191 static inline void ath9k_olc_init(struct ath_hw *ah) 192 { 193 if (!ath9k_hw_private_ops(ah)->olc_init) 194 return; 195 196 return ath9k_hw_private_ops(ah)->olc_init(ah); 197 } 198 199 static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, 200 struct ath9k_channel *chan) 201 { 202 return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan); 203 } 204 205 static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) 206 { 207 return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah); 208 } 209 210 static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah, 211 struct ath9k_channel *chan) 212 { 213 return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan); 214 } 215 216 static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah) 217 { 218 return ath9k_hw_private_ops(ah)->rfbus_req(ah); 219 } 220 221 static inline void ath9k_hw_rfbus_done(struct ath_hw *ah) 222 { 223 return ath9k_hw_private_ops(ah)->rfbus_done(ah); 224 } 225 226 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah) 227 { 228 if (!ath9k_hw_private_ops(ah)->restore_chainmask) 229 return; 230 231 return ath9k_hw_private_ops(ah)->restore_chainmask(ah); 232 } 233 234 static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value) 235 { 236 return ath9k_hw_private_ops(ah)->set_diversity(ah, value); 237 } 238 239 static inline bool ath9k_hw_ani_control(struct ath_hw *ah, 240 enum ath9k_ani_cmd cmd, int param) 241 { 242 return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param); 243 } 244 245 static inline void ath9k_hw_do_getnf(struct ath_hw *ah, 246 int16_t nfarray[NUM_NF_READINGS]) 247 { 248 ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray); 249 } 250 251 static inline bool ath9k_hw_init_cal(struct ath_hw *ah, 252 struct ath9k_channel *chan) 253 { 254 return ath9k_hw_private_ops(ah)->init_cal(ah, chan); 255 } 256 257 static inline void ath9k_hw_setup_calibration(struct ath_hw *ah, 258 struct ath9k_cal_list *currCal) 259 { 260 ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal); 261 } 262 263 #endif /* ATH9K_HW_OPS_H */ 264