1 /* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "htc.h" 18 19 MODULE_AUTHOR("Atheros Communications"); 20 MODULE_LICENSE("Dual BSD/GPL"); 21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); 22 23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 24 module_param_named(debug, ath9k_debug, uint, 0); 25 MODULE_PARM_DESC(debug, "Debugging mask"); 26 27 int htc_modparam_nohwcrypt; 28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30 31 #define CHAN2G(_freq, _idx) { \ 32 .center_freq = (_freq), \ 33 .hw_value = (_idx), \ 34 .max_power = 20, \ 35 } 36 37 #define CHAN5G(_freq, _idx) { \ 38 .band = IEEE80211_BAND_5GHZ, \ 39 .center_freq = (_freq), \ 40 .hw_value = (_idx), \ 41 .max_power = 20, \ 42 } 43 44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193" 45 46 static struct ieee80211_channel ath9k_2ghz_channels[] = { 47 CHAN2G(2412, 0), /* Channel 1 */ 48 CHAN2G(2417, 1), /* Channel 2 */ 49 CHAN2G(2422, 2), /* Channel 3 */ 50 CHAN2G(2427, 3), /* Channel 4 */ 51 CHAN2G(2432, 4), /* Channel 5 */ 52 CHAN2G(2437, 5), /* Channel 6 */ 53 CHAN2G(2442, 6), /* Channel 7 */ 54 CHAN2G(2447, 7), /* Channel 8 */ 55 CHAN2G(2452, 8), /* Channel 9 */ 56 CHAN2G(2457, 9), /* Channel 10 */ 57 CHAN2G(2462, 10), /* Channel 11 */ 58 CHAN2G(2467, 11), /* Channel 12 */ 59 CHAN2G(2472, 12), /* Channel 13 */ 60 CHAN2G(2484, 13), /* Channel 14 */ 61 }; 62 63 static struct ieee80211_channel ath9k_5ghz_channels[] = { 64 /* _We_ call this UNII 1 */ 65 CHAN5G(5180, 14), /* Channel 36 */ 66 CHAN5G(5200, 15), /* Channel 40 */ 67 CHAN5G(5220, 16), /* Channel 44 */ 68 CHAN5G(5240, 17), /* Channel 48 */ 69 /* _We_ call this UNII 2 */ 70 CHAN5G(5260, 18), /* Channel 52 */ 71 CHAN5G(5280, 19), /* Channel 56 */ 72 CHAN5G(5300, 20), /* Channel 60 */ 73 CHAN5G(5320, 21), /* Channel 64 */ 74 /* _We_ call this "Middle band" */ 75 CHAN5G(5500, 22), /* Channel 100 */ 76 CHAN5G(5520, 23), /* Channel 104 */ 77 CHAN5G(5540, 24), /* Channel 108 */ 78 CHAN5G(5560, 25), /* Channel 112 */ 79 CHAN5G(5580, 26), /* Channel 116 */ 80 CHAN5G(5600, 27), /* Channel 120 */ 81 CHAN5G(5620, 28), /* Channel 124 */ 82 CHAN5G(5640, 29), /* Channel 128 */ 83 CHAN5G(5660, 30), /* Channel 132 */ 84 CHAN5G(5680, 31), /* Channel 136 */ 85 CHAN5G(5700, 32), /* Channel 140 */ 86 /* _We_ call this UNII 3 */ 87 CHAN5G(5745, 33), /* Channel 149 */ 88 CHAN5G(5765, 34), /* Channel 153 */ 89 CHAN5G(5785, 35), /* Channel 157 */ 90 CHAN5G(5805, 36), /* Channel 161 */ 91 CHAN5G(5825, 37), /* Channel 165 */ 92 }; 93 94 /* Atheros hardware rate code addition for short premble */ 95 #define SHPCHECK(__hw_rate, __flags) \ 96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) 97 98 #define RATE(_bitrate, _hw_rate, _flags) { \ 99 .bitrate = (_bitrate), \ 100 .flags = (_flags), \ 101 .hw_value = (_hw_rate), \ 102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 103 } 104 105 static struct ieee80211_rate ath9k_legacy_rates[] = { 106 RATE(10, 0x1b, 0), 107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ 108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ 109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ 110 RATE(60, 0x0b, 0), 111 RATE(90, 0x0f, 0), 112 RATE(120, 0x0a, 0), 113 RATE(180, 0x0e, 0), 114 RATE(240, 0x09, 0), 115 RATE(360, 0x0d, 0), 116 RATE(480, 0x08, 0), 117 RATE(540, 0x0c, 0), 118 }; 119 120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) 121 { 122 int time_left; 123 124 if (atomic_read(&priv->htc->tgt_ready) > 0) { 125 atomic_dec(&priv->htc->tgt_ready); 126 return 0; 127 } 128 129 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ 130 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); 131 if (!time_left) { 132 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); 133 return -ETIMEDOUT; 134 } 135 136 atomic_dec(&priv->htc->tgt_ready); 137 138 return 0; 139 } 140 141 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) 142 { 143 ath9k_htc_exit_debug(priv->ah); 144 ath9k_hw_deinit(priv->ah); 145 kfree(priv->ah); 146 priv->ah = NULL; 147 } 148 149 static void ath9k_deinit_device(struct ath9k_htc_priv *priv) 150 { 151 struct ieee80211_hw *hw = priv->hw; 152 153 wiphy_rfkill_stop_polling(hw->wiphy); 154 ath9k_deinit_leds(priv); 155 ieee80211_unregister_hw(hw); 156 ath9k_rx_cleanup(priv); 157 ath9k_tx_cleanup(priv); 158 ath9k_deinit_priv(priv); 159 } 160 161 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, 162 u16 service_id, 163 void (*tx) (void *, 164 struct sk_buff *, 165 enum htc_endpoint_id, 166 bool txok), 167 enum htc_endpoint_id *ep_id) 168 { 169 struct htc_service_connreq req; 170 171 memset(&req, 0, sizeof(struct htc_service_connreq)); 172 173 req.service_id = service_id; 174 req.ep_callbacks.priv = priv; 175 req.ep_callbacks.rx = ath9k_htc_rxep; 176 req.ep_callbacks.tx = tx; 177 178 return htc_connect_service(priv->htc, &req, ep_id); 179 } 180 181 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid, 182 u32 drv_info) 183 { 184 int ret; 185 186 /* WMI CMD*/ 187 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); 188 if (ret) 189 goto err; 190 191 /* Beacon */ 192 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep, 193 &priv->beacon_ep); 194 if (ret) 195 goto err; 196 197 /* CAB */ 198 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, 199 &priv->cab_ep); 200 if (ret) 201 goto err; 202 203 204 /* UAPSD */ 205 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, 206 &priv->uapsd_ep); 207 if (ret) 208 goto err; 209 210 /* MGMT */ 211 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, 212 &priv->mgmt_ep); 213 if (ret) 214 goto err; 215 216 /* DATA BE */ 217 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, 218 &priv->data_be_ep); 219 if (ret) 220 goto err; 221 222 /* DATA BK */ 223 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, 224 &priv->data_bk_ep); 225 if (ret) 226 goto err; 227 228 /* DATA VI */ 229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, 230 &priv->data_vi_ep); 231 if (ret) 232 goto err; 233 234 /* DATA VO */ 235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, 236 &priv->data_vo_ep); 237 if (ret) 238 goto err; 239 240 /* 241 * Setup required credits before initializing HTC. 242 * This is a bit hacky, but, since queuing is done in 243 * the HIF layer, shouldn't matter much. 244 */ 245 246 if (IS_AR7010_DEVICE(drv_info)) 247 priv->htc->credits = 45; 248 else 249 priv->htc->credits = 33; 250 251 ret = htc_init(priv->htc); 252 if (ret) 253 goto err; 254 255 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n", 256 priv->htc->credits); 257 258 return 0; 259 260 err: 261 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); 262 return ret; 263 } 264 265 static int ath9k_reg_notifier(struct wiphy *wiphy, 266 struct regulatory_request *request) 267 { 268 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 269 struct ath9k_htc_priv *priv = hw->priv; 270 271 return ath_reg_notifier_apply(wiphy, request, 272 ath9k_hw_regulatory(priv->ah)); 273 } 274 275 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) 276 { 277 struct ath_hw *ah = (struct ath_hw *) hw_priv; 278 struct ath_common *common = ath9k_hw_common(ah); 279 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 280 __be32 val, reg = cpu_to_be32(reg_offset); 281 int r; 282 283 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 284 (u8 *) ®, sizeof(reg), 285 (u8 *) &val, sizeof(val), 286 100); 287 if (unlikely(r)) { 288 ath_dbg(common, ATH_DBG_WMI, 289 "REGISTER READ FAILED: (0x%04x, %d)\n", 290 reg_offset, r); 291 return -EIO; 292 } 293 294 return be32_to_cpu(val); 295 } 296 297 static void ath9k_multi_regread(void *hw_priv, u32 *addr, 298 u32 *val, u16 count) 299 { 300 struct ath_hw *ah = (struct ath_hw *) hw_priv; 301 struct ath_common *common = ath9k_hw_common(ah); 302 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 303 __be32 tmpaddr[8]; 304 __be32 tmpval[8]; 305 int i, ret; 306 307 for (i = 0; i < count; i++) { 308 tmpaddr[i] = cpu_to_be32(addr[i]); 309 } 310 311 ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 312 (u8 *)tmpaddr , sizeof(u32) * count, 313 (u8 *)tmpval, sizeof(u32) * count, 314 100); 315 if (unlikely(ret)) { 316 ath_dbg(common, ATH_DBG_WMI, 317 "Multiple REGISTER READ FAILED (count: %d)\n", count); 318 } 319 320 for (i = 0; i < count; i++) { 321 val[i] = be32_to_cpu(tmpval[i]); 322 } 323 } 324 325 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) 326 { 327 struct ath_hw *ah = (struct ath_hw *) hw_priv; 328 struct ath_common *common = ath9k_hw_common(ah); 329 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 330 const __be32 buf[2] = { 331 cpu_to_be32(reg_offset), 332 cpu_to_be32(val), 333 }; 334 int r; 335 336 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 337 (u8 *) &buf, sizeof(buf), 338 (u8 *) &val, sizeof(val), 339 100); 340 if (unlikely(r)) { 341 ath_dbg(common, ATH_DBG_WMI, 342 "REGISTER WRITE FAILED:(0x%04x, %d)\n", 343 reg_offset, r); 344 } 345 } 346 347 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) 348 { 349 struct ath_hw *ah = (struct ath_hw *) hw_priv; 350 struct ath_common *common = ath9k_hw_common(ah); 351 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 352 u32 rsp_status; 353 int r; 354 355 mutex_lock(&priv->wmi->multi_write_mutex); 356 357 /* Store the register/value */ 358 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = 359 cpu_to_be32(reg_offset); 360 priv->wmi->multi_write[priv->wmi->multi_write_idx].val = 361 cpu_to_be32(val); 362 363 priv->wmi->multi_write_idx++; 364 365 /* If the buffer is full, send it out. */ 366 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) { 367 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 368 (u8 *) &priv->wmi->multi_write, 369 sizeof(struct register_write) * priv->wmi->multi_write_idx, 370 (u8 *) &rsp_status, sizeof(rsp_status), 371 100); 372 if (unlikely(r)) { 373 ath_dbg(common, ATH_DBG_WMI, 374 "REGISTER WRITE FAILED, multi len: %d\n", 375 priv->wmi->multi_write_idx); 376 } 377 priv->wmi->multi_write_idx = 0; 378 } 379 380 mutex_unlock(&priv->wmi->multi_write_mutex); 381 } 382 383 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) 384 { 385 struct ath_hw *ah = (struct ath_hw *) hw_priv; 386 struct ath_common *common = ath9k_hw_common(ah); 387 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 388 389 if (atomic_read(&priv->wmi->mwrite_cnt)) 390 ath9k_regwrite_buffer(hw_priv, val, reg_offset); 391 else 392 ath9k_regwrite_single(hw_priv, val, reg_offset); 393 } 394 395 static void ath9k_enable_regwrite_buffer(void *hw_priv) 396 { 397 struct ath_hw *ah = (struct ath_hw *) hw_priv; 398 struct ath_common *common = ath9k_hw_common(ah); 399 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 400 401 atomic_inc(&priv->wmi->mwrite_cnt); 402 } 403 404 static void ath9k_regwrite_flush(void *hw_priv) 405 { 406 struct ath_hw *ah = (struct ath_hw *) hw_priv; 407 struct ath_common *common = ath9k_hw_common(ah); 408 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 409 u32 rsp_status; 410 int r; 411 412 atomic_dec(&priv->wmi->mwrite_cnt); 413 414 mutex_lock(&priv->wmi->multi_write_mutex); 415 416 if (priv->wmi->multi_write_idx) { 417 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 418 (u8 *) &priv->wmi->multi_write, 419 sizeof(struct register_write) * priv->wmi->multi_write_idx, 420 (u8 *) &rsp_status, sizeof(rsp_status), 421 100); 422 if (unlikely(r)) { 423 ath_dbg(common, ATH_DBG_WMI, 424 "REGISTER WRITE FAILED, multi len: %d\n", 425 priv->wmi->multi_write_idx); 426 } 427 priv->wmi->multi_write_idx = 0; 428 } 429 430 mutex_unlock(&priv->wmi->multi_write_mutex); 431 } 432 433 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 434 { 435 u32 val; 436 437 val = ath9k_regread(hw_priv, reg_offset); 438 val &= ~clr; 439 val |= set; 440 ath9k_regwrite(hw_priv, val, reg_offset); 441 return val; 442 } 443 444 static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 445 { 446 *csz = L1_CACHE_BYTES >> 2; 447 } 448 449 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 450 { 451 struct ath_hw *ah = (struct ath_hw *) common->ah; 452 453 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 454 455 if (!ath9k_hw_wait(ah, 456 AR_EEPROM_STATUS_DATA, 457 AR_EEPROM_STATUS_DATA_BUSY | 458 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 459 AH_WAIT_TIMEOUT)) 460 return false; 461 462 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 463 AR_EEPROM_STATUS_DATA_VAL); 464 465 return true; 466 } 467 468 static const struct ath_bus_ops ath9k_usb_bus_ops = { 469 .ath_bus_type = ATH_USB, 470 .read_cachesize = ath_usb_read_cachesize, 471 .eeprom_read = ath_usb_eeprom_read, 472 }; 473 474 static void setup_ht_cap(struct ath9k_htc_priv *priv, 475 struct ieee80211_sta_ht_cap *ht_info) 476 { 477 struct ath_common *common = ath9k_hw_common(priv->ah); 478 u8 tx_streams, rx_streams; 479 int i; 480 481 ht_info->ht_supported = true; 482 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 483 IEEE80211_HT_CAP_SM_PS | 484 IEEE80211_HT_CAP_SGI_40 | 485 IEEE80211_HT_CAP_DSSSCCK40; 486 487 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 488 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 489 490 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 491 492 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 493 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 494 495 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 496 497 /* ath9k_htc supports only 1 or 2 stream devices */ 498 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); 499 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); 500 501 ath_dbg(common, ATH_DBG_CONFIG, 502 "TX streams %d, RX streams: %d\n", 503 tx_streams, rx_streams); 504 505 if (tx_streams != rx_streams) { 506 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 507 ht_info->mcs.tx_params |= ((tx_streams - 1) << 508 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 509 } 510 511 for (i = 0; i < rx_streams; i++) 512 ht_info->mcs.rx_mask[i] = 0xff; 513 514 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 515 } 516 517 static int ath9k_init_queues(struct ath9k_htc_priv *priv) 518 { 519 struct ath_common *common = ath9k_hw_common(priv->ah); 520 int i; 521 522 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) 523 priv->hwq_map[i] = -1; 524 525 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); 526 if (priv->beaconq == -1) { 527 ath_err(common, "Unable to setup BEACON xmit queue\n"); 528 goto err; 529 } 530 531 priv->cabq = ath9k_htc_cabq_setup(priv); 532 if (priv->cabq == -1) { 533 ath_err(common, "Unable to setup CAB xmit queue\n"); 534 goto err; 535 } 536 537 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { 538 ath_err(common, "Unable to setup xmit queue for BE traffic\n"); 539 goto err; 540 } 541 542 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { 543 ath_err(common, "Unable to setup xmit queue for BK traffic\n"); 544 goto err; 545 } 546 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { 547 ath_err(common, "Unable to setup xmit queue for VI traffic\n"); 548 goto err; 549 } 550 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { 551 ath_err(common, "Unable to setup xmit queue for VO traffic\n"); 552 goto err; 553 } 554 555 return 0; 556 557 err: 558 return -EINVAL; 559 } 560 561 static void ath9k_init_crypto(struct ath9k_htc_priv *priv) 562 { 563 struct ath_common *common = ath9k_hw_common(priv->ah); 564 int i = 0; 565 566 /* Get the hardware key cache size. */ 567 common->keymax = priv->ah->caps.keycache_size; 568 if (common->keymax > ATH_KEYMAX) { 569 ath_dbg(common, ATH_DBG_ANY, 570 "Warning, using only %u entries in %u key cache\n", 571 ATH_KEYMAX, common->keymax); 572 common->keymax = ATH_KEYMAX; 573 } 574 575 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) 576 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; 577 578 /* 579 * Reset the key cache since some parts do not 580 * reset the contents on initial power up. 581 */ 582 for (i = 0; i < common->keymax; i++) 583 ath_hw_keyreset(common, (u16) i); 584 } 585 586 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) 587 { 588 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 589 priv->sbands[IEEE80211_BAND_2GHZ].channels = 590 ath9k_2ghz_channels; 591 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 592 priv->sbands[IEEE80211_BAND_2GHZ].n_channels = 593 ARRAY_SIZE(ath9k_2ghz_channels); 594 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 595 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 596 ARRAY_SIZE(ath9k_legacy_rates); 597 } 598 599 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 600 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels; 601 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 602 priv->sbands[IEEE80211_BAND_5GHZ].n_channels = 603 ARRAY_SIZE(ath9k_5ghz_channels); 604 priv->sbands[IEEE80211_BAND_5GHZ].bitrates = 605 ath9k_legacy_rates + 4; 606 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 607 ARRAY_SIZE(ath9k_legacy_rates) - 4; 608 } 609 } 610 611 static void ath9k_init_misc(struct ath9k_htc_priv *priv) 612 { 613 struct ath_common *common = ath9k_hw_common(priv->ah); 614 615 common->tx_chainmask = priv->ah->caps.tx_chainmask; 616 common->rx_chainmask = priv->ah->caps.rx_chainmask; 617 618 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 619 620 priv->ah->opmode = NL80211_IFTYPE_STATION; 621 } 622 623 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv) 624 { 625 int qnum; 626 627 switch (priv->ah->btcoex_hw.scheme) { 628 case ATH_BTCOEX_CFG_NONE: 629 break; 630 case ATH_BTCOEX_CFG_3WIRE: 631 priv->ah->btcoex_hw.btactive_gpio = 7; 632 priv->ah->btcoex_hw.btpriority_gpio = 6; 633 priv->ah->btcoex_hw.wlanactive_gpio = 8; 634 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 635 ath9k_hw_btcoex_init_3wire(priv->ah); 636 ath_htc_init_btcoex_work(priv); 637 qnum = priv->hwq_map[WME_AC_BE]; 638 ath9k_hw_init_btcoex_hw(priv->ah, qnum); 639 break; 640 default: 641 WARN_ON(1); 642 break; 643 } 644 } 645 646 static int ath9k_init_priv(struct ath9k_htc_priv *priv, 647 u16 devid, char *product, 648 u32 drv_info) 649 { 650 struct ath_hw *ah = NULL; 651 struct ath_common *common; 652 int ret = 0, csz = 0; 653 654 priv->op_flags |= OP_INVALID; 655 656 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 657 if (!ah) 658 return -ENOMEM; 659 660 ah->hw_version.devid = devid; 661 ah->hw_version.subsysid = 0; /* FIXME */ 662 ah->hw_version.usbdev = drv_info; 663 ah->ah_flags |= AH_USE_EEPROM; 664 ah->reg_ops.read = ath9k_regread; 665 ah->reg_ops.multi_read = ath9k_multi_regread; 666 ah->reg_ops.write = ath9k_regwrite; 667 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer; 668 ah->reg_ops.write_flush = ath9k_regwrite_flush; 669 ah->reg_ops.rmw = ath9k_reg_rmw; 670 priv->ah = ah; 671 672 common = ath9k_hw_common(ah); 673 common->ops = &ah->reg_ops; 674 common->bus_ops = &ath9k_usb_bus_ops; 675 common->ah = ah; 676 common->hw = priv->hw; 677 common->priv = priv; 678 common->debug_mask = ath9k_debug; 679 680 spin_lock_init(&priv->wmi->wmi_lock); 681 spin_lock_init(&priv->beacon_lock); 682 spin_lock_init(&priv->tx_lock); 683 mutex_init(&priv->mutex); 684 mutex_init(&priv->htc_pm_lock); 685 tasklet_init(&priv->swba_tasklet, ath9k_swba_tasklet, 686 (unsigned long)priv); 687 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, 688 (unsigned long)priv); 689 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, 690 (unsigned long)priv); 691 INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work); 692 INIT_WORK(&priv->ps_work, ath9k_ps_work); 693 INIT_WORK(&priv->fatal_work, ath9k_fatal_work); 694 695 /* 696 * Cache line size is used to size and align various 697 * structures used to communicate with the hardware. 698 */ 699 ath_read_cachesize(common, &csz); 700 common->cachelsz = csz << 2; /* convert to bytes */ 701 702 ret = ath9k_hw_init(ah); 703 if (ret) { 704 ath_err(common, 705 "Unable to initialize hardware; initialization status: %d\n", 706 ret); 707 goto err_hw; 708 } 709 710 ret = ath9k_htc_init_debug(ah); 711 if (ret) { 712 ath_err(common, "Unable to create debugfs files\n"); 713 goto err_debug; 714 } 715 716 ret = ath9k_init_queues(priv); 717 if (ret) 718 goto err_queues; 719 720 ath9k_init_crypto(priv); 721 ath9k_init_channels_rates(priv); 722 ath9k_init_misc(priv); 723 724 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) { 725 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE; 726 ath9k_init_btcoex(priv); 727 } 728 729 return 0; 730 731 err_queues: 732 ath9k_htc_exit_debug(ah); 733 err_debug: 734 ath9k_hw_deinit(ah); 735 err_hw: 736 737 kfree(ah); 738 priv->ah = NULL; 739 740 return ret; 741 } 742 743 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, 744 struct ieee80211_hw *hw) 745 { 746 struct ath_common *common = ath9k_hw_common(priv->ah); 747 748 hw->flags = IEEE80211_HW_SIGNAL_DBM | 749 IEEE80211_HW_AMPDU_AGGREGATION | 750 IEEE80211_HW_SPECTRUM_MGMT | 751 IEEE80211_HW_HAS_RATE_CONTROL | 752 IEEE80211_HW_RX_INCLUDES_FCS | 753 IEEE80211_HW_SUPPORTS_PS | 754 IEEE80211_HW_PS_NULLFUNC_STACK; 755 756 hw->wiphy->interface_modes = 757 BIT(NL80211_IFTYPE_STATION) | 758 BIT(NL80211_IFTYPE_ADHOC); 759 760 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 761 762 hw->queues = 4; 763 hw->channel_change_time = 5000; 764 hw->max_listen_interval = 10; 765 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 766 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 767 768 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ 769 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + 770 sizeof(struct htc_frame_hdr) + 4; 771 772 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 773 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 774 &priv->sbands[IEEE80211_BAND_2GHZ]; 775 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 776 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 777 &priv->sbands[IEEE80211_BAND_5GHZ]; 778 779 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 780 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 781 setup_ht_cap(priv, 782 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); 783 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 784 setup_ht_cap(priv, 785 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap); 786 } 787 788 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 789 } 790 791 static int ath9k_init_device(struct ath9k_htc_priv *priv, 792 u16 devid, char *product, u32 drv_info) 793 { 794 struct ieee80211_hw *hw = priv->hw; 795 struct ath_common *common; 796 struct ath_hw *ah; 797 int error = 0; 798 struct ath_regulatory *reg; 799 char hw_name[64]; 800 801 /* Bring up device */ 802 error = ath9k_init_priv(priv, devid, product, drv_info); 803 if (error != 0) 804 goto err_init; 805 806 ah = priv->ah; 807 common = ath9k_hw_common(ah); 808 ath9k_set_hw_capab(priv, hw); 809 810 /* Initialize regulatory */ 811 error = ath_regd_init(&common->regulatory, priv->hw->wiphy, 812 ath9k_reg_notifier); 813 if (error) 814 goto err_regd; 815 816 reg = &common->regulatory; 817 818 /* Setup TX */ 819 error = ath9k_tx_init(priv); 820 if (error != 0) 821 goto err_tx; 822 823 /* Setup RX */ 824 error = ath9k_rx_init(priv); 825 if (error != 0) 826 goto err_rx; 827 828 /* Register with mac80211 */ 829 error = ieee80211_register_hw(hw); 830 if (error) 831 goto err_register; 832 833 /* Handle world regulatory */ 834 if (!ath_is_world_regd(reg)) { 835 error = regulatory_hint(hw->wiphy, reg->alpha2); 836 if (error) 837 goto err_world; 838 } 839 840 ath_dbg(common, ATH_DBG_CONFIG, 841 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, " 842 "BE:%d, BK:%d, VI:%d, VO:%d\n", 843 priv->wmi_cmd_ep, 844 priv->beacon_ep, 845 priv->cab_ep, 846 priv->uapsd_ep, 847 priv->mgmt_ep, 848 priv->data_be_ep, 849 priv->data_bk_ep, 850 priv->data_vi_ep, 851 priv->data_vo_ep); 852 853 ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name)); 854 wiphy_info(hw->wiphy, "%s\n", hw_name); 855 856 ath9k_init_leds(priv); 857 ath9k_start_rfkill_poll(priv); 858 859 return 0; 860 861 err_world: 862 ieee80211_unregister_hw(hw); 863 err_register: 864 ath9k_rx_cleanup(priv); 865 err_rx: 866 ath9k_tx_cleanup(priv); 867 err_tx: 868 /* Nothing */ 869 err_regd: 870 ath9k_deinit_priv(priv); 871 err_init: 872 return error; 873 } 874 875 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 876 u16 devid, char *product, u32 drv_info) 877 { 878 struct ieee80211_hw *hw; 879 struct ath9k_htc_priv *priv; 880 int ret; 881 882 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); 883 if (!hw) 884 return -ENOMEM; 885 886 priv = hw->priv; 887 priv->hw = hw; 888 priv->htc = htc_handle; 889 priv->dev = dev; 890 htc_handle->drv_priv = priv; 891 SET_IEEE80211_DEV(hw, priv->dev); 892 893 ret = ath9k_htc_wait_for_target(priv); 894 if (ret) 895 goto err_free; 896 897 priv->wmi = ath9k_init_wmi(priv); 898 if (!priv->wmi) { 899 ret = -EINVAL; 900 goto err_free; 901 } 902 903 ret = ath9k_init_htc_services(priv, devid, drv_info); 904 if (ret) 905 goto err_init; 906 907 ret = ath9k_init_device(priv, devid, product, drv_info); 908 if (ret) 909 goto err_init; 910 911 return 0; 912 913 err_init: 914 ath9k_deinit_wmi(priv); 915 err_free: 916 ieee80211_free_hw(hw); 917 return ret; 918 } 919 920 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 921 { 922 if (htc_handle->drv_priv) { 923 924 /* Check if the device has been yanked out. */ 925 if (hotunplug) 926 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED; 927 928 ath9k_deinit_device(htc_handle->drv_priv); 929 ath9k_deinit_wmi(htc_handle->drv_priv); 930 ieee80211_free_hw(htc_handle->drv_priv->hw); 931 } 932 } 933 934 #ifdef CONFIG_PM 935 936 void ath9k_htc_suspend(struct htc_target *htc_handle) 937 { 938 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP); 939 } 940 941 int ath9k_htc_resume(struct htc_target *htc_handle) 942 { 943 struct ath9k_htc_priv *priv = htc_handle->drv_priv; 944 int ret; 945 946 ret = ath9k_htc_wait_for_target(priv); 947 if (ret) 948 return ret; 949 950 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid, 951 priv->ah->hw_version.usbdev); 952 return ret; 953 } 954 #endif 955 956 static int __init ath9k_htc_init(void) 957 { 958 int error; 959 960 error = ath9k_htc_debug_create_root(); 961 if (error < 0) { 962 printk(KERN_ERR 963 "ath9k_htc: Unable to create debugfs root: %d\n", 964 error); 965 goto err_dbg; 966 } 967 968 error = ath9k_hif_usb_init(); 969 if (error < 0) { 970 printk(KERN_ERR 971 "ath9k_htc: No USB devices found," 972 " driver not installed.\n"); 973 error = -ENODEV; 974 goto err_usb; 975 } 976 977 return 0; 978 979 err_usb: 980 ath9k_htc_debug_remove_root(); 981 err_dbg: 982 return error; 983 } 984 module_init(ath9k_htc_init); 985 986 static void __exit ath9k_htc_exit(void) 987 { 988 ath9k_hif_usb_exit(); 989 ath9k_htc_debug_remove_root(); 990 printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); 991 } 992 module_exit(ath9k_htc_exit); 993